ath9k: Move LNA code to antenna.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 104 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
105 spin_unlock(&common->cc_lock);
106 }
898c914a 107
a91d75ae
LR
108 unlock:
109 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
110}
111
112void ath9k_ps_restore(struct ath_softc *sc)
113{
898c914a 114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 115 enum ath9k_power_mode mode;
a91d75ae 116 unsigned long flags;
ad128860 117 bool reset;
a91d75ae
LR
118
119 spin_lock_irqsave(&sc->sc_pm_lock, flags);
120 if (--sc->ps_usecount != 0)
121 goto unlock;
122
ad128860
SM
123 if (sc->ps_idle) {
124 ath9k_hw_setrxabort(sc->sc_ah, 1);
125 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 126 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM
127 } else if (sc->ps_enabled &&
128 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
129 PS_WAIT_FOR_CAB |
130 PS_WAIT_FOR_PSPOLL_DATA |
131 PS_WAIT_FOR_TX_ACK))) {
c6c539f0 132 mode = ATH9K_PM_NETWORK_SLEEP;
ad128860 133 } else {
c6c539f0 134 goto unlock;
ad128860 135 }
c6c539f0
FF
136
137 spin_lock(&common->cc_lock);
138 ath_hw_cycle_counters_update(common);
139 spin_unlock(&common->cc_lock);
140
1a8f0d39 141 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
9adcf440 147static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 148{
5ee08656
FF
149 cancel_work_sync(&sc->paprd_work);
150 cancel_work_sync(&sc->hw_check_work);
151 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 152 cancel_delayed_work_sync(&sc->hw_pll_work);
9adcf440 153}
5ee08656 154
9adcf440
FF
155static void ath_cancel_work(struct ath_softc *sc)
156{
157 __ath_cancel_work(sc);
158 cancel_work_sync(&sc->hw_reset_work);
159}
3cbb5dd7 160
af68abad
SM
161static void ath_restart_work(struct ath_softc *sc)
162{
163 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
164
165 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
166
167 if (AR_SREV_9485(sc->sc_ah) || AR_SREV_9340(sc->sc_ah))
168 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
169 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
170
171 ath_start_rx_poll(sc, 3);
172
173 if (!common->disable_ani)
174 ath_start_ani(common);
175}
176
9adcf440
FF
177static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
178{
179 struct ath_hw *ah = sc->sc_ah;
180 struct ath_common *common = ath9k_hw_common(ah);
ceea2a51 181 bool ret = true;
6a6733f2 182
9adcf440 183 ieee80211_stop_queues(sc->hw);
5e848f78 184
9adcf440
FF
185 sc->hw_busy_count = 0;
186 del_timer_sync(&common->ani.timer);
01e18918 187 del_timer_sync(&sc->rx_poll_timer);
ff37e337 188
9adcf440
FF
189 ath9k_debug_samp_bb_mac(sc);
190 ath9k_hw_disable_interrupts(ah);
8b3f4616 191
9adcf440
FF
192 if (!ath_stoprecv(sc))
193 ret = false;
c0d7c7af 194
ceea2a51
FF
195 if (!ath_drain_all_txq(sc, retry_tx))
196 ret = false;
197
9adcf440
FF
198 if (!flush) {
199 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
200 ath_rx_tasklet(sc, 1, true);
201 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
202 } else {
203 ath_flushrecv(sc);
204 }
20bd2a09 205
9adcf440
FF
206 return ret;
207}
ff37e337 208
9adcf440
FF
209static bool ath_complete_reset(struct ath_softc *sc, bool start)
210{
211 struct ath_hw *ah = sc->sc_ah;
212 struct ath_common *common = ath9k_hw_common(ah);
c0d7c7af 213
c0d7c7af 214 if (ath_startrecv(sc) != 0) {
3800276a 215 ath_err(common, "Unable to restart recv logic\n");
9adcf440 216 return false;
c0d7c7af
LR
217 }
218
5048e8c3
RM
219 ath9k_cmn_update_txpow(ah, sc->curtxpow,
220 sc->config.txpowlimit, &sc->curtxpow);
72d874c6 221 ath9k_hw_set_interrupts(ah);
b037b693 222 ath9k_hw_enable_interrupts(ah);
3989279c 223
4cb54fa3 224 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
1186488b 225 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 226 ath_set_beacon(sc);
9adcf440 227
af68abad 228 ath_restart_work(sc);
5ee08656
FF
229 }
230
8da07830
SM
231 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
232 ath_ant_comb_update(sc);
43c35284 233
9adcf440
FF
234 ieee80211_wake_queues(sc->hw);
235
236 return true;
237}
238
239static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
240 bool retry_tx)
241{
242 struct ath_hw *ah = sc->sc_ah;
243 struct ath_common *common = ath9k_hw_common(ah);
244 struct ath9k_hw_cal_data *caldata = NULL;
245 bool fastcc = true;
246 bool flush = false;
247 int r;
248
249 __ath_cancel_work(sc);
250
251 spin_lock_bh(&sc->sc_pcu_lock);
92460412 252
4cb54fa3 253 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF
254 fastcc = false;
255 caldata = &sc->caldata;
256 }
257
258 if (!hchan) {
259 fastcc = false;
260 flush = true;
261 hchan = ah->curchan;
262 }
263
9adcf440
FF
264 if (!ath_prepare_reset(sc, retry_tx, flush))
265 fastcc = false;
266
d2182b69 267 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 268 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
269
270 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
271 if (r) {
272 ath_err(common,
273 "Unable to reset channel, reset status %d\n", r);
274 goto out;
275 }
276
277 if (!ath_complete_reset(sc, true))
278 r = -EIO;
279
280out:
6a6733f2 281 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
282 return r;
283}
284
285
286/*
287 * Set/change channels. If the channel is really being changed, it's done
288 * by reseting the chip. To accomplish this we must first cleanup any pending
289 * DMA, then restart stuff.
290*/
291static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
292 struct ath9k_channel *hchan)
293{
294 int r;
295
296 if (sc->sc_flags & SC_OP_INVALID)
297 return -EIO;
298
9adcf440 299 r = ath_reset_internal(sc, hchan, false);
6a6733f2 300
3989279c 301 return r;
ff37e337
S
302}
303
7e1e3864
BG
304static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
305 struct ieee80211_vif *vif)
ff37e337
S
306{
307 struct ath_node *an;
ff37e337
S
308 an = (struct ath_node *)sta->drv_priv;
309
7f010c93
BG
310#ifdef CONFIG_ATH9K_DEBUGFS
311 spin_lock(&sc->nodes_lock);
312 list_add(&an->list, &sc->nodes);
313 spin_unlock(&sc->nodes_lock);
156369fa 314#endif
7f010c93 315 an->sta = sta;
7e1e3864 316 an->vif = vif;
3d4e20f2 317
a4d6367f 318 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 319 ath_tx_node_init(sc, an);
9e98ac65 320 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
321 sta->ht_cap.ampdu_factor);
322 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
323 }
ff37e337
S
324}
325
326static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
327{
328 struct ath_node *an = (struct ath_node *)sta->drv_priv;
329
7f010c93
BG
330#ifdef CONFIG_ATH9K_DEBUGFS
331 spin_lock(&sc->nodes_lock);
332 list_del(&an->list);
333 spin_unlock(&sc->nodes_lock);
334 an->sta = NULL;
335#endif
336
a4d6367f 337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S
338 ath_tx_node_cleanup(sc, an);
339}
340
55624204 341void ath9k_tasklet(unsigned long data)
ff37e337
S
342{
343 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 344 struct ath_hw *ah = sc->sc_ah;
c46917bb 345 struct ath_common *common = ath9k_hw_common(ah);
af03abec 346
17d7904d 347 u32 status = sc->intrstatus;
b5c80475 348 u32 rxmask;
ff37e337 349
e3927007
FF
350 ath9k_ps_wakeup(sc);
351 spin_lock(&sc->sc_pcu_lock);
352
a4d86d95
RM
353 if ((status & ATH9K_INT_FATAL) ||
354 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
355#ifdef CONFIG_ATH9K_DEBUGFS
356 enum ath_reset_type type;
357
358 if (status & ATH9K_INT_FATAL)
359 type = RESET_TYPE_FATAL_INT;
360 else
361 type = RESET_TYPE_BB_WATCHDOG;
362
363 RESET_STAT_INC(sc, type);
364#endif
236de514 365 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 366 goto out;
063d8be3 367 }
ff37e337 368
4105f807
RM
369 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
370 /*
371 * TSF sync does not look correct; remain awake to sync with
372 * the next Beacon.
373 */
d2182b69 374 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 375 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
376 }
377
b5c80475
FF
378 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
379 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
380 ATH9K_INT_RXORN);
381 else
382 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
383
384 if (status & rxmask) {
b5c80475
FF
385 /* Check for high priority Rx first */
386 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
387 (status & ATH9K_INT_RXHP))
388 ath_rx_tasklet(sc, 0, true);
389
390 ath_rx_tasklet(sc, 0, false);
ff37e337
S
391 }
392
e5003249
VT
393 if (status & ATH9K_INT_TX) {
394 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
395 ath_tx_edma_tasklet(sc);
396 else
397 ath_tx_tasklet(sc);
398 }
063d8be3 399
56ca0dba 400 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 401
e3927007 402out:
ff37e337 403 /* re-enable hardware interrupt */
4df3071e 404 ath9k_hw_enable_interrupts(ah);
6a6733f2 405
52671e43 406 spin_unlock(&sc->sc_pcu_lock);
153e080d 407 ath9k_ps_restore(sc);
ff37e337
S
408}
409
6baff7f9 410irqreturn_t ath_isr(int irq, void *dev)
ff37e337 411{
063d8be3
S
412#define SCHED_INTR ( \
413 ATH9K_INT_FATAL | \
a4d86d95 414 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
415 ATH9K_INT_RXORN | \
416 ATH9K_INT_RXEOL | \
417 ATH9K_INT_RX | \
b5c80475
FF
418 ATH9K_INT_RXLP | \
419 ATH9K_INT_RXHP | \
063d8be3
S
420 ATH9K_INT_TX | \
421 ATH9K_INT_BMISS | \
422 ATH9K_INT_CST | \
ebb8e1d7 423 ATH9K_INT_TSFOOR | \
40dc5392
MSS
424 ATH9K_INT_GENTIMER | \
425 ATH9K_INT_MCI)
063d8be3 426
ff37e337 427 struct ath_softc *sc = dev;
cbe61d8a 428 struct ath_hw *ah = sc->sc_ah;
b5bfc568 429 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
430 enum ath9k_int status;
431 bool sched = false;
432
063d8be3
S
433 /*
434 * The hardware is not ready/present, don't
435 * touch anything. Note this can happen early
436 * on if the IRQ is shared.
437 */
438 if (sc->sc_flags & SC_OP_INVALID)
439 return IRQ_NONE;
ff37e337 440
063d8be3
S
441
442 /* shared irq, not for us */
443
153e080d 444 if (!ath9k_hw_intrpend(ah))
063d8be3 445 return IRQ_NONE;
063d8be3
S
446
447 /*
448 * Figure out the reason(s) for the interrupt. Note
449 * that the hal returns a pseudo-ISR that may include
450 * bits we haven't explicitly enabled so we mask the
451 * value to insure we only process bits we requested.
452 */
453 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 454 status &= ah->imask; /* discard unasked-for bits */
ff37e337 455
063d8be3
S
456 /*
457 * If there are no status bits set, then this interrupt was not
458 * for me (should have been caught above).
459 */
153e080d 460 if (!status)
063d8be3 461 return IRQ_NONE;
ff37e337 462
063d8be3
S
463 /* Cache the status */
464 sc->intrstatus = status;
465
466 if (status & SCHED_INTR)
467 sched = true;
468
469 /*
470 * If a FATAL or RXORN interrupt is received, we have to reset the
471 * chip immediately.
472 */
b5c80475
FF
473 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
474 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
475 goto chip_reset;
476
08578b8f
LR
477 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
478 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
479
480 spin_lock(&common->cc_lock);
481 ath_hw_cycle_counters_update(common);
08578b8f 482 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
483 spin_unlock(&common->cc_lock);
484
08578b8f
LR
485 goto chip_reset;
486 }
487
063d8be3
S
488 if (status & ATH9K_INT_SWBA)
489 tasklet_schedule(&sc->bcon_tasklet);
490
491 if (status & ATH9K_INT_TXURN)
492 ath9k_hw_updatetxtriglevel(ah, true);
493
0682c9b5
RM
494 if (status & ATH9K_INT_RXEOL) {
495 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 496 ath9k_hw_set_interrupts(ah);
b5c80475
FF
497 }
498
063d8be3 499 if (status & ATH9K_INT_MIB) {
ff37e337 500 /*
063d8be3
S
501 * Disable interrupts until we service the MIB
502 * interrupt; otherwise it will continue to
503 * fire.
ff37e337 504 */
4df3071e 505 ath9k_hw_disable_interrupts(ah);
063d8be3
S
506 /*
507 * Let the hal handle the event. We assume
508 * it will clear whatever condition caused
509 * the interrupt.
510 */
88eac2da 511 spin_lock(&common->cc_lock);
bfc472bb 512 ath9k_hw_proc_mib_event(ah);
88eac2da 513 spin_unlock(&common->cc_lock);
4df3071e 514 ath9k_hw_enable_interrupts(ah);
063d8be3 515 }
ff37e337 516
153e080d
VT
517 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
518 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
519 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
520 goto chip_reset;
063d8be3
S
521 /* Clear RxAbort bit so that we can
522 * receive frames */
9ecdef4b 523 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 524 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 525 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 526 }
063d8be3
S
527
528chip_reset:
ff37e337 529
817e11de
S
530 ath_debug_stat_interrupt(sc, status);
531
ff37e337 532 if (sched) {
4df3071e
FF
533 /* turn off every interrupt */
534 ath9k_hw_disable_interrupts(ah);
ff37e337
S
535 tasklet_schedule(&sc->intr_tq);
536 }
537
538 return IRQ_HANDLED;
063d8be3
S
539
540#undef SCHED_INTR
ff37e337
S
541}
542
236de514 543static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 544{
ae8d2858 545 int r;
ff37e337 546
783cd01e 547 ath9k_ps_wakeup(sc);
6a6733f2 548
9adcf440 549 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
550
551 if (retry_tx) {
552 int i;
553 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
554 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
555 spin_lock_bh(&sc->tx.txq[i].axq_lock);
556 ath_txq_schedule(sc, &sc->tx.txq[i]);
557 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
558 }
559 }
560 }
561
783cd01e 562 ath9k_ps_restore(sc);
2ab81d4a 563
ae8d2858 564 return r;
ff37e337
S
565}
566
236de514
FF
567void ath_reset_work(struct work_struct *work)
568{
569 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
570
236de514 571 ath_reset(sc, true);
236de514
FF
572}
573
ff37e337
S
574/**********************/
575/* mac80211 callbacks */
576/**********************/
577
8feceb67 578static int ath9k_start(struct ieee80211_hw *hw)
f078f209 579{
9ac58615 580 struct ath_softc *sc = hw->priv;
af03abec 581 struct ath_hw *ah = sc->sc_ah;
c46917bb 582 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 583 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 584 struct ath9k_channel *init_channel;
82880a7c 585 int r;
f078f209 586
d2182b69 587 ath_dbg(common, CONFIG,
226afe68
JP
588 "Starting driver with initial channel: %d MHz\n",
589 curchan->center_freq);
f078f209 590
f62d816f 591 ath9k_ps_wakeup(sc);
141b38b6
S
592 mutex_lock(&sc->mutex);
593
c344c9cb 594 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
595
596 /* Reset SERDES registers */
84c87dc8 597 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
598
599 /*
600 * The basic interface to setting the hardware in a good
601 * state is ``reset''. On return the hardware is known to
602 * be powered up and with interrupts disabled. This must
603 * be followed by initialization of the appropriate bits
604 * and then setup of the interrupt mask.
605 */
4bdd1e97 606 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
607
608 atomic_set(&ah->intr_ref_cnt, -1);
609
20bd2a09 610 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 611 if (r) {
3800276a
JP
612 ath_err(common,
613 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
614 r, curchan->center_freq);
4bdd1e97 615 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 616 goto mutex_unlock;
ff37e337 617 }
ff37e337 618
ff37e337 619 /* Setup our intr mask. */
b5c80475
FF
620 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
621 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
622 ATH9K_INT_GLOBAL;
623
624 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
625 ah->imask |= ATH9K_INT_RXHP |
626 ATH9K_INT_RXLP |
627 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
628 else
629 ah->imask |= ATH9K_INT_RX;
ff37e337 630
364734fa 631 ah->imask |= ATH9K_INT_GTT;
ff37e337 632
af03abec 633 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 634 ah->imask |= ATH9K_INT_CST;
ff37e337 635
e270e776 636 ath_mci_enable(sc);
40dc5392 637
ff37e337 638 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 639 sc->sc_ah->is_monitoring = false;
ff37e337 640
9adcf440
FF
641 if (!ath_complete_reset(sc, false)) {
642 r = -EIO;
643 spin_unlock_bh(&sc->sc_pcu_lock);
644 goto mutex_unlock;
645 }
ff37e337 646
c0c11741
FF
647 if (ah->led_pin >= 0) {
648 ath9k_hw_cfg_output(ah, ah->led_pin,
649 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
650 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
651 }
652
653 /*
654 * Reset key cache to sane defaults (all entries cleared) instead of
655 * semi-random values after suspend/resume.
656 */
657 ath9k_cmn_init_crypto(sc->sc_ah);
658
9adcf440 659 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 660
df198b17 661 ath9k_start_btcoex(sc);
1773912b 662
8060e169
VT
663 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
664 common->bus_ops->extn_synch_en(common);
665
141b38b6
S
666mutex_unlock:
667 mutex_unlock(&sc->mutex);
668
f62d816f
FF
669 ath9k_ps_restore(sc);
670
ae8d2858 671 return r;
f078f209
LR
672}
673
7bb45683 674static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 675{
9ac58615 676 struct ath_softc *sc = hw->priv;
c46917bb 677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 678 struct ath_tx_control txctl;
1bc14880 679 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 680
96148326 681 if (sc->ps_enabled) {
dc8c4585
JM
682 /*
683 * mac80211 does not set PM field for normal data frames, so we
684 * need to update that based on the current PS mode.
685 */
686 if (ieee80211_is_data(hdr->frame_control) &&
687 !ieee80211_is_nullfunc(hdr->frame_control) &&
688 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 689 ath_dbg(common, PS,
226afe68 690 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
691 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
692 }
693 }
694
ad128860 695 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
696 /*
697 * We are using PS-Poll and mac80211 can request TX while in
698 * power save mode. Need to wake up hardware for the TX to be
699 * completed and if needed, also for RX of buffered frames.
700 */
9a23f9ca 701 ath9k_ps_wakeup(sc);
fdf76622
VT
702 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
703 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 704 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 705 ath_dbg(common, PS,
226afe68 706 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 707 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 708 } else {
d2182b69 709 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 710 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
711 }
712 /*
713 * The actual restore operation will happen only after
ad128860 714 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
715 * the ps_usecount here.
716 */
717 ath9k_ps_restore(sc);
718 }
719
ad128860
SM
720 /*
721 * Cannot tx while the hardware is in full sleep, it first needs a full
722 * chip reset to recover from that
723 */
724 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
725 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
726 goto exit;
727 }
728
528f0c6b 729 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 730 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 731
d2182b69 732 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 733
c52f33d0 734 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 735 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 736 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 737 goto exit;
8feceb67
VT
738 }
739
7bb45683 740 return;
528f0c6b
S
741exit:
742 dev_kfree_skb_any(skb);
f078f209
LR
743}
744
8feceb67 745static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 746{
9ac58615 747 struct ath_softc *sc = hw->priv;
af03abec 748 struct ath_hw *ah = sc->sc_ah;
c46917bb 749 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 750 bool prev_idle;
f078f209 751
4c483817
S
752 mutex_lock(&sc->mutex);
753
9adcf440 754 ath_cancel_work(sc);
01e18918 755 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 756
9c84b797 757 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 758 ath_dbg(common, ANY, "Device not present\n");
4c483817 759 mutex_unlock(&sc->mutex);
9c84b797
S
760 return;
761 }
8feceb67 762
3867cf6a
S
763 /* Ensure HW is awake when we try to shut it down. */
764 ath9k_ps_wakeup(sc);
765
df198b17 766 ath9k_stop_btcoex(sc);
1773912b 767
6a6733f2
LR
768 spin_lock_bh(&sc->sc_pcu_lock);
769
203043f5
SG
770 /* prevent tasklets to enable interrupts once we disable them */
771 ah->imask &= ~ATH9K_INT_GLOBAL;
772
ff37e337
S
773 /* make sure h/w will not generate any interrupt
774 * before setting the invalid flag. */
4df3071e 775 ath9k_hw_disable_interrupts(ah);
ff37e337 776
c0c11741
FF
777 spin_unlock_bh(&sc->sc_pcu_lock);
778
779 /* we can now sync irq and kill any running tasklets, since we already
780 * disabled interrupts and not holding a spin lock */
781 synchronize_irq(sc->irq);
782 tasklet_kill(&sc->intr_tq);
783 tasklet_kill(&sc->bcon_tasklet);
784
785 prev_idle = sc->ps_idle;
786 sc->ps_idle = true;
787
788 spin_lock_bh(&sc->sc_pcu_lock);
789
790 if (ah->led_pin >= 0) {
791 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
792 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
793 }
794
795 ath_prepare_reset(sc, false, true);
ff37e337 796
0d95521e
FF
797 if (sc->rx.frag) {
798 dev_kfree_skb_any(sc->rx.frag);
799 sc->rx.frag = NULL;
800 }
801
c0c11741
FF
802 if (!ah->curchan)
803 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 804
c0c11741
FF
805 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
806 ath9k_hw_phy_disable(ah);
6a6733f2 807
c0c11741 808 ath9k_hw_configpcipowersave(ah, true);
203043f5 809
c0c11741 810 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 811
c0c11741 812 ath9k_ps_restore(sc);
ff37e337
S
813
814 sc->sc_flags |= SC_OP_INVALID;
c0c11741 815 sc->ps_idle = prev_idle;
500c064d 816
141b38b6
S
817 mutex_unlock(&sc->mutex);
818
d2182b69 819 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
820}
821
4801416c
BG
822bool ath9k_uses_beacons(int type)
823{
824 switch (type) {
825 case NL80211_IFTYPE_AP:
826 case NL80211_IFTYPE_ADHOC:
827 case NL80211_IFTYPE_MESH_POINT:
828 return true;
829 default:
830 return false;
831 }
832}
833
834static void ath9k_reclaim_beacon(struct ath_softc *sc,
835 struct ieee80211_vif *vif)
f078f209 836{
1ed32e4f 837 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 838
014cf3bb 839 ath9k_set_beaconing_status(sc, false);
4801416c 840 ath_beacon_return(sc, avp);
014cf3bb 841 ath9k_set_beaconing_status(sc, true);
4801416c
BG
842}
843
844static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
845{
846 struct ath9k_vif_iter_data *iter_data = data;
847 int i;
848
849 if (iter_data->hw_macaddr)
850 for (i = 0; i < ETH_ALEN; i++)
851 iter_data->mask[i] &=
852 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 853
1ed32e4f 854 switch (vif->type) {
4801416c
BG
855 case NL80211_IFTYPE_AP:
856 iter_data->naps++;
f078f209 857 break;
4801416c
BG
858 case NL80211_IFTYPE_STATION:
859 iter_data->nstations++;
e51f3eff 860 break;
05c914fe 861 case NL80211_IFTYPE_ADHOC:
4801416c
BG
862 iter_data->nadhocs++;
863 break;
9cb5412b 864 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
865 iter_data->nmeshes++;
866 break;
867 case NL80211_IFTYPE_WDS:
868 iter_data->nwds++;
f078f209
LR
869 break;
870 default:
4801416c 871 break;
f078f209 872 }
4801416c 873}
f078f209 874
4801416c
BG
875/* Called with sc->mutex held. */
876void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
877 struct ieee80211_vif *vif,
878 struct ath9k_vif_iter_data *iter_data)
879{
9ac58615 880 struct ath_softc *sc = hw->priv;
4801416c
BG
881 struct ath_hw *ah = sc->sc_ah;
882 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 883
4801416c
BG
884 /*
885 * Use the hardware MAC address as reference, the hardware uses it
886 * together with the BSSID mask when matching addresses.
887 */
888 memset(iter_data, 0, sizeof(*iter_data));
889 iter_data->hw_macaddr = common->macaddr;
890 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 891
4801416c
BG
892 if (vif)
893 ath9k_vif_iter(iter_data, vif->addr, vif);
894
895 /* Get list of all active MAC addresses */
4801416c
BG
896 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
897 iter_data);
4801416c 898}
8ca21f01 899
4801416c
BG
900/* Called with sc->mutex held. */
901static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
902 struct ieee80211_vif *vif)
903{
9ac58615 904 struct ath_softc *sc = hw->priv;
4801416c
BG
905 struct ath_hw *ah = sc->sc_ah;
906 struct ath_common *common = ath9k_hw_common(ah);
907 struct ath9k_vif_iter_data iter_data;
8ca21f01 908
4801416c 909 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 910
4801416c
BG
911 /* Set BSSID mask. */
912 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
913 ath_hw_setbssidmask(common);
914
915 /* Set op-mode & TSF */
916 if (iter_data.naps > 0) {
3069168c 917 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 918 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
919 ah->opmode = NL80211_IFTYPE_AP;
920 } else {
921 ath9k_hw_set_tsfadjust(ah, 0);
922 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 923
fd5999cf
JC
924 if (iter_data.nmeshes)
925 ah->opmode = NL80211_IFTYPE_MESH_POINT;
926 else if (iter_data.nwds)
4801416c
BG
927 ah->opmode = NL80211_IFTYPE_AP;
928 else if (iter_data.nadhocs)
929 ah->opmode = NL80211_IFTYPE_ADHOC;
930 else
931 ah->opmode = NL80211_IFTYPE_STATION;
932 }
5640b08e 933
4e30ffa2
VN
934 /*
935 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 936 */
4801416c 937 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
938 if (ah->config.enable_ani)
939 ah->imask |= ATH9K_INT_MIB;
3069168c 940 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
941 } else {
942 ah->imask &= ~ATH9K_INT_MIB;
943 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
944 }
945
72d874c6 946 ath9k_hw_set_interrupts(ah);
4e30ffa2 947
4801416c 948 /* Set up ANI */
2e5ef459 949 if (iter_data.naps > 0) {
729da390 950 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
951
952 if (!common->disable_ani) {
953 sc->sc_flags |= SC_OP_ANI_RUN;
954 ath_start_ani(common);
955 }
956
f60c49b6
RM
957 } else {
958 sc->sc_flags &= ~SC_OP_ANI_RUN;
959 del_timer_sync(&common->ani.timer);
6c3118e2 960 }
4801416c 961}
6f255425 962
4801416c
BG
963/* Called with sc->mutex held, vif counts set up properly. */
964static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
965 struct ieee80211_vif *vif)
966{
9ac58615 967 struct ath_softc *sc = hw->priv;
4801416c
BG
968
969 ath9k_calculate_summary_state(hw, vif);
970
971 if (ath9k_uses_beacons(vif->type)) {
ed2578cd 972 /* Reserve a beacon slot for the vif */
014cf3bb 973 ath9k_set_beaconing_status(sc, false);
ed2578cd 974 ath_beacon_alloc(sc, vif);
014cf3bb 975 ath9k_set_beaconing_status(sc, true);
4801416c 976 }
f078f209
LR
977}
978
4801416c
BG
979static int ath9k_add_interface(struct ieee80211_hw *hw,
980 struct ieee80211_vif *vif)
6b3b991d 981{
9ac58615 982 struct ath_softc *sc = hw->priv;
4801416c
BG
983 struct ath_hw *ah = sc->sc_ah;
984 struct ath_common *common = ath9k_hw_common(ah);
4801416c 985 int ret = 0;
6b3b991d 986
96f372c9 987 ath9k_ps_wakeup(sc);
4801416c 988 mutex_lock(&sc->mutex);
6b3b991d 989
4801416c
BG
990 switch (vif->type) {
991 case NL80211_IFTYPE_STATION:
992 case NL80211_IFTYPE_WDS:
993 case NL80211_IFTYPE_ADHOC:
994 case NL80211_IFTYPE_AP:
995 case NL80211_IFTYPE_MESH_POINT:
996 break;
997 default:
998 ath_err(common, "Interface type %d not yet supported\n",
999 vif->type);
1000 ret = -EOPNOTSUPP;
1001 goto out;
1002 }
6b3b991d 1003
4801416c
BG
1004 if (ath9k_uses_beacons(vif->type)) {
1005 if (sc->nbcnvifs >= ATH_BCBUF) {
1006 ath_err(common, "Not enough beacon buffers when adding"
1007 " new interface of type: %i\n",
1008 vif->type);
1009 ret = -ENOBUFS;
1010 goto out;
1011 }
1012 }
1013
59575d1c
RM
1014 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1015 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1016 sc->nvifs > 0)) {
4801416c
BG
1017 ath_err(common, "Cannot create ADHOC interface when other"
1018 " interfaces already exist.\n");
1019 ret = -EINVAL;
1020 goto out;
6b3b991d 1021 }
4801416c 1022
d2182b69 1023 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1024
4801416c
BG
1025 sc->nvifs++;
1026
1027 ath9k_do_vif_add_setup(hw, vif);
1028out:
1029 mutex_unlock(&sc->mutex);
96f372c9 1030 ath9k_ps_restore(sc);
4801416c 1031 return ret;
6b3b991d
RM
1032}
1033
1034static int ath9k_change_interface(struct ieee80211_hw *hw,
1035 struct ieee80211_vif *vif,
1036 enum nl80211_iftype new_type,
1037 bool p2p)
1038{
9ac58615 1039 struct ath_softc *sc = hw->priv;
6b3b991d 1040 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1041 int ret = 0;
6b3b991d 1042
d2182b69 1043 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 1044 mutex_lock(&sc->mutex);
96f372c9 1045 ath9k_ps_wakeup(sc);
6b3b991d 1046
4801416c
BG
1047 /* See if new interface type is valid. */
1048 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1049 (sc->nvifs > 1)) {
1050 ath_err(common, "When using ADHOC, it must be the only"
1051 " interface.\n");
1052 ret = -EINVAL;
1053 goto out;
1054 }
1055
1056 if (ath9k_uses_beacons(new_type) &&
1057 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1058 if (sc->nbcnvifs >= ATH_BCBUF) {
1059 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1060 ret = -ENOBUFS;
1061 goto out;
6b3b991d 1062 }
6b3b991d 1063 }
4801416c
BG
1064
1065 /* Clean up old vif stuff */
1066 if (ath9k_uses_beacons(vif->type))
1067 ath9k_reclaim_beacon(sc, vif);
1068
1069 /* Add new settings */
6b3b991d
RM
1070 vif->type = new_type;
1071 vif->p2p = p2p;
1072
4801416c 1073 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1074out:
96f372c9 1075 ath9k_ps_restore(sc);
6b3b991d 1076 mutex_unlock(&sc->mutex);
6dab55bf 1077 return ret;
6b3b991d
RM
1078}
1079
8feceb67 1080static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1081 struct ieee80211_vif *vif)
f078f209 1082{
9ac58615 1083 struct ath_softc *sc = hw->priv;
c46917bb 1084 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1085
d2182b69 1086 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1087
96f372c9 1088 ath9k_ps_wakeup(sc);
141b38b6
S
1089 mutex_lock(&sc->mutex);
1090
4801416c 1091 sc->nvifs--;
580f0b8a 1092
8feceb67 1093 /* Reclaim beacon resources */
4801416c 1094 if (ath9k_uses_beacons(vif->type))
6b3b991d 1095 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1096
4801416c 1097 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1098
1099 mutex_unlock(&sc->mutex);
96f372c9 1100 ath9k_ps_restore(sc);
f078f209
LR
1101}
1102
fbab7390 1103static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1104{
3069168c 1105 struct ath_hw *ah = sc->sc_ah;
ad128860 1106 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1107
3f7c5c10 1108 sc->ps_enabled = true;
3069168c
PR
1109 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1110 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1111 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1112 ath9k_hw_set_interrupts(ah);
3f7c5c10 1113 }
fdf76622 1114 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1115 }
ad128860 1116 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1117}
1118
845d708e
SB
1119static void ath9k_disable_ps(struct ath_softc *sc)
1120{
1121 struct ath_hw *ah = sc->sc_ah;
ad128860 1122 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB
1123
1124 sc->ps_enabled = false;
1125 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1126 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1127 ath9k_hw_setrxabort(ah, 0);
1128 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1129 PS_WAIT_FOR_CAB |
1130 PS_WAIT_FOR_PSPOLL_DATA |
1131 PS_WAIT_FOR_TX_ACK);
1132 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1133 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1134 ath9k_hw_set_interrupts(ah);
845d708e
SB
1135 }
1136 }
ad128860 1137 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1138}
1139
e8975581 1140static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1141{
9ac58615 1142 struct ath_softc *sc = hw->priv;
3430098a
FF
1143 struct ath_hw *ah = sc->sc_ah;
1144 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1145 struct ieee80211_conf *conf = &hw->conf;
75600abf 1146 bool reset_channel = false;
f078f209 1147
c0c11741 1148 ath9k_ps_wakeup(sc);
aa33de09 1149 mutex_lock(&sc->mutex);
141b38b6 1150
daa1b6ee 1151 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1152 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
daa1b6ee
FF
1153 if (sc->ps_idle)
1154 ath_cancel_work(sc);
75600abf
FF
1155 else
1156 /*
1157 * The chip needs a reset to properly wake up from
1158 * full sleep
1159 */
1160 reset_channel = ah->chip_fullsleep;
daa1b6ee 1161 }
64839170 1162
e7824a50
LR
1163 /*
1164 * We just prepare to enable PS. We have to wait until our AP has
1165 * ACK'd our null data frame to disable RX otherwise we'll ignore
1166 * those ACKs and end up retransmitting the same null data frames.
1167 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1168 */
3cbb5dd7 1169 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1170 unsigned long flags;
1171 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1172 if (conf->flags & IEEE80211_CONF_PS)
1173 ath9k_enable_ps(sc);
845d708e
SB
1174 else
1175 ath9k_disable_ps(sc);
8ab2cd09 1176 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1177 }
1178
199afd9d
S
1179 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1180 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1181 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1182 sc->sc_ah->is_monitoring = true;
1183 } else {
d2182b69 1184 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1185 sc->sc_ah->is_monitoring = false;
199afd9d
S
1186 }
1187 }
1188
75600abf 1189 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1190 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1191 int pos = curchan->hw_value;
3430098a
FF
1192 int old_pos = -1;
1193 unsigned long flags;
1194
1195 if (ah->curchan)
1196 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1197
d2182b69 1198 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1199 curchan->center_freq, conf->channel_type);
f078f209 1200
3430098a
FF
1201 /* update survey stats for the old channel before switching */
1202 spin_lock_irqsave(&common->cc_lock, flags);
1203 ath_update_survey_stats(sc);
1204 spin_unlock_irqrestore(&common->cc_lock, flags);
1205
e338a85e
RM
1206 /*
1207 * Preserve the current channel values, before updating
1208 * the same channel
1209 */
1a19f77f
RM
1210 if (ah->curchan && (old_pos == pos))
1211 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1212
1213 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1214 curchan, conf->channel_type);
1215
3430098a
FF
1216 /*
1217 * If the operating channel changes, change the survey in-use flags
1218 * along with it.
1219 * Reset the survey data for the new channel, unless we're switching
1220 * back to the operating channel from an off-channel operation.
1221 */
1222 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1223 sc->cur_survey != &sc->survey[pos]) {
1224
1225 if (sc->cur_survey)
1226 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1227
1228 sc->cur_survey = &sc->survey[pos];
1229
1230 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1231 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1232 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1233 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1234 }
1235
0e2dedf9 1236 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1237 ath_err(common, "Unable to set channel\n");
aa33de09 1238 mutex_unlock(&sc->mutex);
e11602b7
S
1239 return -EINVAL;
1240 }
3430098a
FF
1241
1242 /*
1243 * The most recent snapshot of channel->noisefloor for the old
1244 * channel is only available after the hardware reset. Copy it to
1245 * the survey stats now.
1246 */
1247 if (old_pos >= 0)
1248 ath_update_survey_nf(sc, old_pos);
094d05dc 1249 }
f078f209 1250
c9f6a656 1251 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1252 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1253 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1254 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1255 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1256 }
1257
aa33de09 1258 mutex_unlock(&sc->mutex);
c0c11741 1259 ath9k_ps_restore(sc);
141b38b6 1260
f078f209
LR
1261 return 0;
1262}
1263
8feceb67
VT
1264#define SUPPORTED_FILTERS \
1265 (FIF_PROMISC_IN_BSS | \
1266 FIF_ALLMULTI | \
1267 FIF_CONTROL | \
af6a3fc7 1268 FIF_PSPOLL | \
8feceb67
VT
1269 FIF_OTHER_BSS | \
1270 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1271 FIF_PROBE_REQ | \
8feceb67 1272 FIF_FCSFAIL)
c83be688 1273
8feceb67
VT
1274/* FIXME: sc->sc_full_reset ? */
1275static void ath9k_configure_filter(struct ieee80211_hw *hw,
1276 unsigned int changed_flags,
1277 unsigned int *total_flags,
3ac64bee 1278 u64 multicast)
8feceb67 1279{
9ac58615 1280 struct ath_softc *sc = hw->priv;
8feceb67 1281 u32 rfilt;
f078f209 1282
8feceb67
VT
1283 changed_flags &= SUPPORTED_FILTERS;
1284 *total_flags &= SUPPORTED_FILTERS;
f078f209 1285
b77f483f 1286 sc->rx.rxfilter = *total_flags;
aa68aeaa 1287 ath9k_ps_wakeup(sc);
8feceb67
VT
1288 rfilt = ath_calcrxfilter(sc);
1289 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1290 ath9k_ps_restore(sc);
f078f209 1291
d2182b69
JP
1292 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1293 rfilt);
8feceb67 1294}
f078f209 1295
4ca77860
JB
1296static int ath9k_sta_add(struct ieee80211_hw *hw,
1297 struct ieee80211_vif *vif,
1298 struct ieee80211_sta *sta)
8feceb67 1299{
9ac58615 1300 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1301 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1302 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1303 struct ieee80211_key_conf ps_key = { };
f078f209 1304
7e1e3864 1305 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1306
1307 if (vif->type != NL80211_IFTYPE_AP &&
1308 vif->type != NL80211_IFTYPE_AP_VLAN)
1309 return 0;
1310
93ae2dd2 1311 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1312
1313 return 0;
1314}
1315
93ae2dd2
FF
1316static void ath9k_del_ps_key(struct ath_softc *sc,
1317 struct ieee80211_vif *vif,
1318 struct ieee80211_sta *sta)
1319{
1320 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1321 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1322 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1323
1324 if (!an->ps_key)
1325 return;
1326
1327 ath_key_delete(common, &ps_key);
1328}
1329
4ca77860
JB
1330static int ath9k_sta_remove(struct ieee80211_hw *hw,
1331 struct ieee80211_vif *vif,
1332 struct ieee80211_sta *sta)
1333{
9ac58615 1334 struct ath_softc *sc = hw->priv;
4ca77860 1335
93ae2dd2 1336 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1337 ath_node_detach(sc, sta);
1338
1339 return 0;
f078f209
LR
1340}
1341
5519541d
FF
1342static void ath9k_sta_notify(struct ieee80211_hw *hw,
1343 struct ieee80211_vif *vif,
1344 enum sta_notify_cmd cmd,
1345 struct ieee80211_sta *sta)
1346{
1347 struct ath_softc *sc = hw->priv;
1348 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1349
3d4e20f2 1350 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1351 return;
1352
5519541d
FF
1353 switch (cmd) {
1354 case STA_NOTIFY_SLEEP:
1355 an->sleeping = true;
042ec453 1356 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1357 break;
1358 case STA_NOTIFY_AWAKE:
1359 an->sleeping = false;
1360 ath_tx_aggr_wakeup(sc, an);
1361 break;
1362 }
1363}
1364
8a3a3c85
EP
1365static int ath9k_conf_tx(struct ieee80211_hw *hw,
1366 struct ieee80211_vif *vif, u16 queue,
8feceb67 1367 const struct ieee80211_tx_queue_params *params)
f078f209 1368{
9ac58615 1369 struct ath_softc *sc = hw->priv;
c46917bb 1370 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1371 struct ath_txq *txq;
8feceb67 1372 struct ath9k_tx_queue_info qi;
066dae93 1373 int ret = 0;
f078f209 1374
8feceb67
VT
1375 if (queue >= WME_NUM_AC)
1376 return 0;
f078f209 1377
066dae93
FF
1378 txq = sc->tx.txq_map[queue];
1379
96f372c9 1380 ath9k_ps_wakeup(sc);
141b38b6
S
1381 mutex_lock(&sc->mutex);
1382
1ffb0610
S
1383 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1384
8feceb67
VT
1385 qi.tqi_aifs = params->aifs;
1386 qi.tqi_cwmin = params->cw_min;
1387 qi.tqi_cwmax = params->cw_max;
1388 qi.tqi_burstTime = params->txop;
f078f209 1389
d2182b69 1390 ath_dbg(common, CONFIG,
226afe68
JP
1391 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1392 queue, txq->axq_qnum, params->aifs, params->cw_min,
1393 params->cw_max, params->txop);
f078f209 1394
066dae93 1395 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1396 if (ret)
3800276a 1397 ath_err(common, "TXQ Update failed\n");
f078f209 1398
94db2936 1399 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1400 if (queue == WME_AC_BE && !ret)
94db2936
VN
1401 ath_beaconq_config(sc);
1402
141b38b6 1403 mutex_unlock(&sc->mutex);
96f372c9 1404 ath9k_ps_restore(sc);
141b38b6 1405
8feceb67
VT
1406 return ret;
1407}
f078f209 1408
8feceb67
VT
1409static int ath9k_set_key(struct ieee80211_hw *hw,
1410 enum set_key_cmd cmd,
dc822b5d
JB
1411 struct ieee80211_vif *vif,
1412 struct ieee80211_sta *sta,
8feceb67
VT
1413 struct ieee80211_key_conf *key)
1414{
9ac58615 1415 struct ath_softc *sc = hw->priv;
c46917bb 1416 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1417 int ret = 0;
f078f209 1418
3e6109c5 1419 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1420 return -ENOSPC;
1421
5bd5e9a6
CYY
1422 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1423 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1424 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1425 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1426 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1427 /*
1428 * For now, disable hw crypto for the RSN IBSS group keys. This
1429 * could be optimized in the future to use a modified key cache
1430 * design to support per-STA RX GTK, but until that gets
1431 * implemented, use of software crypto for group addressed
1432 * frames is a acceptable to allow RSN IBSS to be used.
1433 */
1434 return -EOPNOTSUPP;
1435 }
1436
141b38b6 1437 mutex_lock(&sc->mutex);
3cbb5dd7 1438 ath9k_ps_wakeup(sc);
d2182b69 1439 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1440
8feceb67
VT
1441 switch (cmd) {
1442 case SET_KEY:
93ae2dd2
FF
1443 if (sta)
1444 ath9k_del_ps_key(sc, vif, sta);
1445
040e539e 1446 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1447 if (ret >= 0) {
1448 key->hw_key_idx = ret;
8feceb67
VT
1449 /* push IV and Michael MIC generation to stack */
1450 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1451 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1452 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1453 if (sc->sc_ah->sw_mgmt_crypto &&
1454 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1455 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1456 ret = 0;
8feceb67
VT
1457 }
1458 break;
1459 case DISABLE_KEY:
040e539e 1460 ath_key_delete(common, key);
8feceb67
VT
1461 break;
1462 default:
1463 ret = -EINVAL;
1464 }
f078f209 1465
3cbb5dd7 1466 ath9k_ps_restore(sc);
141b38b6
S
1467 mutex_unlock(&sc->mutex);
1468
8feceb67
VT
1469 return ret;
1470}
4f5ef75b
RM
1471static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1472{
1473 struct ath_softc *sc = data;
1474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1475 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1476 struct ath_vif *avp = (void *)vif->drv_priv;
1477
2e5ef459
RM
1478 /*
1479 * Skip iteration if primary station vif's bss info
1480 * was not changed
1481 */
1482 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1483 return;
1484
1485 if (bss_conf->assoc) {
1486 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1487 avp->primary_sta_vif = true;
4f5ef75b
RM
1488 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1489 common->curaid = bss_conf->aid;
1490 ath9k_hw_write_associd(sc->sc_ah);
d2182b69
JP
1491 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1492 bss_conf->aid, common->curbssid);
2e5ef459
RM
1493 ath_beacon_config(sc, vif);
1494 /*
1495 * Request a re-configuration of Beacon related timers
1496 * on the receipt of the first Beacon frame (i.e.,
1497 * after time sync with the AP).
1498 */
1499 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1500 /* Reset rssi stats */
1501 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1502 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1503
01e18918
RM
1504 ath_start_rx_poll(sc, 3);
1505
05c0be2f
MSS
1506 if (!common->disable_ani) {
1507 sc->sc_flags |= SC_OP_ANI_RUN;
1508 ath_start_ani(common);
1509 }
1510
4f5ef75b
RM
1511 }
1512}
1513
1514static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1515{
1516 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1517 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1518 struct ath_vif *avp = (void *)vif->drv_priv;
1519
2e5ef459
RM
1520 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1521 return;
1522
4f5ef75b
RM
1523 /* Reconfigure bss info */
1524 if (avp->primary_sta_vif && !bss_conf->assoc) {
d2182b69 1525 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
99e4d43a
RM
1526 common->curaid, common->curbssid);
1527 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
1528 avp->primary_sta_vif = false;
1529 memset(common->curbssid, 0, ETH_ALEN);
1530 common->curaid = 0;
1531 }
1532
1533 ieee80211_iterate_active_interfaces_atomic(
1534 sc->hw, ath9k_bss_iter, sc);
1535
1536 /*
1537 * None of station vifs are associated.
1538 * Clear bssid & aid
1539 */
2e5ef459 1540 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 1541 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
1542 /* Stop ANI */
1543 sc->sc_flags &= ~SC_OP_ANI_RUN;
1544 del_timer_sync(&common->ani.timer);
01e18918 1545 del_timer_sync(&sc->rx_poll_timer);
d2c71c20 1546 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 1547 }
4f5ef75b 1548}
f078f209 1549
8feceb67
VT
1550static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1551 struct ieee80211_vif *vif,
1552 struct ieee80211_bss_conf *bss_conf,
1553 u32 changed)
1554{
9ac58615 1555 struct ath_softc *sc = hw->priv;
2d0ddec5 1556 struct ath_hw *ah = sc->sc_ah;
1510718d 1557 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1558 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1559 int slottime;
f078f209 1560
96f372c9 1561 ath9k_ps_wakeup(sc);
141b38b6
S
1562 mutex_lock(&sc->mutex);
1563
9f61903c 1564 if (changed & BSS_CHANGED_ASSOC) {
4f5ef75b 1565 ath9k_config_bss(sc, vif);
2d0ddec5 1566
d2182b69 1567 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
226afe68 1568 common->curbssid, common->curaid);
c6089ccc 1569 }
2d0ddec5 1570
2e5ef459
RM
1571 if (changed & BSS_CHANGED_IBSS) {
1572 /* There can be only one vif available */
1573 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1574 common->curaid = bss_conf->aid;
1575 ath9k_hw_write_associd(sc->sc_ah);
1576
1577 if (bss_conf->ibss_joined) {
1578 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1579
1580 if (!common->disable_ani) {
1581 sc->sc_flags |= SC_OP_ANI_RUN;
1582 ath_start_ani(common);
1583 }
1584
2e5ef459
RM
1585 } else {
1586 sc->sc_flags &= ~SC_OP_ANI_RUN;
1587 del_timer_sync(&common->ani.timer);
01e18918 1588 del_timer_sync(&sc->rx_poll_timer);
2e5ef459
RM
1589 }
1590 }
1591
ed2578cd
RM
1592 /*
1593 * In case of AP mode, the HW TSF has to be reset
1594 * when the beacon interval changes.
1595 */
1596 if ((changed & BSS_CHANGED_BEACON_INT) &&
1597 (vif->type == NL80211_IFTYPE_AP))
1598 sc->sc_flags |= SC_OP_TSF_RESET;
1599
1600 /* Configure beaconing (AP, IBSS, MESH) */
1601 if (ath9k_uses_beacons(vif->type) &&
1602 ((changed & BSS_CHANGED_BEACON) ||
1603 (changed & BSS_CHANGED_BEACON_ENABLED) ||
1604 (changed & BSS_CHANGED_BEACON_INT))) {
014cf3bb 1605 ath9k_set_beaconing_status(sc, false);
ed2578cd
RM
1606 if (bss_conf->enable_beacon)
1607 ath_beacon_alloc(sc, vif);
1608 else
1609 avp->is_bslot_active = false;
1610 ath_beacon_config(sc, vif);
014cf3bb 1611 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
1612 }
1613
1614 if (changed & BSS_CHANGED_ERP_SLOT) {
1615 if (bss_conf->use_short_slot)
1616 slottime = 9;
1617 else
1618 slottime = 20;
1619 if (vif->type == NL80211_IFTYPE_AP) {
1620 /*
1621 * Defer update, so that connected stations can adjust
1622 * their settings at the same time.
1623 * See beacon.c for more details
1624 */
1625 sc->beacon.slottime = slottime;
1626 sc->beacon.updateslot = UPDATE;
1627 } else {
1628 ah->slottime = slottime;
1629 ath9k_hw_init_global_settings(ah);
1630 }
2d0ddec5
JB
1631 }
1632
141b38b6 1633 mutex_unlock(&sc->mutex);
96f372c9 1634 ath9k_ps_restore(sc);
8feceb67 1635}
f078f209 1636
37a41b4a 1637static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1638{
9ac58615 1639 struct ath_softc *sc = hw->priv;
8feceb67 1640 u64 tsf;
f078f209 1641
141b38b6 1642 mutex_lock(&sc->mutex);
9abbfb27 1643 ath9k_ps_wakeup(sc);
141b38b6 1644 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1645 ath9k_ps_restore(sc);
141b38b6 1646 mutex_unlock(&sc->mutex);
f078f209 1647
8feceb67
VT
1648 return tsf;
1649}
f078f209 1650
37a41b4a
EP
1651static void ath9k_set_tsf(struct ieee80211_hw *hw,
1652 struct ieee80211_vif *vif,
1653 u64 tsf)
3b5d665b 1654{
9ac58615 1655 struct ath_softc *sc = hw->priv;
3b5d665b 1656
141b38b6 1657 mutex_lock(&sc->mutex);
9abbfb27 1658 ath9k_ps_wakeup(sc);
141b38b6 1659 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1660 ath9k_ps_restore(sc);
141b38b6 1661 mutex_unlock(&sc->mutex);
3b5d665b
AF
1662}
1663
37a41b4a 1664static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1665{
9ac58615 1666 struct ath_softc *sc = hw->priv;
c83be688 1667
141b38b6 1668 mutex_lock(&sc->mutex);
21526d57
LR
1669
1670 ath9k_ps_wakeup(sc);
141b38b6 1671 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1672 ath9k_ps_restore(sc);
1673
141b38b6 1674 mutex_unlock(&sc->mutex);
8feceb67 1675}
f078f209 1676
8feceb67 1677static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1678 struct ieee80211_vif *vif,
141b38b6
S
1679 enum ieee80211_ampdu_mlme_action action,
1680 struct ieee80211_sta *sta,
0b01f030 1681 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1682{
9ac58615 1683 struct ath_softc *sc = hw->priv;
8feceb67 1684 int ret = 0;
f078f209 1685
85ad181e
JB
1686 local_bh_disable();
1687
8feceb67
VT
1688 switch (action) {
1689 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1690 break;
1691 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1692 break;
1693 case IEEE80211_AMPDU_TX_START:
8b685ba9 1694 ath9k_ps_wakeup(sc);
231c3a1f
FF
1695 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1696 if (!ret)
1697 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1698 ath9k_ps_restore(sc);
8feceb67
VT
1699 break;
1700 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1701 ath9k_ps_wakeup(sc);
f83da965 1702 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1703 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1704 ath9k_ps_restore(sc);
8feceb67 1705 break;
b1720231 1706 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1707 ath9k_ps_wakeup(sc);
8469cdef 1708 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1709 ath9k_ps_restore(sc);
8469cdef 1710 break;
8feceb67 1711 default:
3800276a 1712 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1713 }
1714
85ad181e
JB
1715 local_bh_enable();
1716
8feceb67 1717 return ret;
f078f209
LR
1718}
1719
62dad5b0
BP
1720static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1721 struct survey_info *survey)
1722{
9ac58615 1723 struct ath_softc *sc = hw->priv;
3430098a 1724 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1725 struct ieee80211_supported_band *sband;
3430098a
FF
1726 struct ieee80211_channel *chan;
1727 unsigned long flags;
1728 int pos;
1729
1730 spin_lock_irqsave(&common->cc_lock, flags);
1731 if (idx == 0)
1732 ath_update_survey_stats(sc);
39162dbe
FF
1733
1734 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1735 if (sband && idx >= sband->n_channels) {
1736 idx -= sband->n_channels;
1737 sband = NULL;
1738 }
62dad5b0 1739
39162dbe
FF
1740 if (!sband)
1741 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1742
3430098a
FF
1743 if (!sband || idx >= sband->n_channels) {
1744 spin_unlock_irqrestore(&common->cc_lock, flags);
1745 return -ENOENT;
4f1a5a4b 1746 }
62dad5b0 1747
3430098a
FF
1748 chan = &sband->channels[idx];
1749 pos = chan->hw_value;
1750 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1751 survey->channel = chan;
1752 spin_unlock_irqrestore(&common->cc_lock, flags);
1753
62dad5b0
BP
1754 return 0;
1755}
1756
e239d859
FF
1757static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1758{
9ac58615 1759 struct ath_softc *sc = hw->priv;
e239d859
FF
1760 struct ath_hw *ah = sc->sc_ah;
1761
1762 mutex_lock(&sc->mutex);
1763 ah->coverage_class = coverage_class;
8b2a3827
MSS
1764
1765 ath9k_ps_wakeup(sc);
e239d859 1766 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
1767 ath9k_ps_restore(sc);
1768
e239d859
FF
1769 mutex_unlock(&sc->mutex);
1770}
1771
69081624
VT
1772static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1773{
69081624 1774 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
1775 struct ath_hw *ah = sc->sc_ah;
1776 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
1777 int timeout = 200; /* ms */
1778 int i, j;
2f6fc351 1779 bool drain_txq;
69081624
VT
1780
1781 mutex_lock(&sc->mutex);
69081624
VT
1782 cancel_delayed_work_sync(&sc->tx_complete_work);
1783
6a6b3f3e 1784 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1785 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
1786 mutex_unlock(&sc->mutex);
1787 return;
1788 }
1789
99aa55b6 1790 if (sc->sc_flags & SC_OP_INVALID) {
d2182b69 1791 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
1792 mutex_unlock(&sc->mutex);
1793 return;
1794 }
1795
86271e46 1796 for (j = 0; j < timeout; j++) {
108697c4 1797 bool npend = false;
86271e46
FF
1798
1799 if (j)
1800 usleep_range(1000, 2000);
69081624 1801
86271e46
FF
1802 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1803 if (!ATH_TXQ_SETUP(sc, i))
1804 continue;
1805
108697c4
MSS
1806 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1807
1808 if (npend)
1809 break;
69081624 1810 }
86271e46
FF
1811
1812 if (!npend)
9df0d6a2 1813 break;
69081624
VT
1814 }
1815
9df0d6a2
FF
1816 if (drop) {
1817 ath9k_ps_wakeup(sc);
1818 spin_lock_bh(&sc->sc_pcu_lock);
1819 drain_txq = ath_drain_all_txq(sc, false);
1820 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1821
9df0d6a2
FF
1822 if (!drain_txq)
1823 ath_reset(sc, false);
9adcf440 1824
9df0d6a2
FF
1825 ath9k_ps_restore(sc);
1826 ieee80211_wake_queues(hw);
1827 }
d78f4b3e 1828
69081624
VT
1829 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1830 mutex_unlock(&sc->mutex);
1831}
1832
15b91e83
VN
1833static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1834{
1835 struct ath_softc *sc = hw->priv;
1836 int i;
1837
1838 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1839 if (!ATH_TXQ_SETUP(sc, i))
1840 continue;
1841
1842 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1843 return true;
1844 }
1845 return false;
1846}
1847
5595f119 1848static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
1849{
1850 struct ath_softc *sc = hw->priv;
1851 struct ath_hw *ah = sc->sc_ah;
1852 struct ieee80211_vif *vif;
1853 struct ath_vif *avp;
1854 struct ath_buf *bf;
1855 struct ath_tx_status ts;
4286df60 1856 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
1857 int status;
1858
1859 vif = sc->beacon.bslot[0];
1860 if (!vif)
1861 return 0;
1862
1863 avp = (void *)vif->drv_priv;
1864 if (!avp->is_bslot_active)
1865 return 0;
1866
4286df60 1867 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
1868 tasklet_disable(&sc->bcon_tasklet);
1869
1870 bf = avp->av_bcbuf;
1871 if (!bf || !bf->bf_mpdu)
1872 goto skip;
1873
1874 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1875 if (status == -EINPROGRESS)
1876 goto skip;
1877
1878 sc->beacon.tx_processed = true;
1879 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1880
1881skip:
1882 tasklet_enable(&sc->bcon_tasklet);
1883 }
1884
1885 return sc->beacon.tx_last;
1886}
1887
52c94f41
MSS
1888static int ath9k_get_stats(struct ieee80211_hw *hw,
1889 struct ieee80211_low_level_stats *stats)
1890{
1891 struct ath_softc *sc = hw->priv;
1892 struct ath_hw *ah = sc->sc_ah;
1893 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1894
1895 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1896 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1897 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1898 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1899 return 0;
1900}
1901
43c35284
FF
1902static u32 fill_chainmask(u32 cap, u32 new)
1903{
1904 u32 filled = 0;
1905 int i;
1906
1907 for (i = 0; cap && new; i++, cap >>= 1) {
1908 if (!(cap & BIT(0)))
1909 continue;
1910
1911 if (new & BIT(0))
1912 filled |= BIT(i);
1913
1914 new >>= 1;
1915 }
1916
1917 return filled;
1918}
1919
1920static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1921{
1922 struct ath_softc *sc = hw->priv;
1923 struct ath_hw *ah = sc->sc_ah;
1924
1925 if (!rx_ant || !tx_ant)
1926 return -EINVAL;
1927
1928 sc->ant_rx = rx_ant;
1929 sc->ant_tx = tx_ant;
1930
1931 if (ah->caps.rx_chainmask == 1)
1932 return 0;
1933
1934 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1935 if (AR_SREV_9100(ah))
1936 ah->rxchainmask = 0x7;
1937 else
1938 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1939
1940 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1941 ath9k_reload_chainmask_settings(sc);
1942
1943 return 0;
1944}
1945
1946static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1947{
1948 struct ath_softc *sc = hw->priv;
1949
1950 *tx_ant = sc->ant_tx;
1951 *rx_ant = sc->ant_rx;
1952 return 0;
1953}
1954
b90bd9d1
BG
1955#ifdef CONFIG_ATH9K_DEBUGFS
1956
1957/* Ethtool support for get-stats */
1958
1959#define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1960static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1961 "tx_pkts_nic",
1962 "tx_bytes_nic",
1963 "rx_pkts_nic",
1964 "rx_bytes_nic",
1965 AMKSTR(d_tx_pkts),
1966 AMKSTR(d_tx_bytes),
1967 AMKSTR(d_tx_mpdus_queued),
1968 AMKSTR(d_tx_mpdus_completed),
1969 AMKSTR(d_tx_mpdu_xretries),
1970 AMKSTR(d_tx_aggregates),
1971 AMKSTR(d_tx_ampdus_queued_hw),
1972 AMKSTR(d_tx_ampdus_queued_sw),
1973 AMKSTR(d_tx_ampdus_completed),
1974 AMKSTR(d_tx_ampdu_retries),
1975 AMKSTR(d_tx_ampdu_xretries),
1976 AMKSTR(d_tx_fifo_underrun),
1977 AMKSTR(d_tx_op_exceeded),
1978 AMKSTR(d_tx_timer_expiry),
1979 AMKSTR(d_tx_desc_cfg_err),
1980 AMKSTR(d_tx_data_underrun),
1981 AMKSTR(d_tx_delim_underrun),
1982
1983 "d_rx_decrypt_crc_err",
1984 "d_rx_phy_err",
1985 "d_rx_mic_err",
1986 "d_rx_pre_delim_crc_err",
1987 "d_rx_post_delim_crc_err",
1988 "d_rx_decrypt_busy_err",
1989
1990 "d_rx_phyerr_radar",
1991 "d_rx_phyerr_ofdm_timing",
1992 "d_rx_phyerr_cck_timing",
1993
1994};
1995#define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1996
1997static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1998 struct ieee80211_vif *vif,
1999 u32 sset, u8 *data)
2000{
2001 if (sset == ETH_SS_STATS)
2002 memcpy(data, *ath9k_gstrings_stats,
2003 sizeof(ath9k_gstrings_stats));
2004}
2005
2006static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
2007 struct ieee80211_vif *vif, int sset)
2008{
2009 if (sset == ETH_SS_STATS)
2010 return ATH9K_SSTATS_LEN;
2011 return 0;
2012}
2013
2014#define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
2015#define AWDATA(elem) \
2016 do { \
2017 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
2018 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
2019 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
2020 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
2021 } while (0)
2022
2023#define AWDATA_RX(elem) \
2024 do { \
2025 data[i++] = sc->debug.stats.rxstats.elem; \
2026 } while (0)
2027
2028static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2029 struct ieee80211_vif *vif,
2030 struct ethtool_stats *stats, u64 *data)
2031{
2032 struct ath_softc *sc = hw->priv;
2033 int i = 0;
2034
2035 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2036 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2037 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2038 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2039 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2040 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2041 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2042 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2043 AWDATA_RX(rx_pkts_all);
2044 AWDATA_RX(rx_bytes_all);
2045
2046 AWDATA(tx_pkts_all);
2047 AWDATA(tx_bytes_all);
2048 AWDATA(queued);
2049 AWDATA(completed);
2050 AWDATA(xretries);
2051 AWDATA(a_aggr);
2052 AWDATA(a_queued_hw);
2053 AWDATA(a_queued_sw);
2054 AWDATA(a_completed);
2055 AWDATA(a_retries);
2056 AWDATA(a_xretries);
2057 AWDATA(fifo_underrun);
2058 AWDATA(xtxop);
2059 AWDATA(timer_exp);
2060 AWDATA(desc_cfg_err);
2061 AWDATA(data_underrun);
2062 AWDATA(delim_underrun);
2063
2064 AWDATA_RX(decrypt_crc_err);
2065 AWDATA_RX(phy_err);
2066 AWDATA_RX(mic_err);
2067 AWDATA_RX(pre_delim_crc_err);
2068 AWDATA_RX(post_delim_crc_err);
2069 AWDATA_RX(decrypt_busy_err);
2070
2071 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2072 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2073 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2074
2075 WARN_ON(i != ATH9K_SSTATS_LEN);
2076}
2077
2078/* End of ethtool get-stats functions */
2079
2080#endif
2081
2082
6baff7f9 2083struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2084 .tx = ath9k_tx,
2085 .start = ath9k_start,
2086 .stop = ath9k_stop,
2087 .add_interface = ath9k_add_interface,
6b3b991d 2088 .change_interface = ath9k_change_interface,
8feceb67
VT
2089 .remove_interface = ath9k_remove_interface,
2090 .config = ath9k_config,
8feceb67 2091 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2092 .sta_add = ath9k_sta_add,
2093 .sta_remove = ath9k_sta_remove,
5519541d 2094 .sta_notify = ath9k_sta_notify,
8feceb67 2095 .conf_tx = ath9k_conf_tx,
8feceb67 2096 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2097 .set_key = ath9k_set_key,
8feceb67 2098 .get_tsf = ath9k_get_tsf,
3b5d665b 2099 .set_tsf = ath9k_set_tsf,
8feceb67 2100 .reset_tsf = ath9k_reset_tsf,
4233df6b 2101 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2102 .get_survey = ath9k_get_survey,
3b319aae 2103 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2104 .set_coverage_class = ath9k_set_coverage_class,
69081624 2105 .flush = ath9k_flush,
15b91e83 2106 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2107 .tx_last_beacon = ath9k_tx_last_beacon,
2108 .get_stats = ath9k_get_stats,
43c35284
FF
2109 .set_antenna = ath9k_set_antenna,
2110 .get_antenna = ath9k_get_antenna,
b90bd9d1
BG
2111
2112#ifdef CONFIG_ATH9K_DEBUGFS
2113 .get_et_sset_count = ath9k_get_et_sset_count,
2114 .get_et_stats = ath9k_get_et_stats,
2115 .get_et_strings = ath9k_get_et_strings,
2116#endif
8feceb67 2117};