mwifiex: fix invalid access of PCIe RxBD ring buffer descriptor
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
6dcc3444
SM
22static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
313eb87f 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S
26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
69081624
VT
60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61{
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
69081624
VT
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71}
72
6d79cb4c 73static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
74{
75 unsigned long flags;
76 bool ret;
77
9ecdef4b
LR
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
81
82 return ret;
83}
84
a91d75ae
LR
85void ath9k_ps_wakeup(struct ath_softc *sc)
86{
898c914a 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 88 unsigned long flags;
fbb078fc 89 enum ath9k_power_mode power_mode;
a91d75ae
LR
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
fbb078fc 95 power_mode = sc->sc_ah->power_mode;
9ecdef4b 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 97
898c914a
FF
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
fbb078fc
FF
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
108 spin_unlock(&common->cc_lock);
109 }
898c914a 110
a91d75ae
LR
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113}
114
115void ath9k_ps_restore(struct ath_softc *sc)
116{
898c914a 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 118 enum ath9k_power_mode mode;
a91d75ae 119 unsigned long flags;
ad128860 120 bool reset;
a91d75ae
LR
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
ad128860
SM
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 129 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
c6c539f0 136 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
ad128860 139 } else {
c6c539f0 140 goto unlock;
ad128860 141 }
c6c539f0
FF
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
1a8f0d39 147 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151}
152
9adcf440 153static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 154{
5ee08656
FF
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 158 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 159
bf52592f 160#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
bf52592f 163#endif
9adcf440 164}
5ee08656 165
9adcf440
FF
166static void ath_cancel_work(struct ath_softc *sc)
167{
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170}
3cbb5dd7 171
af68abad
SM
172static void ath_restart_work(struct ath_softc *sc)
173{
af68abad
SM
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
c12b6021
GJ
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
af68abad
SM
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
da0d45f7 182 ath_start_ani(sc);
af68abad
SM
183}
184
9ebea382 185static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF
186{
187 struct ath_hw *ah = sc->sc_ah;
ceea2a51 188 bool ret = true;
6a6733f2 189
9adcf440 190 ieee80211_stop_queues(sc->hw);
5e848f78 191
9adcf440 192 sc->hw_busy_count = 0;
da0d45f7 193 ath_stop_ani(sc);
01e18918 194 del_timer_sync(&sc->rx_poll_timer);
ff37e337 195
9adcf440
FF
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
8b3f4616 198
1381559b 199 if (!ath_drain_all_txq(sc))
9adcf440 200 ret = false;
c0d7c7af 201
0a62acb1 202 if (!ath_stoprecv(sc))
ceea2a51
FF
203 ret = false;
204
9adcf440
FF
205 return ret;
206}
ff37e337 207
9adcf440
FF
208static bool ath_complete_reset(struct ath_softc *sc, bool start)
209{
210 struct ath_hw *ah = sc->sc_ah;
211 struct ath_common *common = ath9k_hw_common(ah);
196fb860 212 unsigned long flags;
c0d7c7af 213
c0d7c7af 214 if (ath_startrecv(sc) != 0) {
3800276a 215 ath_err(common, "Unable to restart recv logic\n");
9adcf440 216 return false;
c0d7c7af
LR
217 }
218
5048e8c3
RM
219 ath9k_cmn_update_txpow(ah, sc->curtxpow,
220 sc->config.txpowlimit, &sc->curtxpow);
b74713d0
SM
221
222 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
72d874c6 223 ath9k_hw_set_interrupts(ah);
b037b693 224 ath9k_hw_enable_interrupts(ah);
3989279c 225
4cb54fa3 226 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
196fb860
SM
227 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
228 goto work;
229
ef4ad633 230 ath9k_set_beacon(sc);
196fb860
SM
231
232 if (ah->opmode == NL80211_IFTYPE_STATION &&
233 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
234 spin_lock_irqsave(&sc->sc_pm_lock, flags);
235 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
236 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
237 }
238 work:
af68abad 239 ath_restart_work(sc);
5ee08656
FF
240 }
241
8da07830
SM
242 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
243 ath_ant_comb_update(sc);
43c35284 244
9adcf440
FF
245 ieee80211_wake_queues(sc->hw);
246
247 return true;
248}
249
1381559b 250static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF
251{
252 struct ath_hw *ah = sc->sc_ah;
253 struct ath_common *common = ath9k_hw_common(ah);
254 struct ath9k_hw_cal_data *caldata = NULL;
255 bool fastcc = true;
9adcf440
FF
256 int r;
257
258 __ath_cancel_work(sc);
259
4668cce5 260 tasklet_disable(&sc->intr_tq);
9adcf440 261 spin_lock_bh(&sc->sc_pcu_lock);
92460412 262
4cb54fa3 263 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF
264 fastcc = false;
265 caldata = &sc->caldata;
266 }
267
268 if (!hchan) {
269 fastcc = false;
9adcf440
FF
270 hchan = ah->curchan;
271 }
272
9ebea382 273 if (!ath_prepare_reset(sc))
9adcf440
FF
274 fastcc = false;
275
d2182b69 276 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 277 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
278
279 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
280 if (r) {
281 ath_err(common,
282 "Unable to reset channel, reset status %d\n", r);
283 goto out;
284 }
285
e82cb03f
RM
286 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
287 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
288 ath9k_mci_set_txpower(sc, true, false);
289
9adcf440
FF
290 if (!ath_complete_reset(sc, true))
291 r = -EIO;
292
293out:
6a6733f2 294 spin_unlock_bh(&sc->sc_pcu_lock);
4668cce5
FF
295 tasklet_enable(&sc->intr_tq);
296
9adcf440
FF
297 return r;
298}
299
300
301/*
302 * Set/change channels. If the channel is really being changed, it's done
303 * by reseting the chip. To accomplish this we must first cleanup any pending
304 * DMA, then restart stuff.
305*/
306static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
307 struct ath9k_channel *hchan)
308{
309 int r;
310
781b14a3 311 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
9adcf440
FF
312 return -EIO;
313
1381559b 314 r = ath_reset_internal(sc, hchan);
6a6733f2 315
3989279c 316 return r;
ff37e337
S
317}
318
7e1e3864
BG
319static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
320 struct ieee80211_vif *vif)
ff37e337
S
321{
322 struct ath_node *an;
313eb87f 323 u8 density;
ff37e337
S
324 an = (struct ath_node *)sta->drv_priv;
325
a145daf7 326 an->sc = sc;
7f010c93 327 an->sta = sta;
7e1e3864 328 an->vif = vif;
3d4e20f2 329
a4d6367f 330 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 331 ath_tx_node_init(sc, an);
9e98ac65 332 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc 333 sta->ht_cap.ampdu_factor);
313eb87f
SE
334 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
335 an->mpdudensity = density;
87792efc 336 }
ff37e337
S
337}
338
339static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
340{
341 struct ath_node *an = (struct ath_node *)sta->drv_priv;
342
a4d6367f 343 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S
344 ath_tx_node_cleanup(sc, an);
345}
346
55624204 347void ath9k_tasklet(unsigned long data)
ff37e337
S
348{
349 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 350 struct ath_hw *ah = sc->sc_ah;
c46917bb 351 struct ath_common *common = ath9k_hw_common(ah);
124b979b 352 enum ath_reset_type type;
07c15a3f 353 unsigned long flags;
17d7904d 354 u32 status = sc->intrstatus;
b5c80475 355 u32 rxmask;
ff37e337 356
e3927007
FF
357 ath9k_ps_wakeup(sc);
358 spin_lock(&sc->sc_pcu_lock);
359
a4d86d95
RM
360 if ((status & ATH9K_INT_FATAL) ||
361 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
362
363 if (status & ATH9K_INT_FATAL)
364 type = RESET_TYPE_FATAL_INT;
365 else
366 type = RESET_TYPE_BB_WATCHDOG;
367
124b979b 368 ath9k_queue_reset(sc, type);
e3927007 369 goto out;
063d8be3 370 }
ff37e337 371
07c15a3f 372 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM
373 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
374 /*
375 * TSF sync does not look correct; remain awake to sync with
376 * the next Beacon.
377 */
d2182b69 378 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 379 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 380 }
07c15a3f 381 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 382
b5c80475
FF
383 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
384 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
385 ATH9K_INT_RXORN);
386 else
387 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
388
389 if (status & rxmask) {
b5c80475
FF
390 /* Check for high priority Rx first */
391 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
392 (status & ATH9K_INT_RXHP))
393 ath_rx_tasklet(sc, 0, true);
394
395 ath_rx_tasklet(sc, 0, false);
ff37e337
S
396 }
397
e5003249
VT
398 if (status & ATH9K_INT_TX) {
399 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
400 ath_tx_edma_tasklet(sc);
401 else
402 ath_tx_tasklet(sc);
403 }
063d8be3 404
56ca0dba 405 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 406
e3927007 407out:
ff37e337 408 /* re-enable hardware interrupt */
4df3071e 409 ath9k_hw_enable_interrupts(ah);
6a6733f2 410
52671e43 411 spin_unlock(&sc->sc_pcu_lock);
153e080d 412 ath9k_ps_restore(sc);
ff37e337
S
413}
414
6baff7f9 415irqreturn_t ath_isr(int irq, void *dev)
ff37e337 416{
063d8be3
S
417#define SCHED_INTR ( \
418 ATH9K_INT_FATAL | \
a4d86d95 419 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
420 ATH9K_INT_RXORN | \
421 ATH9K_INT_RXEOL | \
422 ATH9K_INT_RX | \
b5c80475
FF
423 ATH9K_INT_RXLP | \
424 ATH9K_INT_RXHP | \
063d8be3
S
425 ATH9K_INT_TX | \
426 ATH9K_INT_BMISS | \
427 ATH9K_INT_CST | \
ebb8e1d7 428 ATH9K_INT_TSFOOR | \
40dc5392
MSS
429 ATH9K_INT_GENTIMER | \
430 ATH9K_INT_MCI)
063d8be3 431
ff37e337 432 struct ath_softc *sc = dev;
cbe61d8a 433 struct ath_hw *ah = sc->sc_ah;
b5bfc568 434 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
435 enum ath9k_int status;
436 bool sched = false;
437
063d8be3
S
438 /*
439 * The hardware is not ready/present, don't
440 * touch anything. Note this can happen early
441 * on if the IRQ is shared.
442 */
781b14a3 443 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
063d8be3 444 return IRQ_NONE;
ff37e337 445
063d8be3
S
446 /* shared irq, not for us */
447
153e080d 448 if (!ath9k_hw_intrpend(ah))
063d8be3 449 return IRQ_NONE;
063d8be3 450
f41a9b3b
FF
451 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
452 ath9k_hw_kill_interrupts(ah);
b74713d0 453 return IRQ_HANDLED;
f41a9b3b 454 }
b74713d0 455
063d8be3
S
456 /*
457 * Figure out the reason(s) for the interrupt. Note
458 * that the hal returns a pseudo-ISR that may include
459 * bits we haven't explicitly enabled so we mask the
460 * value to insure we only process bits we requested.
461 */
462 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 463 status &= ah->imask; /* discard unasked-for bits */
ff37e337 464
063d8be3
S
465 /*
466 * If there are no status bits set, then this interrupt was not
467 * for me (should have been caught above).
468 */
153e080d 469 if (!status)
063d8be3 470 return IRQ_NONE;
ff37e337 471
063d8be3
S
472 /* Cache the status */
473 sc->intrstatus = status;
474
475 if (status & SCHED_INTR)
476 sched = true;
477
478 /*
479 * If a FATAL or RXORN interrupt is received, we have to reset the
480 * chip immediately.
481 */
b5c80475
FF
482 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
483 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
484 goto chip_reset;
485
08578b8f
LR
486 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
487 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
488
489 spin_lock(&common->cc_lock);
490 ath_hw_cycle_counters_update(common);
08578b8f 491 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
492 spin_unlock(&common->cc_lock);
493
08578b8f
LR
494 goto chip_reset;
495 }
ca90ef44
RM
496#ifdef CONFIG_PM_SLEEP
497 if (status & ATH9K_INT_BMISS) {
498 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
499 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
500 atomic_inc(&sc->wow_got_bmiss_intr);
501 atomic_dec(&sc->wow_sleep_proc_intr);
502 }
503 }
504#endif
063d8be3
S
505 if (status & ATH9K_INT_SWBA)
506 tasklet_schedule(&sc->bcon_tasklet);
507
508 if (status & ATH9K_INT_TXURN)
509 ath9k_hw_updatetxtriglevel(ah, true);
510
0682c9b5
RM
511 if (status & ATH9K_INT_RXEOL) {
512 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 513 ath9k_hw_set_interrupts(ah);
b5c80475
FF
514 }
515
153e080d
VT
516 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
517 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
518 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
519 goto chip_reset;
063d8be3
S
520 /* Clear RxAbort bit so that we can
521 * receive frames */
9ecdef4b 522 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 523 spin_lock(&sc->sc_pm_lock);
153e080d 524 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 525 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 526 spin_unlock(&sc->sc_pm_lock);
ff37e337 527 }
063d8be3
S
528
529chip_reset:
ff37e337 530
817e11de
S
531 ath_debug_stat_interrupt(sc, status);
532
ff37e337 533 if (sched) {
4df3071e
FF
534 /* turn off every interrupt */
535 ath9k_hw_disable_interrupts(ah);
ff37e337
S
536 tasklet_schedule(&sc->intr_tq);
537 }
538
539 return IRQ_HANDLED;
063d8be3
S
540
541#undef SCHED_INTR
ff37e337
S
542}
543
1381559b 544static int ath_reset(struct ath_softc *sc)
ff37e337 545{
1381559b 546 int i, r;
ff37e337 547
783cd01e 548 ath9k_ps_wakeup(sc);
6a6733f2 549
1381559b 550 r = ath_reset_internal(sc, NULL);
ff37e337 551
1381559b
FF
552 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
553 if (!ATH_TXQ_SETUP(sc, i))
554 continue;
555
556 spin_lock_bh(&sc->tx.txq[i].axq_lock);
557 ath_txq_schedule(sc, &sc->tx.txq[i]);
558 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
559 }
560
783cd01e 561 ath9k_ps_restore(sc);
2ab81d4a 562
ae8d2858 563 return r;
ff37e337
S
564}
565
124b979b
RM
566void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
567{
568#ifdef CONFIG_ATH9K_DEBUGFS
569 RESET_STAT_INC(sc, type);
570#endif
571 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
572 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
573}
574
236de514
FF
575void ath_reset_work(struct work_struct *work)
576{
577 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
578
1381559b 579 ath_reset(sc);
236de514
FF
580}
581
ff37e337
S
582/**********************/
583/* mac80211 callbacks */
584/**********************/
585
8feceb67 586static int ath9k_start(struct ieee80211_hw *hw)
f078f209 587{
9ac58615 588 struct ath_softc *sc = hw->priv;
af03abec 589 struct ath_hw *ah = sc->sc_ah;
c46917bb 590 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 591 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 592 struct ath9k_channel *init_channel;
82880a7c 593 int r;
f078f209 594
d2182b69 595 ath_dbg(common, CONFIG,
226afe68
JP
596 "Starting driver with initial channel: %d MHz\n",
597 curchan->center_freq);
f078f209 598
f62d816f 599 ath9k_ps_wakeup(sc);
141b38b6
S
600 mutex_lock(&sc->mutex);
601
c344c9cb 602 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
603
604 /* Reset SERDES registers */
84c87dc8 605 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
606
607 /*
608 * The basic interface to setting the hardware in a good
609 * state is ``reset''. On return the hardware is known to
610 * be powered up and with interrupts disabled. This must
611 * be followed by initialization of the appropriate bits
612 * and then setup of the interrupt mask.
613 */
4bdd1e97 614 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
615
616 atomic_set(&ah->intr_ref_cnt, -1);
617
20bd2a09 618 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 619 if (r) {
3800276a
JP
620 ath_err(common,
621 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
622 r, curchan->center_freq);
ceb26a60 623 ah->reset_power_on = false;
ff37e337 624 }
ff37e337 625
ff37e337 626 /* Setup our intr mask. */
b5c80475
FF
627 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
628 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
629 ATH9K_INT_GLOBAL;
630
631 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
632 ah->imask |= ATH9K_INT_RXHP |
633 ATH9K_INT_RXLP |
634 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
635 else
636 ah->imask |= ATH9K_INT_RX;
ff37e337 637
364734fa 638 ah->imask |= ATH9K_INT_GTT;
ff37e337 639
af03abec 640 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 641 ah->imask |= ATH9K_INT_CST;
ff37e337 642
e270e776 643 ath_mci_enable(sc);
40dc5392 644
781b14a3 645 clear_bit(SC_OP_INVALID, &sc->sc_flags);
5f841b41 646 sc->sc_ah->is_monitoring = false;
ff37e337 647
ceb26a60
FF
648 if (!ath_complete_reset(sc, false))
649 ah->reset_power_on = false;
ff37e337 650
c0c11741
FF
651 if (ah->led_pin >= 0) {
652 ath9k_hw_cfg_output(ah, ah->led_pin,
653 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
654 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
655 }
656
657 /*
658 * Reset key cache to sane defaults (all entries cleared) instead of
659 * semi-random values after suspend/resume.
660 */
661 ath9k_cmn_init_crypto(sc->sc_ah);
662
9adcf440 663 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 664
141b38b6
S
665 mutex_unlock(&sc->mutex);
666
f62d816f
FF
667 ath9k_ps_restore(sc);
668
ceb26a60 669 return 0;
f078f209
LR
670}
671
36323f81
TH
672static void ath9k_tx(struct ieee80211_hw *hw,
673 struct ieee80211_tx_control *control,
674 struct sk_buff *skb)
f078f209 675{
9ac58615 676 struct ath_softc *sc = hw->priv;
c46917bb 677 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 678 struct ath_tx_control txctl;
1bc14880 679 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 680 unsigned long flags;
528f0c6b 681
96148326 682 if (sc->ps_enabled) {
dc8c4585
JM
683 /*
684 * mac80211 does not set PM field for normal data frames, so we
685 * need to update that based on the current PS mode.
686 */
687 if (ieee80211_is_data(hdr->frame_control) &&
688 !ieee80211_is_nullfunc(hdr->frame_control) &&
689 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 690 ath_dbg(common, PS,
226afe68 691 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
692 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
693 }
694 }
695
ad128860 696 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
697 /*
698 * We are using PS-Poll and mac80211 can request TX while in
699 * power save mode. Need to wake up hardware for the TX to be
700 * completed and if needed, also for RX of buffered frames.
701 */
9a23f9ca 702 ath9k_ps_wakeup(sc);
07c15a3f 703 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT
704 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
705 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 706 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 707 ath_dbg(common, PS,
226afe68 708 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 709 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 710 } else {
d2182b69 711 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 712 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
713 }
714 /*
715 * The actual restore operation will happen only after
ad128860 716 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
717 * the ps_usecount here.
718 */
07c15a3f 719 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM
720 ath9k_ps_restore(sc);
721 }
722
ad128860
SM
723 /*
724 * Cannot tx while the hardware is in full sleep, it first needs a full
725 * chip reset to recover from that
726 */
727 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
728 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
729 goto exit;
730 }
731
528f0c6b 732 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 733 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 734 txctl.sta = control->sta;
528f0c6b 735
d2182b69 736 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 737
c52f33d0 738 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 739 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 740 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 741 goto exit;
8feceb67
VT
742 }
743
7bb45683 744 return;
528f0c6b 745exit:
249ee722 746 ieee80211_free_txskb(hw, skb);
f078f209
LR
747}
748
8feceb67 749static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 750{
9ac58615 751 struct ath_softc *sc = hw->priv;
af03abec 752 struct ath_hw *ah = sc->sc_ah;
c46917bb 753 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 754 bool prev_idle;
f078f209 755
4c483817
S
756 mutex_lock(&sc->mutex);
757
9adcf440 758 ath_cancel_work(sc);
01e18918 759 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 760
781b14a3 761 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 762 ath_dbg(common, ANY, "Device not present\n");
4c483817 763 mutex_unlock(&sc->mutex);
9c84b797
S
764 return;
765 }
8feceb67 766
3867cf6a
S
767 /* Ensure HW is awake when we try to shut it down. */
768 ath9k_ps_wakeup(sc);
769
6a6733f2
LR
770 spin_lock_bh(&sc->sc_pcu_lock);
771
203043f5
SG
772 /* prevent tasklets to enable interrupts once we disable them */
773 ah->imask &= ~ATH9K_INT_GLOBAL;
774
ff37e337
S
775 /* make sure h/w will not generate any interrupt
776 * before setting the invalid flag. */
4df3071e 777 ath9k_hw_disable_interrupts(ah);
ff37e337 778
c0c11741
FF
779 spin_unlock_bh(&sc->sc_pcu_lock);
780
781 /* we can now sync irq and kill any running tasklets, since we already
782 * disabled interrupts and not holding a spin lock */
783 synchronize_irq(sc->irq);
784 tasklet_kill(&sc->intr_tq);
785 tasklet_kill(&sc->bcon_tasklet);
786
787 prev_idle = sc->ps_idle;
788 sc->ps_idle = true;
789
790 spin_lock_bh(&sc->sc_pcu_lock);
791
792 if (ah->led_pin >= 0) {
793 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
794 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
795 }
796
9ebea382 797 ath_prepare_reset(sc);
ff37e337 798
0d95521e
FF
799 if (sc->rx.frag) {
800 dev_kfree_skb_any(sc->rx.frag);
801 sc->rx.frag = NULL;
802 }
803
c0c11741
FF
804 if (!ah->curchan)
805 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 806
c0c11741
FF
807 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
808 ath9k_hw_phy_disable(ah);
6a6733f2 809
c0c11741 810 ath9k_hw_configpcipowersave(ah, true);
203043f5 811
c0c11741 812 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 813
c0c11741 814 ath9k_ps_restore(sc);
ff37e337 815
781b14a3 816 set_bit(SC_OP_INVALID, &sc->sc_flags);
c0c11741 817 sc->ps_idle = prev_idle;
500c064d 818
141b38b6
S
819 mutex_unlock(&sc->mutex);
820
d2182b69 821 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
822}
823
4801416c
BG
824bool ath9k_uses_beacons(int type)
825{
826 switch (type) {
827 case NL80211_IFTYPE_AP:
828 case NL80211_IFTYPE_ADHOC:
829 case NL80211_IFTYPE_MESH_POINT:
830 return true;
831 default:
832 return false;
833 }
834}
835
4801416c
BG
836static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
837{
838 struct ath9k_vif_iter_data *iter_data = data;
839 int i;
840
841 if (iter_data->hw_macaddr)
842 for (i = 0; i < ETH_ALEN; i++)
843 iter_data->mask[i] &=
844 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 845
1ed32e4f 846 switch (vif->type) {
4801416c
BG
847 case NL80211_IFTYPE_AP:
848 iter_data->naps++;
f078f209 849 break;
4801416c
BG
850 case NL80211_IFTYPE_STATION:
851 iter_data->nstations++;
e51f3eff 852 break;
05c914fe 853 case NL80211_IFTYPE_ADHOC:
4801416c
BG
854 iter_data->nadhocs++;
855 break;
9cb5412b 856 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
857 iter_data->nmeshes++;
858 break;
859 case NL80211_IFTYPE_WDS:
860 iter_data->nwds++;
f078f209
LR
861 break;
862 default:
4801416c 863 break;
f078f209 864 }
4801416c 865}
f078f209 866
6dcc3444
SM
867static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
868{
869 struct ath_softc *sc = data;
870 struct ath_vif *avp = (void *)vif->drv_priv;
871
872 if (vif->type != NL80211_IFTYPE_STATION)
873 return;
874
875 if (avp->primary_sta_vif)
876 ath9k_set_assoc_state(sc, vif);
877}
878
4801416c
BG
879/* Called with sc->mutex held. */
880void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
881 struct ieee80211_vif *vif,
882 struct ath9k_vif_iter_data *iter_data)
883{
9ac58615 884 struct ath_softc *sc = hw->priv;
4801416c
BG
885 struct ath_hw *ah = sc->sc_ah;
886 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 887
4801416c
BG
888 /*
889 * Use the hardware MAC address as reference, the hardware uses it
890 * together with the BSSID mask when matching addresses.
891 */
892 memset(iter_data, 0, sizeof(*iter_data));
893 iter_data->hw_macaddr = common->macaddr;
894 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 895
4801416c
BG
896 if (vif)
897 ath9k_vif_iter(iter_data, vif->addr, vif);
898
899 /* Get list of all active MAC addresses */
8b2c9824
JB
900 ieee80211_iterate_active_interfaces_atomic(
901 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
902 ath9k_vif_iter, iter_data);
4801416c 903}
8ca21f01 904
4801416c
BG
905/* Called with sc->mutex held. */
906static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
907 struct ieee80211_vif *vif)
908{
9ac58615 909 struct ath_softc *sc = hw->priv;
4801416c
BG
910 struct ath_hw *ah = sc->sc_ah;
911 struct ath_common *common = ath9k_hw_common(ah);
912 struct ath9k_vif_iter_data iter_data;
6dcc3444 913 enum nl80211_iftype old_opmode = ah->opmode;
8ca21f01 914
4801416c 915 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 916
4801416c
BG
917 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
918 ath_hw_setbssidmask(common);
919
4801416c 920 if (iter_data.naps > 0) {
60ca9f87 921 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG
922 ah->opmode = NL80211_IFTYPE_AP;
923 } else {
60ca9f87 924 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 925
fd5999cf
JC
926 if (iter_data.nmeshes)
927 ah->opmode = NL80211_IFTYPE_MESH_POINT;
928 else if (iter_data.nwds)
4801416c
BG
929 ah->opmode = NL80211_IFTYPE_AP;
930 else if (iter_data.nadhocs)
931 ah->opmode = NL80211_IFTYPE_ADHOC;
932 else
933 ah->opmode = NL80211_IFTYPE_STATION;
934 }
5640b08e 935
df35d29e
SM
936 ath9k_hw_setopmode(ah);
937
198823fd 938 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 939 ah->imask |= ATH9K_INT_TSFOOR;
198823fd 940 else
4801416c 941 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f 942
72d874c6 943 ath9k_hw_set_interrupts(ah);
6dcc3444
SM
944
945 /*
946 * If we are changing the opmode to STATION,
947 * a beacon sync needs to be done.
948 */
949 if (ah->opmode == NL80211_IFTYPE_STATION &&
950 old_opmode == NL80211_IFTYPE_AP &&
951 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
8b2c9824
JB
952 ieee80211_iterate_active_interfaces_atomic(
953 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
954 ath9k_sta_vif_iter, sc);
6dcc3444 955 }
4801416c 956}
6f255425 957
4801416c
BG
958static int ath9k_add_interface(struct ieee80211_hw *hw,
959 struct ieee80211_vif *vif)
6b3b991d 960{
9ac58615 961 struct ath_softc *sc = hw->priv;
4801416c
BG
962 struct ath_hw *ah = sc->sc_ah;
963 struct ath_common *common = ath9k_hw_common(ah);
6b3b991d 964
4801416c 965 mutex_lock(&sc->mutex);
6b3b991d 966
d2182b69 967 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c
BG
968 sc->nvifs++;
969
327967cb 970 ath9k_ps_wakeup(sc);
130ef6e9 971 ath9k_calculate_summary_state(hw, vif);
327967cb
MSS
972 ath9k_ps_restore(sc);
973
130ef6e9
SM
974 if (ath9k_uses_beacons(vif->type))
975 ath9k_beacon_assign_slot(sc, vif);
976
4801416c 977 mutex_unlock(&sc->mutex);
327967cb 978 return 0;
6b3b991d
RM
979}
980
981static int ath9k_change_interface(struct ieee80211_hw *hw,
982 struct ieee80211_vif *vif,
983 enum nl80211_iftype new_type,
984 bool p2p)
985{
9ac58615 986 struct ath_softc *sc = hw->priv;
6b3b991d
RM
987 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
988
d2182b69 989 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 990 mutex_lock(&sc->mutex);
4801416c 991
4801416c 992 if (ath9k_uses_beacons(vif->type))
130ef6e9 993 ath9k_beacon_remove_slot(sc, vif);
4801416c 994
6b3b991d
RM
995 vif->type = new_type;
996 vif->p2p = p2p;
997
327967cb 998 ath9k_ps_wakeup(sc);
130ef6e9 999 ath9k_calculate_summary_state(hw, vif);
327967cb
MSS
1000 ath9k_ps_restore(sc);
1001
130ef6e9
SM
1002 if (ath9k_uses_beacons(vif->type))
1003 ath9k_beacon_assign_slot(sc, vif);
1004
6b3b991d 1005 mutex_unlock(&sc->mutex);
327967cb 1006 return 0;
6b3b991d
RM
1007}
1008
8feceb67 1009static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1010 struct ieee80211_vif *vif)
f078f209 1011{
9ac58615 1012 struct ath_softc *sc = hw->priv;
c46917bb 1013 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1014
d2182b69 1015 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1016
141b38b6
S
1017 mutex_lock(&sc->mutex);
1018
4801416c 1019 sc->nvifs--;
580f0b8a 1020
4801416c 1021 if (ath9k_uses_beacons(vif->type))
130ef6e9 1022 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1023
327967cb 1024 ath9k_ps_wakeup(sc);
4801416c 1025 ath9k_calculate_summary_state(hw, NULL);
327967cb 1026 ath9k_ps_restore(sc);
141b38b6
S
1027
1028 mutex_unlock(&sc->mutex);
f078f209
LR
1029}
1030
fbab7390 1031static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1032{
3069168c 1033 struct ath_hw *ah = sc->sc_ah;
ad128860 1034 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1035
3f7c5c10 1036 sc->ps_enabled = true;
3069168c
PR
1037 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1038 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1039 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1040 ath9k_hw_set_interrupts(ah);
3f7c5c10 1041 }
fdf76622 1042 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1043 }
ad128860 1044 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1045}
1046
845d708e
SB
1047static void ath9k_disable_ps(struct ath_softc *sc)
1048{
1049 struct ath_hw *ah = sc->sc_ah;
ad128860 1050 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB
1051
1052 sc->ps_enabled = false;
1053 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1054 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1055 ath9k_hw_setrxabort(ah, 0);
1056 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1057 PS_WAIT_FOR_CAB |
1058 PS_WAIT_FOR_PSPOLL_DATA |
1059 PS_WAIT_FOR_TX_ACK);
1060 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1061 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1062 ath9k_hw_set_interrupts(ah);
845d708e
SB
1063 }
1064 }
ad128860 1065 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1066}
1067
e93d083f
SW
1068void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1069{
1070 struct ath_softc *sc = hw->priv;
1071 struct ath_hw *ah = sc->sc_ah;
1072 struct ath_common *common = ath9k_hw_common(ah);
1073 u32 rxfilter;
1074
1075 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1076 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1077 return;
1078 }
1079
1080 ath9k_ps_wakeup(sc);
1081 rxfilter = ath9k_hw_getrxfilter(ah);
1082 ath9k_hw_setrxfilter(ah, rxfilter |
1083 ATH9K_RX_FILTER_PHYRADAR |
1084 ATH9K_RX_FILTER_PHYERR);
1085
1086 /* TODO: usually this should not be neccesary, but for some reason
1087 * (or in some mode?) the trigger must be called after the
1088 * configuration, otherwise the register will have its values reset
1089 * (on my ar9220 to value 0x01002310)
1090 */
1091 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1092 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1093 ath9k_ps_restore(sc);
1094}
1095
1096int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1097 enum spectral_mode spectral_mode)
1098{
1099 struct ath_softc *sc = hw->priv;
1100 struct ath_hw *ah = sc->sc_ah;
1101 struct ath_common *common = ath9k_hw_common(ah);
1102 struct ath_spec_scan param;
1103
1104 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1105 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1106 return -1;
1107 }
1108
1109 /* NOTE: this will generate a few samples ...
1110 *
1111 * TODO: review default parameters, and/or define an interface to set
1112 * them.
1113 */
1114 param.enabled = 1;
1115 param.short_repeat = true;
1116 param.count = 8;
1117 param.endless = false;
1118 param.period = 0xFF;
1119 param.fft_period = 0xF;
1120
1121 switch (spectral_mode) {
1122 case SPECTRAL_DISABLED:
1123 param.enabled = 0;
1124 break;
1125 case SPECTRAL_BACKGROUND:
1126 /* send endless samples.
1127 * TODO: is this really useful for "background"?
1128 */
1129 param.endless = 1;
1130 break;
1131 case SPECTRAL_CHANSCAN:
1132 break;
1133 case SPECTRAL_MANUAL:
1134 break;
1135 default:
1136 return -1;
1137 }
1138
1139 ath9k_ps_wakeup(sc);
1140 ath9k_hw_ops(ah)->spectral_scan_config(ah, &param);
1141 ath9k_ps_restore(sc);
1142
1143 sc->spectral_mode = spectral_mode;
1144
1145 return 0;
1146}
1147
e8975581 1148static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1149{
9ac58615 1150 struct ath_softc *sc = hw->priv;
3430098a
FF
1151 struct ath_hw *ah = sc->sc_ah;
1152 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1153 struct ieee80211_conf *conf = &hw->conf;
75600abf 1154 bool reset_channel = false;
f078f209 1155
c0c11741 1156 ath9k_ps_wakeup(sc);
aa33de09 1157 mutex_lock(&sc->mutex);
141b38b6 1158
daa1b6ee 1159 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1160 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1161 if (sc->ps_idle) {
daa1b6ee 1162 ath_cancel_work(sc);
b73f3e78
RM
1163 ath9k_stop_btcoex(sc);
1164 } else {
1165 ath9k_start_btcoex(sc);
75600abf
FF
1166 /*
1167 * The chip needs a reset to properly wake up from
1168 * full sleep
1169 */
1170 reset_channel = ah->chip_fullsleep;
b73f3e78 1171 }
daa1b6ee 1172 }
64839170 1173
e7824a50
LR
1174 /*
1175 * We just prepare to enable PS. We have to wait until our AP has
1176 * ACK'd our null data frame to disable RX otherwise we'll ignore
1177 * those ACKs and end up retransmitting the same null data frames.
1178 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1179 */
3cbb5dd7 1180 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1181 unsigned long flags;
1182 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1183 if (conf->flags & IEEE80211_CONF_PS)
1184 ath9k_enable_ps(sc);
845d708e
SB
1185 else
1186 ath9k_disable_ps(sc);
8ab2cd09 1187 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1188 }
1189
199afd9d
S
1190 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1191 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1192 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1193 sc->sc_ah->is_monitoring = true;
1194 } else {
d2182b69 1195 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1196 sc->sc_ah->is_monitoring = false;
199afd9d
S
1197 }
1198 }
1199
75600abf 1200 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1201 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1202 int pos = curchan->hw_value;
3430098a
FF
1203 int old_pos = -1;
1204 unsigned long flags;
1205
1206 if (ah->curchan)
1207 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1208
d2182b69 1209 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1210 curchan->center_freq, conf->channel_type);
f078f209 1211
3430098a
FF
1212 /* update survey stats for the old channel before switching */
1213 spin_lock_irqsave(&common->cc_lock, flags);
1214 ath_update_survey_stats(sc);
1215 spin_unlock_irqrestore(&common->cc_lock, flags);
1216
e338a85e
RM
1217 /*
1218 * Preserve the current channel values, before updating
1219 * the same channel
1220 */
1a19f77f
RM
1221 if (ah->curchan && (old_pos == pos))
1222 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1223
1224 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1225 curchan, conf->channel_type);
1226
3430098a
FF
1227 /*
1228 * If the operating channel changes, change the survey in-use flags
1229 * along with it.
1230 * Reset the survey data for the new channel, unless we're switching
1231 * back to the operating channel from an off-channel operation.
1232 */
1233 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1234 sc->cur_survey != &sc->survey[pos]) {
1235
1236 if (sc->cur_survey)
1237 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1238
1239 sc->cur_survey = &sc->survey[pos];
1240
1241 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1242 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1243 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1244 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1245 }
1246
0e2dedf9 1247 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1248 ath_err(common, "Unable to set channel\n");
aa33de09 1249 mutex_unlock(&sc->mutex);
8389fb3f 1250 ath9k_ps_restore(sc);
e11602b7
S
1251 return -EINVAL;
1252 }
3430098a
FF
1253
1254 /*
1255 * The most recent snapshot of channel->noisefloor for the old
1256 * channel is only available after the hardware reset. Copy it to
1257 * the survey stats now.
1258 */
1259 if (old_pos >= 0)
1260 ath_update_survey_nf(sc, old_pos);
e93d083f
SW
1261
1262 /* perform spectral scan if requested. */
1263 if (sc->scanning && sc->spectral_mode == SPECTRAL_CHANSCAN)
1264 ath9k_spectral_scan_trigger(hw);
1265
094d05dc 1266 }
f078f209 1267
c9f6a656 1268 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1269 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1270 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1271 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1272 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1273 }
1274
aa33de09 1275 mutex_unlock(&sc->mutex);
c0c11741 1276 ath9k_ps_restore(sc);
141b38b6 1277
f078f209
LR
1278 return 0;
1279}
1280
8feceb67
VT
1281#define SUPPORTED_FILTERS \
1282 (FIF_PROMISC_IN_BSS | \
1283 FIF_ALLMULTI | \
1284 FIF_CONTROL | \
af6a3fc7 1285 FIF_PSPOLL | \
8feceb67
VT
1286 FIF_OTHER_BSS | \
1287 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1288 FIF_PROBE_REQ | \
8feceb67 1289 FIF_FCSFAIL)
c83be688 1290
8feceb67
VT
1291/* FIXME: sc->sc_full_reset ? */
1292static void ath9k_configure_filter(struct ieee80211_hw *hw,
1293 unsigned int changed_flags,
1294 unsigned int *total_flags,
3ac64bee 1295 u64 multicast)
8feceb67 1296{
9ac58615 1297 struct ath_softc *sc = hw->priv;
8feceb67 1298 u32 rfilt;
f078f209 1299
8feceb67
VT
1300 changed_flags &= SUPPORTED_FILTERS;
1301 *total_flags &= SUPPORTED_FILTERS;
f078f209 1302
b77f483f 1303 sc->rx.rxfilter = *total_flags;
aa68aeaa 1304 ath9k_ps_wakeup(sc);
8feceb67
VT
1305 rfilt = ath_calcrxfilter(sc);
1306 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1307 ath9k_ps_restore(sc);
f078f209 1308
d2182b69
JP
1309 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1310 rfilt);
8feceb67 1311}
f078f209 1312
4ca77860
JB
1313static int ath9k_sta_add(struct ieee80211_hw *hw,
1314 struct ieee80211_vif *vif,
1315 struct ieee80211_sta *sta)
8feceb67 1316{
9ac58615 1317 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1318 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1319 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1320 struct ieee80211_key_conf ps_key = { };
f078f209 1321
7e1e3864 1322 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1323
1324 if (vif->type != NL80211_IFTYPE_AP &&
1325 vif->type != NL80211_IFTYPE_AP_VLAN)
1326 return 0;
1327
93ae2dd2 1328 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1329
1330 return 0;
1331}
1332
93ae2dd2
FF
1333static void ath9k_del_ps_key(struct ath_softc *sc,
1334 struct ieee80211_vif *vif,
1335 struct ieee80211_sta *sta)
1336{
1337 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1338 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1339 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1340
1341 if (!an->ps_key)
1342 return;
1343
1344 ath_key_delete(common, &ps_key);
1345}
1346
4ca77860
JB
1347static int ath9k_sta_remove(struct ieee80211_hw *hw,
1348 struct ieee80211_vif *vif,
1349 struct ieee80211_sta *sta)
1350{
9ac58615 1351 struct ath_softc *sc = hw->priv;
4ca77860 1352
93ae2dd2 1353 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1354 ath_node_detach(sc, sta);
1355
1356 return 0;
f078f209
LR
1357}
1358
5519541d
FF
1359static void ath9k_sta_notify(struct ieee80211_hw *hw,
1360 struct ieee80211_vif *vif,
1361 enum sta_notify_cmd cmd,
1362 struct ieee80211_sta *sta)
1363{
1364 struct ath_softc *sc = hw->priv;
1365 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1366
3d4e20f2 1367 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1368 return;
1369
5519541d
FF
1370 switch (cmd) {
1371 case STA_NOTIFY_SLEEP:
1372 an->sleeping = true;
042ec453 1373 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1374 break;
1375 case STA_NOTIFY_AWAKE:
1376 an->sleeping = false;
1377 ath_tx_aggr_wakeup(sc, an);
1378 break;
1379 }
1380}
1381
8a3a3c85
EP
1382static int ath9k_conf_tx(struct ieee80211_hw *hw,
1383 struct ieee80211_vif *vif, u16 queue,
8feceb67 1384 const struct ieee80211_tx_queue_params *params)
f078f209 1385{
9ac58615 1386 struct ath_softc *sc = hw->priv;
c46917bb 1387 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1388 struct ath_txq *txq;
8feceb67 1389 struct ath9k_tx_queue_info qi;
066dae93 1390 int ret = 0;
f078f209 1391
bea843c7 1392 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1393 return 0;
f078f209 1394
066dae93
FF
1395 txq = sc->tx.txq_map[queue];
1396
96f372c9 1397 ath9k_ps_wakeup(sc);
141b38b6
S
1398 mutex_lock(&sc->mutex);
1399
1ffb0610
S
1400 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1401
8feceb67
VT
1402 qi.tqi_aifs = params->aifs;
1403 qi.tqi_cwmin = params->cw_min;
1404 qi.tqi_cwmax = params->cw_max;
531bd079 1405 qi.tqi_burstTime = params->txop * 32;
f078f209 1406
d2182b69 1407 ath_dbg(common, CONFIG,
226afe68
JP
1408 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1409 queue, txq->axq_qnum, params->aifs, params->cw_min,
1410 params->cw_max, params->txop);
f078f209 1411
aa5955c3 1412 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1413 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1414 if (ret)
3800276a 1415 ath_err(common, "TXQ Update failed\n");
f078f209 1416
141b38b6 1417 mutex_unlock(&sc->mutex);
96f372c9 1418 ath9k_ps_restore(sc);
141b38b6 1419
8feceb67
VT
1420 return ret;
1421}
f078f209 1422
8feceb67
VT
1423static int ath9k_set_key(struct ieee80211_hw *hw,
1424 enum set_key_cmd cmd,
dc822b5d
JB
1425 struct ieee80211_vif *vif,
1426 struct ieee80211_sta *sta,
8feceb67
VT
1427 struct ieee80211_key_conf *key)
1428{
9ac58615 1429 struct ath_softc *sc = hw->priv;
c46917bb 1430 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1431 int ret = 0;
f078f209 1432
3e6109c5 1433 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1434 return -ENOSPC;
1435
5bd5e9a6
CYY
1436 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1437 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1438 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1439 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1440 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1441 /*
1442 * For now, disable hw crypto for the RSN IBSS group keys. This
1443 * could be optimized in the future to use a modified key cache
1444 * design to support per-STA RX GTK, but until that gets
1445 * implemented, use of software crypto for group addressed
1446 * frames is a acceptable to allow RSN IBSS to be used.
1447 */
1448 return -EOPNOTSUPP;
1449 }
1450
141b38b6 1451 mutex_lock(&sc->mutex);
3cbb5dd7 1452 ath9k_ps_wakeup(sc);
d2182b69 1453 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1454
8feceb67
VT
1455 switch (cmd) {
1456 case SET_KEY:
93ae2dd2
FF
1457 if (sta)
1458 ath9k_del_ps_key(sc, vif, sta);
1459
040e539e 1460 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1461 if (ret >= 0) {
1462 key->hw_key_idx = ret;
8feceb67
VT
1463 /* push IV and Michael MIC generation to stack */
1464 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1465 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1466 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1467 if (sc->sc_ah->sw_mgmt_crypto &&
1468 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1469 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1470 ret = 0;
8feceb67
VT
1471 }
1472 break;
1473 case DISABLE_KEY:
040e539e 1474 ath_key_delete(common, key);
8feceb67
VT
1475 break;
1476 default:
1477 ret = -EINVAL;
1478 }
f078f209 1479
3cbb5dd7 1480 ath9k_ps_restore(sc);
141b38b6
S
1481 mutex_unlock(&sc->mutex);
1482
8feceb67
VT
1483 return ret;
1484}
6c43c090
SM
1485
1486static void ath9k_set_assoc_state(struct ath_softc *sc,
1487 struct ieee80211_vif *vif)
4f5ef75b 1488{
4f5ef75b 1489 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4f5ef75b 1490 struct ath_vif *avp = (void *)vif->drv_priv;
6c43c090 1491 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
07c15a3f 1492 unsigned long flags;
6c43c090
SM
1493
1494 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1495 avp->primary_sta_vif = true;
1496
2e5ef459 1497 /*
6c43c090
SM
1498 * Set the AID, BSSID and do beacon-sync only when
1499 * the HW opmode is STATION.
1500 *
1501 * But the primary bit is set above in any case.
2e5ef459 1502 */
6c43c090 1503 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2e5ef459
RM
1504 return;
1505
6c43c090
SM
1506 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1507 common->curaid = bss_conf->aid;
1508 ath9k_hw_write_associd(sc->sc_ah);
07c15a3f 1509
6c43c090
SM
1510 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1511 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1512
6c43c090
SM
1513 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1514 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1515 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
05c0be2f 1516
50072ebc
RM
1517 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1518 ath9k_mci_update_wlan_channels(sc, false);
1519
6c43c090
SM
1520 ath_dbg(common, CONFIG,
1521 "Primary Station interface: %pM, BSSID: %pM\n",
1522 vif->addr, common->curbssid);
4f5ef75b
RM
1523}
1524
6c43c090 1525static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
4f5ef75b 1526{
6c43c090 1527 struct ath_softc *sc = data;
4f5ef75b 1528 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
4f5ef75b 1529
6c43c090 1530 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2e5ef459
RM
1531 return;
1532
6c43c090
SM
1533 if (bss_conf->assoc)
1534 ath9k_set_assoc_state(sc, vif);
4f5ef75b 1535}
f078f209 1536
8feceb67
VT
1537static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1538 struct ieee80211_vif *vif,
1539 struct ieee80211_bss_conf *bss_conf,
1540 u32 changed)
1541{
da0d45f7
SM
1542#define CHECK_ANI \
1543 (BSS_CHANGED_ASSOC | \
1544 BSS_CHANGED_IBSS | \
1545 BSS_CHANGED_BEACON_ENABLED)
1546
9ac58615 1547 struct ath_softc *sc = hw->priv;
2d0ddec5 1548 struct ath_hw *ah = sc->sc_ah;
1510718d 1549 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1550 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1551 int slottime;
f078f209 1552
96f372c9 1553 ath9k_ps_wakeup(sc);
141b38b6
S
1554 mutex_lock(&sc->mutex);
1555
9f61903c 1556 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM
1557 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1558 bss_conf->bssid, bss_conf->assoc);
1559
1560 if (avp->primary_sta_vif && !bss_conf->assoc) {
1561 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1562 avp->primary_sta_vif = false;
1563
1564 if (ah->opmode == NL80211_IFTYPE_STATION)
1565 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1566 }
1567
8b2c9824
JB
1568 ieee80211_iterate_active_interfaces_atomic(
1569 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1570 ath9k_bss_assoc_iter, sc);
2d0ddec5 1571
6c43c090
SM
1572 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1573 ah->opmode == NL80211_IFTYPE_STATION) {
1574 memset(common->curbssid, 0, ETH_ALEN);
1575 common->curaid = 0;
1576 ath9k_hw_write_associd(sc->sc_ah);
50072ebc
RM
1577 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1578 ath9k_mci_update_wlan_channels(sc, true);
6c43c090 1579 }
c6089ccc 1580 }
2d0ddec5 1581
2e5ef459 1582 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM
1583 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1584 common->curaid = bss_conf->aid;
1585 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM
1586 }
1587
ef4ad633
SM
1588 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1589 (changed & BSS_CHANGED_BEACON_INT)) {
2f8e82e8
SM
1590 if (ah->opmode == NL80211_IFTYPE_AP &&
1591 bss_conf->enable_beacon)
1592 ath9k_set_tsfadjust(sc, vif);
ef4ad633
SM
1593 if (ath9k_allow_beacon_config(sc, vif))
1594 ath9k_beacon_config(sc, vif, changed);
0005baf4
FF
1595 }
1596
1597 if (changed & BSS_CHANGED_ERP_SLOT) {
1598 if (bss_conf->use_short_slot)
1599 slottime = 9;
1600 else
1601 slottime = 20;
1602 if (vif->type == NL80211_IFTYPE_AP) {
1603 /*
1604 * Defer update, so that connected stations can adjust
1605 * their settings at the same time.
1606 * See beacon.c for more details
1607 */
1608 sc->beacon.slottime = slottime;
1609 sc->beacon.updateslot = UPDATE;
1610 } else {
1611 ah->slottime = slottime;
1612 ath9k_hw_init_global_settings(ah);
1613 }
2d0ddec5
JB
1614 }
1615
da0d45f7
SM
1616 if (changed & CHECK_ANI)
1617 ath_check_ani(sc);
1618
141b38b6 1619 mutex_unlock(&sc->mutex);
96f372c9 1620 ath9k_ps_restore(sc);
da0d45f7
SM
1621
1622#undef CHECK_ANI
8feceb67 1623}
f078f209 1624
37a41b4a 1625static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1626{
9ac58615 1627 struct ath_softc *sc = hw->priv;
8feceb67 1628 u64 tsf;
f078f209 1629
141b38b6 1630 mutex_lock(&sc->mutex);
9abbfb27 1631 ath9k_ps_wakeup(sc);
141b38b6 1632 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1633 ath9k_ps_restore(sc);
141b38b6 1634 mutex_unlock(&sc->mutex);
f078f209 1635
8feceb67
VT
1636 return tsf;
1637}
f078f209 1638
37a41b4a
EP
1639static void ath9k_set_tsf(struct ieee80211_hw *hw,
1640 struct ieee80211_vif *vif,
1641 u64 tsf)
3b5d665b 1642{
9ac58615 1643 struct ath_softc *sc = hw->priv;
3b5d665b 1644
141b38b6 1645 mutex_lock(&sc->mutex);
9abbfb27 1646 ath9k_ps_wakeup(sc);
141b38b6 1647 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1648 ath9k_ps_restore(sc);
141b38b6 1649 mutex_unlock(&sc->mutex);
3b5d665b
AF
1650}
1651
37a41b4a 1652static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1653{
9ac58615 1654 struct ath_softc *sc = hw->priv;
c83be688 1655
141b38b6 1656 mutex_lock(&sc->mutex);
21526d57
LR
1657
1658 ath9k_ps_wakeup(sc);
141b38b6 1659 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1660 ath9k_ps_restore(sc);
1661
141b38b6 1662 mutex_unlock(&sc->mutex);
8feceb67 1663}
f078f209 1664
8feceb67 1665static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1666 struct ieee80211_vif *vif,
141b38b6
S
1667 enum ieee80211_ampdu_mlme_action action,
1668 struct ieee80211_sta *sta,
0b01f030 1669 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1670{
9ac58615 1671 struct ath_softc *sc = hw->priv;
8feceb67 1672 int ret = 0;
f078f209 1673
85ad181e
JB
1674 local_bh_disable();
1675
8feceb67
VT
1676 switch (action) {
1677 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1678 break;
1679 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1680 break;
1681 case IEEE80211_AMPDU_TX_START:
8b685ba9 1682 ath9k_ps_wakeup(sc);
231c3a1f
FF
1683 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1684 if (!ret)
1685 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1686 ath9k_ps_restore(sc);
8feceb67 1687 break;
18b559d5
JB
1688 case IEEE80211_AMPDU_TX_STOP_CONT:
1689 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1690 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
8b685ba9 1691 ath9k_ps_wakeup(sc);
f83da965 1692 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1693 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1694 ath9k_ps_restore(sc);
8feceb67 1695 break;
b1720231 1696 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1697 ath9k_ps_wakeup(sc);
8469cdef 1698 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1699 ath9k_ps_restore(sc);
8469cdef 1700 break;
8feceb67 1701 default:
3800276a 1702 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1703 }
1704
85ad181e
JB
1705 local_bh_enable();
1706
8feceb67 1707 return ret;
f078f209
LR
1708}
1709
62dad5b0
BP
1710static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1711 struct survey_info *survey)
1712{
9ac58615 1713 struct ath_softc *sc = hw->priv;
3430098a 1714 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1715 struct ieee80211_supported_band *sband;
3430098a
FF
1716 struct ieee80211_channel *chan;
1717 unsigned long flags;
1718 int pos;
1719
1720 spin_lock_irqsave(&common->cc_lock, flags);
1721 if (idx == 0)
1722 ath_update_survey_stats(sc);
39162dbe
FF
1723
1724 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1725 if (sband && idx >= sband->n_channels) {
1726 idx -= sband->n_channels;
1727 sband = NULL;
1728 }
62dad5b0 1729
39162dbe
FF
1730 if (!sband)
1731 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1732
3430098a
FF
1733 if (!sband || idx >= sband->n_channels) {
1734 spin_unlock_irqrestore(&common->cc_lock, flags);
1735 return -ENOENT;
4f1a5a4b 1736 }
62dad5b0 1737
3430098a
FF
1738 chan = &sband->channels[idx];
1739 pos = chan->hw_value;
1740 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1741 survey->channel = chan;
1742 spin_unlock_irqrestore(&common->cc_lock, flags);
1743
62dad5b0
BP
1744 return 0;
1745}
1746
e239d859
FF
1747static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1748{
9ac58615 1749 struct ath_softc *sc = hw->priv;
e239d859
FF
1750 struct ath_hw *ah = sc->sc_ah;
1751
1752 mutex_lock(&sc->mutex);
1753 ah->coverage_class = coverage_class;
8b2a3827
MSS
1754
1755 ath9k_ps_wakeup(sc);
e239d859 1756 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
1757 ath9k_ps_restore(sc);
1758
e239d859
FF
1759 mutex_unlock(&sc->mutex);
1760}
1761
69081624
VT
1762static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1763{
69081624 1764 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
1765 struct ath_hw *ah = sc->sc_ah;
1766 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
1767 int timeout = 200; /* ms */
1768 int i, j;
2f6fc351 1769 bool drain_txq;
69081624
VT
1770
1771 mutex_lock(&sc->mutex);
69081624
VT
1772 cancel_delayed_work_sync(&sc->tx_complete_work);
1773
6a6b3f3e 1774 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1775 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
1776 mutex_unlock(&sc->mutex);
1777 return;
1778 }
1779
781b14a3 1780 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 1781 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
1782 mutex_unlock(&sc->mutex);
1783 return;
1784 }
1785
86271e46 1786 for (j = 0; j < timeout; j++) {
108697c4 1787 bool npend = false;
86271e46
FF
1788
1789 if (j)
1790 usleep_range(1000, 2000);
69081624 1791
86271e46
FF
1792 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1793 if (!ATH_TXQ_SETUP(sc, i))
1794 continue;
1795
108697c4
MSS
1796 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1797
1798 if (npend)
1799 break;
69081624 1800 }
86271e46
FF
1801
1802 if (!npend)
9df0d6a2 1803 break;
69081624
VT
1804 }
1805
9df0d6a2
FF
1806 if (drop) {
1807 ath9k_ps_wakeup(sc);
1808 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 1809 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 1810 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1811
9df0d6a2 1812 if (!drain_txq)
1381559b 1813 ath_reset(sc);
9adcf440 1814
9df0d6a2
FF
1815 ath9k_ps_restore(sc);
1816 ieee80211_wake_queues(hw);
1817 }
d78f4b3e 1818
69081624
VT
1819 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1820 mutex_unlock(&sc->mutex);
1821}
1822
15b91e83
VN
1823static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1824{
1825 struct ath_softc *sc = hw->priv;
1826 int i;
1827
1828 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1829 if (!ATH_TXQ_SETUP(sc, i))
1830 continue;
1831
1832 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1833 return true;
1834 }
1835 return false;
1836}
1837
5595f119 1838static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
1839{
1840 struct ath_softc *sc = hw->priv;
1841 struct ath_hw *ah = sc->sc_ah;
1842 struct ieee80211_vif *vif;
1843 struct ath_vif *avp;
1844 struct ath_buf *bf;
1845 struct ath_tx_status ts;
4286df60 1846 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
1847 int status;
1848
1849 vif = sc->beacon.bslot[0];
1850 if (!vif)
1851 return 0;
1852
aa45fe96 1853 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF
1854 return 0;
1855
aa45fe96
SM
1856 avp = (void *)vif->drv_priv;
1857
4286df60 1858 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
1859 tasklet_disable(&sc->bcon_tasklet);
1860
1861 bf = avp->av_bcbuf;
1862 if (!bf || !bf->bf_mpdu)
1863 goto skip;
1864
1865 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1866 if (status == -EINPROGRESS)
1867 goto skip;
1868
1869 sc->beacon.tx_processed = true;
1870 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1871
1872skip:
1873 tasklet_enable(&sc->bcon_tasklet);
1874 }
1875
1876 return sc->beacon.tx_last;
1877}
1878
52c94f41
MSS
1879static int ath9k_get_stats(struct ieee80211_hw *hw,
1880 struct ieee80211_low_level_stats *stats)
1881{
1882 struct ath_softc *sc = hw->priv;
1883 struct ath_hw *ah = sc->sc_ah;
1884 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1885
1886 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1887 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1888 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1889 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1890 return 0;
1891}
1892
43c35284
FF
1893static u32 fill_chainmask(u32 cap, u32 new)
1894{
1895 u32 filled = 0;
1896 int i;
1897
1898 for (i = 0; cap && new; i++, cap >>= 1) {
1899 if (!(cap & BIT(0)))
1900 continue;
1901
1902 if (new & BIT(0))
1903 filled |= BIT(i);
1904
1905 new >>= 1;
1906 }
1907
1908 return filled;
1909}
1910
5d9c7e3c
FF
1911static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1912{
fea92cbf
FF
1913 if (AR_SREV_9300_20_OR_LATER(ah))
1914 return true;
1915
5d9c7e3c
FF
1916 switch (val & 0x7) {
1917 case 0x1:
1918 case 0x3:
1919 case 0x7:
1920 return true;
1921 case 0x2:
1922 return (ah->caps.rx_chainmask == 1);
1923 default:
1924 return false;
1925 }
1926}
1927
43c35284
FF
1928static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1929{
1930 struct ath_softc *sc = hw->priv;
1931 struct ath_hw *ah = sc->sc_ah;
1932
5d9c7e3c
FF
1933 if (ah->caps.rx_chainmask != 1)
1934 rx_ant |= tx_ant;
1935
1936 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF
1937 return -EINVAL;
1938
1939 sc->ant_rx = rx_ant;
1940 sc->ant_tx = tx_ant;
1941
1942 if (ah->caps.rx_chainmask == 1)
1943 return 0;
1944
1945 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1946 if (AR_SREV_9100(ah))
1947 ah->rxchainmask = 0x7;
1948 else
1949 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1950
1951 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1952 ath9k_reload_chainmask_settings(sc);
1953
1954 return 0;
1955}
1956
1957static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1958{
1959 struct ath_softc *sc = hw->priv;
1960
1961 *tx_ant = sc->ant_tx;
1962 *rx_ant = sc->ant_rx;
1963 return 0;
1964}
1965
b11e640a
MSS
1966#ifdef CONFIG_PM_SLEEP
1967
1968static void ath9k_wow_map_triggers(struct ath_softc *sc,
1969 struct cfg80211_wowlan *wowlan,
1970 u32 *wow_triggers)
1971{
1972 if (wowlan->disconnect)
1973 *wow_triggers |= AH_WOW_LINK_CHANGE |
1974 AH_WOW_BEACON_MISS;
1975 if (wowlan->magic_pkt)
1976 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1977
1978 if (wowlan->n_patterns)
1979 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1980
1981 sc->wow_enabled = *wow_triggers;
1982
1983}
1984
1985static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1986{
1987 struct ath_hw *ah = sc->sc_ah;
1988 struct ath_common *common = ath9k_hw_common(ah);
1989 struct ath9k_hw_capabilities *pcaps = &ah->caps;
1990 int pattern_count = 0;
1991 int i, byte_cnt;
1992 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1993 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1994
1995 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1996 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1997
1998 /*
1999 * Create Dissassociate / Deauthenticate packet filter
2000 *
2001 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2002 * +--------------+----------+---------+--------+--------+----
2003 * + Frame Control+ Duration + DA + SA + BSSID +
2004 * +--------------+----------+---------+--------+--------+----
2005 *
2006 * The above is the management frame format for disassociate/
2007 * deauthenticate pattern, from this we need to match the first byte
2008 * of 'Frame Control' and DA, SA, and BSSID fields
2009 * (skipping 2nd byte of FC and Duration feild.
2010 *
2011 * Disassociate pattern
2012 * --------------------
2013 * Frame control = 00 00 1010
2014 * DA, SA, BSSID = x:x:x:x:x:x
2015 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2016 * | x:x:x:x:x:x -- 22 bytes
2017 *
2018 * Deauthenticate pattern
2019 * ----------------------
2020 * Frame control = 00 00 1100
2021 * DA, SA, BSSID = x:x:x:x:x:x
2022 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2023 * | x:x:x:x:x:x -- 22 bytes
2024 */
2025
2026 /* Create Disassociate Pattern first */
2027
2028 byte_cnt = 0;
2029
2030 /* Fill out the mask with all FF's */
2031
2032 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2033 dis_deauth_mask[i] = 0xff;
2034
2035 /* copy the first byte of frame control field */
2036 dis_deauth_pattern[byte_cnt] = 0xa0;
2037 byte_cnt++;
2038
2039 /* skip 2nd byte of frame control and Duration field */
2040 byte_cnt += 3;
2041
2042 /*
2043 * need not match the destination mac address, it can be a broadcast
2044 * mac address or an unicast to this station
2045 */
2046 byte_cnt += 6;
2047
2048 /* copy the source mac address */
2049 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2050
2051 byte_cnt += 6;
2052
2053 /* copy the bssid, its same as the source mac address */
2054
2055 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2056
2057 /* Create Disassociate pattern mask */
2058
2059 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2060
2061 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2062 /*
2063 * for AR9280, because of hardware limitation, the
2064 * first 4 bytes have to be matched for all patterns.
2065 * the mask for disassociation and de-auth pattern
2066 * matching need to enable the first 4 bytes.
2067 * also the duration field needs to be filled.
2068 */
2069 dis_deauth_mask[0] = 0xf0;
2070
2071 /*
2072 * fill in duration field
2073 FIXME: what is the exact value ?
2074 */
2075 dis_deauth_pattern[2] = 0xff;
2076 dis_deauth_pattern[3] = 0xff;
2077 } else {
2078 dis_deauth_mask[0] = 0xfe;
2079 }
2080
2081 dis_deauth_mask[1] = 0x03;
2082 dis_deauth_mask[2] = 0xc0;
2083 } else {
2084 dis_deauth_mask[0] = 0xef;
2085 dis_deauth_mask[1] = 0x3f;
2086 dis_deauth_mask[2] = 0x00;
2087 dis_deauth_mask[3] = 0xfc;
2088 }
2089
2090 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2091
2092 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2093 pattern_count, byte_cnt);
2094
2095 pattern_count++;
2096 /*
2097 * for de-authenticate pattern, only the first byte of the frame
2098 * control field gets changed from 0xA0 to 0xC0
2099 */
2100 dis_deauth_pattern[0] = 0xC0;
2101
2102 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2103 pattern_count, byte_cnt);
2104
2105}
2106
2107static void ath9k_wow_add_pattern(struct ath_softc *sc,
2108 struct cfg80211_wowlan *wowlan)
2109{
2110 struct ath_hw *ah = sc->sc_ah;
2111 struct ath9k_wow_pattern *wow_pattern = NULL;
2112 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2113 int mask_len;
2114 s8 i = 0;
2115
2116 if (!wowlan->n_patterns)
2117 return;
2118
2119 /*
2120 * Add the new user configured patterns
2121 */
2122 for (i = 0; i < wowlan->n_patterns; i++) {
2123
2124 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2125
2126 if (!wow_pattern)
2127 return;
2128
2129 /*
2130 * TODO: convert the generic user space pattern to
2131 * appropriate chip specific/802.11 pattern.
2132 */
2133
2134 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2135 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2136 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2137 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2138 patterns[i].pattern_len);
2139 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2140 wow_pattern->pattern_len = patterns[i].pattern_len;
2141
2142 /*
2143 * just need to take care of deauth and disssoc pattern,
2144 * make sure we don't overwrite them.
2145 */
2146
2147 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2148 wow_pattern->mask_bytes,
2149 i + 2,
2150 wow_pattern->pattern_len);
2151 kfree(wow_pattern);
2152
2153 }
2154
2155}
2156
2157static int ath9k_suspend(struct ieee80211_hw *hw,
2158 struct cfg80211_wowlan *wowlan)
2159{
2160 struct ath_softc *sc = hw->priv;
2161 struct ath_hw *ah = sc->sc_ah;
2162 struct ath_common *common = ath9k_hw_common(ah);
2163 u32 wow_triggers_enabled = 0;
2164 int ret = 0;
2165
2166 mutex_lock(&sc->mutex);
2167
2168 ath_cancel_work(sc);
5686cac5 2169 ath_stop_ani(sc);
b11e640a
MSS
2170 del_timer_sync(&sc->rx_poll_timer);
2171
2172 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2173 ath_dbg(common, ANY, "Device not present\n");
2174 ret = -EINVAL;
2175 goto fail_wow;
2176 }
2177
2178 if (WARN_ON(!wowlan)) {
2179 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2180 ret = -EINVAL;
2181 goto fail_wow;
2182 }
2183
2184 if (!device_can_wakeup(sc->dev)) {
2185 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2186 ret = 1;
2187 goto fail_wow;
2188 }
2189
2190 /*
2191 * none of the sta vifs are associated
2192 * and we are not currently handling multivif
2193 * cases, for instance we have to seperately
2194 * configure 'keep alive frame' for each
2195 * STA.
2196 */
2197
2198 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2199 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2200 ret = 1;
2201 goto fail_wow;
2202 }
2203
2204 if (sc->nvifs > 1) {
2205 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2206 ret = 1;
2207 goto fail_wow;
2208 }
2209
2210 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2211
2212 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2213 wow_triggers_enabled);
2214
2215 ath9k_ps_wakeup(sc);
2216
2217 ath9k_stop_btcoex(sc);
2218
2219 /*
2220 * Enable wake up on recieving disassoc/deauth
2221 * frame by default.
2222 */
2223 ath9k_wow_add_disassoc_deauth_pattern(sc);
2224
2225 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2226 ath9k_wow_add_pattern(sc, wowlan);
2227
2228 spin_lock_bh(&sc->sc_pcu_lock);
2229 /*
2230 * To avoid false wake, we enable beacon miss interrupt only
2231 * when we go to sleep. We save the current interrupt mask
2232 * so we can restore it after the system wakes up
2233 */
2234 sc->wow_intr_before_sleep = ah->imask;
2235 ah->imask &= ~ATH9K_INT_GLOBAL;
2236 ath9k_hw_disable_interrupts(ah);
2237 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2238 ath9k_hw_set_interrupts(ah);
2239 ath9k_hw_enable_interrupts(ah);
2240
2241 spin_unlock_bh(&sc->sc_pcu_lock);
2242
2243 /*
2244 * we can now sync irq and kill any running tasklets, since we already
2245 * disabled interrupts and not holding a spin lock
2246 */
2247 synchronize_irq(sc->irq);
2248 tasklet_kill(&sc->intr_tq);
2249
2250 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2251
2252 ath9k_ps_restore(sc);
2253 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2254 atomic_inc(&sc->wow_sleep_proc_intr);
2255
2256fail_wow:
2257 mutex_unlock(&sc->mutex);
2258 return ret;
2259}
2260
2261static int ath9k_resume(struct ieee80211_hw *hw)
2262{
2263 struct ath_softc *sc = hw->priv;
2264 struct ath_hw *ah = sc->sc_ah;
2265 struct ath_common *common = ath9k_hw_common(ah);
2266 u32 wow_status;
2267
2268 mutex_lock(&sc->mutex);
2269
2270 ath9k_ps_wakeup(sc);
2271
2272 spin_lock_bh(&sc->sc_pcu_lock);
2273
2274 ath9k_hw_disable_interrupts(ah);
2275 ah->imask = sc->wow_intr_before_sleep;
2276 ath9k_hw_set_interrupts(ah);
2277 ath9k_hw_enable_interrupts(ah);
2278
2279 spin_unlock_bh(&sc->sc_pcu_lock);
2280
2281 wow_status = ath9k_hw_wow_wakeup(ah);
2282
2283 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2284 /*
2285 * some devices may not pick beacon miss
2286 * as the reason they woke up so we add
2287 * that here for that shortcoming.
2288 */
2289 wow_status |= AH_WOW_BEACON_MISS;
2290 atomic_dec(&sc->wow_got_bmiss_intr);
2291 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2292 }
2293
2294 atomic_dec(&sc->wow_sleep_proc_intr);
2295
2296 if (wow_status) {
2297 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2298 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2299 }
2300
2301 ath_restart_work(sc);
2302 ath9k_start_btcoex(sc);
2303
2304 ath9k_ps_restore(sc);
2305 mutex_unlock(&sc->mutex);
2306
2307 return 0;
2308}
2309
2310static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2311{
2312 struct ath_softc *sc = hw->priv;
2313
2314 mutex_lock(&sc->mutex);
2315 device_init_wakeup(sc->dev, 1);
2316 device_set_wakeup_enable(sc->dev, enabled);
2317 mutex_unlock(&sc->mutex);
2318}
2319
2320#endif
e93d083f
SW
2321static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2322{
2323 struct ath_softc *sc = hw->priv;
2324
2325 sc->scanning = 1;
2326}
2327
2328static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2329{
2330 struct ath_softc *sc = hw->priv;
2331
2332 sc->scanning = 0;
2333}
b11e640a 2334
6baff7f9 2335struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2336 .tx = ath9k_tx,
2337 .start = ath9k_start,
2338 .stop = ath9k_stop,
2339 .add_interface = ath9k_add_interface,
6b3b991d 2340 .change_interface = ath9k_change_interface,
8feceb67
VT
2341 .remove_interface = ath9k_remove_interface,
2342 .config = ath9k_config,
8feceb67 2343 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2344 .sta_add = ath9k_sta_add,
2345 .sta_remove = ath9k_sta_remove,
5519541d 2346 .sta_notify = ath9k_sta_notify,
8feceb67 2347 .conf_tx = ath9k_conf_tx,
8feceb67 2348 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2349 .set_key = ath9k_set_key,
8feceb67 2350 .get_tsf = ath9k_get_tsf,
3b5d665b 2351 .set_tsf = ath9k_set_tsf,
8feceb67 2352 .reset_tsf = ath9k_reset_tsf,
4233df6b 2353 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2354 .get_survey = ath9k_get_survey,
3b319aae 2355 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2356 .set_coverage_class = ath9k_set_coverage_class,
69081624 2357 .flush = ath9k_flush,
15b91e83 2358 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2359 .tx_last_beacon = ath9k_tx_last_beacon,
2360 .get_stats = ath9k_get_stats,
43c35284
FF
2361 .set_antenna = ath9k_set_antenna,
2362 .get_antenna = ath9k_get_antenna,
b90bd9d1 2363
b11e640a
MSS
2364#ifdef CONFIG_PM_SLEEP
2365 .suspend = ath9k_suspend,
2366 .resume = ath9k_resume,
2367 .set_wakeup = ath9k_set_wakeup,
2368#endif
2369
b90bd9d1
BG
2370#ifdef CONFIG_ATH9K_DEBUGFS
2371 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM
2372 .get_et_stats = ath9k_get_et_stats,
2373 .get_et_strings = ath9k_get_et_strings,
2374#endif
2375
2376#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
2377 .sta_add_debugfs = ath9k_sta_add_debugfs,
2378 .sta_remove_debugfs = ath9k_sta_remove_debugfs,
b90bd9d1 2379#endif
e93d083f
SW
2380 .sw_scan_start = ath9k_sw_scan_start,
2381 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67 2382};