Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ff37e337 S |
21 | static void ath_update_txpow(struct ath_softc *sc) |
22 | { | |
cbe61d8a | 23 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 24 | |
17d7904d | 25 | if (sc->curtxpow != sc->config.txpowlimit) { |
de40f316 | 26 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); |
ff37e337 | 27 | /* read back in case value is clamped */ |
9cc3271f | 28 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
29 | } |
30 | } | |
31 | ||
32 | static u8 parse_mpdudensity(u8 mpdudensity) | |
33 | { | |
34 | /* | |
35 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
36 | * 0 for no restriction | |
37 | * 1 for 1/4 us | |
38 | * 2 for 1/2 us | |
39 | * 3 for 1 us | |
40 | * 4 for 2 us | |
41 | * 5 for 4 us | |
42 | * 6 for 8 us | |
43 | * 7 for 16 us | |
44 | */ | |
45 | switch (mpdudensity) { | |
46 | case 0: | |
47 | return 0; | |
48 | case 1: | |
49 | case 2: | |
50 | case 3: | |
51 | /* Our lower layer calculations limit our precision to | |
52 | 1 microsecond */ | |
53 | return 1; | |
54 | case 4: | |
55 | return 2; | |
56 | case 5: | |
57 | return 4; | |
58 | case 6: | |
59 | return 8; | |
60 | case 7: | |
61 | return 16; | |
62 | default: | |
63 | return 0; | |
64 | } | |
65 | } | |
66 | ||
82880a7c VT |
67 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
68 | struct ieee80211_hw *hw) | |
69 | { | |
70 | struct ieee80211_channel *curchan = hw->conf.channel; | |
71 | struct ath9k_channel *channel; | |
72 | u8 chan_idx; | |
73 | ||
74 | chan_idx = curchan->hw_value; | |
75 | channel = &sc->sc_ah->channels[chan_idx]; | |
76 | ath9k_update_ichannel(sc, hw, channel); | |
77 | return channel; | |
78 | } | |
79 | ||
55624204 | 80 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
81 | { |
82 | unsigned long flags; | |
83 | bool ret; | |
84 | ||
9ecdef4b LR |
85 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
86 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
87 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
88 | |
89 | return ret; | |
90 | } | |
91 | ||
a91d75ae LR |
92 | void ath9k_ps_wakeup(struct ath_softc *sc) |
93 | { | |
898c914a | 94 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 95 | unsigned long flags; |
fbb078fc | 96 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
97 | |
98 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
99 | if (++sc->ps_usecount != 1) | |
100 | goto unlock; | |
101 | ||
fbb078fc | 102 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 103 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 104 | |
898c914a FF |
105 | /* |
106 | * While the hardware is asleep, the cycle counters contain no | |
107 | * useful data. Better clear them now so that they don't mess up | |
108 | * survey data results. | |
109 | */ | |
fbb078fc FF |
110 | if (power_mode != ATH9K_PM_AWAKE) { |
111 | spin_lock(&common->cc_lock); | |
112 | ath_hw_cycle_counters_update(common); | |
113 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
114 | spin_unlock(&common->cc_lock); | |
115 | } | |
898c914a | 116 | |
a91d75ae LR |
117 | unlock: |
118 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
119 | } | |
120 | ||
121 | void ath9k_ps_restore(struct ath_softc *sc) | |
122 | { | |
898c914a | 123 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
124 | unsigned long flags; |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (--sc->ps_usecount != 0) | |
128 | goto unlock; | |
129 | ||
898c914a FF |
130 | spin_lock(&common->cc_lock); |
131 | ath_hw_cycle_counters_update(common); | |
132 | spin_unlock(&common->cc_lock); | |
133 | ||
1dbfd9d4 VN |
134 | if (sc->ps_idle) |
135 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
136 | else if (sc->ps_enabled && | |
137 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
138 | PS_WAIT_FOR_CAB | |
139 | PS_WAIT_FOR_PSPOLL_DATA | | |
140 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 141 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
142 | |
143 | unlock: | |
144 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
145 | } | |
146 | ||
5ee08656 FF |
147 | static void ath_start_ani(struct ath_common *common) |
148 | { | |
149 | struct ath_hw *ah = common->ah; | |
150 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
151 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
152 | ||
153 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
154 | return; | |
155 | ||
156 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
157 | return; | |
158 | ||
159 | common->ani.longcal_timer = timestamp; | |
160 | common->ani.shortcal_timer = timestamp; | |
161 | common->ani.checkani_timer = timestamp; | |
162 | ||
163 | mod_timer(&common->ani.timer, | |
164 | jiffies + | |
165 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
166 | } | |
167 | ||
3430098a FF |
168 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
169 | { | |
170 | struct ath_hw *ah = sc->sc_ah; | |
171 | struct ath9k_channel *chan = &ah->channels[channel]; | |
172 | struct survey_info *survey = &sc->survey[channel]; | |
173 | ||
174 | if (chan->noisefloor) { | |
175 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
176 | survey->noise = chan->noisefloor; | |
177 | } | |
178 | } | |
179 | ||
180 | static void ath_update_survey_stats(struct ath_softc *sc) | |
181 | { | |
182 | struct ath_hw *ah = sc->sc_ah; | |
183 | struct ath_common *common = ath9k_hw_common(ah); | |
184 | int pos = ah->curchan - &ah->channels[0]; | |
185 | struct survey_info *survey = &sc->survey[pos]; | |
186 | struct ath_cycle_counters *cc = &common->cc_survey; | |
187 | unsigned int div = common->clockrate * 1000; | |
188 | ||
0845735e FF |
189 | if (!ah->curchan) |
190 | return; | |
191 | ||
898c914a FF |
192 | if (ah->power_mode == ATH9K_PM_AWAKE) |
193 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
194 | |
195 | if (cc->cycles > 0) { | |
196 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
197 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
198 | SURVEY_INFO_CHANNEL_TIME_RX | | |
199 | SURVEY_INFO_CHANNEL_TIME_TX; | |
200 | survey->channel_time += cc->cycles / div; | |
201 | survey->channel_time_busy += cc->rx_busy / div; | |
202 | survey->channel_time_rx += cc->rx_frame / div; | |
203 | survey->channel_time_tx += cc->tx_frame / div; | |
204 | } | |
205 | memset(cc, 0, sizeof(*cc)); | |
206 | ||
207 | ath_update_survey_nf(sc, pos); | |
208 | } | |
209 | ||
ff37e337 S |
210 | /* |
211 | * Set/change channels. If the channel is really being changed, it's done | |
212 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
213 | * DMA, then restart stuff. | |
214 | */ | |
0e2dedf9 JM |
215 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
216 | struct ath9k_channel *hchan) | |
ff37e337 | 217 | { |
20bd2a09 | 218 | struct ath_wiphy *aphy = hw->priv; |
cbe61d8a | 219 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 220 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 221 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 222 | bool fastcc = true, stopped; |
ae8d2858 | 223 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 224 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 225 | int r; |
ff37e337 S |
226 | |
227 | if (sc->sc_flags & SC_OP_INVALID) | |
228 | return -EIO; | |
229 | ||
5ee08656 FF |
230 | del_timer_sync(&common->ani.timer); |
231 | cancel_work_sync(&sc->paprd_work); | |
232 | cancel_work_sync(&sc->hw_check_work); | |
233 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
234 | ||
3cbb5dd7 VN |
235 | ath9k_ps_wakeup(sc); |
236 | ||
6a6733f2 LR |
237 | spin_lock_bh(&sc->sc_pcu_lock); |
238 | ||
c0d7c7af LR |
239 | /* |
240 | * This is only performed if the channel settings have | |
241 | * actually changed. | |
242 | * | |
243 | * To switch channels clear any pending DMA operations; | |
244 | * wait long enough for the RX fifo to drain, reset the | |
245 | * hardware at the new frequency, and then re-enable | |
246 | * the relevant bits of the h/w. | |
247 | */ | |
4df3071e | 248 | ath9k_hw_disable_interrupts(ah); |
080e1a25 | 249 | stopped = ath_drain_all_txq(sc, false); |
5e848f78 | 250 | |
080e1a25 FF |
251 | if (!ath_stoprecv(sc)) |
252 | stopped = false; | |
ff37e337 | 253 | |
c0d7c7af LR |
254 | /* XXX: do not flush receive queue here. We don't want |
255 | * to flush data frames already in queue because of | |
256 | * changing channel. */ | |
ff37e337 | 257 | |
5ee08656 | 258 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
259 | fastcc = false; |
260 | ||
20bd2a09 FF |
261 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
262 | caldata = &aphy->caldata; | |
263 | ||
226afe68 JP |
264 | ath_dbg(common, ATH_DBG_CONFIG, |
265 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | |
266 | sc->sc_ah->curchan->channel, | |
267 | channel->center_freq, conf_is_ht40(conf), | |
268 | fastcc); | |
ff37e337 | 269 | |
20bd2a09 | 270 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 271 | if (r) { |
3800276a JP |
272 | ath_err(common, |
273 | "Unable to reset channel (%u MHz), reset status %d\n", | |
274 | channel->center_freq, r); | |
3989279c | 275 | goto ps_restore; |
ff37e337 | 276 | } |
c0d7c7af | 277 | |
c0d7c7af | 278 | if (ath_startrecv(sc) != 0) { |
3800276a | 279 | ath_err(common, "Unable to restart recv logic\n"); |
3989279c GJ |
280 | r = -EIO; |
281 | goto ps_restore; | |
c0d7c7af LR |
282 | } |
283 | ||
c0d7c7af | 284 | ath_update_txpow(sc); |
3069168c | 285 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 286 | |
48a6a468 | 287 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
1186488b RM |
288 | if (sc->sc_flags & SC_OP_BEACONS) |
289 | ath_beacon_config(sc, NULL); | |
5ee08656 | 290 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
48a6a468 | 291 | ath_start_ani(common); |
5ee08656 FF |
292 | } |
293 | ||
3989279c | 294 | ps_restore: |
6a6733f2 LR |
295 | spin_unlock_bh(&sc->sc_pcu_lock); |
296 | ||
3cbb5dd7 | 297 | ath9k_ps_restore(sc); |
3989279c | 298 | return r; |
ff37e337 S |
299 | } |
300 | ||
9f42c2b6 FF |
301 | static void ath_paprd_activate(struct ath_softc *sc) |
302 | { | |
303 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 304 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 305 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
306 | int chain; |
307 | ||
20bd2a09 | 308 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
309 | return; |
310 | ||
311 | ath9k_ps_wakeup(sc); | |
ddfef792 | 312 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 313 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 314 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
315 | continue; |
316 | ||
20bd2a09 | 317 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
318 | } |
319 | ||
320 | ar9003_paprd_enable(ah, true); | |
321 | ath9k_ps_restore(sc); | |
322 | } | |
323 | ||
7607cbe2 FF |
324 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
325 | { | |
326 | struct ieee80211_hw *hw = sc->hw; | |
327 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
328 | struct ath_tx_control txctl; | |
329 | int time_left; | |
330 | ||
331 | memset(&txctl, 0, sizeof(txctl)); | |
332 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
333 | ||
334 | memset(tx_info, 0, sizeof(*tx_info)); | |
335 | tx_info->band = hw->conf.channel->band; | |
336 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
337 | tx_info->control.rates[0].idx = 0; | |
338 | tx_info->control.rates[0].count = 1; | |
339 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
340 | tx_info->control.rates[1].idx = -1; | |
341 | ||
342 | init_completion(&sc->paprd_complete); | |
343 | sc->paprd_pending = true; | |
344 | txctl.paprd = BIT(chain); | |
345 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
346 | return false; | |
347 | ||
348 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
349 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
350 | sc->paprd_pending = false; | |
351 | ||
352 | if (!time_left) | |
353 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, | |
354 | "Timeout waiting for paprd training on TX chain %d\n", | |
355 | chain); | |
356 | ||
357 | return !!time_left; | |
358 | } | |
359 | ||
9f42c2b6 FF |
360 | void ath_paprd_calibrate(struct work_struct *work) |
361 | { | |
362 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
363 | struct ieee80211_hw *hw = sc->hw; | |
364 | struct ath_hw *ah = sc->sc_ah; | |
365 | struct ieee80211_hdr *hdr; | |
366 | struct sk_buff *skb = NULL; | |
20bd2a09 | 367 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 368 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 369 | int ftype; |
9f42c2b6 FF |
370 | int chain_ok = 0; |
371 | int chain; | |
372 | int len = 1800; | |
9f42c2b6 | 373 | |
20bd2a09 FF |
374 | if (!caldata) |
375 | return; | |
376 | ||
1bf38661 FF |
377 | if (ar9003_paprd_init_table(ah) < 0) |
378 | return; | |
379 | ||
9f42c2b6 FF |
380 | skb = alloc_skb(len, GFP_KERNEL); |
381 | if (!skb) | |
382 | return; | |
383 | ||
9f42c2b6 FF |
384 | skb_put(skb, len); |
385 | memset(skb->data, 0, len); | |
386 | hdr = (struct ieee80211_hdr *)skb->data; | |
387 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
388 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 389 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
390 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
391 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
392 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
393 | ||
47399f1a | 394 | ath9k_ps_wakeup(sc); |
9f42c2b6 | 395 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 396 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
397 | continue; |
398 | ||
399 | chain_ok = 0; | |
9f42c2b6 | 400 | |
7607cbe2 FF |
401 | ath_dbg(common, ATH_DBG_CALIBRATE, |
402 | "Sending PAPRD frame for thermal measurement " | |
403 | "on chain %d\n", chain); | |
404 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
405 | goto fail_paprd; | |
9f42c2b6 | 406 | |
9f42c2b6 | 407 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 408 | |
7607cbe2 FF |
409 | ath_dbg(common, ATH_DBG_CALIBRATE, |
410 | "Sending PAPRD training frame on chain %d\n", chain); | |
411 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 412 | goto fail_paprd; |
9f42c2b6 FF |
413 | |
414 | if (!ar9003_paprd_is_done(ah)) | |
415 | break; | |
416 | ||
20bd2a09 | 417 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
418 | break; |
419 | ||
420 | chain_ok = 1; | |
421 | } | |
422 | kfree_skb(skb); | |
423 | ||
424 | if (chain_ok) { | |
20bd2a09 | 425 | caldata->paprd_done = true; |
9f42c2b6 FF |
426 | ath_paprd_activate(sc); |
427 | } | |
428 | ||
ca369eb4 | 429 | fail_paprd: |
9f42c2b6 FF |
430 | ath9k_ps_restore(sc); |
431 | } | |
432 | ||
ff37e337 S |
433 | /* |
434 | * This routine performs the periodic noise floor calibration function | |
435 | * that is used to adjust and optimize the chip performance. This | |
436 | * takes environmental changes (location, temperature) into account. | |
437 | * When the task is complete, it reschedules itself depending on the | |
438 | * appropriate interval that was calculated. | |
439 | */ | |
55624204 | 440 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 441 | { |
20977d3e S |
442 | struct ath_softc *sc = (struct ath_softc *)data; |
443 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 444 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
445 | bool longcal = false; |
446 | bool shortcal = false; | |
447 | bool aniflag = false; | |
448 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 449 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 450 | unsigned long flags; |
6044474e FF |
451 | |
452 | if (ah->caldata && ah->caldata->nfcal_interference) | |
453 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
454 | else | |
455 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 456 | |
20977d3e S |
457 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
458 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 459 | |
1ffc1c61 JM |
460 | /* Only calibrate if awake */ |
461 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
462 | goto set_timer; | |
463 | ||
464 | ath9k_ps_wakeup(sc); | |
465 | ||
ff37e337 | 466 | /* Long calibration runs independently of short calibration. */ |
6044474e | 467 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 468 | longcal = true; |
226afe68 | 469 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 470 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
471 | } |
472 | ||
17d7904d | 473 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
474 | if (!common->ani.caldone) { |
475 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 476 | shortcal = true; |
226afe68 JP |
477 | ath_dbg(common, ATH_DBG_ANI, |
478 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
479 | common->ani.shortcal_timer = timestamp; |
480 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
481 | } |
482 | } else { | |
3d536acf | 483 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 484 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
485 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
486 | if (common->ani.caldone) | |
487 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
488 | } |
489 | } | |
490 | ||
491 | /* Verify whether we must check ANI */ | |
e36b27af LR |
492 | if ((timestamp - common->ani.checkani_timer) >= |
493 | ah->config.ani_poll_interval) { | |
ff37e337 | 494 | aniflag = true; |
3d536acf | 495 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
496 | } |
497 | ||
498 | /* Skip all processing if there's nothing to do. */ | |
499 | if (longcal || shortcal || aniflag) { | |
500 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
501 | if (aniflag) { |
502 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 503 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 504 | ath_update_survey_stats(sc); |
b5bfc568 FF |
505 | spin_unlock_irqrestore(&common->cc_lock, flags); |
506 | } | |
ff37e337 S |
507 | |
508 | /* Perform calibration if necessary */ | |
509 | if (longcal || shortcal) { | |
3d536acf | 510 | common->ani.caldone = |
43c27613 LR |
511 | ath9k_hw_calibrate(ah, |
512 | ah->curchan, | |
513 | common->rx_chainmask, | |
514 | longcal); | |
ff37e337 S |
515 | } |
516 | } | |
517 | ||
1ffc1c61 JM |
518 | ath9k_ps_restore(sc); |
519 | ||
20977d3e | 520 | set_timer: |
ff37e337 S |
521 | /* |
522 | * Set timer interval based on previous results. | |
523 | * The interval must be the shortest necessary to satisfy ANI, | |
524 | * short calibration and long calibration. | |
525 | */ | |
aac9207e | 526 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 527 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
528 | cal_interval = min(cal_interval, |
529 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 530 | if (!common->ani.caldone) |
20977d3e | 531 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 532 | |
3d536acf | 533 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
534 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
535 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 536 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 537 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
538 | ath_paprd_activate(sc); |
539 | } | |
ff37e337 S |
540 | } |
541 | ||
ff37e337 S |
542 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
543 | { | |
544 | struct ath_node *an; | |
ea066d5a | 545 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
546 | an = (struct ath_node *)sta->drv_priv; |
547 | ||
ea066d5a MSS |
548 | if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM) |
549 | sc->sc_flags |= SC_OP_ENABLE_APM; | |
550 | ||
87792efc | 551 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 552 | ath_tx_node_init(sc, an); |
9e98ac65 | 553 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
554 | sta->ht_cap.ampdu_factor); |
555 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
556 | } | |
ff37e337 S |
557 | } |
558 | ||
559 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
560 | { | |
561 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
562 | ||
563 | if (sc->sc_flags & SC_OP_TXAGGR) | |
564 | ath_tx_node_cleanup(sc, an); | |
565 | } | |
566 | ||
347809fc FF |
567 | void ath_hw_check(struct work_struct *work) |
568 | { | |
569 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
570 | int i; | |
571 | ||
572 | ath9k_ps_wakeup(sc); | |
573 | ||
574 | for (i = 0; i < 3; i++) { | |
575 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
576 | goto out; | |
577 | ||
578 | msleep(1); | |
579 | } | |
fac6b6a0 | 580 | ath_reset(sc, true); |
347809fc FF |
581 | |
582 | out: | |
583 | ath9k_ps_restore(sc); | |
584 | } | |
585 | ||
55624204 | 586 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
587 | { |
588 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 589 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 590 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 591 | |
17d7904d | 592 | u32 status = sc->intrstatus; |
b5c80475 | 593 | u32 rxmask; |
ff37e337 | 594 | |
153e080d VT |
595 | ath9k_ps_wakeup(sc); |
596 | ||
347809fc | 597 | if (status & ATH9K_INT_FATAL) { |
fac6b6a0 | 598 | ath_reset(sc, true); |
153e080d | 599 | ath9k_ps_restore(sc); |
ff37e337 | 600 | return; |
063d8be3 | 601 | } |
ff37e337 | 602 | |
52671e43 | 603 | spin_lock(&sc->sc_pcu_lock); |
6a6733f2 | 604 | |
347809fc FF |
605 | if (!ath9k_hw_check_alive(ah)) |
606 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
607 | ||
b5c80475 FF |
608 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
609 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
610 | ATH9K_INT_RXORN); | |
611 | else | |
612 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
613 | ||
614 | if (status & rxmask) { | |
b5c80475 FF |
615 | /* Check for high priority Rx first */ |
616 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
617 | (status & ATH9K_INT_RXHP)) | |
618 | ath_rx_tasklet(sc, 0, true); | |
619 | ||
620 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
621 | } |
622 | ||
e5003249 VT |
623 | if (status & ATH9K_INT_TX) { |
624 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
625 | ath_tx_edma_tasklet(sc); | |
626 | else | |
627 | ath_tx_tasklet(sc); | |
628 | } | |
063d8be3 | 629 | |
96148326 | 630 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
631 | /* |
632 | * TSF sync does not look correct; remain awake to sync with | |
633 | * the next Beacon. | |
634 | */ | |
226afe68 JP |
635 | ath_dbg(common, ATH_DBG_PS, |
636 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 637 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
638 | } |
639 | ||
766ec4a9 | 640 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
641 | if (status & ATH9K_INT_GENTIMER) |
642 | ath_gen_timer_isr(sc->sc_ah); | |
643 | ||
ff37e337 | 644 | /* re-enable hardware interrupt */ |
4df3071e | 645 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 646 | |
52671e43 | 647 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 648 | ath9k_ps_restore(sc); |
ff37e337 S |
649 | } |
650 | ||
6baff7f9 | 651 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 652 | { |
063d8be3 S |
653 | #define SCHED_INTR ( \ |
654 | ATH9K_INT_FATAL | \ | |
655 | ATH9K_INT_RXORN | \ | |
656 | ATH9K_INT_RXEOL | \ | |
657 | ATH9K_INT_RX | \ | |
b5c80475 FF |
658 | ATH9K_INT_RXLP | \ |
659 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
660 | ATH9K_INT_TX | \ |
661 | ATH9K_INT_BMISS | \ | |
662 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
663 | ATH9K_INT_TSFOOR | \ |
664 | ATH9K_INT_GENTIMER) | |
063d8be3 | 665 | |
ff37e337 | 666 | struct ath_softc *sc = dev; |
cbe61d8a | 667 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 668 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
669 | enum ath9k_int status; |
670 | bool sched = false; | |
671 | ||
063d8be3 S |
672 | /* |
673 | * The hardware is not ready/present, don't | |
674 | * touch anything. Note this can happen early | |
675 | * on if the IRQ is shared. | |
676 | */ | |
677 | if (sc->sc_flags & SC_OP_INVALID) | |
678 | return IRQ_NONE; | |
ff37e337 | 679 | |
063d8be3 S |
680 | |
681 | /* shared irq, not for us */ | |
682 | ||
153e080d | 683 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 684 | return IRQ_NONE; |
063d8be3 S |
685 | |
686 | /* | |
687 | * Figure out the reason(s) for the interrupt. Note | |
688 | * that the hal returns a pseudo-ISR that may include | |
689 | * bits we haven't explicitly enabled so we mask the | |
690 | * value to insure we only process bits we requested. | |
691 | */ | |
692 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 693 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 694 | |
063d8be3 S |
695 | /* |
696 | * If there are no status bits set, then this interrupt was not | |
697 | * for me (should have been caught above). | |
698 | */ | |
153e080d | 699 | if (!status) |
063d8be3 | 700 | return IRQ_NONE; |
ff37e337 | 701 | |
063d8be3 S |
702 | /* Cache the status */ |
703 | sc->intrstatus = status; | |
704 | ||
705 | if (status & SCHED_INTR) | |
706 | sched = true; | |
707 | ||
708 | /* | |
709 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
710 | * chip immediately. | |
711 | */ | |
b5c80475 FF |
712 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
713 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
714 | goto chip_reset; |
715 | ||
08578b8f LR |
716 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
717 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
718 | |
719 | spin_lock(&common->cc_lock); | |
720 | ath_hw_cycle_counters_update(common); | |
08578b8f | 721 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
722 | spin_unlock(&common->cc_lock); |
723 | ||
08578b8f LR |
724 | goto chip_reset; |
725 | } | |
726 | ||
063d8be3 S |
727 | if (status & ATH9K_INT_SWBA) |
728 | tasklet_schedule(&sc->bcon_tasklet); | |
729 | ||
730 | if (status & ATH9K_INT_TXURN) | |
731 | ath9k_hw_updatetxtriglevel(ah, true); | |
732 | ||
b5c80475 FF |
733 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
734 | if (status & ATH9K_INT_RXEOL) { | |
735 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
736 | ath9k_hw_set_interrupts(ah, ah->imask); | |
737 | } | |
738 | } | |
739 | ||
063d8be3 | 740 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 741 | /* |
063d8be3 S |
742 | * Disable interrupts until we service the MIB |
743 | * interrupt; otherwise it will continue to | |
744 | * fire. | |
ff37e337 | 745 | */ |
4df3071e | 746 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
747 | /* |
748 | * Let the hal handle the event. We assume | |
749 | * it will clear whatever condition caused | |
750 | * the interrupt. | |
751 | */ | |
88eac2da | 752 | spin_lock(&common->cc_lock); |
bfc472bb | 753 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 754 | spin_unlock(&common->cc_lock); |
4df3071e | 755 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 756 | } |
ff37e337 | 757 | |
153e080d VT |
758 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
759 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
760 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
761 | goto chip_reset; | |
063d8be3 S |
762 | /* Clear RxAbort bit so that we can |
763 | * receive frames */ | |
9ecdef4b | 764 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 765 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 766 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 767 | } |
063d8be3 S |
768 | |
769 | chip_reset: | |
ff37e337 | 770 | |
817e11de S |
771 | ath_debug_stat_interrupt(sc, status); |
772 | ||
ff37e337 | 773 | if (sched) { |
4df3071e FF |
774 | /* turn off every interrupt */ |
775 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
776 | tasklet_schedule(&sc->intr_tq); |
777 | } | |
778 | ||
779 | return IRQ_HANDLED; | |
063d8be3 S |
780 | |
781 | #undef SCHED_INTR | |
ff37e337 S |
782 | } |
783 | ||
f078f209 | 784 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 785 | struct ieee80211_channel *chan, |
094d05dc | 786 | enum nl80211_channel_type channel_type) |
f078f209 LR |
787 | { |
788 | u32 chanmode = 0; | |
f078f209 LR |
789 | |
790 | switch (chan->band) { | |
791 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
792 | switch(channel_type) { |
793 | case NL80211_CHAN_NO_HT: | |
794 | case NL80211_CHAN_HT20: | |
f078f209 | 795 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
796 | break; |
797 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 798 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
799 | break; |
800 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 801 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
802 | break; |
803 | } | |
f078f209 LR |
804 | break; |
805 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
806 | switch(channel_type) { |
807 | case NL80211_CHAN_NO_HT: | |
808 | case NL80211_CHAN_HT20: | |
f078f209 | 809 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
810 | break; |
811 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 812 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
813 | break; |
814 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 815 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
816 | break; |
817 | } | |
f078f209 LR |
818 | break; |
819 | default: | |
820 | break; | |
821 | } | |
822 | ||
823 | return chanmode; | |
824 | } | |
825 | ||
8feceb67 | 826 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
9fa23e17 | 827 | struct ieee80211_hw *hw, |
5640b08e | 828 | struct ieee80211_vif *vif, |
8feceb67 | 829 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 830 | { |
9fa23e17 | 831 | struct ath_wiphy *aphy = hw->priv; |
f2b2143e | 832 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 833 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 834 | |
8feceb67 | 835 | if (bss_conf->assoc) { |
226afe68 JP |
836 | ath_dbg(common, ATH_DBG_CONFIG, |
837 | "Bss Info ASSOC %d, bssid: %pM\n", | |
838 | bss_conf->aid, common->curbssid); | |
f078f209 | 839 | |
8feceb67 | 840 | /* New association, store aid */ |
1510718d | 841 | common->curaid = bss_conf->aid; |
f2b2143e | 842 | ath9k_hw_write_associd(ah); |
2664f201 SB |
843 | |
844 | /* | |
845 | * Request a re-configuration of Beacon related timers | |
846 | * on the receipt of the first Beacon frame (i.e., | |
847 | * after time sync with the AP). | |
848 | */ | |
1b04b930 | 849 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 850 | |
8feceb67 | 851 | /* Configure the beacon */ |
2c3db3d5 | 852 | ath_beacon_config(sc, vif); |
f078f209 | 853 | |
8feceb67 | 854 | /* Reset rssi stats */ |
9fa23e17 | 855 | aphy->last_rssi = ATH_RSSI_DUMMY_MARKER; |
22e66a4c | 856 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 857 | |
6c3118e2 | 858 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 859 | ath_start_ani(common); |
8feceb67 | 860 | } else { |
226afe68 | 861 | ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 862 | common->curaid = 0; |
f38faa31 | 863 | /* Stop ANI */ |
6c3118e2 | 864 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 865 | del_timer_sync(&common->ani.timer); |
f078f209 | 866 | } |
8feceb67 | 867 | } |
f078f209 | 868 | |
68a89116 | 869 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 870 | { |
cbe61d8a | 871 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 872 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 873 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 874 | int r; |
500c064d | 875 | |
3cbb5dd7 | 876 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
877 | spin_lock_bh(&sc->sc_pcu_lock); |
878 | ||
93b1b37f | 879 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 880 | |
159cd468 VT |
881 | if (!ah->curchan) |
882 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
883 | ||
20bd2a09 | 884 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 885 | if (r) { |
3800276a JP |
886 | ath_err(common, |
887 | "Unable to reset channel (%u MHz), reset status %d\n", | |
888 | channel->center_freq, r); | |
500c064d | 889 | } |
500c064d VT |
890 | |
891 | ath_update_txpow(sc); | |
892 | if (ath_startrecv(sc) != 0) { | |
3800276a | 893 | ath_err(common, "Unable to restart recv logic\n"); |
c2731b81 | 894 | goto out; |
500c064d | 895 | } |
500c064d | 896 | if (sc->sc_flags & SC_OP_BEACONS) |
2c3db3d5 | 897 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
898 | |
899 | /* Re-Enable interrupts */ | |
3069168c | 900 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
901 | |
902 | /* Enable LED */ | |
08fc5c1b | 903 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 904 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 905 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 906 | |
68a89116 | 907 | ieee80211_wake_queues(hw); |
c2731b81 | 908 | out: |
6a6733f2 LR |
909 | spin_unlock_bh(&sc->sc_pcu_lock); |
910 | ||
3cbb5dd7 | 911 | ath9k_ps_restore(sc); |
500c064d VT |
912 | } |
913 | ||
68a89116 | 914 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 915 | { |
cbe61d8a | 916 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 917 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 918 | int r; |
500c064d | 919 | |
3cbb5dd7 | 920 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
921 | spin_lock_bh(&sc->sc_pcu_lock); |
922 | ||
68a89116 | 923 | ieee80211_stop_queues(hw); |
500c064d | 924 | |
982723df VN |
925 | /* |
926 | * Keep the LED on when the radio is disabled | |
927 | * during idle unassociated state. | |
928 | */ | |
929 | if (!sc->ps_idle) { | |
930 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
931 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
932 | } | |
500c064d VT |
933 | |
934 | /* Disable interrupts */ | |
4df3071e | 935 | ath9k_hw_disable_interrupts(ah); |
500c064d | 936 | |
043a0405 | 937 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 | 938 | |
500c064d VT |
939 | ath_stoprecv(sc); /* turn off frame recv */ |
940 | ath_flushrecv(sc); /* flush recv queue */ | |
941 | ||
159cd468 | 942 | if (!ah->curchan) |
68a89116 | 943 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 944 | |
20bd2a09 | 945 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 946 | if (r) { |
3800276a JP |
947 | ath_err(ath9k_hw_common(sc->sc_ah), |
948 | "Unable to reset channel (%u MHz), reset status %d\n", | |
949 | channel->center_freq, r); | |
500c064d | 950 | } |
500c064d VT |
951 | |
952 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 953 | |
93b1b37f | 954 | ath9k_hw_configpcipowersave(ah, 1, 1); |
6a6733f2 LR |
955 | |
956 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 957 | ath9k_ps_restore(sc); |
6a6733f2 | 958 | |
9ecdef4b | 959 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
960 | } |
961 | ||
ff37e337 S |
962 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
963 | { | |
cbe61d8a | 964 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 965 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 966 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 967 | int r; |
ff37e337 | 968 | |
2ab81d4a S |
969 | /* Stop ANI */ |
970 | del_timer_sync(&common->ani.timer); | |
971 | ||
6a6733f2 LR |
972 | spin_lock_bh(&sc->sc_pcu_lock); |
973 | ||
cc9c378a S |
974 | ieee80211_stop_queues(hw); |
975 | ||
4df3071e | 976 | ath9k_hw_disable_interrupts(ah); |
043a0405 | 977 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 | 978 | |
ff37e337 S |
979 | ath_stoprecv(sc); |
980 | ath_flushrecv(sc); | |
981 | ||
20bd2a09 | 982 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 983 | if (r) |
3800276a JP |
984 | ath_err(common, |
985 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
986 | |
987 | if (ath_startrecv(sc) != 0) | |
3800276a | 988 | ath_err(common, "Unable to start recv logic\n"); |
ff37e337 S |
989 | |
990 | /* | |
991 | * We may be doing a reset in response to a request | |
992 | * that changes the channel so update any state that | |
993 | * might change as a result. | |
994 | */ | |
ff37e337 S |
995 | ath_update_txpow(sc); |
996 | ||
52b8ac92 | 997 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 998 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 999 | |
3069168c | 1000 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1001 | |
1002 | if (retry_tx) { | |
1003 | int i; | |
1004 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1005 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1006 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1007 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1008 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1009 | } |
1010 | } | |
1011 | } | |
1012 | ||
cc9c378a | 1013 | ieee80211_wake_queues(hw); |
6a6733f2 | 1014 | spin_unlock_bh(&sc->sc_pcu_lock); |
cc9c378a | 1015 | |
2ab81d4a S |
1016 | /* Start ANI */ |
1017 | ath_start_ani(common); | |
1018 | ||
ae8d2858 | 1019 | return r; |
ff37e337 S |
1020 | } |
1021 | ||
5f8e077c LR |
1022 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1023 | * this redundant data */ | |
0e2dedf9 JM |
1024 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1025 | struct ath9k_channel *ichan) | |
5f8e077c | 1026 | { |
5f8e077c LR |
1027 | struct ieee80211_channel *chan = hw->conf.channel; |
1028 | struct ieee80211_conf *conf = &hw->conf; | |
1029 | ||
1030 | ichan->channel = chan->center_freq; | |
1031 | ichan->chan = chan; | |
1032 | ||
1033 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1034 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1035 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1036 | } else { |
1037 | ichan->chanmode = CHANNEL_A; | |
1038 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1039 | } | |
1040 | ||
25c56eec | 1041 | if (conf_is_ht(conf)) |
5f8e077c LR |
1042 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1043 | conf->channel_type); | |
5f8e077c LR |
1044 | } |
1045 | ||
ff37e337 S |
1046 | /**********************/ |
1047 | /* mac80211 callbacks */ | |
1048 | /**********************/ | |
1049 | ||
8feceb67 | 1050 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1051 | { |
bce048d7 JM |
1052 | struct ath_wiphy *aphy = hw->priv; |
1053 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1054 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1055 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1056 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1057 | struct ath9k_channel *init_channel; |
82880a7c | 1058 | int r; |
f078f209 | 1059 | |
226afe68 JP |
1060 | ath_dbg(common, ATH_DBG_CONFIG, |
1061 | "Starting driver with initial channel: %d MHz\n", | |
1062 | curchan->center_freq); | |
f078f209 | 1063 | |
141b38b6 S |
1064 | mutex_lock(&sc->mutex); |
1065 | ||
9580a222 JM |
1066 | if (ath9k_wiphy_started(sc)) { |
1067 | if (sc->chan_idx == curchan->hw_value) { | |
1068 | /* | |
1069 | * Already on the operational channel, the new wiphy | |
1070 | * can be marked active. | |
1071 | */ | |
1072 | aphy->state = ATH_WIPHY_ACTIVE; | |
1073 | ieee80211_wake_queues(hw); | |
1074 | } else { | |
1075 | /* | |
1076 | * Another wiphy is on another channel, start the new | |
1077 | * wiphy in paused state. | |
1078 | */ | |
1079 | aphy->state = ATH_WIPHY_PAUSED; | |
1080 | ieee80211_stop_queues(hw); | |
1081 | } | |
1082 | mutex_unlock(&sc->mutex); | |
1083 | return 0; | |
1084 | } | |
1085 | aphy->state = ATH_WIPHY_ACTIVE; | |
1086 | ||
8feceb67 | 1087 | /* setup initial channel */ |
f078f209 | 1088 | |
82880a7c | 1089 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1090 | |
82880a7c | 1091 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1092 | |
1093 | /* Reset SERDES registers */ | |
af03abec | 1094 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1095 | |
1096 | /* | |
1097 | * The basic interface to setting the hardware in a good | |
1098 | * state is ``reset''. On return the hardware is known to | |
1099 | * be powered up and with interrupts disabled. This must | |
1100 | * be followed by initialization of the appropriate bits | |
1101 | * and then setup of the interrupt mask. | |
1102 | */ | |
4bdd1e97 | 1103 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1104 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1105 | if (r) { |
3800276a JP |
1106 | ath_err(common, |
1107 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1108 | r, curchan->center_freq); | |
4bdd1e97 | 1109 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1110 | goto mutex_unlock; |
ff37e337 | 1111 | } |
ff37e337 S |
1112 | |
1113 | /* | |
1114 | * This is needed only to setup initial state | |
1115 | * but it's best done after a reset. | |
1116 | */ | |
1117 | ath_update_txpow(sc); | |
8feceb67 | 1118 | |
ff37e337 S |
1119 | /* |
1120 | * Setup the hardware after reset: | |
1121 | * The receive engine is set going. | |
1122 | * Frame transmit is handled entirely | |
1123 | * in the frame output path; there's nothing to do | |
1124 | * here except setup the interrupt mask. | |
1125 | */ | |
1126 | if (ath_startrecv(sc) != 0) { | |
3800276a | 1127 | ath_err(common, "Unable to start recv logic\n"); |
141b38b6 | 1128 | r = -EIO; |
4bdd1e97 | 1129 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1130 | goto mutex_unlock; |
f078f209 | 1131 | } |
4bdd1e97 | 1132 | spin_unlock_bh(&sc->sc_pcu_lock); |
8feceb67 | 1133 | |
ff37e337 | 1134 | /* Setup our intr mask. */ |
b5c80475 FF |
1135 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1136 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1137 | ATH9K_INT_GLOBAL; | |
1138 | ||
1139 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1140 | ah->imask |= ATH9K_INT_RXHP | |
1141 | ATH9K_INT_RXLP | | |
1142 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1143 | else |
1144 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1145 | |
364734fa | 1146 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1147 | |
af03abec | 1148 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1149 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1150 | |
ff37e337 | 1151 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1152 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1153 | |
1154 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1155 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1156 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1157 | |
bce048d7 | 1158 | ieee80211_wake_queues(hw); |
ff37e337 | 1159 | |
42935eca | 1160 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1161 | |
766ec4a9 LR |
1162 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1163 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1164 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1165 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1166 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1167 | |
5bb12791 LR |
1168 | if (common->bus_ops->bt_coex_prep) |
1169 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1170 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1171 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1172 | } |
1173 | ||
2b7e6bce MSS |
1174 | /* User has the option to provide pm-qos value as a module |
1175 | * parameter rather than using the default value of | |
1176 | * 'ATH9K_PM_QOS_DEFAULT_VALUE'. | |
1177 | */ | |
4dc3530d | 1178 | pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value); |
10598c12 | 1179 | |
8060e169 VT |
1180 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1181 | common->bus_ops->extn_synch_en(common); | |
1182 | ||
141b38b6 S |
1183 | mutex_unlock: |
1184 | mutex_unlock(&sc->mutex); | |
1185 | ||
ae8d2858 | 1186 | return r; |
f078f209 LR |
1187 | } |
1188 | ||
8feceb67 VT |
1189 | static int ath9k_tx(struct ieee80211_hw *hw, |
1190 | struct sk_buff *skb) | |
f078f209 | 1191 | { |
bce048d7 JM |
1192 | struct ath_wiphy *aphy = hw->priv; |
1193 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1194 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1195 | struct ath_tx_control txctl; |
1bc14880 | 1196 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1197 | |
8089cc47 | 1198 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
226afe68 JP |
1199 | ath_dbg(common, ATH_DBG_XMIT, |
1200 | "ath9k: %s: TX in unexpected wiphy state %d\n", | |
1201 | wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1202 | goto exit; |
1203 | } | |
1204 | ||
96148326 | 1205 | if (sc->ps_enabled) { |
dc8c4585 JM |
1206 | /* |
1207 | * mac80211 does not set PM field for normal data frames, so we | |
1208 | * need to update that based on the current PS mode. | |
1209 | */ | |
1210 | if (ieee80211_is_data(hdr->frame_control) && | |
1211 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1212 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1213 | ath_dbg(common, ATH_DBG_PS, |
1214 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1215 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1216 | } | |
1217 | } | |
1218 | ||
9a23f9ca JM |
1219 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1220 | /* | |
1221 | * We are using PS-Poll and mac80211 can request TX while in | |
1222 | * power save mode. Need to wake up hardware for the TX to be | |
1223 | * completed and if needed, also for RX of buffered frames. | |
1224 | */ | |
9a23f9ca | 1225 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1226 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1227 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1228 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1229 | ath_dbg(common, ATH_DBG_PS, |
1230 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1231 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1232 | } else { |
226afe68 JP |
1233 | ath_dbg(common, ATH_DBG_PS, |
1234 | "Wake up to complete TX\n"); | |
1b04b930 | 1235 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1236 | } |
1237 | /* | |
1238 | * The actual restore operation will happen only after | |
1239 | * the sc_flags bit is cleared. We are just dropping | |
1240 | * the ps_usecount here. | |
1241 | */ | |
1242 | ath9k_ps_restore(sc); | |
1243 | } | |
1244 | ||
528f0c6b | 1245 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1246 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1247 | |
226afe68 | 1248 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1249 | |
c52f33d0 | 1250 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1251 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1252 | goto exit; |
8feceb67 VT |
1253 | } |
1254 | ||
528f0c6b S |
1255 | return 0; |
1256 | exit: | |
1257 | dev_kfree_skb_any(skb); | |
8feceb67 | 1258 | return 0; |
f078f209 LR |
1259 | } |
1260 | ||
8feceb67 | 1261 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1262 | { |
bce048d7 JM |
1263 | struct ath_wiphy *aphy = hw->priv; |
1264 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1265 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1266 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1267 | int i; |
f078f209 | 1268 | |
4c483817 S |
1269 | mutex_lock(&sc->mutex); |
1270 | ||
9580a222 JM |
1271 | aphy->state = ATH_WIPHY_INACTIVE; |
1272 | ||
9a75c2ff VN |
1273 | if (led_blink) |
1274 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1275 | ||
c94dbff7 | 1276 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1277 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1278 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1279 | |
447a42c2 RM |
1280 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1281 | if (sc->sec_wiphy[i]) | |
1282 | break; | |
1283 | } | |
1284 | ||
1285 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1286 | cancel_delayed_work_sync(&sc->wiphy_work); |
1287 | cancel_work_sync(&sc->chan_work); | |
1288 | } | |
1289 | ||
9c84b797 | 1290 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1291 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1292 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1293 | return; |
1294 | } | |
8feceb67 | 1295 | |
9580a222 JM |
1296 | if (ath9k_wiphy_started(sc)) { |
1297 | mutex_unlock(&sc->mutex); | |
1298 | return; /* another wiphy still in use */ | |
1299 | } | |
1300 | ||
3867cf6a S |
1301 | /* Ensure HW is awake when we try to shut it down. */ |
1302 | ath9k_ps_wakeup(sc); | |
1303 | ||
766ec4a9 | 1304 | if (ah->btcoex_hw.enabled) { |
af03abec | 1305 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1306 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1307 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1308 | } |
1309 | ||
6a6733f2 LR |
1310 | spin_lock_bh(&sc->sc_pcu_lock); |
1311 | ||
ff37e337 S |
1312 | /* make sure h/w will not generate any interrupt |
1313 | * before setting the invalid flag. */ | |
4df3071e | 1314 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1315 | |
1316 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1317 | ath_drain_all_txq(sc, false); |
ff37e337 | 1318 | ath_stoprecv(sc); |
af03abec | 1319 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1320 | } else |
b77f483f | 1321 | sc->rx.rxlink = NULL; |
ff37e337 | 1322 | |
ff37e337 | 1323 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1324 | ath9k_hw_disable(ah); |
1325 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
6a6733f2 LR |
1326 | |
1327 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1328 | ||
3867cf6a S |
1329 | ath9k_ps_restore(sc); |
1330 | ||
a08e7ade | 1331 | sc->ps_idle = true; |
afe68d0a | 1332 | ath9k_set_wiphy_idle(aphy, true); |
a08e7ade | 1333 | ath_radio_disable(sc, hw); |
ff37e337 S |
1334 | |
1335 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1336 | |
98c316e3 | 1337 | pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE); |
10598c12 | 1338 | |
141b38b6 S |
1339 | mutex_unlock(&sc->mutex); |
1340 | ||
226afe68 | 1341 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1342 | } |
1343 | ||
8feceb67 | 1344 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1345 | struct ieee80211_vif *vif) |
f078f209 | 1346 | { |
bce048d7 JM |
1347 | struct ath_wiphy *aphy = hw->priv; |
1348 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1349 | struct ath_hw *ah = sc->sc_ah; |
1350 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1351 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1352 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1353 | int ret = 0; |
8feceb67 | 1354 | |
141b38b6 S |
1355 | mutex_lock(&sc->mutex); |
1356 | ||
1ed32e4f | 1357 | switch (vif->type) { |
05c914fe | 1358 | case NL80211_IFTYPE_STATION: |
d97809db | 1359 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1360 | break; |
e51f3eff BJ |
1361 | case NL80211_IFTYPE_WDS: |
1362 | ic_opmode = NL80211_IFTYPE_WDS; | |
1363 | break; | |
05c914fe | 1364 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1365 | case NL80211_IFTYPE_AP: |
9cb5412b | 1366 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1367 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1368 | ret = -ENOBUFS; | |
1369 | goto out; | |
1370 | } | |
1ed32e4f | 1371 | ic_opmode = vif->type; |
f078f209 LR |
1372 | break; |
1373 | default: | |
3800276a JP |
1374 | ath_err(common, "Interface type %d not yet supported\n", |
1375 | vif->type); | |
2c3db3d5 JM |
1376 | ret = -EOPNOTSUPP; |
1377 | goto out; | |
f078f209 LR |
1378 | } |
1379 | ||
226afe68 JP |
1380 | ath_dbg(common, ATH_DBG_CONFIG, |
1381 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1382 | |
17d7904d | 1383 | /* Set the VIF opmode */ |
5640b08e S |
1384 | avp->av_opmode = ic_opmode; |
1385 | avp->av_bslot = -1; | |
1386 | ||
2c3db3d5 | 1387 | sc->nvifs++; |
8ca21f01 | 1388 | |
364734fa | 1389 | ath9k_set_bssid_mask(hw, vif); |
8ca21f01 | 1390 | |
2c3db3d5 JM |
1391 | if (sc->nvifs > 1) |
1392 | goto out; /* skip global settings for secondary vif */ | |
1393 | ||
b238e90e | 1394 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1395 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1396 | sc->sc_flags |= SC_OP_TSF_RESET; |
1397 | } | |
5640b08e | 1398 | |
5640b08e | 1399 | /* Set the device opmode */ |
3069168c | 1400 | ah->opmode = ic_opmode; |
5640b08e | 1401 | |
4e30ffa2 VN |
1402 | /* |
1403 | * Enable MIB interrupts when there are hardware phy counters. | |
1404 | * Note we only do this (at the moment) for station mode. | |
1405 | */ | |
1ed32e4f JB |
1406 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1407 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1408 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1409 | if (ah->config.enable_ani) |
1410 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1411 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1412 | } |
1413 | ||
3069168c | 1414 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1415 | |
1ed32e4f | 1416 | if (vif->type == NL80211_IFTYPE_AP || |
5f841b41 | 1417 | vif->type == NL80211_IFTYPE_ADHOC) { |
6c3118e2 | 1418 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 1419 | ath_start_ani(common); |
6c3118e2 | 1420 | } |
6f255425 | 1421 | |
2c3db3d5 | 1422 | out: |
141b38b6 | 1423 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1424 | return ret; |
f078f209 LR |
1425 | } |
1426 | ||
6b3b991d RM |
1427 | static void ath9k_reclaim_beacon(struct ath_softc *sc, |
1428 | struct ieee80211_vif *vif) | |
1429 | { | |
1430 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1431 | ||
1432 | /* Disable SWBA interrupt */ | |
1433 | sc->sc_ah->imask &= ~ATH9K_INT_SWBA; | |
1434 | ath9k_ps_wakeup(sc); | |
1435 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); | |
1436 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1437 | tasklet_kill(&sc->bcon_tasklet); | |
1438 | ath9k_ps_restore(sc); | |
1439 | ||
1440 | ath_beacon_return(sc, avp); | |
1441 | sc->sc_flags &= ~SC_OP_BEACONS; | |
1442 | ||
1443 | if (sc->nbcnvifs > 0) { | |
1444 | /* Re-enable beaconing */ | |
1445 | sc->sc_ah->imask |= ATH9K_INT_SWBA; | |
1446 | ath9k_ps_wakeup(sc); | |
1447 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); | |
1448 | ath9k_ps_restore(sc); | |
1449 | } | |
1450 | } | |
1451 | ||
1452 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1453 | struct ieee80211_vif *vif, | |
1454 | enum nl80211_iftype new_type, | |
1455 | bool p2p) | |
1456 | { | |
1457 | struct ath_wiphy *aphy = hw->priv; | |
1458 | struct ath_softc *sc = aphy->sc; | |
1459 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
6dab55bf | 1460 | int ret = 0; |
6b3b991d RM |
1461 | |
1462 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1463 | mutex_lock(&sc->mutex); | |
1464 | ||
1465 | switch (new_type) { | |
1466 | case NL80211_IFTYPE_AP: | |
1467 | case NL80211_IFTYPE_ADHOC: | |
1468 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1469 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1470 | ret = -ENOBUFS; |
1471 | goto out; | |
6b3b991d RM |
1472 | } |
1473 | break; | |
1474 | case NL80211_IFTYPE_STATION: | |
1475 | /* Stop ANI */ | |
1476 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1477 | del_timer_sync(&common->ani.timer); | |
1478 | if ((vif->type == NL80211_IFTYPE_AP) || | |
1479 | (vif->type == NL80211_IFTYPE_ADHOC)) | |
1480 | ath9k_reclaim_beacon(sc, vif); | |
1481 | break; | |
1482 | default: | |
1483 | ath_err(common, "Interface type %d not yet supported\n", | |
1484 | vif->type); | |
6dab55bf DC |
1485 | ret = -ENOTSUPP; |
1486 | goto out; | |
6b3b991d RM |
1487 | } |
1488 | vif->type = new_type; | |
1489 | vif->p2p = p2p; | |
1490 | ||
6dab55bf | 1491 | out: |
6b3b991d | 1492 | mutex_unlock(&sc->mutex); |
6dab55bf | 1493 | return ret; |
6b3b991d RM |
1494 | } |
1495 | ||
8feceb67 | 1496 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1497 | struct ieee80211_vif *vif) |
f078f209 | 1498 | { |
bce048d7 JM |
1499 | struct ath_wiphy *aphy = hw->priv; |
1500 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1501 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1502 | |
226afe68 | 1503 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1504 | |
141b38b6 S |
1505 | mutex_lock(&sc->mutex); |
1506 | ||
6f255425 | 1507 | /* Stop ANI */ |
6c3118e2 | 1508 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1509 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1510 | |
8feceb67 | 1511 | /* Reclaim beacon resources */ |
9cb5412b PE |
1512 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1513 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
6b3b991d RM |
1514 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) |
1515 | ath9k_reclaim_beacon(sc, vif); | |
2c3db3d5 | 1516 | |
17d7904d | 1517 | sc->nvifs--; |
141b38b6 S |
1518 | |
1519 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1520 | } |
1521 | ||
fbab7390 | 1522 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1523 | { |
3069168c PR |
1524 | struct ath_hw *ah = sc->sc_ah; |
1525 | ||
3f7c5c10 | 1526 | sc->ps_enabled = true; |
3069168c PR |
1527 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1528 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1529 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1530 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1531 | } |
fdf76622 | 1532 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1533 | } |
3f7c5c10 SB |
1534 | } |
1535 | ||
845d708e SB |
1536 | static void ath9k_disable_ps(struct ath_softc *sc) |
1537 | { | |
1538 | struct ath_hw *ah = sc->sc_ah; | |
1539 | ||
1540 | sc->ps_enabled = false; | |
1541 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1542 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1543 | ath9k_hw_setrxabort(ah, 0); | |
1544 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1545 | PS_WAIT_FOR_CAB | | |
1546 | PS_WAIT_FOR_PSPOLL_DATA | | |
1547 | PS_WAIT_FOR_TX_ACK); | |
1548 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1549 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1550 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1551 | } | |
1552 | } | |
1553 | ||
1554 | } | |
1555 | ||
e8975581 | 1556 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1557 | { |
bce048d7 JM |
1558 | struct ath_wiphy *aphy = hw->priv; |
1559 | struct ath_softc *sc = aphy->sc; | |
3430098a FF |
1560 | struct ath_hw *ah = sc->sc_ah; |
1561 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1562 | struct ieee80211_conf *conf = &hw->conf; |
194b7c13 | 1563 | bool disable_radio; |
f078f209 | 1564 | |
aa33de09 | 1565 | mutex_lock(&sc->mutex); |
141b38b6 | 1566 | |
194b7c13 LR |
1567 | /* |
1568 | * Leave this as the first check because we need to turn on the | |
1569 | * radio if it was disabled before prior to processing the rest | |
1570 | * of the changes. Likewise we must only disable the radio towards | |
1571 | * the end. | |
1572 | */ | |
64839170 | 1573 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1574 | bool enable_radio; |
1575 | bool all_wiphys_idle; | |
1576 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1577 | |
1578 | spin_lock_bh(&sc->wiphy_lock); | |
1579 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1580 | ath9k_set_wiphy_idle(aphy, idle); |
1581 | ||
11446011 | 1582 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1583 | |
1584 | /* | |
1585 | * After we unlock here its possible another wiphy | |
1586 | * can be re-renabled so to account for that we will | |
1587 | * only disable the radio toward the end of this routine | |
1588 | * if by then all wiphys are still idle. | |
1589 | */ | |
64839170 LR |
1590 | spin_unlock_bh(&sc->wiphy_lock); |
1591 | ||
194b7c13 | 1592 | if (enable_radio) { |
1dbfd9d4 | 1593 | sc->ps_idle = false; |
68a89116 | 1594 | ath_radio_enable(sc, hw); |
226afe68 JP |
1595 | ath_dbg(common, ATH_DBG_CONFIG, |
1596 | "not-idle: enabling radio\n"); | |
64839170 LR |
1597 | } |
1598 | } | |
1599 | ||
e7824a50 LR |
1600 | /* |
1601 | * We just prepare to enable PS. We have to wait until our AP has | |
1602 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1603 | * those ACKs and end up retransmitting the same null data frames. | |
1604 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1605 | */ | |
3cbb5dd7 | 1606 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1607 | unsigned long flags; |
1608 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1609 | if (conf->flags & IEEE80211_CONF_PS) |
1610 | ath9k_enable_ps(sc); | |
845d708e SB |
1611 | else |
1612 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1613 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1614 | } |
1615 | ||
199afd9d S |
1616 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1617 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1618 | ath_dbg(common, ATH_DBG_CONFIG, |
1619 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1620 | sc->sc_ah->is_monitoring = true; |
1621 | } else { | |
226afe68 JP |
1622 | ath_dbg(common, ATH_DBG_CONFIG, |
1623 | "Monitor mode is disabled\n"); | |
5f841b41 | 1624 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1625 | } |
1626 | } | |
1627 | ||
4797938c | 1628 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1629 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1630 | int pos = curchan->hw_value; |
3430098a FF |
1631 | int old_pos = -1; |
1632 | unsigned long flags; | |
1633 | ||
1634 | if (ah->curchan) | |
1635 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1636 | |
0e2dedf9 JM |
1637 | aphy->chan_idx = pos; |
1638 | aphy->chan_is_ht = conf_is_ht(conf); | |
5ee08656 FF |
1639 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1640 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1641 | else | |
1642 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1643 | |
8089cc47 JM |
1644 | if (aphy->state == ATH_WIPHY_SCAN || |
1645 | aphy->state == ATH_WIPHY_ACTIVE) | |
1646 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1647 | else { | |
1648 | /* | |
1649 | * Do not change operational channel based on a paused | |
1650 | * wiphy changes. | |
1651 | */ | |
1652 | goto skip_chan_change; | |
1653 | } | |
0e2dedf9 | 1654 | |
226afe68 JP |
1655 | ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1656 | curchan->center_freq); | |
f078f209 | 1657 | |
5f8e077c | 1658 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1659 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1660 | |
3430098a FF |
1661 | /* update survey stats for the old channel before switching */ |
1662 | spin_lock_irqsave(&common->cc_lock, flags); | |
1663 | ath_update_survey_stats(sc); | |
1664 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1665 | ||
1666 | /* | |
1667 | * If the operating channel changes, change the survey in-use flags | |
1668 | * along with it. | |
1669 | * Reset the survey data for the new channel, unless we're switching | |
1670 | * back to the operating channel from an off-channel operation. | |
1671 | */ | |
1672 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1673 | sc->cur_survey != &sc->survey[pos]) { | |
1674 | ||
1675 | if (sc->cur_survey) | |
1676 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1677 | ||
1678 | sc->cur_survey = &sc->survey[pos]; | |
1679 | ||
1680 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1681 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1682 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1683 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1684 | } | |
1685 | ||
0e2dedf9 | 1686 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1687 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1688 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1689 | return -EINVAL; |
1690 | } | |
3430098a FF |
1691 | |
1692 | /* | |
1693 | * The most recent snapshot of channel->noisefloor for the old | |
1694 | * channel is only available after the hardware reset. Copy it to | |
1695 | * the survey stats now. | |
1696 | */ | |
1697 | if (old_pos >= 0) | |
1698 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1699 | } |
f078f209 | 1700 | |
8089cc47 | 1701 | skip_chan_change: |
c9f6a656 | 1702 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1703 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1704 | ath_update_txpow(sc); |
1705 | } | |
f078f209 | 1706 | |
194b7c13 LR |
1707 | spin_lock_bh(&sc->wiphy_lock); |
1708 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1709 | spin_unlock_bh(&sc->wiphy_lock); | |
1710 | ||
64839170 | 1711 | if (disable_radio) { |
226afe68 | 1712 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1713 | sc->ps_idle = true; |
68a89116 | 1714 | ath_radio_disable(sc, hw); |
64839170 LR |
1715 | } |
1716 | ||
aa33de09 | 1717 | mutex_unlock(&sc->mutex); |
141b38b6 | 1718 | |
f078f209 LR |
1719 | return 0; |
1720 | } | |
1721 | ||
8feceb67 VT |
1722 | #define SUPPORTED_FILTERS \ |
1723 | (FIF_PROMISC_IN_BSS | \ | |
1724 | FIF_ALLMULTI | \ | |
1725 | FIF_CONTROL | \ | |
af6a3fc7 | 1726 | FIF_PSPOLL | \ |
8feceb67 VT |
1727 | FIF_OTHER_BSS | \ |
1728 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1729 | FIF_PROBE_REQ | \ |
8feceb67 | 1730 | FIF_FCSFAIL) |
c83be688 | 1731 | |
8feceb67 VT |
1732 | /* FIXME: sc->sc_full_reset ? */ |
1733 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1734 | unsigned int changed_flags, | |
1735 | unsigned int *total_flags, | |
3ac64bee | 1736 | u64 multicast) |
8feceb67 | 1737 | { |
bce048d7 JM |
1738 | struct ath_wiphy *aphy = hw->priv; |
1739 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1740 | u32 rfilt; |
f078f209 | 1741 | |
8feceb67 VT |
1742 | changed_flags &= SUPPORTED_FILTERS; |
1743 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1744 | |
b77f483f | 1745 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1746 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1747 | rfilt = ath_calcrxfilter(sc); |
1748 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1749 | ath9k_ps_restore(sc); |
f078f209 | 1750 | |
226afe68 JP |
1751 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1752 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1753 | } |
f078f209 | 1754 | |
4ca77860 JB |
1755 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1756 | struct ieee80211_vif *vif, | |
1757 | struct ieee80211_sta *sta) | |
8feceb67 | 1758 | { |
bce048d7 JM |
1759 | struct ath_wiphy *aphy = hw->priv; |
1760 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1761 | |
4ca77860 JB |
1762 | ath_node_attach(sc, sta); |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1768 | struct ieee80211_vif *vif, | |
1769 | struct ieee80211_sta *sta) | |
1770 | { | |
1771 | struct ath_wiphy *aphy = hw->priv; | |
1772 | struct ath_softc *sc = aphy->sc; | |
1773 | ||
1774 | ath_node_detach(sc, sta); | |
1775 | ||
1776 | return 0; | |
f078f209 LR |
1777 | } |
1778 | ||
141b38b6 | 1779 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1780 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1781 | { |
bce048d7 JM |
1782 | struct ath_wiphy *aphy = hw->priv; |
1783 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1784 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1785 | struct ath_txq *txq; |
8feceb67 | 1786 | struct ath9k_tx_queue_info qi; |
066dae93 | 1787 | int ret = 0; |
f078f209 | 1788 | |
8feceb67 VT |
1789 | if (queue >= WME_NUM_AC) |
1790 | return 0; | |
f078f209 | 1791 | |
066dae93 FF |
1792 | txq = sc->tx.txq_map[queue]; |
1793 | ||
141b38b6 S |
1794 | mutex_lock(&sc->mutex); |
1795 | ||
1ffb0610 S |
1796 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1797 | ||
8feceb67 VT |
1798 | qi.tqi_aifs = params->aifs; |
1799 | qi.tqi_cwmin = params->cw_min; | |
1800 | qi.tqi_cwmax = params->cw_max; | |
1801 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1802 | |
226afe68 JP |
1803 | ath_dbg(common, ATH_DBG_CONFIG, |
1804 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1805 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1806 | params->cw_max, params->txop); | |
f078f209 | 1807 | |
066dae93 | 1808 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1809 | if (ret) |
3800276a | 1810 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1811 | |
94db2936 | 1812 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1813 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1814 | ath_beaconq_config(sc); |
1815 | ||
141b38b6 S |
1816 | mutex_unlock(&sc->mutex); |
1817 | ||
8feceb67 VT |
1818 | return ret; |
1819 | } | |
f078f209 | 1820 | |
8feceb67 VT |
1821 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1822 | enum set_key_cmd cmd, | |
dc822b5d JB |
1823 | struct ieee80211_vif *vif, |
1824 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1825 | struct ieee80211_key_conf *key) |
1826 | { | |
bce048d7 JM |
1827 | struct ath_wiphy *aphy = hw->priv; |
1828 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1829 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1830 | int ret = 0; |
f078f209 | 1831 | |
b3bd89ce JM |
1832 | if (modparam_nohwcrypt) |
1833 | return -ENOSPC; | |
1834 | ||
141b38b6 | 1835 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1836 | ath9k_ps_wakeup(sc); |
226afe68 | 1837 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1838 | |
8feceb67 VT |
1839 | switch (cmd) { |
1840 | case SET_KEY: | |
040e539e | 1841 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1842 | if (ret >= 0) { |
1843 | key->hw_key_idx = ret; | |
8feceb67 VT |
1844 | /* push IV and Michael MIC generation to stack */ |
1845 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1846 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1847 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1848 | if (sc->sc_ah->sw_mgmt_crypto && |
1849 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1850 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1851 | ret = 0; |
8feceb67 VT |
1852 | } |
1853 | break; | |
1854 | case DISABLE_KEY: | |
040e539e | 1855 | ath_key_delete(common, key); |
8feceb67 VT |
1856 | break; |
1857 | default: | |
1858 | ret = -EINVAL; | |
1859 | } | |
f078f209 | 1860 | |
3cbb5dd7 | 1861 | ath9k_ps_restore(sc); |
141b38b6 S |
1862 | mutex_unlock(&sc->mutex); |
1863 | ||
8feceb67 VT |
1864 | return ret; |
1865 | } | |
f078f209 | 1866 | |
8feceb67 VT |
1867 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1868 | struct ieee80211_vif *vif, | |
1869 | struct ieee80211_bss_conf *bss_conf, | |
1870 | u32 changed) | |
1871 | { | |
bce048d7 JM |
1872 | struct ath_wiphy *aphy = hw->priv; |
1873 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1874 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1875 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1876 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1877 | int slottime; |
c6089ccc | 1878 | int error; |
f078f209 | 1879 | |
141b38b6 S |
1880 | mutex_lock(&sc->mutex); |
1881 | ||
c6089ccc S |
1882 | if (changed & BSS_CHANGED_BSSID) { |
1883 | /* Set BSSID */ | |
1884 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1885 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1886 | common->curaid = 0; |
f2b2143e | 1887 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1888 | |
c6089ccc S |
1889 | /* Set aggregation protection mode parameters */ |
1890 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1891 | |
226afe68 JP |
1892 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
1893 | common->curbssid, common->curaid); | |
2d0ddec5 | 1894 | |
c6089ccc S |
1895 | /* need to reconfigure the beacon */ |
1896 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1897 | } | |
2d0ddec5 | 1898 | |
c6089ccc S |
1899 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1900 | if ((changed & BSS_CHANGED_BEACON) || | |
1901 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1902 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1903 | error = ath_beacon_alloc(aphy, vif); | |
1904 | if (!error) | |
1905 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1906 | } |
1907 | ||
1908 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1909 | if (bss_conf->use_short_slot) | |
1910 | slottime = 9; | |
1911 | else | |
1912 | slottime = 20; | |
1913 | if (vif->type == NL80211_IFTYPE_AP) { | |
1914 | /* | |
1915 | * Defer update, so that connected stations can adjust | |
1916 | * their settings at the same time. | |
1917 | * See beacon.c for more details | |
1918 | */ | |
1919 | sc->beacon.slottime = slottime; | |
1920 | sc->beacon.updateslot = UPDATE; | |
1921 | } else { | |
1922 | ah->slottime = slottime; | |
1923 | ath9k_hw_init_global_settings(ah); | |
1924 | } | |
2d0ddec5 JB |
1925 | } |
1926 | ||
c6089ccc S |
1927 | /* Disable transmission of beacons */ |
1928 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1929 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1930 | |
c6089ccc S |
1931 | if (changed & BSS_CHANGED_BEACON_INT) { |
1932 | sc->beacon_interval = bss_conf->beacon_int; | |
1933 | /* | |
1934 | * In case of AP mode, the HW TSF has to be reset | |
1935 | * when the beacon interval changes. | |
1936 | */ | |
1937 | if (vif->type == NL80211_IFTYPE_AP) { | |
1938 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1939 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1940 | error = ath_beacon_alloc(aphy, vif); |
1941 | if (!error) | |
1942 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1943 | } else { |
1944 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1945 | } |
1946 | } | |
1947 | ||
8feceb67 | 1948 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
1949 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1950 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1951 | if (bss_conf->use_short_preamble) |
1952 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1953 | else | |
1954 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1955 | } | |
f078f209 | 1956 | |
8feceb67 | 1957 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
1958 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1959 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1960 | if (bss_conf->use_cts_prot && |
1961 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1962 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1963 | else | |
1964 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1965 | } | |
f078f209 | 1966 | |
8feceb67 | 1967 | if (changed & BSS_CHANGED_ASSOC) { |
226afe68 | 1968 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1969 | bss_conf->assoc); |
9fa23e17 | 1970 | ath9k_bss_assoc_info(sc, hw, vif, bss_conf); |
8feceb67 | 1971 | } |
141b38b6 S |
1972 | |
1973 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1974 | } |
f078f209 | 1975 | |
8feceb67 VT |
1976 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1977 | { | |
1978 | u64 tsf; | |
bce048d7 JM |
1979 | struct ath_wiphy *aphy = hw->priv; |
1980 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1981 | |
141b38b6 | 1982 | mutex_lock(&sc->mutex); |
9abbfb27 | 1983 | ath9k_ps_wakeup(sc); |
141b38b6 | 1984 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1985 | ath9k_ps_restore(sc); |
141b38b6 | 1986 | mutex_unlock(&sc->mutex); |
f078f209 | 1987 | |
8feceb67 VT |
1988 | return tsf; |
1989 | } | |
f078f209 | 1990 | |
3b5d665b AF |
1991 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1992 | { | |
bce048d7 JM |
1993 | struct ath_wiphy *aphy = hw->priv; |
1994 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1995 | |
141b38b6 | 1996 | mutex_lock(&sc->mutex); |
9abbfb27 | 1997 | ath9k_ps_wakeup(sc); |
141b38b6 | 1998 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1999 | ath9k_ps_restore(sc); |
141b38b6 | 2000 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2001 | } |
2002 | ||
8feceb67 VT |
2003 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2004 | { | |
bce048d7 JM |
2005 | struct ath_wiphy *aphy = hw->priv; |
2006 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2007 | |
141b38b6 | 2008 | mutex_lock(&sc->mutex); |
21526d57 LR |
2009 | |
2010 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2011 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2012 | ath9k_ps_restore(sc); |
2013 | ||
141b38b6 | 2014 | mutex_unlock(&sc->mutex); |
8feceb67 | 2015 | } |
f078f209 | 2016 | |
8feceb67 | 2017 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2018 | struct ieee80211_vif *vif, |
141b38b6 S |
2019 | enum ieee80211_ampdu_mlme_action action, |
2020 | struct ieee80211_sta *sta, | |
2021 | u16 tid, u16 *ssn) | |
8feceb67 | 2022 | { |
bce048d7 JM |
2023 | struct ath_wiphy *aphy = hw->priv; |
2024 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2025 | int ret = 0; |
f078f209 | 2026 | |
85ad181e JB |
2027 | local_bh_disable(); |
2028 | ||
8feceb67 VT |
2029 | switch (action) { |
2030 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2031 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2032 | ret = -ENOTSUPP; | |
8feceb67 VT |
2033 | break; |
2034 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2035 | break; |
2036 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2037 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2038 | return -EOPNOTSUPP; | |
2039 | ||
8b685ba9 | 2040 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2041 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2042 | if (!ret) | |
2043 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2044 | ath9k_ps_restore(sc); |
8feceb67 VT |
2045 | break; |
2046 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2047 | ath9k_ps_wakeup(sc); |
f83da965 | 2048 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2049 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2050 | ath9k_ps_restore(sc); |
8feceb67 | 2051 | break; |
b1720231 | 2052 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2053 | ath9k_ps_wakeup(sc); |
8469cdef | 2054 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2055 | ath9k_ps_restore(sc); |
8469cdef | 2056 | break; |
8feceb67 | 2057 | default: |
3800276a | 2058 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2059 | } |
2060 | ||
85ad181e JB |
2061 | local_bh_enable(); |
2062 | ||
8feceb67 | 2063 | return ret; |
f078f209 LR |
2064 | } |
2065 | ||
62dad5b0 BP |
2066 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2067 | struct survey_info *survey) | |
2068 | { | |
2069 | struct ath_wiphy *aphy = hw->priv; | |
2070 | struct ath_softc *sc = aphy->sc; | |
3430098a | 2071 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2072 | struct ieee80211_supported_band *sband; |
3430098a FF |
2073 | struct ieee80211_channel *chan; |
2074 | unsigned long flags; | |
2075 | int pos; | |
2076 | ||
2077 | spin_lock_irqsave(&common->cc_lock, flags); | |
2078 | if (idx == 0) | |
2079 | ath_update_survey_stats(sc); | |
39162dbe FF |
2080 | |
2081 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2082 | if (sband && idx >= sband->n_channels) { | |
2083 | idx -= sband->n_channels; | |
2084 | sband = NULL; | |
2085 | } | |
62dad5b0 | 2086 | |
39162dbe FF |
2087 | if (!sband) |
2088 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2089 | |
3430098a FF |
2090 | if (!sband || idx >= sband->n_channels) { |
2091 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2092 | return -ENOENT; | |
4f1a5a4b | 2093 | } |
62dad5b0 | 2094 | |
3430098a FF |
2095 | chan = &sband->channels[idx]; |
2096 | pos = chan->hw_value; | |
2097 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2098 | survey->channel = chan; | |
2099 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2100 | ||
62dad5b0 BP |
2101 | return 0; |
2102 | } | |
2103 | ||
0c98de65 S |
2104 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2105 | { | |
bce048d7 JM |
2106 | struct ath_wiphy *aphy = hw->priv; |
2107 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2108 | |
3d832611 | 2109 | mutex_lock(&sc->mutex); |
8089cc47 | 2110 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 2111 | /* |
30888338 LR |
2112 | * There is a race here in mac80211 but fixing it requires |
2113 | * we revisit how we handle the scan complete callback. | |
2114 | * After mac80211 fixes we will not have configured hardware | |
2115 | * to the home channel nor would we have configured the RX | |
2116 | * filter yet. | |
8089cc47 | 2117 | */ |
3d832611 | 2118 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2119 | return; |
2120 | } | |
2121 | ||
2122 | aphy->state = ATH_WIPHY_SCAN; | |
2123 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
3d832611 | 2124 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2125 | } |
2126 | ||
30888338 LR |
2127 | /* |
2128 | * XXX: this requires a revisit after the driver | |
2129 | * scan_complete gets moved to another place/removed in mac80211. | |
2130 | */ | |
0c98de65 S |
2131 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2132 | { | |
bce048d7 JM |
2133 | struct ath_wiphy *aphy = hw->priv; |
2134 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2135 | |
3d832611 | 2136 | mutex_lock(&sc->mutex); |
8089cc47 | 2137 | aphy->state = ATH_WIPHY_ACTIVE; |
3d832611 | 2138 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2139 | } |
2140 | ||
e239d859 FF |
2141 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2142 | { | |
2143 | struct ath_wiphy *aphy = hw->priv; | |
2144 | struct ath_softc *sc = aphy->sc; | |
2145 | struct ath_hw *ah = sc->sc_ah; | |
2146 | ||
2147 | mutex_lock(&sc->mutex); | |
2148 | ah->coverage_class = coverage_class; | |
2149 | ath9k_hw_init_global_settings(ah); | |
2150 | mutex_unlock(&sc->mutex); | |
2151 | } | |
2152 | ||
6baff7f9 | 2153 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2154 | .tx = ath9k_tx, |
2155 | .start = ath9k_start, | |
2156 | .stop = ath9k_stop, | |
2157 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2158 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2159 | .remove_interface = ath9k_remove_interface, |
2160 | .config = ath9k_config, | |
8feceb67 | 2161 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2162 | .sta_add = ath9k_sta_add, |
2163 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2164 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2165 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2166 | .set_key = ath9k_set_key, |
8feceb67 | 2167 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2168 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2169 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2170 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2171 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2172 | .sw_scan_start = ath9k_sw_scan_start, |
2173 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2174 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2175 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2176 | }; |