Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
65 | else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
66 | pending = !list_empty(&txq->txq_fifo_pending); | |
67 | ||
68 | spin_unlock_bh(&txq->axq_lock); | |
69 | return pending; | |
70 | } | |
71 | ||
55624204 | 72 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
73 | { |
74 | unsigned long flags; | |
75 | bool ret; | |
76 | ||
9ecdef4b LR |
77 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
78 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
79 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
80 | |
81 | return ret; | |
82 | } | |
83 | ||
a91d75ae LR |
84 | void ath9k_ps_wakeup(struct ath_softc *sc) |
85 | { | |
898c914a | 86 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 87 | unsigned long flags; |
fbb078fc | 88 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
89 | |
90 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
91 | if (++sc->ps_usecount != 1) | |
92 | goto unlock; | |
93 | ||
fbb078fc | 94 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 95 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 96 | |
898c914a FF |
97 | /* |
98 | * While the hardware is asleep, the cycle counters contain no | |
99 | * useful data. Better clear them now so that they don't mess up | |
100 | * survey data results. | |
101 | */ | |
fbb078fc FF |
102 | if (power_mode != ATH9K_PM_AWAKE) { |
103 | spin_lock(&common->cc_lock); | |
104 | ath_hw_cycle_counters_update(common); | |
105 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
106 | spin_unlock(&common->cc_lock); | |
107 | } | |
898c914a | 108 | |
a91d75ae LR |
109 | unlock: |
110 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
111 | } | |
112 | ||
113 | void ath9k_ps_restore(struct ath_softc *sc) | |
114 | { | |
898c914a | 115 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
116 | unsigned long flags; |
117 | ||
118 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
119 | if (--sc->ps_usecount != 0) | |
120 | goto unlock; | |
121 | ||
898c914a FF |
122 | spin_lock(&common->cc_lock); |
123 | ath_hw_cycle_counters_update(common); | |
124 | spin_unlock(&common->cc_lock); | |
125 | ||
1dbfd9d4 VN |
126 | if (sc->ps_idle) |
127 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
128 | else if (sc->ps_enabled && | |
129 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
130 | PS_WAIT_FOR_CAB | |
131 | PS_WAIT_FOR_PSPOLL_DATA | | |
132 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 133 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
134 | |
135 | unlock: | |
136 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
137 | } | |
138 | ||
5ee08656 FF |
139 | static void ath_start_ani(struct ath_common *common) |
140 | { | |
141 | struct ath_hw *ah = common->ah; | |
142 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
143 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
144 | ||
145 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
146 | return; | |
147 | ||
148 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
149 | return; | |
150 | ||
151 | common->ani.longcal_timer = timestamp; | |
152 | common->ani.shortcal_timer = timestamp; | |
153 | common->ani.checkani_timer = timestamp; | |
154 | ||
155 | mod_timer(&common->ani.timer, | |
156 | jiffies + | |
157 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
158 | } | |
159 | ||
3430098a FF |
160 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
161 | { | |
162 | struct ath_hw *ah = sc->sc_ah; | |
163 | struct ath9k_channel *chan = &ah->channels[channel]; | |
164 | struct survey_info *survey = &sc->survey[channel]; | |
165 | ||
166 | if (chan->noisefloor) { | |
167 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
168 | survey->noise = chan->noisefloor; | |
169 | } | |
170 | } | |
171 | ||
cb8d61de FF |
172 | /* |
173 | * Updates the survey statistics and returns the busy time since last | |
174 | * update in %, if the measurement duration was long enough for the | |
175 | * result to be useful, -1 otherwise. | |
176 | */ | |
177 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
178 | { |
179 | struct ath_hw *ah = sc->sc_ah; | |
180 | struct ath_common *common = ath9k_hw_common(ah); | |
181 | int pos = ah->curchan - &ah->channels[0]; | |
182 | struct survey_info *survey = &sc->survey[pos]; | |
183 | struct ath_cycle_counters *cc = &common->cc_survey; | |
184 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 185 | int ret = 0; |
3430098a | 186 | |
0845735e | 187 | if (!ah->curchan) |
cb8d61de | 188 | return -1; |
0845735e | 189 | |
898c914a FF |
190 | if (ah->power_mode == ATH9K_PM_AWAKE) |
191 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
192 | |
193 | if (cc->cycles > 0) { | |
194 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
195 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
196 | SURVEY_INFO_CHANNEL_TIME_RX | | |
197 | SURVEY_INFO_CHANNEL_TIME_TX; | |
198 | survey->channel_time += cc->cycles / div; | |
199 | survey->channel_time_busy += cc->rx_busy / div; | |
200 | survey->channel_time_rx += cc->rx_frame / div; | |
201 | survey->channel_time_tx += cc->tx_frame / div; | |
202 | } | |
cb8d61de FF |
203 | |
204 | if (cc->cycles < div) | |
205 | return -1; | |
206 | ||
207 | if (cc->cycles > 0) | |
208 | ret = cc->rx_busy * 100 / cc->cycles; | |
209 | ||
3430098a FF |
210 | memset(cc, 0, sizeof(*cc)); |
211 | ||
212 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
213 | |
214 | return ret; | |
3430098a FF |
215 | } |
216 | ||
ff37e337 S |
217 | /* |
218 | * Set/change channels. If the channel is really being changed, it's done | |
219 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
220 | * DMA, then restart stuff. | |
221 | */ | |
0e2dedf9 JM |
222 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
223 | struct ath9k_channel *hchan) | |
ff37e337 | 224 | { |
cbe61d8a | 225 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 226 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 227 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 228 | bool fastcc = true, stopped; |
ae8d2858 | 229 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 230 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 231 | int r; |
ff37e337 S |
232 | |
233 | if (sc->sc_flags & SC_OP_INVALID) | |
234 | return -EIO; | |
235 | ||
cb8d61de FF |
236 | sc->hw_busy_count = 0; |
237 | ||
5ee08656 FF |
238 | del_timer_sync(&common->ani.timer); |
239 | cancel_work_sync(&sc->paprd_work); | |
240 | cancel_work_sync(&sc->hw_check_work); | |
241 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 242 | cancel_delayed_work_sync(&sc->hw_pll_work); |
5ee08656 | 243 | |
3cbb5dd7 VN |
244 | ath9k_ps_wakeup(sc); |
245 | ||
6a6733f2 LR |
246 | spin_lock_bh(&sc->sc_pcu_lock); |
247 | ||
c0d7c7af LR |
248 | /* |
249 | * This is only performed if the channel settings have | |
250 | * actually changed. | |
251 | * | |
252 | * To switch channels clear any pending DMA operations; | |
253 | * wait long enough for the RX fifo to drain, reset the | |
254 | * hardware at the new frequency, and then re-enable | |
255 | * the relevant bits of the h/w. | |
256 | */ | |
4df3071e | 257 | ath9k_hw_disable_interrupts(ah); |
080e1a25 | 258 | stopped = ath_drain_all_txq(sc, false); |
5e848f78 | 259 | |
080e1a25 FF |
260 | if (!ath_stoprecv(sc)) |
261 | stopped = false; | |
ff37e337 | 262 | |
8b3f4616 FF |
263 | if (!ath9k_hw_check_alive(ah)) |
264 | stopped = false; | |
265 | ||
c0d7c7af LR |
266 | /* XXX: do not flush receive queue here. We don't want |
267 | * to flush data frames already in queue because of | |
268 | * changing channel. */ | |
ff37e337 | 269 | |
5ee08656 | 270 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
271 | fastcc = false; |
272 | ||
20bd2a09 | 273 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
9ac58615 | 274 | caldata = &sc->caldata; |
20bd2a09 | 275 | |
226afe68 JP |
276 | ath_dbg(common, ATH_DBG_CONFIG, |
277 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | |
278 | sc->sc_ah->curchan->channel, | |
279 | channel->center_freq, conf_is_ht40(conf), | |
280 | fastcc); | |
ff37e337 | 281 | |
20bd2a09 | 282 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 283 | if (r) { |
3800276a JP |
284 | ath_err(common, |
285 | "Unable to reset channel (%u MHz), reset status %d\n", | |
286 | channel->center_freq, r); | |
3989279c | 287 | goto ps_restore; |
ff37e337 | 288 | } |
c0d7c7af | 289 | |
c0d7c7af | 290 | if (ath_startrecv(sc) != 0) { |
3800276a | 291 | ath_err(common, "Unable to restart recv logic\n"); |
3989279c GJ |
292 | r = -EIO; |
293 | goto ps_restore; | |
c0d7c7af LR |
294 | } |
295 | ||
5048e8c3 RM |
296 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
297 | sc->config.txpowlimit, &sc->curtxpow); | |
3069168c | 298 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 299 | |
48a6a468 | 300 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
1186488b RM |
301 | if (sc->sc_flags & SC_OP_BEACONS) |
302 | ath_beacon_config(sc, NULL); | |
5ee08656 | 303 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 304 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
48a6a468 | 305 | ath_start_ani(common); |
5ee08656 FF |
306 | } |
307 | ||
3989279c | 308 | ps_restore: |
92460412 FF |
309 | ieee80211_wake_queues(hw); |
310 | ||
6a6733f2 LR |
311 | spin_unlock_bh(&sc->sc_pcu_lock); |
312 | ||
3cbb5dd7 | 313 | ath9k_ps_restore(sc); |
3989279c | 314 | return r; |
ff37e337 S |
315 | } |
316 | ||
9f42c2b6 FF |
317 | static void ath_paprd_activate(struct ath_softc *sc) |
318 | { | |
319 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 320 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 321 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
322 | int chain; |
323 | ||
20bd2a09 | 324 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
325 | return; |
326 | ||
327 | ath9k_ps_wakeup(sc); | |
ddfef792 | 328 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 329 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 330 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
331 | continue; |
332 | ||
20bd2a09 | 333 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
334 | } |
335 | ||
336 | ar9003_paprd_enable(ah, true); | |
337 | ath9k_ps_restore(sc); | |
338 | } | |
339 | ||
7607cbe2 FF |
340 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
341 | { | |
342 | struct ieee80211_hw *hw = sc->hw; | |
343 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
344 | struct ath_hw *ah = sc->sc_ah; |
345 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
346 | struct ath_tx_control txctl; |
347 | int time_left; | |
348 | ||
349 | memset(&txctl, 0, sizeof(txctl)); | |
350 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
351 | ||
352 | memset(tx_info, 0, sizeof(*tx_info)); | |
353 | tx_info->band = hw->conf.channel->band; | |
354 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
355 | tx_info->control.rates[0].idx = 0; | |
356 | tx_info->control.rates[0].count = 1; | |
357 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
358 | tx_info->control.rates[1].idx = -1; | |
359 | ||
360 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 361 | txctl.paprd = BIT(chain); |
47960077 MSS |
362 | |
363 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
364 | ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n"); | |
365 | dev_kfree_skb_any(skb); | |
7607cbe2 | 366 | return false; |
47960077 | 367 | } |
7607cbe2 FF |
368 | |
369 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
370 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
371 | |
372 | if (!time_left) | |
373 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, | |
374 | "Timeout waiting for paprd training on TX chain %d\n", | |
375 | chain); | |
376 | ||
377 | return !!time_left; | |
378 | } | |
379 | ||
9f42c2b6 FF |
380 | void ath_paprd_calibrate(struct work_struct *work) |
381 | { | |
382 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
383 | struct ieee80211_hw *hw = sc->hw; | |
384 | struct ath_hw *ah = sc->sc_ah; | |
385 | struct ieee80211_hdr *hdr; | |
386 | struct sk_buff *skb = NULL; | |
20bd2a09 | 387 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 388 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 389 | int ftype; |
9f42c2b6 FF |
390 | int chain_ok = 0; |
391 | int chain; | |
392 | int len = 1800; | |
9f42c2b6 | 393 | |
20bd2a09 FF |
394 | if (!caldata) |
395 | return; | |
396 | ||
1bf38661 FF |
397 | if (ar9003_paprd_init_table(ah) < 0) |
398 | return; | |
399 | ||
9f42c2b6 FF |
400 | skb = alloc_skb(len, GFP_KERNEL); |
401 | if (!skb) | |
402 | return; | |
403 | ||
9f42c2b6 FF |
404 | skb_put(skb, len); |
405 | memset(skb->data, 0, len); | |
406 | hdr = (struct ieee80211_hdr *)skb->data; | |
407 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
408 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 409 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
410 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
411 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
412 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
413 | ||
47399f1a | 414 | ath9k_ps_wakeup(sc); |
9f42c2b6 | 415 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 416 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
417 | continue; |
418 | ||
419 | chain_ok = 0; | |
9f42c2b6 | 420 | |
7607cbe2 FF |
421 | ath_dbg(common, ATH_DBG_CALIBRATE, |
422 | "Sending PAPRD frame for thermal measurement " | |
423 | "on chain %d\n", chain); | |
424 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
425 | goto fail_paprd; | |
9f42c2b6 | 426 | |
9f42c2b6 | 427 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 428 | |
7607cbe2 FF |
429 | ath_dbg(common, ATH_DBG_CALIBRATE, |
430 | "Sending PAPRD training frame on chain %d\n", chain); | |
431 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 432 | goto fail_paprd; |
9f42c2b6 FF |
433 | |
434 | if (!ar9003_paprd_is_done(ah)) | |
435 | break; | |
436 | ||
20bd2a09 | 437 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
438 | break; |
439 | ||
440 | chain_ok = 1; | |
441 | } | |
442 | kfree_skb(skb); | |
443 | ||
444 | if (chain_ok) { | |
20bd2a09 | 445 | caldata->paprd_done = true; |
9f42c2b6 FF |
446 | ath_paprd_activate(sc); |
447 | } | |
448 | ||
ca369eb4 | 449 | fail_paprd: |
9f42c2b6 FF |
450 | ath9k_ps_restore(sc); |
451 | } | |
452 | ||
ff37e337 S |
453 | /* |
454 | * This routine performs the periodic noise floor calibration function | |
455 | * that is used to adjust and optimize the chip performance. This | |
456 | * takes environmental changes (location, temperature) into account. | |
457 | * When the task is complete, it reschedules itself depending on the | |
458 | * appropriate interval that was calculated. | |
459 | */ | |
55624204 | 460 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 461 | { |
20977d3e S |
462 | struct ath_softc *sc = (struct ath_softc *)data; |
463 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 464 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
465 | bool longcal = false; |
466 | bool shortcal = false; | |
467 | bool aniflag = false; | |
468 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 469 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 470 | unsigned long flags; |
6044474e FF |
471 | |
472 | if (ah->caldata && ah->caldata->nfcal_interference) | |
473 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
474 | else | |
475 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 476 | |
20977d3e S |
477 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
478 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 479 | |
1ffc1c61 JM |
480 | /* Only calibrate if awake */ |
481 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
482 | goto set_timer; | |
483 | ||
484 | ath9k_ps_wakeup(sc); | |
485 | ||
ff37e337 | 486 | /* Long calibration runs independently of short calibration. */ |
6044474e | 487 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 488 | longcal = true; |
226afe68 | 489 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 490 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
491 | } |
492 | ||
17d7904d | 493 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
494 | if (!common->ani.caldone) { |
495 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 496 | shortcal = true; |
226afe68 JP |
497 | ath_dbg(common, ATH_DBG_ANI, |
498 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
499 | common->ani.shortcal_timer = timestamp; |
500 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
501 | } |
502 | } else { | |
3d536acf | 503 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 504 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
505 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
506 | if (common->ani.caldone) | |
507 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
508 | } |
509 | } | |
510 | ||
511 | /* Verify whether we must check ANI */ | |
e36b27af LR |
512 | if ((timestamp - common->ani.checkani_timer) >= |
513 | ah->config.ani_poll_interval) { | |
ff37e337 | 514 | aniflag = true; |
3d536acf | 515 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
516 | } |
517 | ||
518 | /* Skip all processing if there's nothing to do. */ | |
519 | if (longcal || shortcal || aniflag) { | |
520 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
521 | if (aniflag) { |
522 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 523 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 524 | ath_update_survey_stats(sc); |
b5bfc568 FF |
525 | spin_unlock_irqrestore(&common->cc_lock, flags); |
526 | } | |
ff37e337 S |
527 | |
528 | /* Perform calibration if necessary */ | |
529 | if (longcal || shortcal) { | |
3d536acf | 530 | common->ani.caldone = |
43c27613 LR |
531 | ath9k_hw_calibrate(ah, |
532 | ah->curchan, | |
533 | common->rx_chainmask, | |
534 | longcal); | |
ff37e337 S |
535 | } |
536 | } | |
537 | ||
1ffc1c61 JM |
538 | ath9k_ps_restore(sc); |
539 | ||
20977d3e | 540 | set_timer: |
ff37e337 S |
541 | /* |
542 | * Set timer interval based on previous results. | |
543 | * The interval must be the shortest necessary to satisfy ANI, | |
544 | * short calibration and long calibration. | |
545 | */ | |
aac9207e | 546 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 547 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
548 | cal_interval = min(cal_interval, |
549 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 550 | if (!common->ani.caldone) |
20977d3e | 551 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 552 | |
3d536acf | 553 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
554 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
555 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 556 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 557 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
558 | ath_paprd_activate(sc); |
559 | } | |
ff37e337 S |
560 | } |
561 | ||
ff37e337 S |
562 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
563 | { | |
564 | struct ath_node *an; | |
ea066d5a | 565 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
566 | an = (struct ath_node *)sta->drv_priv; |
567 | ||
7f010c93 BG |
568 | #ifdef CONFIG_ATH9K_DEBUGFS |
569 | spin_lock(&sc->nodes_lock); | |
570 | list_add(&an->list, &sc->nodes); | |
571 | spin_unlock(&sc->nodes_lock); | |
572 | an->sta = sta; | |
573 | #endif | |
ea066d5a MSS |
574 | if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM) |
575 | sc->sc_flags |= SC_OP_ENABLE_APM; | |
576 | ||
87792efc | 577 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 578 | ath_tx_node_init(sc, an); |
9e98ac65 | 579 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
580 | sta->ht_cap.ampdu_factor); |
581 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
582 | } | |
ff37e337 S |
583 | } |
584 | ||
585 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
586 | { | |
587 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
588 | ||
7f010c93 BG |
589 | #ifdef CONFIG_ATH9K_DEBUGFS |
590 | spin_lock(&sc->nodes_lock); | |
591 | list_del(&an->list); | |
592 | spin_unlock(&sc->nodes_lock); | |
593 | an->sta = NULL; | |
594 | #endif | |
595 | ||
ff37e337 S |
596 | if (sc->sc_flags & SC_OP_TXAGGR) |
597 | ath_tx_node_cleanup(sc, an); | |
598 | } | |
599 | ||
347809fc FF |
600 | void ath_hw_check(struct work_struct *work) |
601 | { | |
602 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
cb8d61de FF |
603 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
604 | unsigned long flags; | |
605 | int busy; | |
347809fc FF |
606 | |
607 | ath9k_ps_wakeup(sc); | |
cb8d61de FF |
608 | if (ath9k_hw_check_alive(sc->sc_ah)) |
609 | goto out; | |
347809fc | 610 | |
cb8d61de FF |
611 | spin_lock_irqsave(&common->cc_lock, flags); |
612 | busy = ath_update_survey_stats(sc); | |
613 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
347809fc | 614 | |
cb8d61de FF |
615 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " |
616 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | |
617 | if (busy >= 99) { | |
618 | if (++sc->hw_busy_count >= 3) | |
619 | ath_reset(sc, true); | |
620 | } else if (busy >= 0) | |
621 | sc->hw_busy_count = 0; | |
347809fc FF |
622 | |
623 | out: | |
624 | ath9k_ps_restore(sc); | |
625 | } | |
626 | ||
55624204 | 627 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
628 | { |
629 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 630 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 631 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 632 | |
17d7904d | 633 | u32 status = sc->intrstatus; |
b5c80475 | 634 | u32 rxmask; |
ff37e337 | 635 | |
347809fc | 636 | if (status & ATH9K_INT_FATAL) { |
fac6b6a0 | 637 | ath_reset(sc, true); |
ff37e337 | 638 | return; |
063d8be3 | 639 | } |
ff37e337 | 640 | |
783cd01e | 641 | ath9k_ps_wakeup(sc); |
52671e43 | 642 | spin_lock(&sc->sc_pcu_lock); |
6a6733f2 | 643 | |
8b3f4616 FF |
644 | /* |
645 | * Only run the baseband hang check if beacons stop working in AP or | |
646 | * IBSS mode, because it has a high false positive rate. For station | |
647 | * mode it should not be necessary, since the upper layers will detect | |
648 | * this through a beacon miss automatically and the following channel | |
649 | * change will trigger a hardware reset anyway | |
650 | */ | |
651 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
652 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
653 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
654 | ||
b5c80475 FF |
655 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
656 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
657 | ATH9K_INT_RXORN); | |
658 | else | |
659 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
660 | ||
661 | if (status & rxmask) { | |
b5c80475 FF |
662 | /* Check for high priority Rx first */ |
663 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
664 | (status & ATH9K_INT_RXHP)) | |
665 | ath_rx_tasklet(sc, 0, true); | |
666 | ||
667 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
668 | } |
669 | ||
e5003249 VT |
670 | if (status & ATH9K_INT_TX) { |
671 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
672 | ath_tx_edma_tasklet(sc); | |
673 | else | |
674 | ath_tx_tasklet(sc); | |
675 | } | |
063d8be3 | 676 | |
96148326 | 677 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
678 | /* |
679 | * TSF sync does not look correct; remain awake to sync with | |
680 | * the next Beacon. | |
681 | */ | |
226afe68 JP |
682 | ath_dbg(common, ATH_DBG_PS, |
683 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 684 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
685 | } |
686 | ||
766ec4a9 | 687 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
688 | if (status & ATH9K_INT_GENTIMER) |
689 | ath_gen_timer_isr(sc->sc_ah); | |
690 | ||
ff37e337 | 691 | /* re-enable hardware interrupt */ |
4df3071e | 692 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 693 | |
52671e43 | 694 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 695 | ath9k_ps_restore(sc); |
ff37e337 S |
696 | } |
697 | ||
6baff7f9 | 698 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 699 | { |
063d8be3 S |
700 | #define SCHED_INTR ( \ |
701 | ATH9K_INT_FATAL | \ | |
702 | ATH9K_INT_RXORN | \ | |
703 | ATH9K_INT_RXEOL | \ | |
704 | ATH9K_INT_RX | \ | |
b5c80475 FF |
705 | ATH9K_INT_RXLP | \ |
706 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
707 | ATH9K_INT_TX | \ |
708 | ATH9K_INT_BMISS | \ | |
709 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
710 | ATH9K_INT_TSFOOR | \ |
711 | ATH9K_INT_GENTIMER) | |
063d8be3 | 712 | |
ff37e337 | 713 | struct ath_softc *sc = dev; |
cbe61d8a | 714 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 715 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
716 | enum ath9k_int status; |
717 | bool sched = false; | |
718 | ||
063d8be3 S |
719 | /* |
720 | * The hardware is not ready/present, don't | |
721 | * touch anything. Note this can happen early | |
722 | * on if the IRQ is shared. | |
723 | */ | |
724 | if (sc->sc_flags & SC_OP_INVALID) | |
725 | return IRQ_NONE; | |
ff37e337 | 726 | |
063d8be3 S |
727 | |
728 | /* shared irq, not for us */ | |
729 | ||
153e080d | 730 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 731 | return IRQ_NONE; |
063d8be3 S |
732 | |
733 | /* | |
734 | * Figure out the reason(s) for the interrupt. Note | |
735 | * that the hal returns a pseudo-ISR that may include | |
736 | * bits we haven't explicitly enabled so we mask the | |
737 | * value to insure we only process bits we requested. | |
738 | */ | |
739 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 740 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 741 | |
063d8be3 S |
742 | /* |
743 | * If there are no status bits set, then this interrupt was not | |
744 | * for me (should have been caught above). | |
745 | */ | |
153e080d | 746 | if (!status) |
063d8be3 | 747 | return IRQ_NONE; |
ff37e337 | 748 | |
063d8be3 S |
749 | /* Cache the status */ |
750 | sc->intrstatus = status; | |
751 | ||
752 | if (status & SCHED_INTR) | |
753 | sched = true; | |
754 | ||
755 | /* | |
756 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
757 | * chip immediately. | |
758 | */ | |
b5c80475 FF |
759 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
760 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
761 | goto chip_reset; |
762 | ||
08578b8f LR |
763 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
764 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
765 | |
766 | spin_lock(&common->cc_lock); | |
767 | ath_hw_cycle_counters_update(common); | |
08578b8f | 768 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
769 | spin_unlock(&common->cc_lock); |
770 | ||
08578b8f LR |
771 | goto chip_reset; |
772 | } | |
773 | ||
063d8be3 S |
774 | if (status & ATH9K_INT_SWBA) |
775 | tasklet_schedule(&sc->bcon_tasklet); | |
776 | ||
777 | if (status & ATH9K_INT_TXURN) | |
778 | ath9k_hw_updatetxtriglevel(ah, true); | |
779 | ||
b5c80475 FF |
780 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
781 | if (status & ATH9K_INT_RXEOL) { | |
782 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
783 | ath9k_hw_set_interrupts(ah, ah->imask); | |
784 | } | |
785 | } | |
786 | ||
063d8be3 | 787 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 788 | /* |
063d8be3 S |
789 | * Disable interrupts until we service the MIB |
790 | * interrupt; otherwise it will continue to | |
791 | * fire. | |
ff37e337 | 792 | */ |
4df3071e | 793 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
794 | /* |
795 | * Let the hal handle the event. We assume | |
796 | * it will clear whatever condition caused | |
797 | * the interrupt. | |
798 | */ | |
88eac2da | 799 | spin_lock(&common->cc_lock); |
bfc472bb | 800 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 801 | spin_unlock(&common->cc_lock); |
4df3071e | 802 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 803 | } |
ff37e337 | 804 | |
153e080d VT |
805 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
806 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
807 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
808 | goto chip_reset; | |
063d8be3 S |
809 | /* Clear RxAbort bit so that we can |
810 | * receive frames */ | |
9ecdef4b | 811 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 812 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 813 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 814 | } |
063d8be3 S |
815 | |
816 | chip_reset: | |
ff37e337 | 817 | |
817e11de S |
818 | ath_debug_stat_interrupt(sc, status); |
819 | ||
ff37e337 | 820 | if (sched) { |
4df3071e FF |
821 | /* turn off every interrupt */ |
822 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
823 | tasklet_schedule(&sc->intr_tq); |
824 | } | |
825 | ||
826 | return IRQ_HANDLED; | |
063d8be3 S |
827 | |
828 | #undef SCHED_INTR | |
ff37e337 S |
829 | } |
830 | ||
8feceb67 | 831 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
9fa23e17 | 832 | struct ieee80211_hw *hw, |
5640b08e | 833 | struct ieee80211_vif *vif, |
8feceb67 | 834 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 835 | { |
f2b2143e | 836 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 837 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 838 | |
8feceb67 | 839 | if (bss_conf->assoc) { |
226afe68 JP |
840 | ath_dbg(common, ATH_DBG_CONFIG, |
841 | "Bss Info ASSOC %d, bssid: %pM\n", | |
842 | bss_conf->aid, common->curbssid); | |
f078f209 | 843 | |
8feceb67 | 844 | /* New association, store aid */ |
1510718d | 845 | common->curaid = bss_conf->aid; |
f2b2143e | 846 | ath9k_hw_write_associd(ah); |
2664f201 SB |
847 | |
848 | /* | |
849 | * Request a re-configuration of Beacon related timers | |
850 | * on the receipt of the first Beacon frame (i.e., | |
851 | * after time sync with the AP). | |
852 | */ | |
1b04b930 | 853 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 854 | |
8feceb67 | 855 | /* Configure the beacon */ |
2c3db3d5 | 856 | ath_beacon_config(sc, vif); |
f078f209 | 857 | |
8feceb67 | 858 | /* Reset rssi stats */ |
9ac58615 | 859 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
22e66a4c | 860 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 861 | |
6c3118e2 | 862 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 863 | ath_start_ani(common); |
8feceb67 | 864 | } else { |
226afe68 | 865 | ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 866 | common->curaid = 0; |
f38faa31 | 867 | /* Stop ANI */ |
6c3118e2 | 868 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 869 | del_timer_sync(&common->ani.timer); |
f078f209 | 870 | } |
8feceb67 | 871 | } |
f078f209 | 872 | |
68a89116 | 873 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 874 | { |
cbe61d8a | 875 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 876 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 877 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 878 | int r; |
500c064d | 879 | |
3cbb5dd7 | 880 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
881 | spin_lock_bh(&sc->sc_pcu_lock); |
882 | ||
93b1b37f | 883 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 884 | |
159cd468 | 885 | if (!ah->curchan) |
c344c9cb | 886 | ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); |
159cd468 | 887 | |
20bd2a09 | 888 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 889 | if (r) { |
3800276a JP |
890 | ath_err(common, |
891 | "Unable to reset channel (%u MHz), reset status %d\n", | |
892 | channel->center_freq, r); | |
500c064d | 893 | } |
500c064d | 894 | |
5048e8c3 RM |
895 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
896 | sc->config.txpowlimit, &sc->curtxpow); | |
500c064d | 897 | if (ath_startrecv(sc) != 0) { |
3800276a | 898 | ath_err(common, "Unable to restart recv logic\n"); |
c2731b81 | 899 | goto out; |
500c064d | 900 | } |
500c064d | 901 | if (sc->sc_flags & SC_OP_BEACONS) |
2c3db3d5 | 902 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
903 | |
904 | /* Re-Enable interrupts */ | |
3069168c | 905 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
906 | |
907 | /* Enable LED */ | |
08fc5c1b | 908 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 909 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 910 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 911 | |
68a89116 | 912 | ieee80211_wake_queues(hw); |
c2731b81 | 913 | out: |
6a6733f2 LR |
914 | spin_unlock_bh(&sc->sc_pcu_lock); |
915 | ||
3cbb5dd7 | 916 | ath9k_ps_restore(sc); |
500c064d VT |
917 | } |
918 | ||
68a89116 | 919 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 920 | { |
cbe61d8a | 921 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 922 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 923 | int r; |
500c064d | 924 | |
3cbb5dd7 | 925 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
926 | spin_lock_bh(&sc->sc_pcu_lock); |
927 | ||
68a89116 | 928 | ieee80211_stop_queues(hw); |
500c064d | 929 | |
982723df VN |
930 | /* |
931 | * Keep the LED on when the radio is disabled | |
932 | * during idle unassociated state. | |
933 | */ | |
934 | if (!sc->ps_idle) { | |
935 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
936 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
937 | } | |
500c064d VT |
938 | |
939 | /* Disable interrupts */ | |
4df3071e | 940 | ath9k_hw_disable_interrupts(ah); |
500c064d | 941 | |
043a0405 | 942 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 | 943 | |
500c064d VT |
944 | ath_stoprecv(sc); /* turn off frame recv */ |
945 | ath_flushrecv(sc); /* flush recv queue */ | |
946 | ||
159cd468 | 947 | if (!ah->curchan) |
c344c9cb | 948 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
159cd468 | 949 | |
20bd2a09 | 950 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 951 | if (r) { |
3800276a JP |
952 | ath_err(ath9k_hw_common(sc->sc_ah), |
953 | "Unable to reset channel (%u MHz), reset status %d\n", | |
954 | channel->center_freq, r); | |
500c064d | 955 | } |
500c064d VT |
956 | |
957 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 958 | |
93b1b37f | 959 | ath9k_hw_configpcipowersave(ah, 1, 1); |
6a6733f2 LR |
960 | |
961 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 962 | ath9k_ps_restore(sc); |
500c064d VT |
963 | } |
964 | ||
ff37e337 S |
965 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
966 | { | |
cbe61d8a | 967 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 968 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 969 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 970 | int r; |
ff37e337 | 971 | |
cb8d61de FF |
972 | sc->hw_busy_count = 0; |
973 | ||
2ab81d4a S |
974 | /* Stop ANI */ |
975 | del_timer_sync(&common->ani.timer); | |
976 | ||
783cd01e | 977 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
978 | spin_lock_bh(&sc->sc_pcu_lock); |
979 | ||
cc9c378a S |
980 | ieee80211_stop_queues(hw); |
981 | ||
4df3071e | 982 | ath9k_hw_disable_interrupts(ah); |
043a0405 | 983 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 | 984 | |
ff37e337 S |
985 | ath_stoprecv(sc); |
986 | ath_flushrecv(sc); | |
987 | ||
20bd2a09 | 988 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 989 | if (r) |
3800276a JP |
990 | ath_err(common, |
991 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
992 | |
993 | if (ath_startrecv(sc) != 0) | |
3800276a | 994 | ath_err(common, "Unable to start recv logic\n"); |
ff37e337 S |
995 | |
996 | /* | |
997 | * We may be doing a reset in response to a request | |
998 | * that changes the channel so update any state that | |
999 | * might change as a result. | |
1000 | */ | |
5048e8c3 RM |
1001 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1002 | sc->config.txpowlimit, &sc->curtxpow); | |
ff37e337 | 1003 | |
52b8ac92 | 1004 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 1005 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1006 | |
3069168c | 1007 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1008 | |
1009 | if (retry_tx) { | |
1010 | int i; | |
1011 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1012 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1013 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1014 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1015 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1016 | } |
1017 | } | |
1018 | } | |
1019 | ||
cc9c378a | 1020 | ieee80211_wake_queues(hw); |
6a6733f2 | 1021 | spin_unlock_bh(&sc->sc_pcu_lock); |
cc9c378a | 1022 | |
2ab81d4a S |
1023 | /* Start ANI */ |
1024 | ath_start_ani(common); | |
783cd01e | 1025 | ath9k_ps_restore(sc); |
2ab81d4a | 1026 | |
ae8d2858 | 1027 | return r; |
ff37e337 S |
1028 | } |
1029 | ||
ff37e337 S |
1030 | /**********************/ |
1031 | /* mac80211 callbacks */ | |
1032 | /**********************/ | |
1033 | ||
8feceb67 | 1034 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1035 | { |
9ac58615 | 1036 | struct ath_softc *sc = hw->priv; |
af03abec | 1037 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1038 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1039 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1040 | struct ath9k_channel *init_channel; |
82880a7c | 1041 | int r; |
f078f209 | 1042 | |
226afe68 JP |
1043 | ath_dbg(common, ATH_DBG_CONFIG, |
1044 | "Starting driver with initial channel: %d MHz\n", | |
1045 | curchan->center_freq); | |
f078f209 | 1046 | |
141b38b6 S |
1047 | mutex_lock(&sc->mutex); |
1048 | ||
8feceb67 | 1049 | /* setup initial channel */ |
82880a7c | 1050 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1051 | |
c344c9cb | 1052 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1053 | |
1054 | /* Reset SERDES registers */ | |
af03abec | 1055 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1056 | |
1057 | /* | |
1058 | * The basic interface to setting the hardware in a good | |
1059 | * state is ``reset''. On return the hardware is known to | |
1060 | * be powered up and with interrupts disabled. This must | |
1061 | * be followed by initialization of the appropriate bits | |
1062 | * and then setup of the interrupt mask. | |
1063 | */ | |
4bdd1e97 | 1064 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1065 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1066 | if (r) { |
3800276a JP |
1067 | ath_err(common, |
1068 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1069 | r, curchan->center_freq); | |
4bdd1e97 | 1070 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1071 | goto mutex_unlock; |
ff37e337 | 1072 | } |
ff37e337 S |
1073 | |
1074 | /* | |
1075 | * This is needed only to setup initial state | |
1076 | * but it's best done after a reset. | |
1077 | */ | |
5048e8c3 RM |
1078 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1079 | sc->config.txpowlimit, &sc->curtxpow); | |
8feceb67 | 1080 | |
ff37e337 S |
1081 | /* |
1082 | * Setup the hardware after reset: | |
1083 | * The receive engine is set going. | |
1084 | * Frame transmit is handled entirely | |
1085 | * in the frame output path; there's nothing to do | |
1086 | * here except setup the interrupt mask. | |
1087 | */ | |
1088 | if (ath_startrecv(sc) != 0) { | |
3800276a | 1089 | ath_err(common, "Unable to start recv logic\n"); |
141b38b6 | 1090 | r = -EIO; |
4bdd1e97 | 1091 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1092 | goto mutex_unlock; |
f078f209 | 1093 | } |
4bdd1e97 | 1094 | spin_unlock_bh(&sc->sc_pcu_lock); |
8feceb67 | 1095 | |
ff37e337 | 1096 | /* Setup our intr mask. */ |
b5c80475 FF |
1097 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1098 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1099 | ATH9K_INT_GLOBAL; | |
1100 | ||
1101 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1102 | ah->imask |= ATH9K_INT_RXHP | |
1103 | ATH9K_INT_RXLP | | |
1104 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1105 | else |
1106 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1107 | |
364734fa | 1108 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1109 | |
af03abec | 1110 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1111 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1112 | |
ff37e337 | 1113 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1114 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1115 | |
1116 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1117 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1118 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1119 | |
bce048d7 | 1120 | ieee80211_wake_queues(hw); |
ff37e337 | 1121 | |
42935eca | 1122 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1123 | |
766ec4a9 LR |
1124 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1125 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1126 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1127 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1128 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1129 | |
5bb12791 LR |
1130 | if (common->bus_ops->bt_coex_prep) |
1131 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1132 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1133 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1134 | } |
1135 | ||
8060e169 VT |
1136 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1137 | common->bus_ops->extn_synch_en(common); | |
1138 | ||
141b38b6 S |
1139 | mutex_unlock: |
1140 | mutex_unlock(&sc->mutex); | |
1141 | ||
ae8d2858 | 1142 | return r; |
f078f209 LR |
1143 | } |
1144 | ||
8feceb67 VT |
1145 | static int ath9k_tx(struct ieee80211_hw *hw, |
1146 | struct sk_buff *skb) | |
f078f209 | 1147 | { |
9ac58615 | 1148 | struct ath_softc *sc = hw->priv; |
c46917bb | 1149 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1150 | struct ath_tx_control txctl; |
1bc14880 | 1151 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1152 | |
96148326 | 1153 | if (sc->ps_enabled) { |
dc8c4585 JM |
1154 | /* |
1155 | * mac80211 does not set PM field for normal data frames, so we | |
1156 | * need to update that based on the current PS mode. | |
1157 | */ | |
1158 | if (ieee80211_is_data(hdr->frame_control) && | |
1159 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1160 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1161 | ath_dbg(common, ATH_DBG_PS, |
1162 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1163 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1164 | } | |
1165 | } | |
1166 | ||
9a23f9ca JM |
1167 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1168 | /* | |
1169 | * We are using PS-Poll and mac80211 can request TX while in | |
1170 | * power save mode. Need to wake up hardware for the TX to be | |
1171 | * completed and if needed, also for RX of buffered frames. | |
1172 | */ | |
9a23f9ca | 1173 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1174 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1175 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1176 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1177 | ath_dbg(common, ATH_DBG_PS, |
1178 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1179 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1180 | } else { |
226afe68 JP |
1181 | ath_dbg(common, ATH_DBG_PS, |
1182 | "Wake up to complete TX\n"); | |
1b04b930 | 1183 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1184 | } |
1185 | /* | |
1186 | * The actual restore operation will happen only after | |
1187 | * the sc_flags bit is cleared. We are just dropping | |
1188 | * the ps_usecount here. | |
1189 | */ | |
1190 | ath9k_ps_restore(sc); | |
1191 | } | |
1192 | ||
528f0c6b | 1193 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1194 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1195 | |
226afe68 | 1196 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1197 | |
c52f33d0 | 1198 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1199 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1200 | goto exit; |
8feceb67 VT |
1201 | } |
1202 | ||
528f0c6b S |
1203 | return 0; |
1204 | exit: | |
1205 | dev_kfree_skb_any(skb); | |
8feceb67 | 1206 | return 0; |
f078f209 LR |
1207 | } |
1208 | ||
8feceb67 | 1209 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1210 | { |
9ac58615 | 1211 | struct ath_softc *sc = hw->priv; |
af03abec | 1212 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1213 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1214 | |
4c483817 S |
1215 | mutex_lock(&sc->mutex); |
1216 | ||
9a75c2ff VN |
1217 | if (led_blink) |
1218 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1219 | ||
c94dbff7 | 1220 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 1221 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9f42c2b6 | 1222 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1223 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1224 | |
9c84b797 | 1225 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1226 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1227 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1228 | return; |
1229 | } | |
8feceb67 | 1230 | |
3867cf6a S |
1231 | /* Ensure HW is awake when we try to shut it down. */ |
1232 | ath9k_ps_wakeup(sc); | |
1233 | ||
766ec4a9 | 1234 | if (ah->btcoex_hw.enabled) { |
af03abec | 1235 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1236 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1237 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1238 | } |
1239 | ||
6a6733f2 LR |
1240 | spin_lock_bh(&sc->sc_pcu_lock); |
1241 | ||
203043f5 SG |
1242 | /* prevent tasklets to enable interrupts once we disable them */ |
1243 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1244 | ||
ff37e337 S |
1245 | /* make sure h/w will not generate any interrupt |
1246 | * before setting the invalid flag. */ | |
4df3071e | 1247 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1248 | |
1249 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1250 | ath_drain_all_txq(sc, false); |
ff37e337 | 1251 | ath_stoprecv(sc); |
af03abec | 1252 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1253 | } else |
b77f483f | 1254 | sc->rx.rxlink = NULL; |
ff37e337 | 1255 | |
0d95521e FF |
1256 | if (sc->rx.frag) { |
1257 | dev_kfree_skb_any(sc->rx.frag); | |
1258 | sc->rx.frag = NULL; | |
1259 | } | |
1260 | ||
ff37e337 | 1261 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1262 | ath9k_hw_disable(ah); |
1263 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
6a6733f2 LR |
1264 | |
1265 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1266 | ||
203043f5 SG |
1267 | /* we can now sync irq and kill any running tasklets, since we already |
1268 | * disabled interrupts and not holding a spin lock */ | |
1269 | synchronize_irq(sc->irq); | |
1270 | tasklet_kill(&sc->intr_tq); | |
1271 | tasklet_kill(&sc->bcon_tasklet); | |
1272 | ||
3867cf6a S |
1273 | ath9k_ps_restore(sc); |
1274 | ||
a08e7ade LR |
1275 | sc->ps_idle = true; |
1276 | ath_radio_disable(sc, hw); | |
ff37e337 S |
1277 | |
1278 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1279 | |
141b38b6 S |
1280 | mutex_unlock(&sc->mutex); |
1281 | ||
226afe68 | 1282 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1283 | } |
1284 | ||
4801416c BG |
1285 | bool ath9k_uses_beacons(int type) |
1286 | { | |
1287 | switch (type) { | |
1288 | case NL80211_IFTYPE_AP: | |
1289 | case NL80211_IFTYPE_ADHOC: | |
1290 | case NL80211_IFTYPE_MESH_POINT: | |
1291 | return true; | |
1292 | default: | |
1293 | return false; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1298 | struct ieee80211_vif *vif) | |
f078f209 | 1299 | { |
1ed32e4f | 1300 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1301 | |
014cf3bb | 1302 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1303 | ath_beacon_return(sc, avp); |
014cf3bb | 1304 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1305 | sc->sc_flags &= ~SC_OP_BEACONS; |
4801416c BG |
1306 | } |
1307 | ||
1308 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1309 | { | |
1310 | struct ath9k_vif_iter_data *iter_data = data; | |
1311 | int i; | |
1312 | ||
1313 | if (iter_data->hw_macaddr) | |
1314 | for (i = 0; i < ETH_ALEN; i++) | |
1315 | iter_data->mask[i] &= | |
1316 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1317 | |
1ed32e4f | 1318 | switch (vif->type) { |
4801416c BG |
1319 | case NL80211_IFTYPE_AP: |
1320 | iter_data->naps++; | |
f078f209 | 1321 | break; |
4801416c BG |
1322 | case NL80211_IFTYPE_STATION: |
1323 | iter_data->nstations++; | |
e51f3eff | 1324 | break; |
05c914fe | 1325 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1326 | iter_data->nadhocs++; |
1327 | break; | |
9cb5412b | 1328 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1329 | iter_data->nmeshes++; |
1330 | break; | |
1331 | case NL80211_IFTYPE_WDS: | |
1332 | iter_data->nwds++; | |
f078f209 LR |
1333 | break; |
1334 | default: | |
4801416c BG |
1335 | iter_data->nothers++; |
1336 | break; | |
f078f209 | 1337 | } |
4801416c | 1338 | } |
f078f209 | 1339 | |
4801416c BG |
1340 | /* Called with sc->mutex held. */ |
1341 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1342 | struct ieee80211_vif *vif, | |
1343 | struct ath9k_vif_iter_data *iter_data) | |
1344 | { | |
9ac58615 | 1345 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1346 | struct ath_hw *ah = sc->sc_ah; |
1347 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1348 | |
4801416c BG |
1349 | /* |
1350 | * Use the hardware MAC address as reference, the hardware uses it | |
1351 | * together with the BSSID mask when matching addresses. | |
1352 | */ | |
1353 | memset(iter_data, 0, sizeof(*iter_data)); | |
1354 | iter_data->hw_macaddr = common->macaddr; | |
1355 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1356 | |
4801416c BG |
1357 | if (vif) |
1358 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1359 | ||
1360 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1361 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1362 | iter_data); | |
4801416c | 1363 | } |
8ca21f01 | 1364 | |
4801416c BG |
1365 | /* Called with sc->mutex held. */ |
1366 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1367 | struct ieee80211_vif *vif) | |
1368 | { | |
9ac58615 | 1369 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1370 | struct ath_hw *ah = sc->sc_ah; |
1371 | struct ath_common *common = ath9k_hw_common(ah); | |
1372 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1373 | |
4801416c | 1374 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1375 | |
4c89fe95 | 1376 | ath9k_ps_wakeup(sc); |
4801416c BG |
1377 | /* Set BSSID mask. */ |
1378 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1379 | ath_hw_setbssidmask(common); | |
1380 | ||
1381 | /* Set op-mode & TSF */ | |
1382 | if (iter_data.naps > 0) { | |
3069168c | 1383 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1384 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1385 | ah->opmode = NL80211_IFTYPE_AP; |
1386 | } else { | |
1387 | ath9k_hw_set_tsfadjust(ah, 0); | |
1388 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1389 | |
4801416c BG |
1390 | if (iter_data.nwds + iter_data.nmeshes) |
1391 | ah->opmode = NL80211_IFTYPE_AP; | |
1392 | else if (iter_data.nadhocs) | |
1393 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1394 | else | |
1395 | ah->opmode = NL80211_IFTYPE_STATION; | |
1396 | } | |
5640b08e | 1397 | |
4e30ffa2 VN |
1398 | /* |
1399 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1400 | */ |
4801416c | 1401 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1402 | if (ah->config.enable_ani) |
1403 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1404 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1405 | } else { |
1406 | ah->imask &= ~ATH9K_INT_MIB; | |
1407 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1408 | } |
1409 | ||
3069168c | 1410 | ath9k_hw_set_interrupts(ah, ah->imask); |
4c89fe95 | 1411 | ath9k_ps_restore(sc); |
4e30ffa2 | 1412 | |
4801416c BG |
1413 | /* Set up ANI */ |
1414 | if ((iter_data.naps + iter_data.nadhocs) > 0) { | |
6c3118e2 | 1415 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 1416 | ath_start_ani(common); |
4801416c BG |
1417 | } else { |
1418 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1419 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1420 | } |
4801416c | 1421 | } |
6f255425 | 1422 | |
4801416c BG |
1423 | /* Called with sc->mutex held, vif counts set up properly. */ |
1424 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1425 | struct ieee80211_vif *vif) | |
1426 | { | |
9ac58615 | 1427 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1428 | |
1429 | ath9k_calculate_summary_state(hw, vif); | |
1430 | ||
1431 | if (ath9k_uses_beacons(vif->type)) { | |
1432 | int error; | |
4801416c BG |
1433 | /* This may fail because upper levels do not have beacons |
1434 | * properly configured yet. That's OK, we assume it | |
1435 | * will be properly configured and then we will be notified | |
1436 | * in the info_changed method and set up beacons properly | |
1437 | * there. | |
1438 | */ | |
014cf3bb | 1439 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1440 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1441 | if (!error) |
4801416c | 1442 | ath_beacon_config(sc, vif); |
014cf3bb | 1443 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1444 | } |
f078f209 LR |
1445 | } |
1446 | ||
4801416c BG |
1447 | |
1448 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1449 | struct ieee80211_vif *vif) | |
6b3b991d | 1450 | { |
9ac58615 | 1451 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1452 | struct ath_hw *ah = sc->sc_ah; |
1453 | struct ath_common *common = ath9k_hw_common(ah); | |
6b3b991d | 1454 | struct ath_vif *avp = (void *)vif->drv_priv; |
4801416c | 1455 | int ret = 0; |
6b3b991d | 1456 | |
4801416c | 1457 | mutex_lock(&sc->mutex); |
6b3b991d | 1458 | |
4801416c BG |
1459 | switch (vif->type) { |
1460 | case NL80211_IFTYPE_STATION: | |
1461 | case NL80211_IFTYPE_WDS: | |
1462 | case NL80211_IFTYPE_ADHOC: | |
1463 | case NL80211_IFTYPE_AP: | |
1464 | case NL80211_IFTYPE_MESH_POINT: | |
1465 | break; | |
1466 | default: | |
1467 | ath_err(common, "Interface type %d not yet supported\n", | |
1468 | vif->type); | |
1469 | ret = -EOPNOTSUPP; | |
1470 | goto out; | |
1471 | } | |
6b3b991d | 1472 | |
4801416c BG |
1473 | if (ath9k_uses_beacons(vif->type)) { |
1474 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1475 | ath_err(common, "Not enough beacon buffers when adding" | |
1476 | " new interface of type: %i\n", | |
1477 | vif->type); | |
1478 | ret = -ENOBUFS; | |
1479 | goto out; | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | if ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1484 | sc->nvifs > 0) { | |
1485 | ath_err(common, "Cannot create ADHOC interface when other" | |
1486 | " interfaces already exist.\n"); | |
1487 | ret = -EINVAL; | |
1488 | goto out; | |
6b3b991d | 1489 | } |
4801416c BG |
1490 | |
1491 | ath_dbg(common, ATH_DBG_CONFIG, | |
1492 | "Attach a VIF of type: %d\n", vif->type); | |
1493 | ||
1494 | /* Set the VIF opmode */ | |
1495 | avp->av_opmode = vif->type; | |
1496 | avp->av_bslot = -1; | |
1497 | ||
1498 | sc->nvifs++; | |
1499 | ||
1500 | ath9k_do_vif_add_setup(hw, vif); | |
1501 | out: | |
1502 | mutex_unlock(&sc->mutex); | |
1503 | return ret; | |
6b3b991d RM |
1504 | } |
1505 | ||
1506 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1507 | struct ieee80211_vif *vif, | |
1508 | enum nl80211_iftype new_type, | |
1509 | bool p2p) | |
1510 | { | |
9ac58615 | 1511 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1512 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1513 | int ret = 0; |
6b3b991d RM |
1514 | |
1515 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1516 | mutex_lock(&sc->mutex); | |
1517 | ||
4801416c BG |
1518 | /* See if new interface type is valid. */ |
1519 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1520 | (sc->nvifs > 1)) { | |
1521 | ath_err(common, "When using ADHOC, it must be the only" | |
1522 | " interface.\n"); | |
1523 | ret = -EINVAL; | |
1524 | goto out; | |
1525 | } | |
1526 | ||
1527 | if (ath9k_uses_beacons(new_type) && | |
1528 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1529 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1530 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1531 | ret = -ENOBUFS; |
1532 | goto out; | |
6b3b991d | 1533 | } |
6b3b991d | 1534 | } |
4801416c BG |
1535 | |
1536 | /* Clean up old vif stuff */ | |
1537 | if (ath9k_uses_beacons(vif->type)) | |
1538 | ath9k_reclaim_beacon(sc, vif); | |
1539 | ||
1540 | /* Add new settings */ | |
6b3b991d RM |
1541 | vif->type = new_type; |
1542 | vif->p2p = p2p; | |
1543 | ||
4801416c | 1544 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1545 | out: |
6b3b991d | 1546 | mutex_unlock(&sc->mutex); |
6dab55bf | 1547 | return ret; |
6b3b991d RM |
1548 | } |
1549 | ||
8feceb67 | 1550 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1551 | struct ieee80211_vif *vif) |
f078f209 | 1552 | { |
9ac58615 | 1553 | struct ath_softc *sc = hw->priv; |
c46917bb | 1554 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1555 | |
226afe68 | 1556 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1557 | |
141b38b6 S |
1558 | mutex_lock(&sc->mutex); |
1559 | ||
4801416c | 1560 | sc->nvifs--; |
580f0b8a | 1561 | |
8feceb67 | 1562 | /* Reclaim beacon resources */ |
4801416c | 1563 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1564 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1565 | |
4801416c | 1566 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1567 | |
1568 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1569 | } |
1570 | ||
fbab7390 | 1571 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1572 | { |
3069168c PR |
1573 | struct ath_hw *ah = sc->sc_ah; |
1574 | ||
3f7c5c10 | 1575 | sc->ps_enabled = true; |
3069168c PR |
1576 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1577 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1578 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1579 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1580 | } |
fdf76622 | 1581 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1582 | } |
3f7c5c10 SB |
1583 | } |
1584 | ||
845d708e SB |
1585 | static void ath9k_disable_ps(struct ath_softc *sc) |
1586 | { | |
1587 | struct ath_hw *ah = sc->sc_ah; | |
1588 | ||
1589 | sc->ps_enabled = false; | |
1590 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1591 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1592 | ath9k_hw_setrxabort(ah, 0); | |
1593 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1594 | PS_WAIT_FOR_CAB | | |
1595 | PS_WAIT_FOR_PSPOLL_DATA | | |
1596 | PS_WAIT_FOR_TX_ACK); | |
1597 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1598 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1599 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | } | |
1604 | ||
e8975581 | 1605 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1606 | { |
9ac58615 | 1607 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1608 | struct ath_hw *ah = sc->sc_ah; |
1609 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1610 | struct ieee80211_conf *conf = &hw->conf; |
7545daf4 | 1611 | bool disable_radio = false; |
f078f209 | 1612 | |
aa33de09 | 1613 | mutex_lock(&sc->mutex); |
141b38b6 | 1614 | |
194b7c13 LR |
1615 | /* |
1616 | * Leave this as the first check because we need to turn on the | |
1617 | * radio if it was disabled before prior to processing the rest | |
1618 | * of the changes. Likewise we must only disable the radio towards | |
1619 | * the end. | |
1620 | */ | |
64839170 | 1621 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 FF |
1622 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
1623 | if (!sc->ps_idle) { | |
68a89116 | 1624 | ath_radio_enable(sc, hw); |
226afe68 JP |
1625 | ath_dbg(common, ATH_DBG_CONFIG, |
1626 | "not-idle: enabling radio\n"); | |
7545daf4 FF |
1627 | } else { |
1628 | disable_radio = true; | |
64839170 LR |
1629 | } |
1630 | } | |
1631 | ||
e7824a50 LR |
1632 | /* |
1633 | * We just prepare to enable PS. We have to wait until our AP has | |
1634 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1635 | * those ACKs and end up retransmitting the same null data frames. | |
1636 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1637 | */ | |
3cbb5dd7 | 1638 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1639 | unsigned long flags; |
1640 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1641 | if (conf->flags & IEEE80211_CONF_PS) |
1642 | ath9k_enable_ps(sc); | |
845d708e SB |
1643 | else |
1644 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1645 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1646 | } |
1647 | ||
199afd9d S |
1648 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1649 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1650 | ath_dbg(common, ATH_DBG_CONFIG, |
1651 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1652 | sc->sc_ah->is_monitoring = true; |
1653 | } else { | |
226afe68 JP |
1654 | ath_dbg(common, ATH_DBG_CONFIG, |
1655 | "Monitor mode is disabled\n"); | |
5f841b41 | 1656 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1657 | } |
1658 | } | |
1659 | ||
4797938c | 1660 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1661 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1662 | int pos = curchan->hw_value; |
3430098a FF |
1663 | int old_pos = -1; |
1664 | unsigned long flags; | |
1665 | ||
1666 | if (ah->curchan) | |
1667 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1668 | |
5ee08656 FF |
1669 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1670 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1671 | else | |
1672 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1673 | |
8c79a610 BG |
1674 | ath_dbg(common, ATH_DBG_CONFIG, |
1675 | "Set channel: %d MHz type: %d\n", | |
1676 | curchan->center_freq, conf->channel_type); | |
f078f209 | 1677 | |
de87f736 RM |
1678 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], |
1679 | curchan, conf->channel_type); | |
e11602b7 | 1680 | |
3430098a FF |
1681 | /* update survey stats for the old channel before switching */ |
1682 | spin_lock_irqsave(&common->cc_lock, flags); | |
1683 | ath_update_survey_stats(sc); | |
1684 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1685 | ||
1686 | /* | |
1687 | * If the operating channel changes, change the survey in-use flags | |
1688 | * along with it. | |
1689 | * Reset the survey data for the new channel, unless we're switching | |
1690 | * back to the operating channel from an off-channel operation. | |
1691 | */ | |
1692 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1693 | sc->cur_survey != &sc->survey[pos]) { | |
1694 | ||
1695 | if (sc->cur_survey) | |
1696 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1697 | ||
1698 | sc->cur_survey = &sc->survey[pos]; | |
1699 | ||
1700 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1701 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1702 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1703 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1704 | } | |
1705 | ||
0e2dedf9 | 1706 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1707 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1708 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1709 | return -EINVAL; |
1710 | } | |
3430098a FF |
1711 | |
1712 | /* | |
1713 | * The most recent snapshot of channel->noisefloor for the old | |
1714 | * channel is only available after the hardware reset. Copy it to | |
1715 | * the survey stats now. | |
1716 | */ | |
1717 | if (old_pos >= 0) | |
1718 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1719 | } |
f078f209 | 1720 | |
c9f6a656 | 1721 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
603b3eef BG |
1722 | ath_dbg(common, ATH_DBG_CONFIG, |
1723 | "Set power: %d\n", conf->power_level); | |
17d7904d | 1724 | sc->config.txpowlimit = 2 * conf->power_level; |
783cd01e | 1725 | ath9k_ps_wakeup(sc); |
5048e8c3 RM |
1726 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1727 | sc->config.txpowlimit, &sc->curtxpow); | |
783cd01e | 1728 | ath9k_ps_restore(sc); |
c9f6a656 | 1729 | } |
f078f209 | 1730 | |
64839170 | 1731 | if (disable_radio) { |
226afe68 | 1732 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1733 | ath_radio_disable(sc, hw); |
64839170 LR |
1734 | } |
1735 | ||
aa33de09 | 1736 | mutex_unlock(&sc->mutex); |
141b38b6 | 1737 | |
f078f209 LR |
1738 | return 0; |
1739 | } | |
1740 | ||
8feceb67 VT |
1741 | #define SUPPORTED_FILTERS \ |
1742 | (FIF_PROMISC_IN_BSS | \ | |
1743 | FIF_ALLMULTI | \ | |
1744 | FIF_CONTROL | \ | |
af6a3fc7 | 1745 | FIF_PSPOLL | \ |
8feceb67 VT |
1746 | FIF_OTHER_BSS | \ |
1747 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1748 | FIF_PROBE_REQ | \ |
8feceb67 | 1749 | FIF_FCSFAIL) |
c83be688 | 1750 | |
8feceb67 VT |
1751 | /* FIXME: sc->sc_full_reset ? */ |
1752 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1753 | unsigned int changed_flags, | |
1754 | unsigned int *total_flags, | |
3ac64bee | 1755 | u64 multicast) |
8feceb67 | 1756 | { |
9ac58615 | 1757 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1758 | u32 rfilt; |
f078f209 | 1759 | |
8feceb67 VT |
1760 | changed_flags &= SUPPORTED_FILTERS; |
1761 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1762 | |
b77f483f | 1763 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1764 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1765 | rfilt = ath_calcrxfilter(sc); |
1766 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1767 | ath9k_ps_restore(sc); |
f078f209 | 1768 | |
226afe68 JP |
1769 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1770 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1771 | } |
f078f209 | 1772 | |
4ca77860 JB |
1773 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1774 | struct ieee80211_vif *vif, | |
1775 | struct ieee80211_sta *sta) | |
8feceb67 | 1776 | { |
9ac58615 | 1777 | struct ath_softc *sc = hw->priv; |
f078f209 | 1778 | |
4ca77860 JB |
1779 | ath_node_attach(sc, sta); |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
1784 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1785 | struct ieee80211_vif *vif, | |
1786 | struct ieee80211_sta *sta) | |
1787 | { | |
9ac58615 | 1788 | struct ath_softc *sc = hw->priv; |
4ca77860 JB |
1789 | |
1790 | ath_node_detach(sc, sta); | |
1791 | ||
1792 | return 0; | |
f078f209 LR |
1793 | } |
1794 | ||
141b38b6 | 1795 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1796 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1797 | { |
9ac58615 | 1798 | struct ath_softc *sc = hw->priv; |
c46917bb | 1799 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1800 | struct ath_txq *txq; |
8feceb67 | 1801 | struct ath9k_tx_queue_info qi; |
066dae93 | 1802 | int ret = 0; |
f078f209 | 1803 | |
8feceb67 VT |
1804 | if (queue >= WME_NUM_AC) |
1805 | return 0; | |
f078f209 | 1806 | |
066dae93 FF |
1807 | txq = sc->tx.txq_map[queue]; |
1808 | ||
141b38b6 S |
1809 | mutex_lock(&sc->mutex); |
1810 | ||
1ffb0610 S |
1811 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1812 | ||
8feceb67 VT |
1813 | qi.tqi_aifs = params->aifs; |
1814 | qi.tqi_cwmin = params->cw_min; | |
1815 | qi.tqi_cwmax = params->cw_max; | |
1816 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1817 | |
226afe68 JP |
1818 | ath_dbg(common, ATH_DBG_CONFIG, |
1819 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1820 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1821 | params->cw_max, params->txop); | |
f078f209 | 1822 | |
066dae93 | 1823 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1824 | if (ret) |
3800276a | 1825 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1826 | |
94db2936 | 1827 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1828 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1829 | ath_beaconq_config(sc); |
1830 | ||
141b38b6 S |
1831 | mutex_unlock(&sc->mutex); |
1832 | ||
8feceb67 VT |
1833 | return ret; |
1834 | } | |
f078f209 | 1835 | |
8feceb67 VT |
1836 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1837 | enum set_key_cmd cmd, | |
dc822b5d JB |
1838 | struct ieee80211_vif *vif, |
1839 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1840 | struct ieee80211_key_conf *key) |
1841 | { | |
9ac58615 | 1842 | struct ath_softc *sc = hw->priv; |
c46917bb | 1843 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1844 | int ret = 0; |
f078f209 | 1845 | |
3e6109c5 | 1846 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1847 | return -ENOSPC; |
1848 | ||
141b38b6 | 1849 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1850 | ath9k_ps_wakeup(sc); |
226afe68 | 1851 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1852 | |
8feceb67 VT |
1853 | switch (cmd) { |
1854 | case SET_KEY: | |
040e539e | 1855 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1856 | if (ret >= 0) { |
1857 | key->hw_key_idx = ret; | |
8feceb67 VT |
1858 | /* push IV and Michael MIC generation to stack */ |
1859 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1860 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1861 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1862 | if (sc->sc_ah->sw_mgmt_crypto && |
1863 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1864 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1865 | ret = 0; |
8feceb67 VT |
1866 | } |
1867 | break; | |
1868 | case DISABLE_KEY: | |
040e539e | 1869 | ath_key_delete(common, key); |
8feceb67 VT |
1870 | break; |
1871 | default: | |
1872 | ret = -EINVAL; | |
1873 | } | |
f078f209 | 1874 | |
3cbb5dd7 | 1875 | ath9k_ps_restore(sc); |
141b38b6 S |
1876 | mutex_unlock(&sc->mutex); |
1877 | ||
8feceb67 VT |
1878 | return ret; |
1879 | } | |
f078f209 | 1880 | |
8feceb67 VT |
1881 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1882 | struct ieee80211_vif *vif, | |
1883 | struct ieee80211_bss_conf *bss_conf, | |
1884 | u32 changed) | |
1885 | { | |
9ac58615 | 1886 | struct ath_softc *sc = hw->priv; |
9814f6b3 | 1887 | struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; |
2d0ddec5 | 1888 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1889 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1890 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1891 | int slottime; |
c6089ccc | 1892 | int error; |
f078f209 | 1893 | |
141b38b6 S |
1894 | mutex_lock(&sc->mutex); |
1895 | ||
c6089ccc S |
1896 | if (changed & BSS_CHANGED_BSSID) { |
1897 | /* Set BSSID */ | |
1898 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1899 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1900 | common->curaid = 0; |
f2b2143e | 1901 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1902 | |
c6089ccc S |
1903 | /* Set aggregation protection mode parameters */ |
1904 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1905 | |
226afe68 JP |
1906 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
1907 | common->curbssid, common->curaid); | |
2d0ddec5 | 1908 | |
c6089ccc S |
1909 | /* need to reconfigure the beacon */ |
1910 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1911 | } | |
2d0ddec5 | 1912 | |
c6089ccc S |
1913 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1914 | if ((changed & BSS_CHANGED_BEACON) || | |
1915 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
014cf3bb | 1916 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1917 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
1918 | if (!error) |
1919 | ath_beacon_config(sc, vif); | |
014cf3bb | 1920 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
1921 | } |
1922 | ||
1923 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1924 | if (bss_conf->use_short_slot) | |
1925 | slottime = 9; | |
1926 | else | |
1927 | slottime = 20; | |
1928 | if (vif->type == NL80211_IFTYPE_AP) { | |
1929 | /* | |
1930 | * Defer update, so that connected stations can adjust | |
1931 | * their settings at the same time. | |
1932 | * See beacon.c for more details | |
1933 | */ | |
1934 | sc->beacon.slottime = slottime; | |
1935 | sc->beacon.updateslot = UPDATE; | |
1936 | } else { | |
1937 | ah->slottime = slottime; | |
1938 | ath9k_hw_init_global_settings(ah); | |
1939 | } | |
2d0ddec5 JB |
1940 | } |
1941 | ||
c6089ccc | 1942 | /* Disable transmission of beacons */ |
014cf3bb RM |
1943 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && |
1944 | !bss_conf->enable_beacon) { | |
1945 | ath9k_set_beaconing_status(sc, false); | |
1946 | avp->is_bslot_active = false; | |
1947 | ath9k_set_beaconing_status(sc, true); | |
1948 | } | |
2d0ddec5 | 1949 | |
c6089ccc | 1950 | if (changed & BSS_CHANGED_BEACON_INT) { |
9814f6b3 | 1951 | cur_conf->beacon_interval = bss_conf->beacon_int; |
c6089ccc S |
1952 | /* |
1953 | * In case of AP mode, the HW TSF has to be reset | |
1954 | * when the beacon interval changes. | |
1955 | */ | |
1956 | if (vif->type == NL80211_IFTYPE_AP) { | |
1957 | sc->sc_flags |= SC_OP_TSF_RESET; | |
014cf3bb | 1958 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1959 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
1960 | if (!error) |
1961 | ath_beacon_config(sc, vif); | |
014cf3bb | 1962 | ath9k_set_beaconing_status(sc, true); |
c6089ccc S |
1963 | } else { |
1964 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1965 | } |
1966 | } | |
1967 | ||
8feceb67 | 1968 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
1969 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1970 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1971 | if (bss_conf->use_short_preamble) |
1972 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1973 | else | |
1974 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1975 | } | |
f078f209 | 1976 | |
8feceb67 | 1977 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
1978 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1979 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1980 | if (bss_conf->use_cts_prot && |
1981 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1982 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1983 | else | |
1984 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1985 | } | |
f078f209 | 1986 | |
8feceb67 | 1987 | if (changed & BSS_CHANGED_ASSOC) { |
226afe68 | 1988 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1989 | bss_conf->assoc); |
9fa23e17 | 1990 | ath9k_bss_assoc_info(sc, hw, vif, bss_conf); |
8feceb67 | 1991 | } |
141b38b6 S |
1992 | |
1993 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1994 | } |
f078f209 | 1995 | |
8feceb67 VT |
1996 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1997 | { | |
9ac58615 | 1998 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1999 | u64 tsf; |
f078f209 | 2000 | |
141b38b6 | 2001 | mutex_lock(&sc->mutex); |
9abbfb27 | 2002 | ath9k_ps_wakeup(sc); |
141b38b6 | 2003 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2004 | ath9k_ps_restore(sc); |
141b38b6 | 2005 | mutex_unlock(&sc->mutex); |
f078f209 | 2006 | |
8feceb67 VT |
2007 | return tsf; |
2008 | } | |
f078f209 | 2009 | |
3b5d665b AF |
2010 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2011 | { | |
9ac58615 | 2012 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2013 | |
141b38b6 | 2014 | mutex_lock(&sc->mutex); |
9abbfb27 | 2015 | ath9k_ps_wakeup(sc); |
141b38b6 | 2016 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2017 | ath9k_ps_restore(sc); |
141b38b6 | 2018 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2019 | } |
2020 | ||
8feceb67 VT |
2021 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2022 | { | |
9ac58615 | 2023 | struct ath_softc *sc = hw->priv; |
c83be688 | 2024 | |
141b38b6 | 2025 | mutex_lock(&sc->mutex); |
21526d57 LR |
2026 | |
2027 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2028 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2029 | ath9k_ps_restore(sc); |
2030 | ||
141b38b6 | 2031 | mutex_unlock(&sc->mutex); |
8feceb67 | 2032 | } |
f078f209 | 2033 | |
8feceb67 | 2034 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2035 | struct ieee80211_vif *vif, |
141b38b6 S |
2036 | enum ieee80211_ampdu_mlme_action action, |
2037 | struct ieee80211_sta *sta, | |
0b01f030 | 2038 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2039 | { |
9ac58615 | 2040 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2041 | int ret = 0; |
f078f209 | 2042 | |
85ad181e JB |
2043 | local_bh_disable(); |
2044 | ||
8feceb67 VT |
2045 | switch (action) { |
2046 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2047 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2048 | ret = -ENOTSUPP; | |
8feceb67 VT |
2049 | break; |
2050 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2051 | break; |
2052 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2053 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2054 | return -EOPNOTSUPP; | |
2055 | ||
8b685ba9 | 2056 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2057 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2058 | if (!ret) | |
2059 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2060 | ath9k_ps_restore(sc); |
8feceb67 VT |
2061 | break; |
2062 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2063 | ath9k_ps_wakeup(sc); |
f83da965 | 2064 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2065 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2066 | ath9k_ps_restore(sc); |
8feceb67 | 2067 | break; |
b1720231 | 2068 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2069 | ath9k_ps_wakeup(sc); |
8469cdef | 2070 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2071 | ath9k_ps_restore(sc); |
8469cdef | 2072 | break; |
8feceb67 | 2073 | default: |
3800276a | 2074 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2075 | } |
2076 | ||
85ad181e JB |
2077 | local_bh_enable(); |
2078 | ||
8feceb67 | 2079 | return ret; |
f078f209 LR |
2080 | } |
2081 | ||
62dad5b0 BP |
2082 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2083 | struct survey_info *survey) | |
2084 | { | |
9ac58615 | 2085 | struct ath_softc *sc = hw->priv; |
3430098a | 2086 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2087 | struct ieee80211_supported_band *sband; |
3430098a FF |
2088 | struct ieee80211_channel *chan; |
2089 | unsigned long flags; | |
2090 | int pos; | |
2091 | ||
2092 | spin_lock_irqsave(&common->cc_lock, flags); | |
2093 | if (idx == 0) | |
2094 | ath_update_survey_stats(sc); | |
39162dbe FF |
2095 | |
2096 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2097 | if (sband && idx >= sband->n_channels) { | |
2098 | idx -= sband->n_channels; | |
2099 | sband = NULL; | |
2100 | } | |
62dad5b0 | 2101 | |
39162dbe FF |
2102 | if (!sband) |
2103 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2104 | |
3430098a FF |
2105 | if (!sband || idx >= sband->n_channels) { |
2106 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2107 | return -ENOENT; | |
4f1a5a4b | 2108 | } |
62dad5b0 | 2109 | |
3430098a FF |
2110 | chan = &sband->channels[idx]; |
2111 | pos = chan->hw_value; | |
2112 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2113 | survey->channel = chan; | |
2114 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2115 | ||
62dad5b0 BP |
2116 | return 0; |
2117 | } | |
2118 | ||
e239d859 FF |
2119 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2120 | { | |
9ac58615 | 2121 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2122 | struct ath_hw *ah = sc->sc_ah; |
2123 | ||
2124 | mutex_lock(&sc->mutex); | |
2125 | ah->coverage_class = coverage_class; | |
2126 | ath9k_hw_init_global_settings(ah); | |
2127 | mutex_unlock(&sc->mutex); | |
2128 | } | |
2129 | ||
69081624 VT |
2130 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2131 | { | |
2132 | #define ATH_FLUSH_TIMEOUT 60 /* ms */ | |
2133 | struct ath_softc *sc = hw->priv; | |
2134 | struct ath_txq *txq; | |
2135 | struct ath_hw *ah = sc->sc_ah; | |
2136 | struct ath_common *common = ath9k_hw_common(ah); | |
2137 | int i, j, npend = 0; | |
2138 | ||
2139 | mutex_lock(&sc->mutex); | |
2140 | ||
2141 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
2142 | ||
2143 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2144 | if (!ATH_TXQ_SETUP(sc, i)) | |
2145 | continue; | |
2146 | txq = &sc->tx.txq[i]; | |
2147 | ||
2148 | if (!drop) { | |
2149 | for (j = 0; j < ATH_FLUSH_TIMEOUT; j++) { | |
2150 | if (!ath9k_has_pending_frames(sc, txq)) | |
2151 | break; | |
2152 | usleep_range(1000, 2000); | |
2153 | } | |
2154 | } | |
2155 | ||
2156 | if (drop || ath9k_has_pending_frames(sc, txq)) { | |
2157 | ath_dbg(common, ATH_DBG_QUEUE, "Drop frames from hw queue:%d\n", | |
2158 | txq->axq_qnum); | |
2159 | spin_lock_bh(&txq->axq_lock); | |
2160 | txq->txq_flush_inprogress = true; | |
2161 | spin_unlock_bh(&txq->axq_lock); | |
2162 | ||
2163 | ath9k_ps_wakeup(sc); | |
2164 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
2165 | npend = ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
2166 | ath9k_ps_restore(sc); | |
2167 | if (npend) | |
2168 | break; | |
2169 | ||
2170 | ath_draintxq(sc, txq, false); | |
2171 | txq->txq_flush_inprogress = false; | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | if (npend) { | |
2176 | ath_reset(sc, false); | |
2177 | txq->txq_flush_inprogress = false; | |
2178 | } | |
2179 | ||
2180 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); | |
2181 | mutex_unlock(&sc->mutex); | |
2182 | } | |
2183 | ||
6baff7f9 | 2184 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2185 | .tx = ath9k_tx, |
2186 | .start = ath9k_start, | |
2187 | .stop = ath9k_stop, | |
2188 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2189 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2190 | .remove_interface = ath9k_remove_interface, |
2191 | .config = ath9k_config, | |
8feceb67 | 2192 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2193 | .sta_add = ath9k_sta_add, |
2194 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2195 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2196 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2197 | .set_key = ath9k_set_key, |
8feceb67 | 2198 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2199 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2200 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2201 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2202 | .get_survey = ath9k_get_survey, |
3b319aae | 2203 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2204 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2205 | .flush = ath9k_flush, |
8feceb67 | 2206 | }; |