Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
54 | u32 txpow; |
55 | ||
17d7904d S |
56 | if (sc->curtxpow != sc->config.txpowlimit) { |
57 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
58 | /* read back in case value is clamped */ |
59 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 60 | sc->curtxpow = txpow; |
ff37e337 S |
61 | } |
62 | } | |
63 | ||
64 | static u8 parse_mpdudensity(u8 mpdudensity) | |
65 | { | |
66 | /* | |
67 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
68 | * 0 for no restriction | |
69 | * 1 for 1/4 us | |
70 | * 2 for 1/2 us | |
71 | * 3 for 1 us | |
72 | * 4 for 2 us | |
73 | * 5 for 4 us | |
74 | * 6 for 8 us | |
75 | * 7 for 16 us | |
76 | */ | |
77 | switch (mpdudensity) { | |
78 | case 0: | |
79 | return 0; | |
80 | case 1: | |
81 | case 2: | |
82 | case 3: | |
83 | /* Our lower layer calculations limit our precision to | |
84 | 1 microsecond */ | |
85 | return 1; | |
86 | case 4: | |
87 | return 2; | |
88 | case 5: | |
89 | return 4; | |
90 | case 6: | |
91 | return 8; | |
92 | case 7: | |
93 | return 16; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
82880a7c VT |
99 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
100 | struct ieee80211_hw *hw) | |
101 | { | |
102 | struct ieee80211_channel *curchan = hw->conf.channel; | |
103 | struct ath9k_channel *channel; | |
104 | u8 chan_idx; | |
105 | ||
106 | chan_idx = curchan->hw_value; | |
107 | channel = &sc->sc_ah->channels[chan_idx]; | |
108 | ath9k_update_ichannel(sc, hw, channel); | |
109 | return channel; | |
110 | } | |
111 | ||
55624204 | 112 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
113 | { |
114 | unsigned long flags; | |
115 | bool ret; | |
116 | ||
9ecdef4b LR |
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
118 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
119 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
120 | |
121 | return ret; | |
122 | } | |
123 | ||
a91d75ae LR |
124 | void ath9k_ps_wakeup(struct ath_softc *sc) |
125 | { | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
129 | if (++sc->ps_usecount != 1) | |
130 | goto unlock; | |
131 | ||
9ecdef4b | 132 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
133 | |
134 | unlock: | |
135 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
136 | } | |
137 | ||
138 | void ath9k_ps_restore(struct ath_softc *sc) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
143 | if (--sc->ps_usecount != 0) | |
144 | goto unlock; | |
145 | ||
1dbfd9d4 VN |
146 | if (sc->ps_idle) |
147 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
148 | else if (sc->ps_enabled && | |
149 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
150 | PS_WAIT_FOR_CAB | |
151 | PS_WAIT_FOR_PSPOLL_DATA | | |
152 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 153 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
154 | |
155 | unlock: | |
156 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
157 | } | |
158 | ||
ff37e337 S |
159 | /* |
160 | * Set/change channels. If the channel is really being changed, it's done | |
161 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
162 | * DMA, then restart stuff. | |
163 | */ | |
0e2dedf9 JM |
164 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
165 | struct ath9k_channel *hchan) | |
ff37e337 | 166 | { |
cbe61d8a | 167 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 168 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 169 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 170 | bool fastcc = true, stopped; |
ae8d2858 LR |
171 | struct ieee80211_channel *channel = hw->conf.channel; |
172 | int r; | |
ff37e337 S |
173 | |
174 | if (sc->sc_flags & SC_OP_INVALID) | |
175 | return -EIO; | |
176 | ||
3cbb5dd7 VN |
177 | ath9k_ps_wakeup(sc); |
178 | ||
c0d7c7af LR |
179 | /* |
180 | * This is only performed if the channel settings have | |
181 | * actually changed. | |
182 | * | |
183 | * To switch channels clear any pending DMA operations; | |
184 | * wait long enough for the RX fifo to drain, reset the | |
185 | * hardware at the new frequency, and then re-enable | |
186 | * the relevant bits of the h/w. | |
187 | */ | |
188 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 189 | ath_drain_all_txq(sc, false); |
c0d7c7af | 190 | stopped = ath_stoprecv(sc); |
ff37e337 | 191 | |
c0d7c7af LR |
192 | /* XXX: do not flush receive queue here. We don't want |
193 | * to flush data frames already in queue because of | |
194 | * changing channel. */ | |
ff37e337 | 195 | |
c0d7c7af LR |
196 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
197 | fastcc = false; | |
198 | ||
c46917bb | 199 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 200 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 201 | sc->sc_ah->curchan->channel, |
25c56eec | 202 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 203 | |
c0d7c7af LR |
204 | spin_lock_bh(&sc->sc_resetlock); |
205 | ||
206 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
207 | if (r) { | |
c46917bb | 208 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 209 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
210 | "reset status %d\n", |
211 | channel->center_freq, r); | |
c0d7c7af | 212 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 213 | goto ps_restore; |
ff37e337 | 214 | } |
c0d7c7af LR |
215 | spin_unlock_bh(&sc->sc_resetlock); |
216 | ||
c0d7c7af LR |
217 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
218 | ||
219 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
220 | ath_print(common, ATH_DBG_FATAL, |
221 | "Unable to restart recv logic\n"); | |
3989279c GJ |
222 | r = -EIO; |
223 | goto ps_restore; | |
c0d7c7af LR |
224 | } |
225 | ||
226 | ath_cache_conf_rate(sc, &hw->conf); | |
227 | ath_update_txpow(sc); | |
3069168c | 228 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c GJ |
229 | |
230 | ps_restore: | |
3cbb5dd7 | 231 | ath9k_ps_restore(sc); |
3989279c | 232 | return r; |
ff37e337 S |
233 | } |
234 | ||
235 | /* | |
236 | * This routine performs the periodic noise floor calibration function | |
237 | * that is used to adjust and optimize the chip performance. This | |
238 | * takes environmental changes (location, temperature) into account. | |
239 | * When the task is complete, it reschedules itself depending on the | |
240 | * appropriate interval that was calculated. | |
241 | */ | |
55624204 | 242 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 243 | { |
20977d3e S |
244 | struct ath_softc *sc = (struct ath_softc *)data; |
245 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 246 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
247 | bool longcal = false; |
248 | bool shortcal = false; | |
249 | bool aniflag = false; | |
250 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 251 | u32 cal_interval, short_cal_interval; |
ff37e337 | 252 | |
20977d3e S |
253 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
254 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 255 | |
1ffc1c61 JM |
256 | /* Only calibrate if awake */ |
257 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
258 | goto set_timer; | |
259 | ||
260 | ath9k_ps_wakeup(sc); | |
261 | ||
ff37e337 | 262 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 263 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 264 | longcal = true; |
c46917bb | 265 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 266 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
267 | } |
268 | ||
17d7904d | 269 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
270 | if (!common->ani.caldone) { |
271 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 272 | shortcal = true; |
c46917bb LR |
273 | ath_print(common, ATH_DBG_ANI, |
274 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
275 | common->ani.shortcal_timer = timestamp; |
276 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
277 | } |
278 | } else { | |
3d536acf | 279 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 280 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
281 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
282 | if (common->ani.caldone) | |
283 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
284 | } |
285 | } | |
286 | ||
287 | /* Verify whether we must check ANI */ | |
3d536acf | 288 | if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 289 | aniflag = true; |
3d536acf | 290 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
291 | } |
292 | ||
293 | /* Skip all processing if there's nothing to do. */ | |
294 | if (longcal || shortcal || aniflag) { | |
295 | /* Call ANI routine if necessary */ | |
296 | if (aniflag) | |
22e66a4c | 297 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
298 | |
299 | /* Perform calibration if necessary */ | |
300 | if (longcal || shortcal) { | |
3d536acf | 301 | common->ani.caldone = |
43c27613 LR |
302 | ath9k_hw_calibrate(ah, |
303 | ah->curchan, | |
304 | common->rx_chainmask, | |
305 | longcal); | |
379f0440 S |
306 | |
307 | if (longcal) | |
3d536acf | 308 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
309 | ah->curchan); |
310 | ||
c46917bb LR |
311 | ath_print(common, ATH_DBG_ANI, |
312 | " calibrate chan %u/%x nf: %d\n", | |
313 | ah->curchan->channel, | |
314 | ah->curchan->channelFlags, | |
3d536acf | 315 | common->ani.noise_floor); |
ff37e337 S |
316 | } |
317 | } | |
318 | ||
1ffc1c61 JM |
319 | ath9k_ps_restore(sc); |
320 | ||
20977d3e | 321 | set_timer: |
ff37e337 S |
322 | /* |
323 | * Set timer interval based on previous results. | |
324 | * The interval must be the shortest necessary to satisfy ANI, | |
325 | * short calibration and long calibration. | |
326 | */ | |
aac9207e | 327 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 328 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 329 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
3d536acf | 330 | if (!common->ani.caldone) |
20977d3e | 331 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 332 | |
3d536acf | 333 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
334 | } |
335 | ||
3d536acf | 336 | static void ath_start_ani(struct ath_common *common) |
415f738e S |
337 | { |
338 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
339 | ||
3d536acf LR |
340 | common->ani.longcal_timer = timestamp; |
341 | common->ani.shortcal_timer = timestamp; | |
342 | common->ani.checkani_timer = timestamp; | |
415f738e | 343 | |
3d536acf | 344 | mod_timer(&common->ani.timer, |
415f738e S |
345 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); |
346 | } | |
347 | ||
ff37e337 S |
348 | /* |
349 | * Update tx/rx chainmask. For legacy association, | |
350 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
351 | * the chainmask configuration, for bt coexistence, use |
352 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 353 | */ |
0e2dedf9 | 354 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 355 | { |
af03abec | 356 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 357 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 358 | |
3d832611 | 359 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 360 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
361 | common->tx_chainmask = ah->caps.tx_chainmask; |
362 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 363 | } else { |
43c27613 LR |
364 | common->tx_chainmask = 1; |
365 | common->rx_chainmask = 1; | |
ff37e337 S |
366 | } |
367 | ||
43c27613 | 368 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 369 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
370 | common->tx_chainmask, |
371 | common->rx_chainmask); | |
ff37e337 S |
372 | } |
373 | ||
374 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
375 | { | |
376 | struct ath_node *an; | |
377 | ||
378 | an = (struct ath_node *)sta->drv_priv; | |
379 | ||
87792efc | 380 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 381 | ath_tx_node_init(sc, an); |
9e98ac65 | 382 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
383 | sta->ht_cap.ampdu_factor); |
384 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 385 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 386 | } |
ff37e337 S |
387 | } |
388 | ||
389 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
390 | { | |
391 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
392 | ||
393 | if (sc->sc_flags & SC_OP_TXAGGR) | |
394 | ath_tx_node_cleanup(sc, an); | |
395 | } | |
396 | ||
55624204 | 397 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
398 | { |
399 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 400 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 401 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 402 | |
17d7904d | 403 | u32 status = sc->intrstatus; |
b5c80475 | 404 | u32 rxmask; |
ff37e337 | 405 | |
153e080d VT |
406 | ath9k_ps_wakeup(sc); |
407 | ||
c9c99e5e FF |
408 | if ((status & ATH9K_INT_FATAL) || |
409 | !ath9k_hw_check_alive(ah)) { | |
ff37e337 | 410 | ath_reset(sc, false); |
153e080d | 411 | ath9k_ps_restore(sc); |
ff37e337 | 412 | return; |
063d8be3 | 413 | } |
ff37e337 | 414 | |
b5c80475 FF |
415 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
416 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
417 | ATH9K_INT_RXORN); | |
418 | else | |
419 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
420 | ||
421 | if (status & rxmask) { | |
063d8be3 | 422 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
423 | |
424 | /* Check for high priority Rx first */ | |
425 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
426 | (status & ATH9K_INT_RXHP)) | |
427 | ath_rx_tasklet(sc, 0, true); | |
428 | ||
429 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 430 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
431 | } |
432 | ||
e5003249 VT |
433 | if (status & ATH9K_INT_TX) { |
434 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
435 | ath_tx_edma_tasklet(sc); | |
436 | else | |
437 | ath_tx_tasklet(sc); | |
438 | } | |
063d8be3 | 439 | |
96148326 | 440 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
441 | /* |
442 | * TSF sync does not look correct; remain awake to sync with | |
443 | * the next Beacon. | |
444 | */ | |
c46917bb LR |
445 | ath_print(common, ATH_DBG_PS, |
446 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 447 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
448 | } |
449 | ||
766ec4a9 | 450 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
451 | if (status & ATH9K_INT_GENTIMER) |
452 | ath_gen_timer_isr(sc->sc_ah); | |
453 | ||
ff37e337 | 454 | /* re-enable hardware interrupt */ |
3069168c | 455 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 456 | ath9k_ps_restore(sc); |
ff37e337 S |
457 | } |
458 | ||
6baff7f9 | 459 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 460 | { |
063d8be3 S |
461 | #define SCHED_INTR ( \ |
462 | ATH9K_INT_FATAL | \ | |
463 | ATH9K_INT_RXORN | \ | |
464 | ATH9K_INT_RXEOL | \ | |
465 | ATH9K_INT_RX | \ | |
b5c80475 FF |
466 | ATH9K_INT_RXLP | \ |
467 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
468 | ATH9K_INT_TX | \ |
469 | ATH9K_INT_BMISS | \ | |
470 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
471 | ATH9K_INT_TSFOOR | \ |
472 | ATH9K_INT_GENTIMER) | |
063d8be3 | 473 | |
ff37e337 | 474 | struct ath_softc *sc = dev; |
cbe61d8a | 475 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
476 | enum ath9k_int status; |
477 | bool sched = false; | |
478 | ||
063d8be3 S |
479 | /* |
480 | * The hardware is not ready/present, don't | |
481 | * touch anything. Note this can happen early | |
482 | * on if the IRQ is shared. | |
483 | */ | |
484 | if (sc->sc_flags & SC_OP_INVALID) | |
485 | return IRQ_NONE; | |
ff37e337 | 486 | |
063d8be3 S |
487 | |
488 | /* shared irq, not for us */ | |
489 | ||
153e080d | 490 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 491 | return IRQ_NONE; |
063d8be3 S |
492 | |
493 | /* | |
494 | * Figure out the reason(s) for the interrupt. Note | |
495 | * that the hal returns a pseudo-ISR that may include | |
496 | * bits we haven't explicitly enabled so we mask the | |
497 | * value to insure we only process bits we requested. | |
498 | */ | |
499 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 500 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 501 | |
063d8be3 S |
502 | /* |
503 | * If there are no status bits set, then this interrupt was not | |
504 | * for me (should have been caught above). | |
505 | */ | |
153e080d | 506 | if (!status) |
063d8be3 | 507 | return IRQ_NONE; |
ff37e337 | 508 | |
063d8be3 S |
509 | /* Cache the status */ |
510 | sc->intrstatus = status; | |
511 | ||
512 | if (status & SCHED_INTR) | |
513 | sched = true; | |
514 | ||
515 | /* | |
516 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
517 | * chip immediately. | |
518 | */ | |
b5c80475 FF |
519 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
520 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
521 | goto chip_reset; |
522 | ||
08578b8f LR |
523 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
524 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
525 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
526 | goto chip_reset; | |
527 | } | |
528 | ||
063d8be3 S |
529 | if (status & ATH9K_INT_SWBA) |
530 | tasklet_schedule(&sc->bcon_tasklet); | |
531 | ||
532 | if (status & ATH9K_INT_TXURN) | |
533 | ath9k_hw_updatetxtriglevel(ah, true); | |
534 | ||
b5c80475 FF |
535 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
536 | if (status & ATH9K_INT_RXEOL) { | |
537 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
538 | ath9k_hw_set_interrupts(ah, ah->imask); | |
539 | } | |
540 | } | |
541 | ||
063d8be3 | 542 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 543 | /* |
063d8be3 S |
544 | * Disable interrupts until we service the MIB |
545 | * interrupt; otherwise it will continue to | |
546 | * fire. | |
ff37e337 | 547 | */ |
063d8be3 S |
548 | ath9k_hw_set_interrupts(ah, 0); |
549 | /* | |
550 | * Let the hal handle the event. We assume | |
551 | * it will clear whatever condition caused | |
552 | * the interrupt. | |
553 | */ | |
22e66a4c | 554 | ath9k_hw_procmibevent(ah); |
3069168c | 555 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 556 | } |
ff37e337 | 557 | |
153e080d VT |
558 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
559 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
560 | /* Clear RxAbort bit so that we can |
561 | * receive frames */ | |
9ecdef4b | 562 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 563 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 564 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 565 | } |
063d8be3 S |
566 | |
567 | chip_reset: | |
ff37e337 | 568 | |
817e11de S |
569 | ath_debug_stat_interrupt(sc, status); |
570 | ||
ff37e337 S |
571 | if (sched) { |
572 | /* turn off every interrupt except SWBA */ | |
3069168c | 573 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
574 | tasklet_schedule(&sc->intr_tq); |
575 | } | |
576 | ||
577 | return IRQ_HANDLED; | |
063d8be3 S |
578 | |
579 | #undef SCHED_INTR | |
ff37e337 S |
580 | } |
581 | ||
f078f209 | 582 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 583 | struct ieee80211_channel *chan, |
094d05dc | 584 | enum nl80211_channel_type channel_type) |
f078f209 LR |
585 | { |
586 | u32 chanmode = 0; | |
f078f209 LR |
587 | |
588 | switch (chan->band) { | |
589 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
590 | switch(channel_type) { |
591 | case NL80211_CHAN_NO_HT: | |
592 | case NL80211_CHAN_HT20: | |
f078f209 | 593 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
594 | break; |
595 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 596 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
597 | break; |
598 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 599 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
600 | break; |
601 | } | |
f078f209 LR |
602 | break; |
603 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
604 | switch(channel_type) { |
605 | case NL80211_CHAN_NO_HT: | |
606 | case NL80211_CHAN_HT20: | |
f078f209 | 607 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
608 | break; |
609 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 610 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
611 | break; |
612 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 613 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
614 | break; |
615 | } | |
f078f209 LR |
616 | break; |
617 | default: | |
618 | break; | |
619 | } | |
620 | ||
621 | return chanmode; | |
622 | } | |
623 | ||
8feceb67 | 624 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 625 | struct ieee80211_vif *vif, |
8feceb67 | 626 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 627 | { |
f2b2143e | 628 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 629 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 630 | |
8feceb67 | 631 | if (bss_conf->assoc) { |
c46917bb LR |
632 | ath_print(common, ATH_DBG_CONFIG, |
633 | "Bss Info ASSOC %d, bssid: %pM\n", | |
634 | bss_conf->aid, common->curbssid); | |
f078f209 | 635 | |
8feceb67 | 636 | /* New association, store aid */ |
1510718d | 637 | common->curaid = bss_conf->aid; |
f2b2143e | 638 | ath9k_hw_write_associd(ah); |
2664f201 SB |
639 | |
640 | /* | |
641 | * Request a re-configuration of Beacon related timers | |
642 | * on the receipt of the first Beacon frame (i.e., | |
643 | * after time sync with the AP). | |
644 | */ | |
1b04b930 | 645 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 646 | |
8feceb67 | 647 | /* Configure the beacon */ |
2c3db3d5 | 648 | ath_beacon_config(sc, vif); |
f078f209 | 649 | |
8feceb67 | 650 | /* Reset rssi stats */ |
22e66a4c | 651 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 652 | |
3d536acf | 653 | ath_start_ani(common); |
8feceb67 | 654 | } else { |
c46917bb | 655 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 656 | common->curaid = 0; |
f38faa31 | 657 | /* Stop ANI */ |
3d536acf | 658 | del_timer_sync(&common->ani.timer); |
f078f209 | 659 | } |
8feceb67 | 660 | } |
f078f209 | 661 | |
68a89116 | 662 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 663 | { |
cbe61d8a | 664 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 665 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 666 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 667 | int r; |
500c064d | 668 | |
3cbb5dd7 | 669 | ath9k_ps_wakeup(sc); |
93b1b37f | 670 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 671 | |
159cd468 VT |
672 | if (!ah->curchan) |
673 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
674 | ||
d2f5b3a6 | 675 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 676 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 677 | if (r) { |
c46917bb | 678 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 679 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
680 | "reset status %d\n", |
681 | channel->center_freq, r); | |
500c064d VT |
682 | } |
683 | spin_unlock_bh(&sc->sc_resetlock); | |
684 | ||
685 | ath_update_txpow(sc); | |
686 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
687 | ath_print(common, ATH_DBG_FATAL, |
688 | "Unable to restart recv logic\n"); | |
500c064d VT |
689 | return; |
690 | } | |
691 | ||
692 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 693 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
694 | |
695 | /* Re-Enable interrupts */ | |
3069168c | 696 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
697 | |
698 | /* Enable LED */ | |
08fc5c1b | 699 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 700 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 701 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 702 | |
68a89116 | 703 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 704 | ath9k_ps_restore(sc); |
500c064d VT |
705 | } |
706 | ||
68a89116 | 707 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 708 | { |
cbe61d8a | 709 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 710 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 711 | int r; |
500c064d | 712 | |
3cbb5dd7 | 713 | ath9k_ps_wakeup(sc); |
68a89116 | 714 | ieee80211_stop_queues(hw); |
500c064d VT |
715 | |
716 | /* Disable LED */ | |
08fc5c1b VN |
717 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
718 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
719 | |
720 | /* Disable interrupts */ | |
721 | ath9k_hw_set_interrupts(ah, 0); | |
722 | ||
043a0405 | 723 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
724 | ath_stoprecv(sc); /* turn off frame recv */ |
725 | ath_flushrecv(sc); /* flush recv queue */ | |
726 | ||
159cd468 | 727 | if (!ah->curchan) |
68a89116 | 728 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 729 | |
500c064d | 730 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 731 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 732 | if (r) { |
c46917bb | 733 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 734 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
735 | "reset status %d\n", |
736 | channel->center_freq, r); | |
500c064d VT |
737 | } |
738 | spin_unlock_bh(&sc->sc_resetlock); | |
739 | ||
740 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 741 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 742 | ath9k_ps_restore(sc); |
9ecdef4b | 743 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
744 | } |
745 | ||
ff37e337 S |
746 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
747 | { | |
cbe61d8a | 748 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 749 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 750 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 751 | int r; |
ff37e337 | 752 | |
2ab81d4a S |
753 | /* Stop ANI */ |
754 | del_timer_sync(&common->ani.timer); | |
755 | ||
cc9c378a S |
756 | ieee80211_stop_queues(hw); |
757 | ||
ff37e337 | 758 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 759 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
760 | ath_stoprecv(sc); |
761 | ath_flushrecv(sc); | |
762 | ||
763 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 764 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 765 | if (r) |
c46917bb LR |
766 | ath_print(common, ATH_DBG_FATAL, |
767 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
768 | spin_unlock_bh(&sc->sc_resetlock); |
769 | ||
770 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
771 | ath_print(common, ATH_DBG_FATAL, |
772 | "Unable to start recv logic\n"); | |
ff37e337 S |
773 | |
774 | /* | |
775 | * We may be doing a reset in response to a request | |
776 | * that changes the channel so update any state that | |
777 | * might change as a result. | |
778 | */ | |
ce111bad | 779 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
780 | |
781 | ath_update_txpow(sc); | |
782 | ||
783 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 784 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 785 | |
3069168c | 786 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
787 | |
788 | if (retry_tx) { | |
789 | int i; | |
790 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
791 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
792 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
793 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
794 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
795 | } |
796 | } | |
797 | } | |
798 | ||
cc9c378a S |
799 | ieee80211_wake_queues(hw); |
800 | ||
2ab81d4a S |
801 | /* Start ANI */ |
802 | ath_start_ani(common); | |
803 | ||
ae8d2858 | 804 | return r; |
ff37e337 S |
805 | } |
806 | ||
ff37e337 S |
807 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
808 | { | |
809 | int qnum; | |
810 | ||
811 | switch (queue) { | |
812 | case 0: | |
b77f483f | 813 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
814 | break; |
815 | case 1: | |
b77f483f | 816 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
817 | break; |
818 | case 2: | |
b77f483f | 819 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
820 | break; |
821 | case 3: | |
b77f483f | 822 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
823 | break; |
824 | default: | |
b77f483f | 825 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
826 | break; |
827 | } | |
828 | ||
829 | return qnum; | |
830 | } | |
831 | ||
832 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
833 | { | |
834 | int qnum; | |
835 | ||
836 | switch (queue) { | |
837 | case ATH9K_WME_AC_VO: | |
838 | qnum = 0; | |
839 | break; | |
840 | case ATH9K_WME_AC_VI: | |
841 | qnum = 1; | |
842 | break; | |
843 | case ATH9K_WME_AC_BE: | |
844 | qnum = 2; | |
845 | break; | |
846 | case ATH9K_WME_AC_BK: | |
847 | qnum = 3; | |
848 | break; | |
849 | default: | |
850 | qnum = -1; | |
851 | break; | |
852 | } | |
853 | ||
854 | return qnum; | |
855 | } | |
856 | ||
5f8e077c LR |
857 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
858 | * this redundant data */ | |
0e2dedf9 JM |
859 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
860 | struct ath9k_channel *ichan) | |
5f8e077c | 861 | { |
5f8e077c LR |
862 | struct ieee80211_channel *chan = hw->conf.channel; |
863 | struct ieee80211_conf *conf = &hw->conf; | |
864 | ||
865 | ichan->channel = chan->center_freq; | |
866 | ichan->chan = chan; | |
867 | ||
868 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
869 | ichan->chanmode = CHANNEL_G; | |
8813262e | 870 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
871 | } else { |
872 | ichan->chanmode = CHANNEL_A; | |
873 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
874 | } | |
875 | ||
25c56eec | 876 | if (conf_is_ht(conf)) |
5f8e077c LR |
877 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
878 | conf->channel_type); | |
5f8e077c LR |
879 | } |
880 | ||
ff37e337 S |
881 | /**********************/ |
882 | /* mac80211 callbacks */ | |
883 | /**********************/ | |
884 | ||
8feceb67 | 885 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 886 | { |
bce048d7 JM |
887 | struct ath_wiphy *aphy = hw->priv; |
888 | struct ath_softc *sc = aphy->sc; | |
af03abec | 889 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 890 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 891 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 892 | struct ath9k_channel *init_channel; |
82880a7c | 893 | int r; |
f078f209 | 894 | |
c46917bb LR |
895 | ath_print(common, ATH_DBG_CONFIG, |
896 | "Starting driver with initial channel: %d MHz\n", | |
897 | curchan->center_freq); | |
f078f209 | 898 | |
141b38b6 S |
899 | mutex_lock(&sc->mutex); |
900 | ||
9580a222 JM |
901 | if (ath9k_wiphy_started(sc)) { |
902 | if (sc->chan_idx == curchan->hw_value) { | |
903 | /* | |
904 | * Already on the operational channel, the new wiphy | |
905 | * can be marked active. | |
906 | */ | |
907 | aphy->state = ATH_WIPHY_ACTIVE; | |
908 | ieee80211_wake_queues(hw); | |
909 | } else { | |
910 | /* | |
911 | * Another wiphy is on another channel, start the new | |
912 | * wiphy in paused state. | |
913 | */ | |
914 | aphy->state = ATH_WIPHY_PAUSED; | |
915 | ieee80211_stop_queues(hw); | |
916 | } | |
917 | mutex_unlock(&sc->mutex); | |
918 | return 0; | |
919 | } | |
920 | aphy->state = ATH_WIPHY_ACTIVE; | |
921 | ||
8feceb67 | 922 | /* setup initial channel */ |
f078f209 | 923 | |
82880a7c | 924 | sc->chan_idx = curchan->hw_value; |
f078f209 | 925 | |
82880a7c | 926 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
927 | |
928 | /* Reset SERDES registers */ | |
af03abec | 929 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
930 | |
931 | /* | |
932 | * The basic interface to setting the hardware in a good | |
933 | * state is ``reset''. On return the hardware is known to | |
934 | * be powered up and with interrupts disabled. This must | |
935 | * be followed by initialization of the appropriate bits | |
936 | * and then setup of the interrupt mask. | |
937 | */ | |
938 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 939 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 940 | if (r) { |
c46917bb LR |
941 | ath_print(common, ATH_DBG_FATAL, |
942 | "Unable to reset hardware; reset status %d " | |
943 | "(freq %u MHz)\n", r, | |
944 | curchan->center_freq); | |
ff37e337 | 945 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 946 | goto mutex_unlock; |
ff37e337 S |
947 | } |
948 | spin_unlock_bh(&sc->sc_resetlock); | |
949 | ||
950 | /* | |
951 | * This is needed only to setup initial state | |
952 | * but it's best done after a reset. | |
953 | */ | |
954 | ath_update_txpow(sc); | |
8feceb67 | 955 | |
ff37e337 S |
956 | /* |
957 | * Setup the hardware after reset: | |
958 | * The receive engine is set going. | |
959 | * Frame transmit is handled entirely | |
960 | * in the frame output path; there's nothing to do | |
961 | * here except setup the interrupt mask. | |
962 | */ | |
963 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
964 | ath_print(common, ATH_DBG_FATAL, |
965 | "Unable to start recv logic\n"); | |
141b38b6 S |
966 | r = -EIO; |
967 | goto mutex_unlock; | |
f078f209 | 968 | } |
8feceb67 | 969 | |
ff37e337 | 970 | /* Setup our intr mask. */ |
b5c80475 FF |
971 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
972 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
973 | ATH9K_INT_GLOBAL; | |
974 | ||
975 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
976 | ah->imask |= ATH9K_INT_RXHP | |
977 | ATH9K_INT_RXLP | | |
978 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
979 | else |
980 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 981 | |
af03abec | 982 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 983 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 984 | |
af03abec | 985 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 986 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 987 | |
ce111bad | 988 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
989 | |
990 | sc->sc_flags &= ~SC_OP_INVALID; | |
991 | ||
992 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
993 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
994 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 995 | |
bce048d7 | 996 | ieee80211_wake_queues(hw); |
ff37e337 | 997 | |
42935eca | 998 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 999 | |
766ec4a9 LR |
1000 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1001 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1002 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1003 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1004 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1005 | |
5bb12791 LR |
1006 | if (common->bus_ops->bt_coex_prep) |
1007 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1008 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1009 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1010 | } |
1011 | ||
141b38b6 S |
1012 | mutex_unlock: |
1013 | mutex_unlock(&sc->mutex); | |
1014 | ||
ae8d2858 | 1015 | return r; |
f078f209 LR |
1016 | } |
1017 | ||
8feceb67 VT |
1018 | static int ath9k_tx(struct ieee80211_hw *hw, |
1019 | struct sk_buff *skb) | |
f078f209 | 1020 | { |
528f0c6b | 1021 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1022 | struct ath_wiphy *aphy = hw->priv; |
1023 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1024 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1025 | struct ath_tx_control txctl; |
1bc14880 BP |
1026 | int padpos, padsize; |
1027 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1028 | int qnum; |
528f0c6b | 1029 | |
8089cc47 | 1030 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1031 | ath_print(common, ATH_DBG_XMIT, |
1032 | "ath9k: %s: TX in unexpected wiphy state " | |
1033 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1034 | goto exit; |
1035 | } | |
1036 | ||
96148326 | 1037 | if (sc->ps_enabled) { |
dc8c4585 JM |
1038 | /* |
1039 | * mac80211 does not set PM field for normal data frames, so we | |
1040 | * need to update that based on the current PS mode. | |
1041 | */ | |
1042 | if (ieee80211_is_data(hdr->frame_control) && | |
1043 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1044 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1045 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1046 | "while in PS mode\n"); | |
dc8c4585 JM |
1047 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1048 | } | |
1049 | } | |
1050 | ||
9a23f9ca JM |
1051 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1052 | /* | |
1053 | * We are using PS-Poll and mac80211 can request TX while in | |
1054 | * power save mode. Need to wake up hardware for the TX to be | |
1055 | * completed and if needed, also for RX of buffered frames. | |
1056 | */ | |
9a23f9ca | 1057 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1058 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1059 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1060 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1061 | ath_print(common, ATH_DBG_PS, |
1062 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1063 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1064 | } else { |
c46917bb LR |
1065 | ath_print(common, ATH_DBG_PS, |
1066 | "Wake up to complete TX\n"); | |
1b04b930 | 1067 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1068 | } |
1069 | /* | |
1070 | * The actual restore operation will happen only after | |
1071 | * the sc_flags bit is cleared. We are just dropping | |
1072 | * the ps_usecount here. | |
1073 | */ | |
1074 | ath9k_ps_restore(sc); | |
1075 | } | |
1076 | ||
528f0c6b | 1077 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1078 | |
8feceb67 VT |
1079 | /* |
1080 | * As a temporary workaround, assign seq# here; this will likely need | |
1081 | * to be cleaned up to work better with Beacon transmission and virtual | |
1082 | * BSSes. | |
1083 | */ | |
1084 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1085 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1086 | sc->tx.seq_no += 0x10; |
8feceb67 | 1087 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1088 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1089 | } |
f078f209 | 1090 | |
8feceb67 | 1091 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1092 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1093 | padsize = padpos & 3; | |
1094 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1095 | if (skb_headroom(skb) < padsize) |
1096 | return -1; | |
1097 | skb_push(skb, padsize); | |
1bc14880 | 1098 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1099 | } |
1100 | ||
84642d6b FF |
1101 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1102 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1103 | |
c46917bb | 1104 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1105 | |
c52f33d0 | 1106 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1107 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1108 | goto exit; |
8feceb67 VT |
1109 | } |
1110 | ||
528f0c6b S |
1111 | return 0; |
1112 | exit: | |
1113 | dev_kfree_skb_any(skb); | |
8feceb67 | 1114 | return 0; |
f078f209 LR |
1115 | } |
1116 | ||
8feceb67 | 1117 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1118 | { |
bce048d7 JM |
1119 | struct ath_wiphy *aphy = hw->priv; |
1120 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1121 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1122 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1123 | |
4c483817 S |
1124 | mutex_lock(&sc->mutex); |
1125 | ||
9580a222 JM |
1126 | aphy->state = ATH_WIPHY_INACTIVE; |
1127 | ||
c94dbff7 LR |
1128 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
1129 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
1130 | ||
1131 | if (!sc->num_sec_wiphy) { | |
1132 | cancel_delayed_work_sync(&sc->wiphy_work); | |
1133 | cancel_work_sync(&sc->chan_work); | |
1134 | } | |
1135 | ||
9c84b797 | 1136 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1137 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1138 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1139 | return; |
1140 | } | |
8feceb67 | 1141 | |
9580a222 JM |
1142 | if (ath9k_wiphy_started(sc)) { |
1143 | mutex_unlock(&sc->mutex); | |
1144 | return; /* another wiphy still in use */ | |
1145 | } | |
1146 | ||
3867cf6a S |
1147 | /* Ensure HW is awake when we try to shut it down. */ |
1148 | ath9k_ps_wakeup(sc); | |
1149 | ||
766ec4a9 | 1150 | if (ah->btcoex_hw.enabled) { |
af03abec | 1151 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1152 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1153 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1154 | } |
1155 | ||
ff37e337 S |
1156 | /* make sure h/w will not generate any interrupt |
1157 | * before setting the invalid flag. */ | |
af03abec | 1158 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1159 | |
1160 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1161 | ath_drain_all_txq(sc, false); |
ff37e337 | 1162 | ath_stoprecv(sc); |
af03abec | 1163 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1164 | } else |
b77f483f | 1165 | sc->rx.rxlink = NULL; |
ff37e337 | 1166 | |
ff37e337 | 1167 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1168 | ath9k_hw_disable(ah); |
1169 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1170 | ath9k_ps_restore(sc); |
1171 | ||
1172 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1173 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1174 | |
1175 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1176 | |
141b38b6 S |
1177 | mutex_unlock(&sc->mutex); |
1178 | ||
c46917bb | 1179 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1180 | } |
1181 | ||
8feceb67 | 1182 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1183 | struct ieee80211_vif *vif) |
f078f209 | 1184 | { |
bce048d7 JM |
1185 | struct ath_wiphy *aphy = hw->priv; |
1186 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1187 | struct ath_hw *ah = sc->sc_ah; |
1188 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1189 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1190 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1191 | int ret = 0; |
8feceb67 | 1192 | |
141b38b6 S |
1193 | mutex_lock(&sc->mutex); |
1194 | ||
3069168c | 1195 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1196 | sc->nvifs > 0) { |
1197 | ret = -ENOBUFS; | |
1198 | goto out; | |
1199 | } | |
1200 | ||
1ed32e4f | 1201 | switch (vif->type) { |
05c914fe | 1202 | case NL80211_IFTYPE_STATION: |
d97809db | 1203 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1204 | break; |
05c914fe | 1205 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1206 | case NL80211_IFTYPE_AP: |
9cb5412b | 1207 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1208 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1209 | ret = -ENOBUFS; | |
1210 | goto out; | |
1211 | } | |
1ed32e4f | 1212 | ic_opmode = vif->type; |
f078f209 LR |
1213 | break; |
1214 | default: | |
c46917bb | 1215 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1216 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1217 | ret = -EOPNOTSUPP; |
1218 | goto out; | |
f078f209 LR |
1219 | } |
1220 | ||
c46917bb LR |
1221 | ath_print(common, ATH_DBG_CONFIG, |
1222 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1223 | |
17d7904d | 1224 | /* Set the VIF opmode */ |
5640b08e S |
1225 | avp->av_opmode = ic_opmode; |
1226 | avp->av_bslot = -1; | |
1227 | ||
2c3db3d5 | 1228 | sc->nvifs++; |
8ca21f01 | 1229 | |
3069168c | 1230 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1231 | ath9k_set_bssid_mask(hw); |
1232 | ||
2c3db3d5 JM |
1233 | if (sc->nvifs > 1) |
1234 | goto out; /* skip global settings for secondary vif */ | |
1235 | ||
b238e90e | 1236 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1237 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1238 | sc->sc_flags |= SC_OP_TSF_RESET; |
1239 | } | |
5640b08e | 1240 | |
5640b08e | 1241 | /* Set the device opmode */ |
3069168c | 1242 | ah->opmode = ic_opmode; |
5640b08e | 1243 | |
4e30ffa2 VN |
1244 | /* |
1245 | * Enable MIB interrupts when there are hardware phy counters. | |
1246 | * Note we only do this (at the moment) for station mode. | |
1247 | */ | |
1ed32e4f JB |
1248 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1249 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1250 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1251 | if (ah->config.enable_ani) |
1252 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1253 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1254 | } |
1255 | ||
3069168c | 1256 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1257 | |
1ed32e4f JB |
1258 | if (vif->type == NL80211_IFTYPE_AP || |
1259 | vif->type == NL80211_IFTYPE_ADHOC || | |
1260 | vif->type == NL80211_IFTYPE_MONITOR) | |
3d536acf | 1261 | ath_start_ani(common); |
6f255425 | 1262 | |
2c3db3d5 | 1263 | out: |
141b38b6 | 1264 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1265 | return ret; |
f078f209 LR |
1266 | } |
1267 | ||
8feceb67 | 1268 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1269 | struct ieee80211_vif *vif) |
f078f209 | 1270 | { |
bce048d7 JM |
1271 | struct ath_wiphy *aphy = hw->priv; |
1272 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1273 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1274 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1275 | int i; |
f078f209 | 1276 | |
c46917bb | 1277 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1278 | |
141b38b6 S |
1279 | mutex_lock(&sc->mutex); |
1280 | ||
6f255425 | 1281 | /* Stop ANI */ |
3d536acf | 1282 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1283 | |
8feceb67 | 1284 | /* Reclaim beacon resources */ |
9cb5412b PE |
1285 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1286 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1287 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1288 | ath9k_ps_wakeup(sc); |
b77f483f | 1289 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1290 | ath9k_ps_restore(sc); |
580f0b8a | 1291 | } |
f078f209 | 1292 | |
74401773 | 1293 | ath_beacon_return(sc, avp); |
8feceb67 | 1294 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1295 | |
2c3db3d5 | 1296 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1297 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1298 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1299 | "slot\n", __func__); | |
1300 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1301 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1302 | } |
1303 | } | |
1304 | ||
17d7904d | 1305 | sc->nvifs--; |
141b38b6 S |
1306 | |
1307 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1308 | } |
1309 | ||
3f7c5c10 SB |
1310 | void ath9k_enable_ps(struct ath_softc *sc) |
1311 | { | |
3069168c PR |
1312 | struct ath_hw *ah = sc->sc_ah; |
1313 | ||
3f7c5c10 | 1314 | sc->ps_enabled = true; |
3069168c PR |
1315 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1316 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1317 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1318 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1319 | } |
fdf76622 | 1320 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1321 | } |
3f7c5c10 SB |
1322 | } |
1323 | ||
e8975581 | 1324 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1325 | { |
bce048d7 JM |
1326 | struct ath_wiphy *aphy = hw->priv; |
1327 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1328 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1329 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1330 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1331 | bool disable_radio; |
f078f209 | 1332 | |
aa33de09 | 1333 | mutex_lock(&sc->mutex); |
141b38b6 | 1334 | |
194b7c13 LR |
1335 | /* |
1336 | * Leave this as the first check because we need to turn on the | |
1337 | * radio if it was disabled before prior to processing the rest | |
1338 | * of the changes. Likewise we must only disable the radio towards | |
1339 | * the end. | |
1340 | */ | |
64839170 | 1341 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1342 | bool enable_radio; |
1343 | bool all_wiphys_idle; | |
1344 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1345 | |
1346 | spin_lock_bh(&sc->wiphy_lock); | |
1347 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1348 | ath9k_set_wiphy_idle(aphy, idle); |
1349 | ||
11446011 | 1350 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1351 | |
1352 | /* | |
1353 | * After we unlock here its possible another wiphy | |
1354 | * can be re-renabled so to account for that we will | |
1355 | * only disable the radio toward the end of this routine | |
1356 | * if by then all wiphys are still idle. | |
1357 | */ | |
64839170 LR |
1358 | spin_unlock_bh(&sc->wiphy_lock); |
1359 | ||
194b7c13 | 1360 | if (enable_radio) { |
1dbfd9d4 | 1361 | sc->ps_idle = false; |
68a89116 | 1362 | ath_radio_enable(sc, hw); |
c46917bb LR |
1363 | ath_print(common, ATH_DBG_CONFIG, |
1364 | "not-idle: enabling radio\n"); | |
64839170 LR |
1365 | } |
1366 | } | |
1367 | ||
e7824a50 LR |
1368 | /* |
1369 | * We just prepare to enable PS. We have to wait until our AP has | |
1370 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1371 | * those ACKs and end up retransmitting the same null data frames. | |
1372 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1373 | */ | |
3cbb5dd7 VN |
1374 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1375 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1376 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1377 | /* |
1378 | * At this point we know hardware has received an ACK | |
1379 | * of a previously sent null data frame. | |
1380 | */ | |
1b04b930 S |
1381 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1382 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1383 | ath9k_enable_ps(sc); |
e7824a50 | 1384 | } |
3cbb5dd7 | 1385 | } else { |
96148326 | 1386 | sc->ps_enabled = false; |
1b04b930 S |
1387 | sc->ps_flags &= ~(PS_ENABLED | |
1388 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1389 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1390 | if (!(ah->caps.hw_caps & |
1391 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1392 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1393 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1394 | PS_WAIT_FOR_CAB | | |
1395 | PS_WAIT_FOR_PSPOLL_DATA | | |
1396 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1397 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1398 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1399 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1400 | ah->imask); |
8782b41d | 1401 | } |
3cbb5dd7 VN |
1402 | } |
1403 | } | |
1404 | } | |
1405 | ||
199afd9d S |
1406 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1407 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1408 | ath_print(common, ATH_DBG_CONFIG, | |
1409 | "HW opmode set to Monitor mode\n"); | |
1410 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1411 | } | |
1412 | } | |
1413 | ||
4797938c | 1414 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1415 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1416 | int pos = curchan->hw_value; |
ae5eb026 | 1417 | |
0e2dedf9 JM |
1418 | aphy->chan_idx = pos; |
1419 | aphy->chan_is_ht = conf_is_ht(conf); | |
1420 | ||
8089cc47 JM |
1421 | if (aphy->state == ATH_WIPHY_SCAN || |
1422 | aphy->state == ATH_WIPHY_ACTIVE) | |
1423 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1424 | else { | |
1425 | /* | |
1426 | * Do not change operational channel based on a paused | |
1427 | * wiphy changes. | |
1428 | */ | |
1429 | goto skip_chan_change; | |
1430 | } | |
0e2dedf9 | 1431 | |
c46917bb LR |
1432 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1433 | curchan->center_freq); | |
f078f209 | 1434 | |
5f8e077c | 1435 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1436 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1437 | |
ecf70441 | 1438 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1439 | |
0e2dedf9 | 1440 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1441 | ath_print(common, ATH_DBG_FATAL, |
1442 | "Unable to set channel\n"); | |
aa33de09 | 1443 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1444 | return -EINVAL; |
1445 | } | |
094d05dc | 1446 | } |
f078f209 | 1447 | |
8089cc47 | 1448 | skip_chan_change: |
c9f6a656 | 1449 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1450 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1451 | ath_update_txpow(sc); |
1452 | } | |
f078f209 | 1453 | |
194b7c13 LR |
1454 | spin_lock_bh(&sc->wiphy_lock); |
1455 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1456 | spin_unlock_bh(&sc->wiphy_lock); | |
1457 | ||
64839170 | 1458 | if (disable_radio) { |
c46917bb | 1459 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1460 | sc->ps_idle = true; |
68a89116 | 1461 | ath_radio_disable(sc, hw); |
64839170 LR |
1462 | } |
1463 | ||
aa33de09 | 1464 | mutex_unlock(&sc->mutex); |
141b38b6 | 1465 | |
f078f209 LR |
1466 | return 0; |
1467 | } | |
1468 | ||
8feceb67 VT |
1469 | #define SUPPORTED_FILTERS \ |
1470 | (FIF_PROMISC_IN_BSS | \ | |
1471 | FIF_ALLMULTI | \ | |
1472 | FIF_CONTROL | \ | |
af6a3fc7 | 1473 | FIF_PSPOLL | \ |
8feceb67 VT |
1474 | FIF_OTHER_BSS | \ |
1475 | FIF_BCN_PRBRESP_PROMISC | \ | |
1476 | FIF_FCSFAIL) | |
c83be688 | 1477 | |
8feceb67 VT |
1478 | /* FIXME: sc->sc_full_reset ? */ |
1479 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1480 | unsigned int changed_flags, | |
1481 | unsigned int *total_flags, | |
3ac64bee | 1482 | u64 multicast) |
8feceb67 | 1483 | { |
bce048d7 JM |
1484 | struct ath_wiphy *aphy = hw->priv; |
1485 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1486 | u32 rfilt; |
f078f209 | 1487 | |
8feceb67 VT |
1488 | changed_flags &= SUPPORTED_FILTERS; |
1489 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1490 | |
b77f483f | 1491 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1492 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1493 | rfilt = ath_calcrxfilter(sc); |
1494 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1495 | ath9k_ps_restore(sc); |
f078f209 | 1496 | |
c46917bb LR |
1497 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1498 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1499 | } |
f078f209 | 1500 | |
4ca77860 JB |
1501 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1502 | struct ieee80211_vif *vif, | |
1503 | struct ieee80211_sta *sta) | |
8feceb67 | 1504 | { |
bce048d7 JM |
1505 | struct ath_wiphy *aphy = hw->priv; |
1506 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1507 | |
4ca77860 JB |
1508 | ath_node_attach(sc, sta); |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1514 | struct ieee80211_vif *vif, | |
1515 | struct ieee80211_sta *sta) | |
1516 | { | |
1517 | struct ath_wiphy *aphy = hw->priv; | |
1518 | struct ath_softc *sc = aphy->sc; | |
1519 | ||
1520 | ath_node_detach(sc, sta); | |
1521 | ||
1522 | return 0; | |
f078f209 LR |
1523 | } |
1524 | ||
141b38b6 | 1525 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1526 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1527 | { |
bce048d7 JM |
1528 | struct ath_wiphy *aphy = hw->priv; |
1529 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1530 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1531 | struct ath9k_tx_queue_info qi; |
1532 | int ret = 0, qnum; | |
f078f209 | 1533 | |
8feceb67 VT |
1534 | if (queue >= WME_NUM_AC) |
1535 | return 0; | |
f078f209 | 1536 | |
141b38b6 S |
1537 | mutex_lock(&sc->mutex); |
1538 | ||
1ffb0610 S |
1539 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1540 | ||
8feceb67 VT |
1541 | qi.tqi_aifs = params->aifs; |
1542 | qi.tqi_cwmin = params->cw_min; | |
1543 | qi.tqi_cwmax = params->cw_max; | |
1544 | qi.tqi_burstTime = params->txop; | |
1545 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1546 | |
c46917bb LR |
1547 | ath_print(common, ATH_DBG_CONFIG, |
1548 | "Configure tx [queue/halq] [%d/%d], " | |
1549 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1550 | queue, qnum, params->aifs, params->cw_min, | |
1551 | params->cw_max, params->txop); | |
f078f209 | 1552 | |
8feceb67 VT |
1553 | ret = ath_txq_update(sc, qnum, &qi); |
1554 | if (ret) | |
c46917bb | 1555 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1556 | |
94db2936 VN |
1557 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1558 | if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret) | |
1559 | ath_beaconq_config(sc); | |
1560 | ||
141b38b6 S |
1561 | mutex_unlock(&sc->mutex); |
1562 | ||
8feceb67 VT |
1563 | return ret; |
1564 | } | |
f078f209 | 1565 | |
8feceb67 VT |
1566 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1567 | enum set_key_cmd cmd, | |
dc822b5d JB |
1568 | struct ieee80211_vif *vif, |
1569 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1570 | struct ieee80211_key_conf *key) |
1571 | { | |
bce048d7 JM |
1572 | struct ath_wiphy *aphy = hw->priv; |
1573 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1574 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1575 | int ret = 0; |
f078f209 | 1576 | |
b3bd89ce JM |
1577 | if (modparam_nohwcrypt) |
1578 | return -ENOSPC; | |
1579 | ||
141b38b6 | 1580 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1581 | ath9k_ps_wakeup(sc); |
c46917bb | 1582 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1583 | |
8feceb67 VT |
1584 | switch (cmd) { |
1585 | case SET_KEY: | |
1f03baad | 1586 | ret = ath9k_cmn_key_config(common, vif, sta, key); |
6ace2891 JM |
1587 | if (ret >= 0) { |
1588 | key->hw_key_idx = ret; | |
8feceb67 VT |
1589 | /* push IV and Michael MIC generation to stack */ |
1590 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1591 | if (key->alg == ALG_TKIP) | |
1592 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1593 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1594 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1595 | ret = 0; |
8feceb67 VT |
1596 | } |
1597 | break; | |
1598 | case DISABLE_KEY: | |
1f03baad | 1599 | ath9k_cmn_key_delete(common, key); |
8feceb67 VT |
1600 | break; |
1601 | default: | |
1602 | ret = -EINVAL; | |
1603 | } | |
f078f209 | 1604 | |
3cbb5dd7 | 1605 | ath9k_ps_restore(sc); |
141b38b6 S |
1606 | mutex_unlock(&sc->mutex); |
1607 | ||
8feceb67 VT |
1608 | return ret; |
1609 | } | |
f078f209 | 1610 | |
8feceb67 VT |
1611 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1612 | struct ieee80211_vif *vif, | |
1613 | struct ieee80211_bss_conf *bss_conf, | |
1614 | u32 changed) | |
1615 | { | |
bce048d7 JM |
1616 | struct ath_wiphy *aphy = hw->priv; |
1617 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1618 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1619 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1620 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1621 | int slottime; |
c6089ccc | 1622 | int error; |
f078f209 | 1623 | |
141b38b6 S |
1624 | mutex_lock(&sc->mutex); |
1625 | ||
c6089ccc S |
1626 | if (changed & BSS_CHANGED_BSSID) { |
1627 | /* Set BSSID */ | |
1628 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1629 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1630 | common->curaid = 0; |
f2b2143e | 1631 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1632 | |
c6089ccc S |
1633 | /* Set aggregation protection mode parameters */ |
1634 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1635 | |
c6089ccc S |
1636 | /* Only legacy IBSS for now */ |
1637 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1638 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1639 | |
c6089ccc S |
1640 | ath_print(common, ATH_DBG_CONFIG, |
1641 | "BSSID: %pM aid: 0x%x\n", | |
1642 | common->curbssid, common->curaid); | |
2d0ddec5 | 1643 | |
c6089ccc S |
1644 | /* need to reconfigure the beacon */ |
1645 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1646 | } | |
2d0ddec5 | 1647 | |
c6089ccc S |
1648 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1649 | if ((changed & BSS_CHANGED_BEACON) || | |
1650 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1651 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1652 | error = ath_beacon_alloc(aphy, vif); | |
1653 | if (!error) | |
1654 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1655 | } |
1656 | ||
1657 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1658 | if (bss_conf->use_short_slot) | |
1659 | slottime = 9; | |
1660 | else | |
1661 | slottime = 20; | |
1662 | if (vif->type == NL80211_IFTYPE_AP) { | |
1663 | /* | |
1664 | * Defer update, so that connected stations can adjust | |
1665 | * their settings at the same time. | |
1666 | * See beacon.c for more details | |
1667 | */ | |
1668 | sc->beacon.slottime = slottime; | |
1669 | sc->beacon.updateslot = UPDATE; | |
1670 | } else { | |
1671 | ah->slottime = slottime; | |
1672 | ath9k_hw_init_global_settings(ah); | |
1673 | } | |
2d0ddec5 JB |
1674 | } |
1675 | ||
c6089ccc S |
1676 | /* Disable transmission of beacons */ |
1677 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1678 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1679 | |
c6089ccc S |
1680 | if (changed & BSS_CHANGED_BEACON_INT) { |
1681 | sc->beacon_interval = bss_conf->beacon_int; | |
1682 | /* | |
1683 | * In case of AP mode, the HW TSF has to be reset | |
1684 | * when the beacon interval changes. | |
1685 | */ | |
1686 | if (vif->type == NL80211_IFTYPE_AP) { | |
1687 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1688 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1689 | error = ath_beacon_alloc(aphy, vif); |
1690 | if (!error) | |
1691 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1692 | } else { |
1693 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1694 | } |
1695 | } | |
1696 | ||
8feceb67 | 1697 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1698 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1699 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1700 | if (bss_conf->use_short_preamble) |
1701 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1702 | else | |
1703 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1704 | } | |
f078f209 | 1705 | |
8feceb67 | 1706 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1707 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1708 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1709 | if (bss_conf->use_cts_prot && |
1710 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1711 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1712 | else | |
1713 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1714 | } | |
f078f209 | 1715 | |
8feceb67 | 1716 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1717 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1718 | bss_conf->assoc); |
5640b08e | 1719 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1720 | } |
141b38b6 S |
1721 | |
1722 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1723 | } |
f078f209 | 1724 | |
8feceb67 VT |
1725 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1726 | { | |
1727 | u64 tsf; | |
bce048d7 JM |
1728 | struct ath_wiphy *aphy = hw->priv; |
1729 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1730 | |
141b38b6 S |
1731 | mutex_lock(&sc->mutex); |
1732 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1733 | mutex_unlock(&sc->mutex); | |
f078f209 | 1734 | |
8feceb67 VT |
1735 | return tsf; |
1736 | } | |
f078f209 | 1737 | |
3b5d665b AF |
1738 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1739 | { | |
bce048d7 JM |
1740 | struct ath_wiphy *aphy = hw->priv; |
1741 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1742 | |
141b38b6 S |
1743 | mutex_lock(&sc->mutex); |
1744 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1745 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1746 | } |
1747 | ||
8feceb67 VT |
1748 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1749 | { | |
bce048d7 JM |
1750 | struct ath_wiphy *aphy = hw->priv; |
1751 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1752 | |
141b38b6 | 1753 | mutex_lock(&sc->mutex); |
21526d57 LR |
1754 | |
1755 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1756 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1757 | ath9k_ps_restore(sc); |
1758 | ||
141b38b6 | 1759 | mutex_unlock(&sc->mutex); |
8feceb67 | 1760 | } |
f078f209 | 1761 | |
8feceb67 | 1762 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1763 | struct ieee80211_vif *vif, |
141b38b6 S |
1764 | enum ieee80211_ampdu_mlme_action action, |
1765 | struct ieee80211_sta *sta, | |
1766 | u16 tid, u16 *ssn) | |
8feceb67 | 1767 | { |
bce048d7 JM |
1768 | struct ath_wiphy *aphy = hw->priv; |
1769 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1770 | int ret = 0; |
f078f209 | 1771 | |
85ad181e JB |
1772 | local_bh_disable(); |
1773 | ||
8feceb67 VT |
1774 | switch (action) { |
1775 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1776 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1777 | ret = -ENOTSUPP; | |
8feceb67 VT |
1778 | break; |
1779 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1780 | break; |
1781 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1782 | ath9k_ps_wakeup(sc); |
f83da965 | 1783 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1784 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1785 | ath9k_ps_restore(sc); |
8feceb67 VT |
1786 | break; |
1787 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1788 | ath9k_ps_wakeup(sc); |
f83da965 | 1789 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1790 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1791 | ath9k_ps_restore(sc); |
8feceb67 | 1792 | break; |
b1720231 | 1793 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1794 | ath9k_ps_wakeup(sc); |
8469cdef | 1795 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1796 | ath9k_ps_restore(sc); |
8469cdef | 1797 | break; |
8feceb67 | 1798 | default: |
c46917bb LR |
1799 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1800 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1801 | } |
1802 | ||
85ad181e JB |
1803 | local_bh_enable(); |
1804 | ||
8feceb67 | 1805 | return ret; |
f078f209 LR |
1806 | } |
1807 | ||
62dad5b0 BP |
1808 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1809 | struct survey_info *survey) | |
1810 | { | |
1811 | struct ath_wiphy *aphy = hw->priv; | |
1812 | struct ath_softc *sc = aphy->sc; | |
1813 | struct ath_hw *ah = sc->sc_ah; | |
1814 | struct ath_common *common = ath9k_hw_common(ah); | |
1815 | struct ieee80211_conf *conf = &hw->conf; | |
1816 | ||
1817 | if (idx != 0) | |
1818 | return -ENOENT; | |
1819 | ||
1820 | survey->channel = conf->channel; | |
1821 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
1822 | survey->noise = common->ani.noise_floor; | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
0c98de65 S |
1827 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
1828 | { | |
bce048d7 JM |
1829 | struct ath_wiphy *aphy = hw->priv; |
1830 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1831 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1832 | |
3d832611 | 1833 | mutex_lock(&sc->mutex); |
8089cc47 JM |
1834 | if (ath9k_wiphy_scanning(sc)) { |
1835 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
1836 | "same time\n"); | |
1837 | /* | |
1838 | * Do not allow the concurrent scanning state for now. This | |
1839 | * could be improved with scanning control moved into ath9k. | |
1840 | */ | |
3d832611 | 1841 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
1842 | return; |
1843 | } | |
1844 | ||
1845 | aphy->state = ATH_WIPHY_SCAN; | |
1846 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 1847 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 1848 | del_timer_sync(&common->ani.timer); |
b6ce5c33 | 1849 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 1850 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1851 | } |
1852 | ||
1853 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
1854 | { | |
bce048d7 JM |
1855 | struct ath_wiphy *aphy = hw->priv; |
1856 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1857 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1858 | |
3d832611 | 1859 | mutex_lock(&sc->mutex); |
8089cc47 | 1860 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 1861 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 1862 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 1863 | ath_start_ani(common); |
b6ce5c33 | 1864 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 1865 | ath_beacon_config(sc, NULL); |
3d832611 | 1866 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1867 | } |
1868 | ||
e239d859 FF |
1869 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1870 | { | |
1871 | struct ath_wiphy *aphy = hw->priv; | |
1872 | struct ath_softc *sc = aphy->sc; | |
1873 | struct ath_hw *ah = sc->sc_ah; | |
1874 | ||
1875 | mutex_lock(&sc->mutex); | |
1876 | ah->coverage_class = coverage_class; | |
1877 | ath9k_hw_init_global_settings(ah); | |
1878 | mutex_unlock(&sc->mutex); | |
1879 | } | |
1880 | ||
6baff7f9 | 1881 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
1882 | .tx = ath9k_tx, |
1883 | .start = ath9k_start, | |
1884 | .stop = ath9k_stop, | |
1885 | .add_interface = ath9k_add_interface, | |
1886 | .remove_interface = ath9k_remove_interface, | |
1887 | .config = ath9k_config, | |
8feceb67 | 1888 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
1889 | .sta_add = ath9k_sta_add, |
1890 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 1891 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 1892 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 1893 | .set_key = ath9k_set_key, |
8feceb67 | 1894 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 1895 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 1896 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 1897 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 1898 | .get_survey = ath9k_get_survey, |
0c98de65 S |
1899 | .sw_scan_start = ath9k_sw_scan_start, |
1900 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 1901 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 1902 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 1903 | }; |