projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath5k: fix mesh beaconing
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
6b45784f 283 "reset status %d\n",
c0d7c7af
LR		 284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
c0d7c7af
LR		 290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
17d7904d 300 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 301 ath9k_ps_restore(sc);
ff37e337
S		 302 return 0;
303}
304
305/*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312static void ath_ani_calibrate(unsigned long data)
313{
20977d3e
S		 314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 320 u32 cal_interval, short_cal_interval;
ff37e337 321
20977d3e
S		 322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
0c98de65 329 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 330 goto set_timer;
ff37e337 331
1ffc1c61
JM		 332 /* Only calibrate if awake */
333 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
334 goto set_timer;
335
336 ath9k_ps_wakeup(sc);
337
ff37e337 338 /* Long calibration runs independently of short calibration. */
17d7904d 339 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 340 longcal = true;
04bd4638 341 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 342 sc->ani.longcal_timer = timestamp;
ff37e337
S		 343 }
344
17d7904d
S		 345 /* Short calibration applies only while caldone is false */
346 if (!sc->ani.caldone) {
20977d3e 347 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 348 shortcal = true;
04bd4638 349 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 350 sc->ani.shortcal_timer = timestamp;
351 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 352 }
353 } else {
17d7904d 354 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 355 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 356 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
357 if (sc->ani.caldone)
358 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 359 }
360 }
361
362 /* Verify whether we must check ANI */
20977d3e 363 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 364 aniflag = true;
17d7904d 365 sc->ani.checkani_timer = timestamp;
ff37e337
S		 366 }
367
368 /* Skip all processing if there's nothing to do. */
369 if (longcal || shortcal || aniflag) {
370 /* Call ANI routine if necessary */
371 if (aniflag)
20977d3e 372 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 373
374 /* Perform calibration if necessary */
375 if (longcal || shortcal) {
379f0440
S		 376 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
377 sc->rx_chainmask, longcal);
378
379 if (longcal)
380 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
381 ah->curchan);
382
383 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
384 ah->curchan->channel, ah->curchan->channelFlags,
385 sc->ani.noise_floor);
ff37e337
S		 386 }
387 }
388
1ffc1c61
JM		 389 ath9k_ps_restore(sc);
390
20977d3e 391set_timer:
ff37e337
S		 392 /*
393 * Set timer interval based on previous results.
394 * The interval must be the shortest necessary to satisfy ANI,
395 * short calibration and long calibration.
396 */
aac9207e 397 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 398 if (sc->sc_ah->config.enable_ani)
aac9207e 399 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 400 if (!sc->ani.caldone)
20977d3e 401 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 402
17d7904d 403 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 404}
405
415f738e
S		 406static void ath_start_ani(struct ath_softc *sc)
407{
408 unsigned long timestamp = jiffies_to_msecs(jiffies);
409
410 sc->ani.longcal_timer = timestamp;
411 sc->ani.shortcal_timer = timestamp;
412 sc->ani.checkani_timer = timestamp;
413
414 mod_timer(&sc->ani.timer,
415 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
416}
417
ff37e337
S		 418/*
419 * Update tx/rx chainmask. For legacy association,
420 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 421 * the chainmask configuration, for bt coexistence, use
422 * the chainmask configuration even in legacy mode.
ff37e337 423 */
0e2dedf9 424void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 425{
c97c92d9 426 if (is_ht ||
2660b81a
S		 427 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
428 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
429 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 430 } else {
17d7904d
S		 431 sc->tx_chainmask = 1;
432 sc->rx_chainmask = 1;
ff37e337
S		 433 }
434
04bd4638 435 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 436 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 437}
438
439static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
440{
441 struct ath_node *an;
442
443 an = (struct ath_node *)sta->drv_priv;
444
87792efc 445 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 446 ath_tx_node_init(sc, an);
87792efc
S		 447 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
448 sta->ht_cap.ampdu_factor);
449 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
450 }
ff37e337
S		 451}
452
453static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
454{
455 struct ath_node *an = (struct ath_node *)sta->drv_priv;
456
457 if (sc->sc_flags & SC_OP_TXAGGR)
458 ath_tx_node_cleanup(sc, an);
459}
460
461static void ath9k_tasklet(unsigned long data)
462{
463 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 464 u32 status = sc->intrstatus;
ff37e337 465
153e080d
VT		 466 ath9k_ps_wakeup(sc);
467
ff37e337 468 if (status & ATH9K_INT_FATAL) {
ff37e337 469 ath_reset(sc, false);
153e080d 470 ath9k_ps_restore(sc);
ff37e337 471 return;
063d8be3 472 }
ff37e337 473
063d8be3
S		 474 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
475 spin_lock_bh(&sc->rx.rxflushlock);
476 ath_rx_tasklet(sc, 0);
477 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 478 }
479
063d8be3
S		 480 if (status & ATH9K_INT_TX)
481 ath_tx_tasklet(sc);
482
54ce846e
JM		 483 if ((status & ATH9K_INT_TSFOOR) &&
484 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
485 /*
486 * TSF sync does not look correct; remain awake to sync with
487 * the next Beacon.
488 */
489 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 490 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 491 }
492
ff37e337 493 /* re-enable hardware interrupt */
17d7904d 494 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 495 ath9k_ps_restore(sc);
ff37e337
S		 496}
497
6baff7f9 498irqreturn_t ath_isr(int irq, void *dev)
ff37e337 499{
063d8be3
S		 500#define SCHED_INTR ( \
501 ATH9K_INT_FATAL | \
502 ATH9K_INT_RXORN | \
503 ATH9K_INT_RXEOL | \
504 ATH9K_INT_RX | \
505 ATH9K_INT_TX | \
506 ATH9K_INT_BMISS | \
507 ATH9K_INT_CST | \
508 ATH9K_INT_TSFOOR)
509
ff37e337 510 struct ath_softc *sc = dev;
cbe61d8a 511 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 512 enum ath9k_int status;
513 bool sched = false;
514
063d8be3
S		 515 /*
516 * The hardware is not ready/present, don't
517 * touch anything. Note this can happen early
518 * on if the IRQ is shared.
519 */
520 if (sc->sc_flags & SC_OP_INVALID)
521 return IRQ_NONE;
ff37e337 522
063d8be3
S		 523
524 /* shared irq, not for us */
525
153e080d 526 if (!ath9k_hw_intrpend(ah))
063d8be3 527 return IRQ_NONE;
063d8be3
S		 528
529 /*
530 * Figure out the reason(s) for the interrupt. Note
531 * that the hal returns a pseudo-ISR that may include
532 * bits we haven't explicitly enabled so we mask the
533 * value to insure we only process bits we requested.
534 */
535 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
536 status &= sc->imask; /* discard unasked-for bits */
ff37e337 537
063d8be3
S		 538 /*
539 * If there are no status bits set, then this interrupt was not
540 * for me (should have been caught above).
541 */
153e080d 542 if (!status)
063d8be3 543 return IRQ_NONE;
ff37e337 544
063d8be3
S		 545 /* Cache the status */
546 sc->intrstatus = status;
547
548 if (status & SCHED_INTR)
549 sched = true;
550
551 /*
552 * If a FATAL or RXORN interrupt is received, we have to reset the
553 * chip immediately.
554 */
555 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
556 goto chip_reset;
557
558 if (status & ATH9K_INT_SWBA)
559 tasklet_schedule(&sc->bcon_tasklet);
560
561 if (status & ATH9K_INT_TXURN)
562 ath9k_hw_updatetxtriglevel(ah, true);
563
564 if (status & ATH9K_INT_MIB) {
ff37e337 565 /*
063d8be3
S		 566 * Disable interrupts until we service the MIB
567 * interrupt; otherwise it will continue to
568 * fire.
ff37e337 569 */
063d8be3
S		 570 ath9k_hw_set_interrupts(ah, 0);
571 /*
572 * Let the hal handle the event. We assume
573 * it will clear whatever condition caused
574 * the interrupt.
575 */
576 ath9k_hw_procmibevent(ah, &sc->nodestats);
577 ath9k_hw_set_interrupts(ah, sc->imask);
578 }
ff37e337 579
153e080d
VT		 580 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
581 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 582 /* Clear RxAbort bit so that we can
583 * receive frames */
584 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 585 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 586 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 587 }
063d8be3
S		 588
589chip_reset:
ff37e337 590
817e11de
S		 591 ath_debug_stat_interrupt(sc, status);
592
ff37e337
S		 593 if (sched) {
594 /* turn off every interrupt except SWBA */
17d7904d 595 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 596 tasklet_schedule(&sc->intr_tq);
597 }
598
599 return IRQ_HANDLED;
063d8be3
S		 600
601#undef SCHED_INTR
ff37e337
S		 602}
603
f078f209 604static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 605 struct ieee80211_channel *chan,
094d05dc 606 enum nl80211_channel_type channel_type)
f078f209
LR		 607{
608 u32 chanmode = 0;
f078f209
LR		 609
610 switch (chan->band) {
611 case IEEE80211_BAND_2GHZ:
094d05dc
S		 612 switch(channel_type) {
613 case NL80211_CHAN_NO_HT:
614 case NL80211_CHAN_HT20:
f078f209 615 chanmode = CHANNEL_G_HT20;
094d05dc
S		 616 break;
617 case NL80211_CHAN_HT40PLUS:
f078f209 618 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 619 break;
620 case NL80211_CHAN_HT40MINUS:
f078f209 621 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 622 break;
623 }
f078f209
LR		 624 break;
625 case IEEE80211_BAND_5GHZ:
094d05dc
S		 626 switch(channel_type) {
627 case NL80211_CHAN_NO_HT:
628 case NL80211_CHAN_HT20:
f078f209 629 chanmode = CHANNEL_A_HT20;
094d05dc
S		 630 break;
631 case NL80211_CHAN_HT40PLUS:
f078f209 632 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 633 break;
634 case NL80211_CHAN_HT40MINUS:
f078f209 635 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 636 break;
637 }
f078f209
LR		 638 break;
639 default:
640 break;
641 }
642
643 return chanmode;
644}
645
6ace2891 646static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 647 struct ath9k_keyval *hk, const u8 *addr,
648 bool authenticator)
f078f209 649{
6ace2891
JM		 650 const u8 *key_rxmic;
651 const u8 *key_txmic;
f078f209 652
6ace2891
JM		 653 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
654 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 655
656 if (addr == NULL) {
d216aaa6
JM		 657 /*
658 * Group key installation - only two key cache entries are used
659 * regardless of splitmic capability since group key is only
660 * used either for TX or RX.
661 */
3f53dd64
JM		 662 if (authenticator) {
663 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
664 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
665 } else {
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
668 }
d216aaa6 669 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 670 }
17d7904d 671 if (!sc->splitmic) {
d216aaa6 672 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 673 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
674 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 675 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 676 }
d216aaa6
JM		 677
678 /* Separate key cache entries for TX and RX */
679
680 /* TX key goes at first index, RX key at +32. */
f078f209 681 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 682 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
683 /* TX MIC entry failed. No need to proceed further */
d8baa939 684 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 685 "Setting TX MIC Key Failed\n");
f078f209
LR		 686 return 0;
687 }
688
689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 /* XXX delete tx key on failure? */
d216aaa6 691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 692}
693
694static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
695{
696 int i;
697
17d7904d
S		 698 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
699 if (test_bit(i, sc->keymap) ||
700 test_bit(i + 64, sc->keymap))
6ace2891 701 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 702 if (sc->splitmic &&
703 (test_bit(i + 32, sc->keymap) ||
704 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 705 continue; /* At least one part of TKIP key allocated */
706
707 /* Found a free slot for a TKIP key */
708 return i;
709 }
710 return -1;
711}
712
713static int ath_reserve_key_cache_slot(struct ath_softc *sc)
714{
715 int i;
716
717 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 718 if (sc->splitmic) {
719 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
720 if (!test_bit(i, sc->keymap) &&
721 (test_bit(i + 32, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i;
17d7904d
S		 725 if (!test_bit(i + 32, sc->keymap) &&
726 (test_bit(i, sc->keymap) ||
727 test_bit(i + 64, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 729 return i + 32;
17d7904d
S		 730 if (!test_bit(i + 64, sc->keymap) &&
731 (test_bit(i , sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64 + 32, sc->keymap)))
ea612132 734 return i + 64;
17d7904d
S		 735 if (!test_bit(i + 64 + 32, sc->keymap) &&
736 (test_bit(i, sc->keymap) ||
737 test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap)))
ea612132 739 return i + 64 + 32;
6ace2891
JM		 740 }
741 } else {
17d7904d
S		 742 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
743 if (!test_bit(i, sc->keymap) &&
744 test_bit(i + 64, sc->keymap))
6ace2891 745 return i;
17d7904d
S		 746 if (test_bit(i, sc->keymap) &&
747 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 748 return i + 64;
749 }
750 }
751
752 /* No partially used TKIP slots, pick any available slot */
17d7904d 753 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 754 /* Do not allow slots that could be needed for TKIP group keys
755 * to be used. This limitation could be removed if we know that
756 * TKIP will not be used. */
757 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
758 continue;
17d7904d 759 if (sc->splitmic) {
be2864cf
JM		 760 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
761 continue;
762 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
763 continue;
764 }
765
17d7904d 766 if (!test_bit(i, sc->keymap))
6ace2891
JM		 767 return i; /* Found a free slot for a key */
768 }
769
770 /* No free slot found */
771 return -1;
f078f209
LR		 772}
773
774static int ath_key_config(struct ath_softc *sc,
3f53dd64 775 struct ieee80211_vif *vif,
dc822b5d 776 struct ieee80211_sta *sta,
f078f209
LR		 777 struct ieee80211_key_conf *key)
778{
f078f209
LR		 779 struct ath9k_keyval hk;
780 const u8 *mac = NULL;
781 int ret = 0;
6ace2891 782 int idx;
f078f209
LR		 783
784 memset(&hk, 0, sizeof(hk));
785
786 switch (key->alg) {
787 case ALG_WEP:
788 hk.kv_type = ATH9K_CIPHER_WEP;
789 break;
790 case ALG_TKIP:
791 hk.kv_type = ATH9K_CIPHER_TKIP;
792 break;
793 case ALG_CCMP:
794 hk.kv_type = ATH9K_CIPHER_AES_CCM;
795 break;
796 default:
ca470b29 797 return -EOPNOTSUPP;
f078f209
LR		 798 }
799
6ace2891 800 hk.kv_len = key->keylen;
f078f209
LR		 801 memcpy(hk.kv_val, key->key, key->keylen);
802
6ace2891
JM		 803 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
804 /* For now, use the default keys for broadcast keys. This may
805 * need to change with virtual interfaces. */
806 idx = key->keyidx;
807 } else if (key->keyidx) {
dc822b5d
JB		 808 if (WARN_ON(!sta))
809 return -EOPNOTSUPP;
810 mac = sta->addr;
811
6ace2891
JM		 812 if (vif->type != NL80211_IFTYPE_AP) {
813 /* Only keyidx 0 should be used with unicast key, but
814 * allow this for client mode for now. */
815 idx = key->keyidx;
816 } else
817 return -EIO;
f078f209 818 } else {
dc822b5d
JB		 819 if (WARN_ON(!sta))
820 return -EOPNOTSUPP;
821 mac = sta->addr;
822
6ace2891
JM		 823 if (key->alg == ALG_TKIP)
824 idx = ath_reserve_key_cache_slot_tkip(sc);
825 else
826 idx = ath_reserve_key_cache_slot(sc);
827 if (idx < 0)
ca470b29 828 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 829 }
830
831 if (key->alg == ALG_TKIP)
3f53dd64
JM		 832 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
833 vif->type == NL80211_IFTYPE_AP);
f078f209 834 else
d216aaa6 835 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 836
837 if (!ret)
838 return -EIO;
839
17d7904d 840 set_bit(idx, sc->keymap);
6ace2891 841 if (key->alg == ALG_TKIP) {
17d7904d
S		 842 set_bit(idx + 64, sc->keymap);
843 if (sc->splitmic) {
844 set_bit(idx + 32, sc->keymap);
845 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 846 }
847 }
848
849 return idx;
f078f209
LR		 850}
851
852static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
853{
6ace2891
JM		 854 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
855 if (key->hw_key_idx < IEEE80211_WEP_NKID)
856 return;
857
17d7904d 858 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 859 if (key->alg != ALG_TKIP)
860 return;
f078f209 861
17d7904d
S		 862 clear_bit(key->hw_key_idx + 64, sc->keymap);
863 if (sc->splitmic) {
864 clear_bit(key->hw_key_idx + 32, sc->keymap);
865 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 866 }
f078f209
LR		 867}
868
eb2599ca
S		 869static void setup_ht_cap(struct ath_softc *sc,
870 struct ieee80211_sta_ht_cap *ht_info)
f078f209 871{
60653678
S		 872#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
873#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 874
d9fe60de
JB		 875 ht_info->ht_supported = true;
876 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
877 IEEE80211_HT_CAP_SM_PS |
878 IEEE80211_HT_CAP_SGI_40 |
879 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 880
60653678
S		 881 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
882 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 883
d9fe60de
JB		 884 /* set up supported mcs set */
885 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 886
17d7904d 887 switch(sc->rx_chainmask) {
eb2599ca
S		 888 case 1:
889 ht_info->mcs.rx_mask[0] = 0xff;
890 break;
3c457265 891 case 3:
eb2599ca
S		 892 case 5:
893 case 7:
894 default:
895 ht_info->mcs.rx_mask[0] = 0xff;
896 ht_info->mcs.rx_mask[1] = 0xff;
897 break;
898 }
899
d9fe60de 900 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 901}
902
8feceb67 903static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 904 struct ieee80211_vif *vif,
8feceb67 905 struct ieee80211_bss_conf *bss_conf)
f078f209 906{
17d7904d 907 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 908
8feceb67 909 if (bss_conf->assoc) {
094d05dc 910 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 911 bss_conf->aid, sc->curbssid);
f078f209 912
8feceb67 913 /* New association, store aid */
d97809db 914 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 915 sc->curaid = bss_conf->aid;
ba52da58 916 ath9k_hw_write_associd(sc);
ccdfeab6
JM		 917
918 /*
919 * Request a re-configuration of Beacon related timers
920 * on the receipt of the first Beacon frame (i.e.,
921 * after time sync with the AP).
922 */
923 sc->sc_flags |= SC_OP_BEACON_SYNC;
8feceb67 924 }
f078f209 925
8feceb67 926 /* Configure the beacon */
2c3db3d5 927 ath_beacon_config(sc, vif);
f078f209 928
8feceb67 929 /* Reset rssi stats */
17d7904d
S		 930 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
931 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
932 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
933 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 934
415f738e 935 ath_start_ani(sc);
8feceb67 936 } else {
1ffb0610 937 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 938 sc->curaid = 0;
f078f209 939 }
8feceb67 940}
f078f209 941
8feceb67
VT		 942/********************************/
943/* LED functions */
944/********************************/
f078f209 945
f2bffa7e
VT		 946static void ath_led_blink_work(struct work_struct *work)
947{
948 struct ath_softc *sc = container_of(work, struct ath_softc,
949 ath_led_blink_work.work);
950
951 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
952 return;
85067c06
VT		 953
954 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
955 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
956 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
957 else
958 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
959 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 960
961 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
962 (sc->sc_flags & SC_OP_LED_ON) ?
963 msecs_to_jiffies(sc->led_off_duration) :
964 msecs_to_jiffies(sc->led_on_duration));
965
85067c06
VT		 966 sc->led_on_duration = sc->led_on_cnt ?
967 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
968 ATH_LED_ON_DURATION_IDLE;
969 sc->led_off_duration = sc->led_off_cnt ?
970 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
971 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 972 sc->led_on_cnt = sc->led_off_cnt = 0;
973 if (sc->sc_flags & SC_OP_LED_ON)
974 sc->sc_flags &= ~SC_OP_LED_ON;
975 else
976 sc->sc_flags |= SC_OP_LED_ON;
977}
978
8feceb67
VT		 979static void ath_led_brightness(struct led_classdev *led_cdev,
980 enum led_brightness brightness)
981{
982 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
983 struct ath_softc *sc = led->sc;
f078f209 984
8feceb67
VT		 985 switch (brightness) {
986 case LED_OFF:
987 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 988 led->led_type == ATH_LED_RADIO) {
989 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
990 (led->led_type == ATH_LED_RADIO));
8feceb67 991 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 992 if (led->led_type == ATH_LED_RADIO)
993 sc->sc_flags &= ~SC_OP_LED_ON;
994 } else {
995 sc->led_off_cnt++;
996 }
8feceb67
VT		 997 break;
998 case LED_FULL:
f2bffa7e 999 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1000 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1001 queue_delayed_work(sc->hw->workqueue,
1002 &sc->ath_led_blink_work, 0);
1003 } else if (led->led_type == ATH_LED_RADIO) {
1004 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1005 sc->sc_flags |= SC_OP_LED_ON;
1006 } else {
1007 sc->led_on_cnt++;
1008 }
8feceb67
VT		 1009 break;
1010 default:
1011 break;
f078f209 1012 }
8feceb67 1013}
f078f209 1014
8feceb67
VT		 1015static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1016 char *trigger)
1017{
1018 int ret;
f078f209 1019
8feceb67
VT		 1020 led->sc = sc;
1021 led->led_cdev.name = led->name;
1022 led->led_cdev.default_trigger = trigger;
1023 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1024
8feceb67
VT		 1025 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1026 if (ret)
1027 DPRINTF(sc, ATH_DBG_FATAL,
1028 "Failed to register led:%s", led->name);
1029 else
1030 led->registered = 1;
1031 return ret;
1032}
f078f209 1033
8feceb67
VT		 1034static void ath_unregister_led(struct ath_led *led)
1035{
1036 if (led->registered) {
1037 led_classdev_unregister(&led->led_cdev);
1038 led->registered = 0;
f078f209 1039 }
f078f209
LR		 1040}
1041
8feceb67 1042static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1043{
f2bffa7e 1044 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1045 ath_unregister_led(&sc->assoc_led);
1046 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1047 ath_unregister_led(&sc->tx_led);
1048 ath_unregister_led(&sc->rx_led);
1049 ath_unregister_led(&sc->radio_led);
1050 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1051}
f078f209 1052
8feceb67
VT		 1053static void ath_init_leds(struct ath_softc *sc)
1054{
1055 char *trigger;
1056 int ret;
f078f209 1057
8feceb67
VT		 1058 /* Configure gpio 1 for output */
1059 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1060 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1061 /* LED off, active low */
1062 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1063
f2bffa7e
VT		 1064 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1065
8feceb67
VT		 1066 trigger = ieee80211_get_radio_led_name(sc->hw);
1067 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1068 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1069 ret = ath_register_led(sc, &sc->radio_led, trigger);
1070 sc->radio_led.led_type = ATH_LED_RADIO;
1071 if (ret)
1072 goto fail;
7dcfdcd9 1073
8feceb67
VT		 1074 trigger = ieee80211_get_assoc_led_name(sc->hw);
1075 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1076 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1077 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1078 sc->assoc_led.led_type = ATH_LED_ASSOC;
1079 if (ret)
1080 goto fail;
f078f209 1081
8feceb67
VT		 1082 trigger = ieee80211_get_tx_led_name(sc->hw);
1083 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1084 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1085 ret = ath_register_led(sc, &sc->tx_led, trigger);
1086 sc->tx_led.led_type = ATH_LED_TX;
1087 if (ret)
1088 goto fail;
f078f209 1089
8feceb67
VT		 1090 trigger = ieee80211_get_rx_led_name(sc->hw);
1091 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1092 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1093 ret = ath_register_led(sc, &sc->rx_led, trigger);
1094 sc->rx_led.led_type = ATH_LED_RX;
1095 if (ret)
1096 goto fail;
f078f209 1097
8feceb67
VT		 1098 return;
1099
1100fail:
1101 ath_deinit_leds(sc);
f078f209
LR		 1102}
1103
7ec3e514 1104void ath_radio_enable(struct ath_softc *sc)
500c064d 1105{
cbe61d8a 1106 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1107 struct ieee80211_channel *channel = sc->hw->conf.channel;
1108 int r;
500c064d 1109
3cbb5dd7 1110 ath9k_ps_wakeup(sc);
d2f5b3a6 1111 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1112
d2f5b3a6 1113 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1114 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1115 if (r) {
500c064d 1116 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1117 "Unable to reset channel %u (%uMhz) ",
6b45784f 1118 "reset status %d\n",
ae8d2858 1119 channel->center_freq, r);
500c064d
VT		 1120 }
1121 spin_unlock_bh(&sc->sc_resetlock);
1122
1123 ath_update_txpow(sc);
1124 if (ath_startrecv(sc) != 0) {
1125 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1126 "Unable to restart recv logic\n");
500c064d
VT		 1127 return;
1128 }
1129
1130 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1131 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1132
1133 /* Re-Enable interrupts */
17d7904d 1134 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1135
1136 /* Enable LED */
1137 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1138 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1139 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1140
1141 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1142 ath9k_ps_restore(sc);
500c064d
VT		 1143}
1144
7ec3e514 1145void ath_radio_disable(struct ath_softc *sc)
500c064d 1146{
cbe61d8a 1147 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1148 struct ieee80211_channel *channel = sc->hw->conf.channel;
1149 int r;
500c064d 1150
3cbb5dd7 1151 ath9k_ps_wakeup(sc);
500c064d
VT		 1152 ieee80211_stop_queues(sc->hw);
1153
1154 /* Disable LED */
1155 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1156 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1157
1158 /* Disable interrupts */
1159 ath9k_hw_set_interrupts(ah, 0);
1160
043a0405 1161 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1162 ath_stoprecv(sc); /* turn off frame recv */
1163 ath_flushrecv(sc); /* flush recv queue */
1164
1165 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1166 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1167 if (r) {
500c064d 1168 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1169 "Unable to reset channel %u (%uMhz) "
6b45784f 1170 "reset status %d\n",
ae8d2858 1171 channel->center_freq, r);
500c064d
VT		 1172 }
1173 spin_unlock_bh(&sc->sc_resetlock);
1174
1175 ath9k_hw_phy_disable(ah);
d2f5b3a6 1176 ath9k_hw_configpcipowersave(ah, 1);
500c064d 1177 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1178 ath9k_ps_restore(sc);
500c064d
VT		 1179}
1180
5077fd35
GJ		 1181#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1182
1183/*******************/
1184/* Rfkill */
1185/*******************/
1186
500c064d
VT		 1187static bool ath_is_rfkill_set(struct ath_softc *sc)
1188{
cbe61d8a 1189 struct ath_hw *ah = sc->sc_ah;
500c064d 1190
2660b81a
S		 1191 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1192 ah->rfkill_polarity;
500c064d
VT		 1193}
1194
19d337df
JB		 1195/* s/w rfkill handlers */
1196static int ath_rfkill_set_block(void *data, bool blocked)
500c064d 1197{
19d337df 1198 struct ath_softc *sc = data;
500c064d 1199
19d337df
JB		 1200 if (blocked)
1201 ath_radio_disable(sc);
1202 else
1203 ath_radio_enable(sc);
500c064d 1204
19d337df 1205 return 0;
500c064d
VT		 1206}
1207
19d337df 1208static void ath_rfkill_poll_state(struct rfkill *rfkill, void *data)
500c064d
VT		 1209{
1210 struct ath_softc *sc = data;
19d337df 1211 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1212
19d337df
JB		 1213 if (rfkill_set_hw_state(rfkill, blocked))
1214 ath_radio_disable(sc);
1215 else
1216 ath_radio_enable(sc);
500c064d
VT		 1217}
1218
1219/* Init s/w rfkill */
1220static int ath_init_sw_rfkill(struct ath_softc *sc)
1221{
19d337df
JB		 1222 sc->rf_kill.ops.set_block = ath_rfkill_set_block;
1223 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1224 sc->rf_kill.ops.poll = ath_rfkill_poll_state;
1225
1226 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1227 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1228
1229 sc->rf_kill.rfkill = rfkill_alloc(sc->rf_kill.rfkill_name,
1230 wiphy_dev(sc->hw->wiphy),
1231 RFKILL_TYPE_WLAN,
1232 &sc->rf_kill.ops, sc);
500c064d
VT		 1233 if (!sc->rf_kill.rfkill) {
1234 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1235 return -ENOMEM;
1236 }
1237
500c064d
VT		 1238 return 0;
1239}
1240
1241/* Deinitialize rfkill */
1242static void ath_deinit_rfkill(struct ath_softc *sc)
1243{
500c064d
VT		 1244 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1245 rfkill_unregister(sc->rf_kill.rfkill);
19d337df 1246 rfkill_destroy(sc->rf_kill.rfkill);
500c064d 1247 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
500c064d
VT		 1248 }
1249}
9c84b797
S		 1250
1251static int ath_start_rfkill_poll(struct ath_softc *sc)
1252{
9c84b797
S		 1253 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1254 if (rfkill_register(sc->rf_kill.rfkill)) {
1255 DPRINTF(sc, ATH_DBG_FATAL,
1256 "Unable to register rfkill\n");
19d337df 1257 rfkill_destroy(sc->rf_kill.rfkill);
9c84b797
S		 1258
1259 /* Deinitialize the device */
39c3c2f2 1260 ath_cleanup(sc);
9c84b797
S		 1261 return -EIO;
1262 } else {
1263 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1264 }
1265 }
1266
1267 return 0;
1268}
500c064d
VT		 1269#endif /* CONFIG_RFKILL */
1270
6baff7f9 1271void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1272{
1273 ath_detach(sc);
1274 free_irq(sc->irq, sc);
1275 ath_bus_cleanup(sc);
c52f33d0 1276 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1277 ieee80211_free_hw(sc->hw);
1278}
1279
6baff7f9 1280void ath_detach(struct ath_softc *sc)
f078f209 1281{
8feceb67 1282 struct ieee80211_hw *hw = sc->hw;
9c84b797 1283 int i = 0;
f078f209 1284
3cbb5dd7
VN		 1285 ath9k_ps_wakeup(sc);
1286
04bd4638 1287 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1288
e97275cb 1289#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1290 ath_deinit_rfkill(sc);
1291#endif
3fcdfb4b 1292 ath_deinit_leds(sc);
0e2dedf9 1293 cancel_work_sync(&sc->chan_work);
f98c3bd2 1294 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1295
c52f33d0
JM		 1296 for (i = 0; i < sc->num_sec_wiphy; i++) {
1297 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1298 if (aphy == NULL)
1299 continue;
1300 sc->sec_wiphy[i] = NULL;
1301 ieee80211_unregister_hw(aphy->hw);
1302 ieee80211_free_hw(aphy->hw);
1303 }
3fcdfb4b 1304 ieee80211_unregister_hw(hw);
8feceb67
VT		 1305 ath_rx_cleanup(sc);
1306 ath_tx_cleanup(sc);
f078f209 1307
9c84b797
S		 1308 tasklet_kill(&sc->intr_tq);
1309 tasklet_kill(&sc->bcon_tasklet);
f078f209 1310
9c84b797
S		 1311 if (!(sc->sc_flags & SC_OP_INVALID))
1312 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1313
9c84b797
S		 1314 /* cleanup tx queues */
1315 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1316 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1317 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1318
1319 ath9k_hw_detach(sc->sc_ah);
826d2680 1320 ath9k_exit_debug(sc);
3cbb5dd7 1321 ath9k_ps_restore(sc);
f078f209
LR		 1322}
1323
e3bb249b
BC		 1324static int ath9k_reg_notifier(struct wiphy *wiphy,
1325 struct regulatory_request *request)
1326{
1327 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1328 struct ath_wiphy *aphy = hw->priv;
1329 struct ath_softc *sc = aphy->sc;
1330 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1331
1332 return ath_reg_notifier_apply(wiphy, request, reg);
1333}
1334
ff37e337
S		 1335static int ath_init(u16 devid, struct ath_softc *sc)
1336{
cbe61d8a 1337 struct ath_hw *ah = NULL;
ff37e337
S		 1338 int status;
1339 int error = 0, i;
1340 int csz = 0;
1341
1342 /* XXX: hardware will not be ready until ath_open() being called */
1343 sc->sc_flags |= SC_OP_INVALID;
88b126af 1344
826d2680
S		 1345 if (ath9k_init_debug(sc) < 0)
1346 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1347
c52f33d0 1348 spin_lock_init(&sc->wiphy_lock);
ff37e337 1349 spin_lock_init(&sc->sc_resetlock);
6158425b 1350 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1351 mutex_init(&sc->mutex);
ff37e337 1352 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1353 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1354 (unsigned long)sc);
1355
1356 /*
1357 * Cache line size is used to size and align various
1358 * structures used to communicate with the hardware.
1359 */
88d15707 1360 ath_read_cachesize(sc, &csz);
ff37e337 1361 /* XXX assert csz is non-zero */
17d7904d 1362 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1363
cbe61d8a 1364 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1365 if (ah == NULL) {
1366 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1367 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1368 error = -ENXIO;
1369 goto bad;
1370 }
1371 sc->sc_ah = ah;
1372
1373 /* Get the hardware key cache size. */
2660b81a 1374 sc->keymax = ah->caps.keycache_size;
17d7904d 1375 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1376 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1377 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1378 ATH_KEYMAX, sc->keymax);
1379 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1380 }
1381
1382 /*
1383 * Reset the key cache since some parts do not
1384 * reset the contents on initial power up.
1385 */
17d7904d 1386 for (i = 0; i < sc->keymax; i++)
ff37e337 1387 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1388
85efc86e 1389 if (error)
ff37e337
S		 1390 goto bad;
1391
1392 /* default to MONITOR mode */
2660b81a 1393 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1394
ff37e337
S		 1395 /* Setup rate tables */
1396
1397 ath_rate_attach(sc);
1398 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1399 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1400
1401 /*
1402 * Allocate hardware transmit queues: one queue for
1403 * beacon frames and one data queue for each QoS
1404 * priority. Note that the hal handles reseting
1405 * these queues at the needed time.
1406 */
b77f483f
S		 1407 sc->beacon.beaconq = ath_beaconq_setup(ah);
1408 if (sc->beacon.beaconq == -1) {
ff37e337 1409 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1410 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1411 error = -EIO;
1412 goto bad2;
1413 }
b77f483f
S		 1414 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1415 if (sc->beacon.cabq == NULL) {
ff37e337 1416 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1417 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1418 error = -EIO;
1419 goto bad2;
1420 }
1421
17d7904d 1422 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1423 ath_cabq_update(sc);
1424
b77f483f
S		 1425 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1426 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1427
1428 /* Setup data queues */
1429 /* NB: ensure BK queue is the lowest priority h/w queue */
1430 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1431 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1432 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1433 error = -EIO;
1434 goto bad2;
1435 }
1436
1437 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1439 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1440 error = -EIO;
1441 goto bad2;
1442 }
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1445 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1446 error = -EIO;
1447 goto bad2;
1448 }
1449 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1450 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1451 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1452 error = -EIO;
1453 goto bad2;
1454 }
1455
1456 /* Initializes the noise floor to a reasonable default value.
1457 * Later on this will be updated during ANI processing. */
1458
17d7904d
S		 1459 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1460 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1461
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)) {
1464 /*
1465 * Whether we should enable h/w TKIP MIC.
1466 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1467 * report WMM capable, so it's always safe to turn on
1468 * TKIP MIC in this case.
1469 */
1470 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1471 0, 1, NULL);
1472 }
1473
1474 /*
1475 * Check whether the separate key cache entries
1476 * are required to handle both tx+rx MIC keys.
1477 * With split mic keys the number of stations is limited
1478 * to 27 otherwise 59.
1479 */
1480 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1481 ATH9K_CIPHER_TKIP, NULL)
1482 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1483 ATH9K_CIPHER_MIC, NULL)
1484 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1485 0, NULL))
17d7904d 1486 sc->splitmic = 1;
ff37e337
S		 1487
1488 /* turn on mcast key search if possible */
1489 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1490 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1491 1, NULL);
1492
17d7904d 1493 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1494
1495 /* 11n Capabilities */
2660b81a 1496 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1497 sc->sc_flags |= SC_OP_TXAGGR;
1498 sc->sc_flags |= SC_OP_RXAGGR;
1499 }
1500
2660b81a
S		 1501 sc->tx_chainmask = ah->caps.tx_chainmask;
1502 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1503
1504 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1505 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1506
8ca21f01 1507 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1508 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1509
b77f483f 1510 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1511
1512 /* initialize beacon slots */
c52f33d0 1513 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1514 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1515 sc->beacon.bslot_aphy[i] = NULL;
1516 }
ff37e337 1517
ff37e337
S		 1518 /* setup channels and rates */
1519
5f8e077c 1520 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1521 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1522 sc->rates[IEEE80211_BAND_2GHZ];
1523 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1524 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1525 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1526
2660b81a 1527 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1528 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1529 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1530 sc->rates[IEEE80211_BAND_5GHZ];
1531 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1532 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1533 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1534 }
1535
2660b81a 1536 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1537 ath9k_hw_btcoex_enable(sc->sc_ah);
1538
ff37e337
S		 1539 return 0;
1540bad2:
1541 /* cleanup tx queues */
1542 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1543 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1544 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1545bad:
1546 if (ah)
1547 ath9k_hw_detach(ah);
40b130a9 1548 ath9k_exit_debug(sc);
ff37e337
S		 1549
1550 return error;
1551}
1552
c52f33d0 1553void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1554{
9c84b797
S		 1555 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1556 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1557 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1558 IEEE80211_HW_AMPDU_AGGREGATION |
1559 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1560 IEEE80211_HW_PS_NULLFUNC_STACK |
1561 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1562
b3bd89ce 1563 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1564 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1565
9c84b797
S		 1566 hw->wiphy->interface_modes =
1567 BIT(NL80211_IFTYPE_AP) |
1568 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1569 BIT(NL80211_IFTYPE_ADHOC) |
1570 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1571
8feceb67 1572 hw->queues = 4;
e63835b0 1573 hw->max_rates = 4;
171387ef 1574 hw->channel_change_time = 5000;
465ca84d 1575 hw->max_listen_interval = 10;
e63835b0 1576 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1577 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1578 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1579
8feceb67 1580 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1581
c52f33d0
JM		 1582 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1583 &sc->sbands[IEEE80211_BAND_2GHZ];
1584 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1585 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1586 &sc->sbands[IEEE80211_BAND_5GHZ];
1587}
1588
1589int ath_attach(u16 devid, struct ath_softc *sc)
1590{
1591 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1592 int error = 0, i;
3a702e49 1593 struct ath_regulatory *reg;
c52f33d0
JM		 1594
1595 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1596
1597 error = ath_init(devid, sc);
1598 if (error != 0)
1599 return error;
1600
1601 /* get mac address from hardware and set in mac80211 */
1602
1603 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1604
1605 ath_set_hw_capab(sc, hw);
1606
c26c2e57
LR		 1607 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1608 ath9k_reg_notifier);
1609 if (error)
1610 return error;
1611
1612 reg = &sc->sc_ah->regulatory;
1613
2660b81a 1614 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1615 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1616 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1617 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1618 }
1619
db93e7b5
SB		 1620 /* initialize tx/rx engine */
1621 error = ath_tx_init(sc, ATH_TXBUF);
1622 if (error != 0)
40b130a9 1623 goto error_attach;
8feceb67 1624
db93e7b5
SB		 1625 error = ath_rx_init(sc, ATH_RXBUF);
1626 if (error != 0)
40b130a9 1627 goto error_attach;
8feceb67 1628
e97275cb 1629#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1630 /* Initialize s/w rfkill */
40b130a9
VT		 1631 error = ath_init_sw_rfkill(sc);
1632 if (error)
1633 goto error_attach;
500c064d
VT		 1634#endif
1635
0e2dedf9 1636 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1637 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1638 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1639
db93e7b5 1640 error = ieee80211_register_hw(hw);
8feceb67 1641
3a702e49 1642 if (!ath_is_world_regd(reg)) {
c02cf373 1643 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1644 if (error)
1645 goto error_attach;
1646 }
5f8e077c 1647
db93e7b5
SB		 1648 /* Initialize LED control */
1649 ath_init_leds(sc);
8feceb67 1650
5f8e077c 1651
8feceb67 1652 return 0;
40b130a9
VT		 1653
1654error_attach:
1655 /* cleanup tx queues */
1656 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1657 if (ATH_TXQ_SETUP(sc, i))
1658 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1659
1660 ath9k_hw_detach(sc->sc_ah);
1661 ath9k_exit_debug(sc);
1662
8feceb67 1663 return error;
f078f209
LR		 1664}
1665
ff37e337
S		 1666int ath_reset(struct ath_softc *sc, bool retry_tx)
1667{
cbe61d8a 1668 struct ath_hw *ah = sc->sc_ah;
030bb495 1669 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1670 int r;
ff37e337
S		 1671
1672 ath9k_hw_set_interrupts(ah, 0);
043a0405 1673 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1674 ath_stoprecv(sc);
1675 ath_flushrecv(sc);
1676
1677 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1678 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1679 if (r)
ff37e337 1680 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1681 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1682 spin_unlock_bh(&sc->sc_resetlock);
1683
1684 if (ath_startrecv(sc) != 0)
04bd4638 1685 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1686
1687 /*
1688 * We may be doing a reset in response to a request
1689 * that changes the channel so update any state that
1690 * might change as a result.
1691 */
ce111bad 1692 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1693
1694 ath_update_txpow(sc);
1695
1696 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1697 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1698
17d7904d 1699 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1700
1701 if (retry_tx) {
1702 int i;
1703 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1704 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1705 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1706 ath_txq_schedule(sc, &sc->tx.txq[i]);
1707 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1708 }
1709 }
1710 }
1711
ae8d2858 1712 return r;
ff37e337
S		 1713}
1714
1715/*
1716 * This function will allocate both the DMA descriptor structure, and the
1717 * buffers it contains. These are used to contain the descriptors used
1718 * by the system.
1719*/
1720int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1721 struct list_head *head, const char *name,
1722 int nbuf, int ndesc)
1723{
1724#define DS2PHYS(_dd, _ds) \
1725 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1726#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1727#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1728
1729 struct ath_desc *ds;
1730 struct ath_buf *bf;
1731 int i, bsize, error;
1732
04bd4638
S		 1733 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1734 name, nbuf, ndesc);
ff37e337 1735
b03a9db9 1736 INIT_LIST_HEAD(head);
ff37e337
S		 1737 /* ath_desc must be a multiple of DWORDs */
1738 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1739 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1740 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1741 error = -ENOMEM;
1742 goto fail;
1743 }
1744
ff37e337
S		 1745 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1746
1747 /*
1748 * Need additional DMA memory because we can't use
1749 * descriptors that cross the 4K page boundary. Assume
1750 * one skipped descriptor per 4K page.
1751 */
2660b81a 1752 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1753 u32 ndesc_skipped =
1754 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1755 u32 dma_len;
1756
1757 while (ndesc_skipped) {
1758 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1759 dd->dd_desc_len += dma_len;
1760
1761 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1762 };
1763 }
1764
1765 /* allocate descriptors */
7da3c55c 1766 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1767 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1768 if (dd->dd_desc == NULL) {
1769 error = -ENOMEM;
1770 goto fail;
1771 }
1772 ds = dd->dd_desc;
04bd4638 1773 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1774 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1775 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1776
1777 /* allocate buffers */
1778 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1779 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1780 if (bf == NULL) {
1781 error = -ENOMEM;
1782 goto fail2;
1783 }
ff37e337
S		 1784 dd->dd_bufptr = bf;
1785
ff37e337
S		 1786 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1787 bf->bf_desc = ds;
1788 bf->bf_daddr = DS2PHYS(dd, ds);
1789
2660b81a 1790 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1791 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1792 /*
1793 * Skip descriptor addresses which can cause 4KB
1794 * boundary crossing (addr + length) with a 32 dword
1795 * descriptor fetch.
1796 */
1797 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1798 ASSERT((caddr_t) bf->bf_desc <
1799 ((caddr_t) dd->dd_desc +
1800 dd->dd_desc_len));
1801
1802 ds += ndesc;
1803 bf->bf_desc = ds;
1804 bf->bf_daddr = DS2PHYS(dd, ds);
1805 }
1806 }
1807 list_add_tail(&bf->list, head);
1808 }
1809 return 0;
1810fail2:
7da3c55c
GJ		 1811 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1812 dd->dd_desc_paddr);
ff37e337
S		 1813fail:
1814 memset(dd, 0, sizeof(*dd));
1815 return error;
1816#undef ATH_DESC_4KB_BOUND_CHECK
1817#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1818#undef DS2PHYS
1819}
1820
1821void ath_descdma_cleanup(struct ath_softc *sc,
1822 struct ath_descdma *dd,
1823 struct list_head *head)
1824{
7da3c55c
GJ		 1825 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1826 dd->dd_desc_paddr);
ff37e337
S		 1827
1828 INIT_LIST_HEAD(head);
1829 kfree(dd->dd_bufptr);
1830 memset(dd, 0, sizeof(*dd));
1831}
1832
1833int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1834{
1835 int qnum;
1836
1837 switch (queue) {
1838 case 0:
b77f483f 1839 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1840 break;
1841 case 1:
b77f483f 1842 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1843 break;
1844 case 2:
b77f483f 1845 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1846 break;
1847 case 3:
b77f483f 1848 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1849 break;
1850 default:
b77f483f 1851 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1852 break;
1853 }
1854
1855 return qnum;
1856}
1857
1858int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1859{
1860 int qnum;
1861
1862 switch (queue) {
1863 case ATH9K_WME_AC_VO:
1864 qnum = 0;
1865 break;
1866 case ATH9K_WME_AC_VI:
1867 qnum = 1;
1868 break;
1869 case ATH9K_WME_AC_BE:
1870 qnum = 2;
1871 break;
1872 case ATH9K_WME_AC_BK:
1873 qnum = 3;
1874 break;
1875 default:
1876 qnum = -1;
1877 break;
1878 }
1879
1880 return qnum;
1881}
1882
5f8e077c
LR		 1883/* XXX: Remove me once we don't depend on ath9k_channel for all
1884 * this redundant data */
0e2dedf9
JM		 1885void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1886 struct ath9k_channel *ichan)
5f8e077c 1887{
5f8e077c
LR		 1888 struct ieee80211_channel *chan = hw->conf.channel;
1889 struct ieee80211_conf *conf = &hw->conf;
1890
1891 ichan->channel = chan->center_freq;
1892 ichan->chan = chan;
1893
1894 if (chan->band == IEEE80211_BAND_2GHZ) {
1895 ichan->chanmode = CHANNEL_G;
1896 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1897 } else {
1898 ichan->chanmode = CHANNEL_A;
1899 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1900 }
1901
1902 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1903
1904 if (conf_is_ht(conf)) {
1905 if (conf_is_ht40(conf))
1906 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1907
1908 ichan->chanmode = ath_get_extchanmode(sc, chan,
1909 conf->channel_type);
1910 }
1911}
1912
ff37e337
S		 1913/**********************/
1914/* mac80211 callbacks */
1915/**********************/
1916
8feceb67 1917static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1918{
bce048d7
JM		 1919 struct ath_wiphy *aphy = hw->priv;
1920 struct ath_softc *sc = aphy->sc;
8feceb67 1921 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1922 struct ath9k_channel *init_channel;
ae8d2858 1923 int r, pos;
f078f209 1924
04bd4638
S		 1925 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1926 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1927
141b38b6
S		 1928 mutex_lock(&sc->mutex);
1929
9580a222
JM		 1930 if (ath9k_wiphy_started(sc)) {
1931 if (sc->chan_idx == curchan->hw_value) {
1932 /*
1933 * Already on the operational channel, the new wiphy
1934 * can be marked active.
1935 */
1936 aphy->state = ATH_WIPHY_ACTIVE;
1937 ieee80211_wake_queues(hw);
1938 } else {
1939 /*
1940 * Another wiphy is on another channel, start the new
1941 * wiphy in paused state.
1942 */
1943 aphy->state = ATH_WIPHY_PAUSED;
1944 ieee80211_stop_queues(hw);
1945 }
1946 mutex_unlock(&sc->mutex);
1947 return 0;
1948 }
1949 aphy->state = ATH_WIPHY_ACTIVE;
1950
8feceb67 1951 /* setup initial channel */
f078f209 1952
5f8e077c 1953 pos = curchan->hw_value;
f078f209 1954
0e2dedf9 1955 sc->chan_idx = pos;
2660b81a 1956 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 1957 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 1958
1959 /* Reset SERDES registers */
1960 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1961
1962 /*
1963 * The basic interface to setting the hardware in a good
1964 * state is ``reset''. On return the hardware is known to
1965 * be powered up and with interrupts disabled. This must
1966 * be followed by initialization of the appropriate bits
1967 * and then setup of the interrupt mask.
1968 */
1969 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1970 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1971 if (r) {
ff37e337 1972 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1973 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1974 "(freq %u MHz)\n", r,
1975 curchan->center_freq);
ff37e337 1976 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1977 goto mutex_unlock;
ff37e337
S		 1978 }
1979 spin_unlock_bh(&sc->sc_resetlock);
1980
1981 /*
1982 * This is needed only to setup initial state
1983 * but it's best done after a reset.
1984 */
1985 ath_update_txpow(sc);
8feceb67 1986
ff37e337
S		 1987 /*
1988 * Setup the hardware after reset:
1989 * The receive engine is set going.
1990 * Frame transmit is handled entirely
1991 * in the frame output path; there's nothing to do
1992 * here except setup the interrupt mask.
1993 */
1994 if (ath_startrecv(sc) != 0) {
1ffb0610 1995 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1996 r = -EIO;
1997 goto mutex_unlock;
f078f209 1998 }
8feceb67 1999
ff37e337 2000 /* Setup our intr mask. */
17d7904d 2001 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2002 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2003 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2004
2660b81a 2005 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2006 sc->imask |= ATH9K_INT_GTT;
ff37e337 2007
2660b81a 2008 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2009 sc->imask |= ATH9K_INT_CST;
ff37e337 2010
ce111bad 2011 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2012
2013 sc->sc_flags &= ~SC_OP_INVALID;
2014
2015 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2016 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2017 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2018
bce048d7 2019 ieee80211_wake_queues(hw);
ff37e337 2020
e97275cb 2021#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2022 r = ath_start_rfkill_poll(sc);
500c064d 2023#endif
141b38b6
S		 2024
2025mutex_unlock:
2026 mutex_unlock(&sc->mutex);
2027
ae8d2858 2028 return r;
f078f209
LR		 2029}
2030
8feceb67
VT		 2031static int ath9k_tx(struct ieee80211_hw *hw,
2032 struct sk_buff *skb)
f078f209 2033{
528f0c6b 2034 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2035 struct ath_wiphy *aphy = hw->priv;
2036 struct ath_softc *sc = aphy->sc;
528f0c6b 2037 struct ath_tx_control txctl;
8feceb67 2038 int hdrlen, padsize;
528f0c6b 2039
8089cc47 2040 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2041 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2042 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2043 goto exit;
2044 }
2045
dc8c4585
JM		 2046 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2047 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2048 /*
2049 * mac80211 does not set PM field for normal data frames, so we
2050 * need to update that based on the current PS mode.
2051 */
2052 if (ieee80211_is_data(hdr->frame_control) &&
2053 !ieee80211_is_nullfunc(hdr->frame_control) &&
2054 !ieee80211_has_pm(hdr->frame_control)) {
2055 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2056 "while in PS mode\n");
2057 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2058 }
2059 }
2060
9a23f9ca
JM		 2061 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2062 /*
2063 * We are using PS-Poll and mac80211 can request TX while in
2064 * power save mode. Need to wake up hardware for the TX to be
2065 * completed and if needed, also for RX of buffered frames.
2066 */
2067 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2068 ath9k_ps_wakeup(sc);
2069 ath9k_hw_setrxabort(sc->sc_ah, 0);
2070 if (ieee80211_is_pspoll(hdr->frame_control)) {
2071 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2072 "buffered frame\n");
2073 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2074 } else {
2075 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2076 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2077 }
2078 /*
2079 * The actual restore operation will happen only after
2080 * the sc_flags bit is cleared. We are just dropping
2081 * the ps_usecount here.
2082 */
2083 ath9k_ps_restore(sc);
2084 }
2085
528f0c6b 2086 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2087
8feceb67
VT		 2088 /*
2089 * As a temporary workaround, assign seq# here; this will likely need
2090 * to be cleaned up to work better with Beacon transmission and virtual
2091 * BSSes.
2092 */
2093 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2094 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2095 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2096 sc->tx.seq_no += 0x10;
8feceb67 2097 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2098 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2099 }
f078f209 2100
8feceb67
VT		 2101 /* Add the padding after the header if this is not already done */
2102 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2103 if (hdrlen & 3) {
2104 padsize = hdrlen % 4;
2105 if (skb_headroom(skb) < padsize)
2106 return -1;
2107 skb_push(skb, padsize);
2108 memmove(skb->data, skb->data + padsize, hdrlen);
2109 }
2110
528f0c6b
S		 2111 /* Check if a tx queue is available */
2112
2113 txctl.txq = ath_test_get_txq(sc, skb);
2114 if (!txctl.txq)
2115 goto exit;
2116
04bd4638 2117 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2118
c52f33d0 2119 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2120 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2121 goto exit;
8feceb67
VT		 2122 }
2123
528f0c6b
S		 2124 return 0;
2125exit:
2126 dev_kfree_skb_any(skb);
8feceb67 2127 return 0;
f078f209
LR		 2128}
2129
8feceb67 2130static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2131{
bce048d7
JM		 2132 struct ath_wiphy *aphy = hw->priv;
2133 struct ath_softc *sc = aphy->sc;
f078f209 2134
9580a222
JM		 2135 aphy->state = ATH_WIPHY_INACTIVE;
2136
9c84b797 2137 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2138 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2139 return;
2140 }
8feceb67 2141
141b38b6 2142 mutex_lock(&sc->mutex);
ff37e337 2143
bce048d7 2144 ieee80211_stop_queues(hw);
ff37e337 2145
9580a222
JM		 2146 if (ath9k_wiphy_started(sc)) {
2147 mutex_unlock(&sc->mutex);
2148 return; /* another wiphy still in use */
2149 }
2150
ff37e337
S		 2151 /* make sure h/w will not generate any interrupt
2152 * before setting the invalid flag. */
2153 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2154
2155 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2156 ath_drain_all_txq(sc, false);
ff37e337
S		 2157 ath_stoprecv(sc);
2158 ath9k_hw_phy_disable(sc->sc_ah);
2159 } else
b77f483f 2160 sc->rx.rxlink = NULL;
ff37e337 2161
19d337df
JB		 2162 rfkill_pause_polling(sc->rf_kill.rfkill);
2163
ff37e337
S		 2164 /* disable HAL and put h/w to sleep */
2165 ath9k_hw_disable(sc->sc_ah);
2166 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2167
2168 sc->sc_flags |= SC_OP_INVALID;
500c064d 2169
141b38b6
S		 2170 mutex_unlock(&sc->mutex);
2171
04bd4638 2172 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2173}
2174
8feceb67
VT		 2175static int ath9k_add_interface(struct ieee80211_hw *hw,
2176 struct ieee80211_if_init_conf *conf)
f078f209 2177{
bce048d7
JM		 2178 struct ath_wiphy *aphy = hw->priv;
2179 struct ath_softc *sc = aphy->sc;
17d7904d 2180 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2181 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2182 int ret = 0;
8feceb67 2183
141b38b6
S		 2184 mutex_lock(&sc->mutex);
2185
8ca21f01
JM		 2186 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2187 sc->nvifs > 0) {
2188 ret = -ENOBUFS;
2189 goto out;
2190 }
2191
8feceb67 2192 switch (conf->type) {
05c914fe 2193 case NL80211_IFTYPE_STATION:
d97809db 2194 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2195 break;
05c914fe 2196 case NL80211_IFTYPE_ADHOC:
05c914fe 2197 case NL80211_IFTYPE_AP:
9cb5412b 2198 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2199 if (sc->nbcnvifs >= ATH_BCBUF) {
2200 ret = -ENOBUFS;
2201 goto out;
2202 }
9cb5412b 2203 ic_opmode = conf->type;
f078f209
LR		 2204 break;
2205 default:
2206 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2207 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2208 ret = -EOPNOTSUPP;
2209 goto out;
f078f209
LR		 2210 }
2211
17d7904d 2212 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2213
17d7904d 2214 /* Set the VIF opmode */
5640b08e
S		 2215 avp->av_opmode = ic_opmode;
2216 avp->av_bslot = -1;
2217
2c3db3d5 2218 sc->nvifs++;
8ca21f01
JM		 2219
2220 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2221 ath9k_set_bssid_mask(hw);
2222
2c3db3d5
JM		 2223 if (sc->nvifs > 1)
2224 goto out; /* skip global settings for secondary vif */
2225
b238e90e 2226 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2227 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2228 sc->sc_flags |= SC_OP_TSF_RESET;
2229 }
5640b08e 2230
5640b08e 2231 /* Set the device opmode */
2660b81a 2232 sc->sc_ah->opmode = ic_opmode;
5640b08e 2233
4e30ffa2
VN		 2234 /*
2235 * Enable MIB interrupts when there are hardware phy counters.
2236 * Note we only do this (at the moment) for station mode.
2237 */
4af9cf4f 2238 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2239 (conf->type == NL80211_IFTYPE_ADHOC) ||
2240 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2241 if (ath9k_hw_phycounters(sc->sc_ah))
2242 sc->imask |= ATH9K_INT_MIB;
2243 sc->imask |= ATH9K_INT_TSFOOR;
2244 }
2245
17d7904d 2246 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2247
415f738e
S		 2248 if (conf->type == NL80211_IFTYPE_AP)
2249 ath_start_ani(sc);
6f255425 2250
2c3db3d5 2251out:
141b38b6 2252 mutex_unlock(&sc->mutex);
2c3db3d5 2253 return ret;
f078f209
LR		 2254}
2255
8feceb67
VT		 2256static void ath9k_remove_interface(struct ieee80211_hw *hw,
2257 struct ieee80211_if_init_conf *conf)
f078f209 2258{
bce048d7
JM		 2259 struct ath_wiphy *aphy = hw->priv;
2260 struct ath_softc *sc = aphy->sc;
17d7904d 2261 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2262 int i;
f078f209 2263
04bd4638 2264 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2265
141b38b6
S		 2266 mutex_lock(&sc->mutex);
2267
6f255425 2268 /* Stop ANI */
17d7904d 2269 del_timer_sync(&sc->ani.timer);
580f0b8a 2270
8feceb67 2271 /* Reclaim beacon resources */
9cb5412b
PE		 2272 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2273 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2274 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2275 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2276 ath_beacon_return(sc, avp);
580f0b8a 2277 }
f078f209 2278
8feceb67 2279 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2280
2c3db3d5
JM		 2281 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2282 if (sc->beacon.bslot[i] == conf->vif) {
2283 printk(KERN_DEBUG "%s: vif had allocated beacon "
2284 "slot\n", __func__);
2285 sc->beacon.bslot[i] = NULL;
c52f33d0 2286 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2287 }
2288 }
2289
17d7904d 2290 sc->nvifs--;
141b38b6
S		 2291
2292 mutex_unlock(&sc->mutex);
f078f209
LR		 2293}
2294
e8975581 2295static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2296{
bce048d7
JM		 2297 struct ath_wiphy *aphy = hw->priv;
2298 struct ath_softc *sc = aphy->sc;
e8975581 2299 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2300 struct ath_hw *ah = sc->sc_ah;
f078f209 2301
aa33de09 2302 mutex_lock(&sc->mutex);
141b38b6 2303
3cbb5dd7
VN		 2304 if (changed & IEEE80211_CONF_CHANGE_PS) {
2305 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2306 if (!(ah->caps.hw_caps &
2307 ATH9K_HW_CAP_AUTOSLEEP)) {
2308 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2309 sc->imask |= ATH9K_INT_TIM_TIMER;
2310 ath9k_hw_set_interrupts(sc->sc_ah,
2311 sc->imask);
2312 }
2313 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2314 }
3cbb5dd7
VN		 2315 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2316 } else {
2317 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2318 if (!(ah->caps.hw_caps &
2319 ATH9K_HW_CAP_AUTOSLEEP)) {
2320 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2321 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2322 SC_OP_WAIT_FOR_CAB |
2323 SC_OP_WAIT_FOR_PSPOLL_DATA |
2324 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2325 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2326 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2327 ath9k_hw_set_interrupts(sc->sc_ah,
2328 sc->imask);
2329 }
3cbb5dd7
VN		 2330 }
2331 }
2332 }
2333
4797938c 2334 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2335 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2336 int pos = curchan->hw_value;
ae5eb026 2337
0e2dedf9
JM		 2338 aphy->chan_idx = pos;
2339 aphy->chan_is_ht = conf_is_ht(conf);
2340
8089cc47
JM		 2341 if (aphy->state == ATH_WIPHY_SCAN ||
2342 aphy->state == ATH_WIPHY_ACTIVE)
2343 ath9k_wiphy_pause_all_forced(sc, aphy);
2344 else {
2345 /*
2346 * Do not change operational channel based on a paused
2347 * wiphy changes.
2348 */
2349 goto skip_chan_change;
2350 }
0e2dedf9 2351
04bd4638
S		 2352 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2353 curchan->center_freq);
f078f209 2354
5f8e077c 2355 /* XXX: remove me eventualy */
0e2dedf9 2356 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2357
ecf70441 2358 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2359
0e2dedf9 2360 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2361 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2362 mutex_unlock(&sc->mutex);
e11602b7
S		 2363 return -EINVAL;
2364 }
094d05dc 2365 }
f078f209 2366
8089cc47 2367skip_chan_change:
5c020dc6 2368 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2369 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2370
aa33de09 2371 mutex_unlock(&sc->mutex);
141b38b6 2372
f078f209
LR		 2373 return 0;
2374}
2375
8feceb67
VT		 2376#define SUPPORTED_FILTERS \
2377 (FIF_PROMISC_IN_BSS | \
2378 FIF_ALLMULTI | \
2379 FIF_CONTROL | \
2380 FIF_OTHER_BSS | \
2381 FIF_BCN_PRBRESP_PROMISC | \
2382 FIF_FCSFAIL)
c83be688 2383
8feceb67
VT		 2384/* FIXME: sc->sc_full_reset ? */
2385static void ath9k_configure_filter(struct ieee80211_hw *hw,
2386 unsigned int changed_flags,
2387 unsigned int *total_flags,
2388 int mc_count,
2389 struct dev_mc_list *mclist)
2390{
bce048d7
JM		 2391 struct ath_wiphy *aphy = hw->priv;
2392 struct ath_softc *sc = aphy->sc;
8feceb67 2393 u32 rfilt;
f078f209 2394
8feceb67
VT		 2395 changed_flags &= SUPPORTED_FILTERS;
2396 *total_flags &= SUPPORTED_FILTERS;
f078f209 2397
b77f483f 2398 sc->rx.rxfilter = *total_flags;
aa68aeaa 2399 ath9k_ps_wakeup(sc);
8feceb67
VT		 2400 rfilt = ath_calcrxfilter(sc);
2401 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2402 ath9k_ps_restore(sc);
f078f209 2403
b77f483f 2404 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2405}
f078f209 2406
8feceb67
VT		 2407static void ath9k_sta_notify(struct ieee80211_hw *hw,
2408 struct ieee80211_vif *vif,
2409 enum sta_notify_cmd cmd,
17741cdc 2410 struct ieee80211_sta *sta)
8feceb67 2411{
bce048d7
JM		 2412 struct ath_wiphy *aphy = hw->priv;
2413 struct ath_softc *sc = aphy->sc;
f078f209 2414
8feceb67
VT		 2415 switch (cmd) {
2416 case STA_NOTIFY_ADD:
5640b08e 2417 ath_node_attach(sc, sta);
8feceb67
VT		 2418 break;
2419 case STA_NOTIFY_REMOVE:
b5aa9bf9 2420 ath_node_detach(sc, sta);
8feceb67
VT		 2421 break;
2422 default:
2423 break;
2424 }
f078f209
LR		 2425}
2426
141b38b6 2427static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2428 const struct ieee80211_tx_queue_params *params)
f078f209 2429{
bce048d7
JM		 2430 struct ath_wiphy *aphy = hw->priv;
2431 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2432 struct ath9k_tx_queue_info qi;
2433 int ret = 0, qnum;
f078f209 2434
8feceb67
VT		 2435 if (queue >= WME_NUM_AC)
2436 return 0;
f078f209 2437
141b38b6
S		 2438 mutex_lock(&sc->mutex);
2439
1ffb0610
S		 2440 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2441
8feceb67
VT		 2442 qi.tqi_aifs = params->aifs;
2443 qi.tqi_cwmin = params->cw_min;
2444 qi.tqi_cwmax = params->cw_max;
2445 qi.tqi_burstTime = params->txop;
2446 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2447
8feceb67 2448 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2449 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2450 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2451 queue, qnum, params->aifs, params->cw_min,
2452 params->cw_max, params->txop);
f078f209 2453
8feceb67
VT		 2454 ret = ath_txq_update(sc, qnum, &qi);
2455 if (ret)
04bd4638 2456 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2457
141b38b6
S		 2458 mutex_unlock(&sc->mutex);
2459
8feceb67
VT		 2460 return ret;
2461}
f078f209 2462
8feceb67
VT		 2463static int ath9k_set_key(struct ieee80211_hw *hw,
2464 enum set_key_cmd cmd,
dc822b5d
JB		 2465 struct ieee80211_vif *vif,
2466 struct ieee80211_sta *sta,
8feceb67
VT		 2467 struct ieee80211_key_conf *key)
2468{
bce048d7
JM		 2469 struct ath_wiphy *aphy = hw->priv;
2470 struct ath_softc *sc = aphy->sc;
8feceb67 2471 int ret = 0;
f078f209 2472
b3bd89ce
JM		 2473 if (modparam_nohwcrypt)
2474 return -ENOSPC;
2475
141b38b6 2476 mutex_lock(&sc->mutex);
3cbb5dd7 2477 ath9k_ps_wakeup(sc);
d8baa939 2478 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2479
8feceb67
VT		 2480 switch (cmd) {
2481 case SET_KEY:
3f53dd64 2482 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2483 if (ret >= 0) {
2484 key->hw_key_idx = ret;
8feceb67
VT		 2485 /* push IV and Michael MIC generation to stack */
2486 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2487 if (key->alg == ALG_TKIP)
2488 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2489 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2490 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2491 ret = 0;
8feceb67
VT		 2492 }
2493 break;
2494 case DISABLE_KEY:
2495 ath_key_delete(sc, key);
8feceb67
VT		 2496 break;
2497 default:
2498 ret = -EINVAL;
2499 }
f078f209 2500
3cbb5dd7 2501 ath9k_ps_restore(sc);
141b38b6
S		 2502 mutex_unlock(&sc->mutex);
2503
8feceb67
VT		 2504 return ret;
2505}
f078f209 2506
8feceb67
VT		 2507static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2508 struct ieee80211_vif *vif,
2509 struct ieee80211_bss_conf *bss_conf,
2510 u32 changed)
2511{
bce048d7
JM		 2512 struct ath_wiphy *aphy = hw->priv;
2513 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2514 struct ath_hw *ah = sc->sc_ah;
2515 struct ath_vif *avp = (void *)vif->drv_priv;
2516 u32 rfilt = 0;
2517 int error, i;
f078f209 2518
141b38b6
S		 2519 mutex_lock(&sc->mutex);
2520
2d0ddec5
JB		 2521 /*
2522 * TODO: Need to decide which hw opmode to use for
2523 * multi-interface cases
2524 * XXX: This belongs into add_interface!
2525 */
2526 if (vif->type == NL80211_IFTYPE_AP &&
2527 ah->opmode != NL80211_IFTYPE_AP) {
2528 ah->opmode = NL80211_IFTYPE_STATION;
2529 ath9k_hw_setopmode(ah);
2530 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2531 sc->curaid = 0;
2532 ath9k_hw_write_associd(sc);
2533 /* Request full reset to get hw opmode changed properly */
2534 sc->sc_flags |= SC_OP_FULL_RESET;
2535 }
2536
2537 if ((changed & BSS_CHANGED_BSSID) &&
2538 !is_zero_ether_addr(bss_conf->bssid)) {
2539 switch (vif->type) {
2540 case NL80211_IFTYPE_STATION:
2541 case NL80211_IFTYPE_ADHOC:
2542 case NL80211_IFTYPE_MESH_POINT:
2543 /* Set BSSID */
2544 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2545 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2546 sc->curaid = 0;
2547 ath9k_hw_write_associd(sc);
2548
2549 /* Set aggregation protection mode parameters */
2550 sc->config.ath_aggr_prot = 0;
2551
2552 DPRINTF(sc, ATH_DBG_CONFIG,
2553 "RX filter 0x%x bssid %pM aid 0x%x\n",
2554 rfilt, sc->curbssid, sc->curaid);
2555
2556 /* need to reconfigure the beacon */
2557 sc->sc_flags &= ~SC_OP_BEACONS ;
2558
2559 break;
2560 default:
2561 break;
2562 }
2563 }
2564
2565 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2566 (vif->type == NL80211_IFTYPE_AP) ||
2567 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2568 if ((changed & BSS_CHANGED_BEACON) ||
2569 (changed & BSS_CHANGED_BEACON_ENABLED &&
2570 bss_conf->enable_beacon)) {
2571 /*
2572 * Allocate and setup the beacon frame.
2573 *
2574 * Stop any previous beacon DMA. This may be
2575 * necessary, for example, when an ibss merge
2576 * causes reconfiguration; we may be called
2577 * with beacon transmission active.
2578 */
2579 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2580
2581 error = ath_beacon_alloc(aphy, vif);
2582 if (!error)
2583 ath_beacon_config(sc, vif);
2584 }
2585 }
2586
2587 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2588 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2589 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2590 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2591 ath9k_hw_keysetmac(sc->sc_ah,
2592 (u16)i,
2593 sc->curbssid);
2594 }
2595
2596 /* Only legacy IBSS for now */
2597 if (vif->type == NL80211_IFTYPE_ADHOC)
2598 ath_update_chainmask(sc, 0);
2599
8feceb67 2600 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2601 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2602 bss_conf->use_short_preamble);
2603 if (bss_conf->use_short_preamble)
2604 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2605 else
2606 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2607 }
f078f209 2608
8feceb67 2609 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2610 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2611 bss_conf->use_cts_prot);
2612 if (bss_conf->use_cts_prot &&
2613 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2614 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2615 else
2616 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2617 }
f078f209 2618
8feceb67 2619 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2620 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2621 bss_conf->assoc);
5640b08e 2622 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2623 }
141b38b6 2624
57c4d7b4
JB		 2625 /*
2626 * The HW TSF has to be reset when the beacon interval changes.
2627 * We set the flag here, and ath_beacon_config_ap() would take this
2628 * into account when it gets called through the subsequent
2629 * config_interface() call - with IFCC_BEACON in the changed field.
2630 */
2631
2632 if (changed & BSS_CHANGED_BEACON_INT) {
2633 sc->sc_flags |= SC_OP_TSF_RESET;
2634 sc->beacon_interval = bss_conf->beacon_int;
2635 }
2636
141b38b6 2637 mutex_unlock(&sc->mutex);
8feceb67 2638}
f078f209 2639
8feceb67
VT		 2640static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2641{
2642 u64 tsf;
bce048d7
JM		 2643 struct ath_wiphy *aphy = hw->priv;
2644 struct ath_softc *sc = aphy->sc;
f078f209 2645
141b38b6
S		 2646 mutex_lock(&sc->mutex);
2647 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2648 mutex_unlock(&sc->mutex);
f078f209 2649
8feceb67
VT		 2650 return tsf;
2651}
f078f209 2652
3b5d665b
AF		 2653static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2654{
bce048d7
JM		 2655 struct ath_wiphy *aphy = hw->priv;
2656 struct ath_softc *sc = aphy->sc;
3b5d665b 2657
141b38b6
S		 2658 mutex_lock(&sc->mutex);
2659 ath9k_hw_settsf64(sc->sc_ah, tsf);
2660 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2661}
2662
8feceb67
VT		 2663static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2664{
bce048d7
JM		 2665 struct ath_wiphy *aphy = hw->priv;
2666 struct ath_softc *sc = aphy->sc;
c83be688 2667
141b38b6
S		 2668 mutex_lock(&sc->mutex);
2669 ath9k_hw_reset_tsf(sc->sc_ah);
2670 mutex_unlock(&sc->mutex);
8feceb67 2671}
f078f209 2672
8feceb67 2673static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2674 enum ieee80211_ampdu_mlme_action action,
2675 struct ieee80211_sta *sta,
2676 u16 tid, u16 *ssn)
8feceb67 2677{
bce048d7
JM		 2678 struct ath_wiphy *aphy = hw->priv;
2679 struct ath_softc *sc = aphy->sc;
8feceb67 2680 int ret = 0;
f078f209 2681
8feceb67
VT		 2682 switch (action) {
2683 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2684 if (!(sc->sc_flags & SC_OP_RXAGGR))
2685 ret = -ENOTSUPP;
8feceb67
VT		 2686 break;
2687 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2688 break;
2689 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2690 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2691 if (ret < 0)
2692 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2693 "Unable to start TX aggregation\n");
8feceb67 2694 else
17741cdc 2695 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2696 break;
2697 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2698 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2699 if (ret < 0)
2700 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2701 "Unable to stop TX aggregation\n");
f078f209 2702
17741cdc 2703 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2704 break;
b1720231 2705 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2706 ath_tx_aggr_resume(sc, sta, tid);
2707 break;
8feceb67 2708 default:
04bd4638 2709 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2710 }
2711
2712 return ret;
f078f209
LR		 2713}
2714
0c98de65
S		 2715static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2716{
bce048d7
JM		 2717 struct ath_wiphy *aphy = hw->priv;
2718 struct ath_softc *sc = aphy->sc;
0c98de65 2719
8089cc47
JM		 2720 if (ath9k_wiphy_scanning(sc)) {
2721 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2722 "same time\n");
2723 /*
2724 * Do not allow the concurrent scanning state for now. This
2725 * could be improved with scanning control moved into ath9k.
2726 */
2727 return;
2728 }
2729
2730 aphy->state = ATH_WIPHY_SCAN;
2731 ath9k_wiphy_pause_all_forced(sc, aphy);
2732
0c98de65
S		 2733 mutex_lock(&sc->mutex);
2734 sc->sc_flags |= SC_OP_SCANNING;
2735 mutex_unlock(&sc->mutex);
2736}
2737
2738static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2739{
bce048d7
JM		 2740 struct ath_wiphy *aphy = hw->priv;
2741 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2742
2743 mutex_lock(&sc->mutex);
8089cc47 2744 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2745 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2746 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2747 mutex_unlock(&sc->mutex);
2748}
2749
6baff7f9 2750struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2751 .tx = ath9k_tx,
2752 .start = ath9k_start,
2753 .stop = ath9k_stop,
2754 .add_interface = ath9k_add_interface,
2755 .remove_interface = ath9k_remove_interface,
2756 .config = ath9k_config,
8feceb67 2757 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2758 .sta_notify = ath9k_sta_notify,
2759 .conf_tx = ath9k_conf_tx,
8feceb67 2760 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2761 .set_key = ath9k_set_key,
8feceb67 2762 .get_tsf = ath9k_get_tsf,
3b5d665b 2763 .set_tsf = ath9k_set_tsf,
8feceb67 2764 .reset_tsf = ath9k_reset_tsf,
4233df6b 2765 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2766 .sw_scan_start = ath9k_sw_scan_start,
2767 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2768};
2769
392dff83
BP		 2770static struct {
2771 u32 version;
2772 const char * name;
2773} ath_mac_bb_names[] = {
2774 { AR_SREV_VERSION_5416_PCI, "5416" },
2775 { AR_SREV_VERSION_5416_PCIE, "5418" },
2776 { AR_SREV_VERSION_9100, "9100" },
2777 { AR_SREV_VERSION_9160, "9160" },
2778 { AR_SREV_VERSION_9280, "9280" },
2779 { AR_SREV_VERSION_9285, "9285" }
2780};
2781
2782static struct {
2783 u16 version;
2784 const char * name;
2785} ath_rf_names[] = {
2786 { 0, "5133" },
2787 { AR_RAD5133_SREV_MAJOR, "5133" },
2788 { AR_RAD5122_SREV_MAJOR, "5122" },
2789 { AR_RAD2133_SREV_MAJOR, "2133" },
2790 { AR_RAD2122_SREV_MAJOR, "2122" }
2791};
2792
2793/*
2794 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2795 */
6baff7f9 2796const char *
392dff83
BP		 2797ath_mac_bb_name(u32 mac_bb_version)
2798{
2799 int i;
2800
2801 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2802 if (ath_mac_bb_names[i].version == mac_bb_version) {
2803 return ath_mac_bb_names[i].name;
2804 }
2805 }
2806
2807 return "????";
2808}
2809
2810/*
2811 * Return the RF name. "????" is returned if the RF is unknown.
2812 */
6baff7f9 2813const char *
392dff83
BP		 2814ath_rf_name(u16 rf_version)
2815{
2816 int i;
2817
2818 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2819 if (ath_rf_names[i].version == rf_version) {
2820 return ath_rf_names[i].name;
2821 }
2822 }
2823
2824 return "????";
2825}
2826
6baff7f9 2827static int __init ath9k_init(void)
f078f209 2828{
ca8a8560
VT		 2829 int error;
2830
ca8a8560
VT		 2831 /* Register rate control algorithm */
2832 error = ath_rate_control_register();
2833 if (error != 0) {
2834 printk(KERN_ERR
b51bb3cd
LR		 2835 "ath9k: Unable to register rate control "
2836 "algorithm: %d\n",
ca8a8560 2837 error);
6baff7f9 2838 goto err_out;
ca8a8560
VT		 2839 }
2840
19d8bc22
GJ		 2841 error = ath9k_debug_create_root();
2842 if (error) {
2843 printk(KERN_ERR
2844 "ath9k: Unable to create debugfs root: %d\n",
2845 error);
2846 goto err_rate_unregister;
2847 }
2848
6baff7f9
GJ		 2849 error = ath_pci_init();
2850 if (error < 0) {
f078f209 2851 printk(KERN_ERR
b51bb3cd 2852 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2853 error = -ENODEV;
19d8bc22 2854 goto err_remove_root;
f078f209
LR		 2855 }
2856
09329d37
GJ		 2857 error = ath_ahb_init();
2858 if (error < 0) {
2859 error = -ENODEV;
2860 goto err_pci_exit;
2861 }
2862
f078f209 2863 return 0;
6baff7f9 2864
09329d37
GJ		 2865 err_pci_exit:
2866 ath_pci_exit();
2867
19d8bc22
GJ		 2868 err_remove_root:
2869 ath9k_debug_remove_root();
6baff7f9
GJ		 2870 err_rate_unregister:
2871 ath_rate_control_unregister();
2872 err_out:
2873 return error;
f078f209 2874}
6baff7f9 2875module_init(ath9k_init);
f078f209 2876
6baff7f9 2877static void __exit ath9k_exit(void)
f078f209 2878{
09329d37 2879 ath_ahb_exit();
6baff7f9 2880 ath_pci_exit();
19d8bc22 2881 ath9k_debug_remove_root();
ca8a8560 2882 ath_rate_control_unregister();
04bd4638 2883 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2884}
6baff7f9 2885module_exit(ath9k_exit);
kernel source for telekom puls (alcatel/mediatek)