ath9k: always call ath_reset from workqueue context
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
114 unsigned long flags;
115
116 spin_lock_irqsave(&sc->sc_pm_lock, flags);
117 if (--sc->ps_usecount != 0)
118 goto unlock;
119
898c914a
FF
120 spin_lock(&common->cc_lock);
121 ath_hw_cycle_counters_update(common);
122 spin_unlock(&common->cc_lock);
123
1dbfd9d4
VN
124 if (sc->ps_idle)
125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
132
133 unlock:
134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
135}
136
05c0be2f 137void ath_start_ani(struct ath_common *common)
5ee08656
FF
138{
139 struct ath_hw *ah = common->ah;
140 unsigned long timestamp = jiffies_to_msecs(jiffies);
141 struct ath_softc *sc = (struct ath_softc *) common->priv;
142
143 if (!(sc->sc_flags & SC_OP_ANI_RUN))
144 return;
145
146 if (sc->sc_flags & SC_OP_OFFCHANNEL)
147 return;
148
149 common->ani.longcal_timer = timestamp;
150 common->ani.shortcal_timer = timestamp;
151 common->ani.checkani_timer = timestamp;
152
153 mod_timer(&common->ani.timer,
154 jiffies +
155 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
156}
157
3430098a
FF
158static void ath_update_survey_nf(struct ath_softc *sc, int channel)
159{
160 struct ath_hw *ah = sc->sc_ah;
161 struct ath9k_channel *chan = &ah->channels[channel];
162 struct survey_info *survey = &sc->survey[channel];
163
164 if (chan->noisefloor) {
165 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 166 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
167 }
168}
169
cb8d61de
FF
170/*
171 * Updates the survey statistics and returns the busy time since last
172 * update in %, if the measurement duration was long enough for the
173 * result to be useful, -1 otherwise.
174 */
175static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
176{
177 struct ath_hw *ah = sc->sc_ah;
178 struct ath_common *common = ath9k_hw_common(ah);
179 int pos = ah->curchan - &ah->channels[0];
180 struct survey_info *survey = &sc->survey[pos];
181 struct ath_cycle_counters *cc = &common->cc_survey;
182 unsigned int div = common->clockrate * 1000;
cb8d61de 183 int ret = 0;
3430098a 184
0845735e 185 if (!ah->curchan)
cb8d61de 186 return -1;
0845735e 187
898c914a
FF
188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF
190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
cb8d61de
FF
201
202 if (cc->cycles < div)
203 return -1;
204
205 if (cc->cycles > 0)
206 ret = cc->rx_busy * 100 / cc->cycles;
207
3430098a
FF
208 memset(cc, 0, sizeof(*cc));
209
210 ath_update_survey_nf(sc, pos);
cb8d61de
FF
211
212 return ret;
3430098a
FF
213}
214
ff37e337
S
215/*
216 * Set/change channels. If the channel is really being changed, it's done
217 * by reseting the chip. To accomplish this we must first cleanup any pending
218 * DMA, then restart stuff.
219*/
5595f119 220static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
0e2dedf9 221 struct ath9k_channel *hchan)
ff37e337 222{
cbe61d8a 223 struct ath_hw *ah = sc->sc_ah;
c46917bb 224 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 225 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 226 bool fastcc = true, stopped;
ae8d2858 227 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 228 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 229 int r;
ff37e337
S
230
231 if (sc->sc_flags & SC_OP_INVALID)
232 return -EIO;
233
cb8d61de
FF
234 sc->hw_busy_count = 0;
235
5ee08656
FF
236 del_timer_sync(&common->ani.timer);
237 cancel_work_sync(&sc->paprd_work);
238 cancel_work_sync(&sc->hw_check_work);
236de514 239 cancel_work_sync(&sc->hw_reset_work);
5ee08656 240 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 241 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 242
3cbb5dd7
VN
243 ath9k_ps_wakeup(sc);
244
6a6733f2
LR
245 spin_lock_bh(&sc->sc_pcu_lock);
246
c0d7c7af
LR
247 /*
248 * This is only performed if the channel settings have
249 * actually changed.
250 *
251 * To switch channels clear any pending DMA operations;
252 * wait long enough for the RX fifo to drain, reset the
253 * hardware at the new frequency, and then re-enable
254 * the relevant bits of the h/w.
255 */
4df3071e 256 ath9k_hw_disable_interrupts(ah);
080e1a25 257 stopped = ath_drain_all_txq(sc, false);
5e848f78 258
080e1a25
FF
259 if (!ath_stoprecv(sc))
260 stopped = false;
ff37e337 261
8b3f4616
FF
262 if (!ath9k_hw_check_alive(ah))
263 stopped = false;
264
c0d7c7af
LR
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
5ee08656 269 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
270 fastcc = false;
271
20bd2a09 272 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 273 caldata = &sc->caldata;
20bd2a09 274
226afe68
JP
275 ath_dbg(common, ATH_DBG_CONFIG,
276 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
277 sc->sc_ah->curchan->channel,
278 channel->center_freq, conf_is_ht40(conf),
279 fastcc);
ff37e337 280
20bd2a09 281 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 282 if (r) {
3800276a
JP
283 ath_err(common,
284 "Unable to reset channel (%u MHz), reset status %d\n",
285 channel->center_freq, r);
3989279c 286 goto ps_restore;
ff37e337 287 }
c0d7c7af 288
c0d7c7af 289 if (ath_startrecv(sc) != 0) {
3800276a 290 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
291 r = -EIO;
292 goto ps_restore;
c0d7c7af
LR
293 }
294
5048e8c3
RM
295 ath9k_cmn_update_txpow(ah, sc->curtxpow,
296 sc->config.txpowlimit, &sc->curtxpow);
3069168c 297 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 298 ath9k_hw_enable_interrupts(ah);
3989279c 299
48a6a468 300 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b 301 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 302 ath_set_beacon(sc);
5ee08656 303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
305 if (!common->disable_ani)
306 ath_start_ani(common);
5ee08656
FF
307 }
308
3989279c 309 ps_restore:
92460412
FF
310 ieee80211_wake_queues(hw);
311
6a6733f2
LR
312 spin_unlock_bh(&sc->sc_pcu_lock);
313
3cbb5dd7 314 ath9k_ps_restore(sc);
3989279c 315 return r;
ff37e337
S
316}
317
9f42c2b6
FF
318static void ath_paprd_activate(struct ath_softc *sc)
319{
320 struct ath_hw *ah = sc->sc_ah;
20bd2a09 321 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
322 int chain;
323
20bd2a09 324 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
325 return;
326
327 ath9k_ps_wakeup(sc);
ddfef792 328 ar9003_paprd_enable(ah, false);
9f42c2b6 329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 330 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
331 continue;
332
20bd2a09 333 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
334 }
335
336 ar9003_paprd_enable(ah, true);
337 ath9k_ps_restore(sc);
338}
339
7607cbe2
FF
340static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
341{
342 struct ieee80211_hw *hw = sc->hw;
343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
344 struct ath_hw *ah = sc->sc_ah;
345 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
346 struct ath_tx_control txctl;
347 int time_left;
348
349 memset(&txctl, 0, sizeof(txctl));
350 txctl.txq = sc->tx.txq_map[WME_AC_BE];
351
352 memset(tx_info, 0, sizeof(*tx_info));
353 tx_info->band = hw->conf.channel->band;
354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
355 tx_info->control.rates[0].idx = 0;
356 tx_info->control.rates[0].count = 1;
357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
358 tx_info->control.rates[1].idx = -1;
359
360 init_completion(&sc->paprd_complete);
7607cbe2 361 txctl.paprd = BIT(chain);
47960077
MSS
362
363 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 364 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 365 dev_kfree_skb_any(skb);
7607cbe2 366 return false;
47960077 367 }
7607cbe2
FF
368
369 time_left = wait_for_completion_timeout(&sc->paprd_complete,
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
371
372 if (!time_left)
d4bb17c4 373 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
374 "Timeout waiting for paprd training on TX chain %d\n",
375 chain);
376
377 return !!time_left;
378}
379
9f42c2b6
FF
380void ath_paprd_calibrate(struct work_struct *work)
381{
382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
383 struct ieee80211_hw *hw = sc->hw;
384 struct ath_hw *ah = sc->sc_ah;
385 struct ieee80211_hdr *hdr;
386 struct sk_buff *skb = NULL;
20bd2a09 387 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 388 struct ath_common *common = ath9k_hw_common(ah);
066dae93 389 int ftype;
9f42c2b6
FF
390 int chain_ok = 0;
391 int chain;
392 int len = 1800;
9f42c2b6 393
20bd2a09
FF
394 if (!caldata)
395 return;
396
b942471b
MSS
397 ath9k_ps_wakeup(sc);
398
1bf38661 399 if (ar9003_paprd_init_table(ah) < 0)
b942471b 400 goto fail_paprd;
1bf38661 401
9f42c2b6
FF
402 skb = alloc_skb(len, GFP_KERNEL);
403 if (!skb)
b942471b 404 goto fail_paprd;
9f42c2b6 405
9f42c2b6
FF
406 skb_put(skb, len);
407 memset(skb->data, 0, len);
408 hdr = (struct ieee80211_hdr *)skb->data;
409 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
410 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 411 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
412 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
413 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
414 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
415
9f42c2b6 416 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
82b2d334 417 if (!(ah->txchainmask & BIT(chain)))
9f42c2b6
FF
418 continue;
419
420 chain_ok = 0;
9f42c2b6 421
7607cbe2
FF
422 ath_dbg(common, ATH_DBG_CALIBRATE,
423 "Sending PAPRD frame for thermal measurement "
424 "on chain %d\n", chain);
425 if (!ath_paprd_send_frame(sc, skb, chain))
426 goto fail_paprd;
9f42c2b6 427
9f42c2b6 428 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 429
7607cbe2
FF
430 ath_dbg(common, ATH_DBG_CALIBRATE,
431 "Sending PAPRD training frame on chain %d\n", chain);
432 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 433 goto fail_paprd;
9f42c2b6 434
d4bb17c4
MSS
435 if (!ar9003_paprd_is_done(ah)) {
436 ath_dbg(common, ATH_DBG_CALIBRATE,
437 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 438 break;
d4bb17c4 439 }
9f42c2b6 440
d4bb17c4
MSS
441 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
442 ath_dbg(common, ATH_DBG_CALIBRATE,
443 "PAPRD create curve failed on chain %d\n",
444 chain);
9f42c2b6 445 break;
d4bb17c4 446 }
9f42c2b6
FF
447
448 chain_ok = 1;
449 }
450 kfree_skb(skb);
451
452 if (chain_ok) {
20bd2a09 453 caldata->paprd_done = true;
9f42c2b6
FF
454 ath_paprd_activate(sc);
455 }
456
ca369eb4 457fail_paprd:
9f42c2b6
FF
458 ath9k_ps_restore(sc);
459}
460
ff37e337
S
461/*
462 * This routine performs the periodic noise floor calibration function
463 * that is used to adjust and optimize the chip performance. This
464 * takes environmental changes (location, temperature) into account.
465 * When the task is complete, it reschedules itself depending on the
466 * appropriate interval that was calculated.
467 */
55624204 468void ath_ani_calibrate(unsigned long data)
ff37e337 469{
20977d3e
S
470 struct ath_softc *sc = (struct ath_softc *)data;
471 struct ath_hw *ah = sc->sc_ah;
c46917bb 472 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
473 bool longcal = false;
474 bool shortcal = false;
475 bool aniflag = false;
476 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 477 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 478 unsigned long flags;
6044474e
FF
479
480 if (ah->caldata && ah->caldata->nfcal_interference)
481 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
482 else
483 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 484
20977d3e
S
485 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
486 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 487
1ffc1c61
JM
488 /* Only calibrate if awake */
489 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
490 goto set_timer;
491
492 ath9k_ps_wakeup(sc);
493
ff37e337 494 /* Long calibration runs independently of short calibration. */
6044474e 495 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 496 longcal = true;
226afe68 497 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 498 common->ani.longcal_timer = timestamp;
ff37e337
S
499 }
500
17d7904d 501 /* Short calibration applies only while caldone is false */
3d536acf
LR
502 if (!common->ani.caldone) {
503 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 504 shortcal = true;
226afe68
JP
505 ath_dbg(common, ATH_DBG_ANI,
506 "shortcal @%lu\n", jiffies);
3d536acf
LR
507 common->ani.shortcal_timer = timestamp;
508 common->ani.resetcal_timer = timestamp;
ff37e337
S
509 }
510 } else {
3d536acf 511 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 512 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
513 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
514 if (common->ani.caldone)
515 common->ani.resetcal_timer = timestamp;
ff37e337
S
516 }
517 }
518
519 /* Verify whether we must check ANI */
e36b27af
LR
520 if ((timestamp - common->ani.checkani_timer) >=
521 ah->config.ani_poll_interval) {
ff37e337 522 aniflag = true;
3d536acf 523 common->ani.checkani_timer = timestamp;
ff37e337
S
524 }
525
e62ddec9
MSS
526 /* Call ANI routine if necessary */
527 if (aniflag) {
528 spin_lock_irqsave(&common->cc_lock, flags);
529 ath9k_hw_ani_monitor(ah, ah->curchan);
530 ath_update_survey_stats(sc);
531 spin_unlock_irqrestore(&common->cc_lock, flags);
532 }
ff37e337 533
e62ddec9
MSS
534 /* Perform calibration if necessary */
535 if (longcal || shortcal) {
536 common->ani.caldone =
537 ath9k_hw_calibrate(ah, ah->curchan,
82b2d334 538 ah->rxchainmask, longcal);
ff37e337
S
539 }
540
1ffc1c61
JM
541 ath9k_ps_restore(sc);
542
20977d3e 543set_timer:
ff37e337
S
544 /*
545 * Set timer interval based on previous results.
546 * The interval must be the shortest necessary to satisfy ANI,
547 * short calibration and long calibration.
548 */
cf3af748 549 ath9k_debug_samp_bb_mac(sc);
aac9207e 550 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 551 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
552 cal_interval = min(cal_interval,
553 (u32)ah->config.ani_poll_interval);
3d536acf 554 if (!common->ani.caldone)
20977d3e 555 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 556
3d536acf 557 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
558 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
559 if (!ah->caldata->paprd_done)
9f42c2b6 560 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 561 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
562 ath_paprd_activate(sc);
563 }
ff37e337
S
564}
565
ff37e337
S
566static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
567{
568 struct ath_node *an;
ff37e337
S
569 an = (struct ath_node *)sta->drv_priv;
570
7f010c93
BG
571#ifdef CONFIG_ATH9K_DEBUGFS
572 spin_lock(&sc->nodes_lock);
573 list_add(&an->list, &sc->nodes);
574 spin_unlock(&sc->nodes_lock);
575 an->sta = sta;
576#endif
87792efc 577 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 578 ath_tx_node_init(sc, an);
9e98ac65 579 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
580 sta->ht_cap.ampdu_factor);
581 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
582 }
ff37e337
S
583}
584
585static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
586{
587 struct ath_node *an = (struct ath_node *)sta->drv_priv;
588
7f010c93
BG
589#ifdef CONFIG_ATH9K_DEBUGFS
590 spin_lock(&sc->nodes_lock);
591 list_del(&an->list);
592 spin_unlock(&sc->nodes_lock);
593 an->sta = NULL;
594#endif
595
ff37e337
S
596 if (sc->sc_flags & SC_OP_TXAGGR)
597 ath_tx_node_cleanup(sc, an);
598}
599
9eab61c2 600
55624204 601void ath9k_tasklet(unsigned long data)
ff37e337
S
602{
603 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 604 struct ath_hw *ah = sc->sc_ah;
c46917bb 605 struct ath_common *common = ath9k_hw_common(ah);
af03abec 606
17d7904d 607 u32 status = sc->intrstatus;
b5c80475 608 u32 rxmask;
ff37e337 609
a4d86d95
RM
610 if ((status & ATH9K_INT_FATAL) ||
611 (status & ATH9K_INT_BB_WATCHDOG)) {
236de514 612 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
ff37e337 613 return;
063d8be3 614 }
ff37e337 615
783cd01e 616 ath9k_ps_wakeup(sc);
52671e43 617 spin_lock(&sc->sc_pcu_lock);
6a6733f2 618
8b3f4616
FF
619 /*
620 * Only run the baseband hang check if beacons stop working in AP or
621 * IBSS mode, because it has a high false positive rate. For station
622 * mode it should not be necessary, since the upper layers will detect
623 * this through a beacon miss automatically and the following channel
624 * change will trigger a hardware reset anyway
625 */
626 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
627 !ath9k_hw_check_alive(ah))
347809fc
FF
628 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
629
4105f807
RM
630 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
631 /*
632 * TSF sync does not look correct; remain awake to sync with
633 * the next Beacon.
634 */
635 ath_dbg(common, ATH_DBG_PS,
636 "TSFOOR - Sync with next Beacon\n");
e8fe7336 637 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807
RM
638 }
639
b5c80475
FF
640 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
641 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
642 ATH9K_INT_RXORN);
643 else
644 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
645
646 if (status & rxmask) {
b5c80475
FF
647 /* Check for high priority Rx first */
648 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
649 (status & ATH9K_INT_RXHP))
650 ath_rx_tasklet(sc, 0, true);
651
652 ath_rx_tasklet(sc, 0, false);
ff37e337
S
653 }
654
e5003249
VT
655 if (status & ATH9K_INT_TX) {
656 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
657 ath_tx_edma_tasklet(sc);
658 else
659 ath_tx_tasklet(sc);
660 }
063d8be3 661
766ec4a9 662 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
663 if (status & ATH9K_INT_GENTIMER)
664 ath_gen_timer_isr(sc->sc_ah);
665
ff37e337 666 /* re-enable hardware interrupt */
4df3071e 667 ath9k_hw_enable_interrupts(ah);
6a6733f2 668
52671e43 669 spin_unlock(&sc->sc_pcu_lock);
153e080d 670 ath9k_ps_restore(sc);
ff37e337
S
671}
672
6baff7f9 673irqreturn_t ath_isr(int irq, void *dev)
ff37e337 674{
063d8be3
S
675#define SCHED_INTR ( \
676 ATH9K_INT_FATAL | \
a4d86d95 677 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
678 ATH9K_INT_RXORN | \
679 ATH9K_INT_RXEOL | \
680 ATH9K_INT_RX | \
b5c80475
FF
681 ATH9K_INT_RXLP | \
682 ATH9K_INT_RXHP | \
063d8be3
S
683 ATH9K_INT_TX | \
684 ATH9K_INT_BMISS | \
685 ATH9K_INT_CST | \
ebb8e1d7
VT
686 ATH9K_INT_TSFOOR | \
687 ATH9K_INT_GENTIMER)
063d8be3 688
ff37e337 689 struct ath_softc *sc = dev;
cbe61d8a 690 struct ath_hw *ah = sc->sc_ah;
b5bfc568 691 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
692 enum ath9k_int status;
693 bool sched = false;
694
063d8be3
S
695 /*
696 * The hardware is not ready/present, don't
697 * touch anything. Note this can happen early
698 * on if the IRQ is shared.
699 */
700 if (sc->sc_flags & SC_OP_INVALID)
701 return IRQ_NONE;
ff37e337 702
063d8be3
S
703
704 /* shared irq, not for us */
705
153e080d 706 if (!ath9k_hw_intrpend(ah))
063d8be3 707 return IRQ_NONE;
063d8be3
S
708
709 /*
710 * Figure out the reason(s) for the interrupt. Note
711 * that the hal returns a pseudo-ISR that may include
712 * bits we haven't explicitly enabled so we mask the
713 * value to insure we only process bits we requested.
714 */
715 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 716 status &= ah->imask; /* discard unasked-for bits */
ff37e337 717
063d8be3
S
718 /*
719 * If there are no status bits set, then this interrupt was not
720 * for me (should have been caught above).
721 */
153e080d 722 if (!status)
063d8be3 723 return IRQ_NONE;
ff37e337 724
063d8be3
S
725 /* Cache the status */
726 sc->intrstatus = status;
727
728 if (status & SCHED_INTR)
729 sched = true;
730
731 /*
732 * If a FATAL or RXORN interrupt is received, we have to reset the
733 * chip immediately.
734 */
b5c80475
FF
735 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
736 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
737 goto chip_reset;
738
08578b8f
LR
739 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
740 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
741
742 spin_lock(&common->cc_lock);
743 ath_hw_cycle_counters_update(common);
08578b8f 744 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
745 spin_unlock(&common->cc_lock);
746
08578b8f
LR
747 goto chip_reset;
748 }
749
063d8be3
S
750 if (status & ATH9K_INT_SWBA)
751 tasklet_schedule(&sc->bcon_tasklet);
752
753 if (status & ATH9K_INT_TXURN)
754 ath9k_hw_updatetxtriglevel(ah, true);
755
0682c9b5
RM
756 if (status & ATH9K_INT_RXEOL) {
757 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
758 ath9k_hw_set_interrupts(ah, ah->imask);
b5c80475
FF
759 }
760
063d8be3 761 if (status & ATH9K_INT_MIB) {
ff37e337 762 /*
063d8be3
S
763 * Disable interrupts until we service the MIB
764 * interrupt; otherwise it will continue to
765 * fire.
ff37e337 766 */
4df3071e 767 ath9k_hw_disable_interrupts(ah);
063d8be3
S
768 /*
769 * Let the hal handle the event. We assume
770 * it will clear whatever condition caused
771 * the interrupt.
772 */
88eac2da 773 spin_lock(&common->cc_lock);
bfc472bb 774 ath9k_hw_proc_mib_event(ah);
88eac2da 775 spin_unlock(&common->cc_lock);
4df3071e 776 ath9k_hw_enable_interrupts(ah);
063d8be3 777 }
ff37e337 778
153e080d
VT
779 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
780 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
781 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
782 goto chip_reset;
063d8be3
S
783 /* Clear RxAbort bit so that we can
784 * receive frames */
9ecdef4b 785 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 786 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 787 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 788 }
063d8be3
S
789
790chip_reset:
ff37e337 791
817e11de
S
792 ath_debug_stat_interrupt(sc, status);
793
ff37e337 794 if (sched) {
4df3071e
FF
795 /* turn off every interrupt */
796 ath9k_hw_disable_interrupts(ah);
ff37e337
S
797 tasklet_schedule(&sc->intr_tq);
798 }
799
800 return IRQ_HANDLED;
063d8be3
S
801
802#undef SCHED_INTR
ff37e337
S
803}
804
5595f119 805static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 806{
cbe61d8a 807 struct ath_hw *ah = sc->sc_ah;
c46917bb 808 struct ath_common *common = ath9k_hw_common(ah);
68a89116 809 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 810 int r;
500c064d 811
3cbb5dd7 812 ath9k_ps_wakeup(sc);
6a6733f2 813 spin_lock_bh(&sc->sc_pcu_lock);
e8fe7336 814 atomic_set(&ah->intr_ref_cnt, -1);
6a6733f2 815
84c87dc8 816 ath9k_hw_configpcipowersave(ah, false);
ae8d2858 817
159cd468 818 if (!ah->curchan)
c344c9cb 819 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 820
20bd2a09 821 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 822 if (r) {
3800276a
JP
823 ath_err(common,
824 "Unable to reset channel (%u MHz), reset status %d\n",
825 channel->center_freq, r);
500c064d 826 }
500c064d 827
5048e8c3
RM
828 ath9k_cmn_update_txpow(ah, sc->curtxpow,
829 sc->config.txpowlimit, &sc->curtxpow);
500c064d 830 if (ath_startrecv(sc) != 0) {
3800276a 831 ath_err(common, "Unable to restart recv logic\n");
c2731b81 832 goto out;
500c064d 833 }
500c064d 834 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 835 ath_set_beacon(sc); /* restart beacons */
500c064d
VT
836
837 /* Re-Enable interrupts */
3069168c 838 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 839 ath9k_hw_enable_interrupts(ah);
500c064d
VT
840
841 /* Enable LED */
08fc5c1b 842 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 843 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 844 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 845
68a89116 846 ieee80211_wake_queues(hw);
7e3514fd
VN
847 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
848
c2731b81 849out:
6a6733f2
LR
850 spin_unlock_bh(&sc->sc_pcu_lock);
851
3cbb5dd7 852 ath9k_ps_restore(sc);
500c064d
VT
853}
854
68a89116 855void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 856{
cbe61d8a 857 struct ath_hw *ah = sc->sc_ah;
68a89116 858 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 859 int r;
500c064d 860
3cbb5dd7 861 ath9k_ps_wakeup(sc);
7e3514fd
VN
862 cancel_delayed_work_sync(&sc->hw_pll_work);
863
6a6733f2
LR
864 spin_lock_bh(&sc->sc_pcu_lock);
865
68a89116 866 ieee80211_stop_queues(hw);
500c064d 867
982723df
VN
868 /*
869 * Keep the LED on when the radio is disabled
870 * during idle unassociated state.
871 */
872 if (!sc->ps_idle) {
873 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
874 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
875 }
500c064d
VT
876
877 /* Disable interrupts */
4df3071e 878 ath9k_hw_disable_interrupts(ah);
500c064d 879
043a0405 880 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 881
500c064d
VT
882 ath_stoprecv(sc); /* turn off frame recv */
883 ath_flushrecv(sc); /* flush recv queue */
884
159cd468 885 if (!ah->curchan)
c344c9cb 886 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 887
20bd2a09 888 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 889 if (r) {
3800276a
JP
890 ath_err(ath9k_hw_common(sc->sc_ah),
891 "Unable to reset channel (%u MHz), reset status %d\n",
892 channel->center_freq, r);
500c064d 893 }
500c064d
VT
894
895 ath9k_hw_phy_disable(ah);
5e848f78 896
84c87dc8 897 ath9k_hw_configpcipowersave(ah, true);
6a6733f2
LR
898
899 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 900 ath9k_ps_restore(sc);
500c064d
VT
901}
902
236de514 903static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 904{
cbe61d8a 905 struct ath_hw *ah = sc->sc_ah;
c46917bb 906 struct ath_common *common = ath9k_hw_common(ah);
030bb495 907 struct ieee80211_hw *hw = sc->hw;
ae8d2858 908 int r;
ff37e337 909
cb8d61de
FF
910 sc->hw_busy_count = 0;
911
cf3af748 912 ath9k_debug_samp_bb_mac(sc);
2ab81d4a 913 /* Stop ANI */
05c0be2f 914
2ab81d4a
S
915 del_timer_sync(&common->ani.timer);
916
783cd01e 917 ath9k_ps_wakeup(sc);
6a6733f2 918
cc9c378a
S
919 ieee80211_stop_queues(hw);
920
4df3071e 921 ath9k_hw_disable_interrupts(ah);
043a0405 922 ath_drain_all_txq(sc, retry_tx);
5e848f78 923
ff37e337
S
924 ath_stoprecv(sc);
925 ath_flushrecv(sc);
926
20bd2a09 927 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 928 if (r)
3800276a
JP
929 ath_err(common,
930 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
931
932 if (ath_startrecv(sc) != 0)
3800276a 933 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
934
935 /*
936 * We may be doing a reset in response to a request
937 * that changes the channel so update any state that
938 * might change as a result.
939 */
5048e8c3
RM
940 ath9k_cmn_update_txpow(ah, sc->curtxpow,
941 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 942
52b8ac92 943 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
99e4d43a 944 ath_set_beacon(sc); /* restart beacons */
ff37e337 945
3069168c 946 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 947 ath9k_hw_enable_interrupts(ah);
ff37e337
S
948
949 if (retry_tx) {
950 int i;
951 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
952 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
953 spin_lock_bh(&sc->tx.txq[i].axq_lock);
954 ath_txq_schedule(sc, &sc->tx.txq[i]);
955 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
956 }
957 }
958 }
959
cc9c378a
S
960 ieee80211_wake_queues(hw);
961
2ab81d4a 962 /* Start ANI */
05c0be2f
MSS
963 if (!common->disable_ani)
964 ath_start_ani(common);
965
783cd01e 966 ath9k_ps_restore(sc);
2ab81d4a 967
ae8d2858 968 return r;
ff37e337
S
969}
970
236de514
FF
971void ath_reset_work(struct work_struct *work)
972{
973 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
974
975 spin_lock_bh(&sc->sc_pcu_lock);
976 ath_reset(sc, true);
977 spin_unlock_bh(&sc->sc_pcu_lock);
978}
979
e8cfe9f8
FF
980void ath_hw_check(struct work_struct *work)
981{
982 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
983 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
984 unsigned long flags;
985 int busy;
986
987 ath9k_ps_wakeup(sc);
988 if (ath9k_hw_check_alive(sc->sc_ah))
989 goto out;
990
991 spin_lock_irqsave(&common->cc_lock, flags);
992 busy = ath_update_survey_stats(sc);
993 spin_unlock_irqrestore(&common->cc_lock, flags);
994
995 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
996 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
997 if (busy >= 99) {
998 if (++sc->hw_busy_count >= 3) {
999 spin_lock_bh(&sc->sc_pcu_lock);
1000 ath_reset(sc, true);
1001 spin_unlock_bh(&sc->sc_pcu_lock);
1002 }
1003
1004 } else if (busy >= 0)
1005 sc->hw_busy_count = 0;
1006
1007out:
1008 ath9k_ps_restore(sc);
1009}
1010
1011static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1012{
1013 static int count;
1014 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1015
1016 if (pll_sqsum >= 0x40000) {
1017 count++;
1018 if (count == 3) {
1019 /* Rx is hung for more than 500ms. Reset it */
1020 ath_dbg(common, ATH_DBG_RESET,
1021 "Possible RX hang, resetting");
1022 spin_lock_bh(&sc->sc_pcu_lock);
1023 ath_reset(sc, true);
1024 spin_unlock_bh(&sc->sc_pcu_lock);
1025 count = 0;
1026 }
1027 } else
1028 count = 0;
1029}
1030
1031void ath_hw_pll_work(struct work_struct *work)
1032{
1033 struct ath_softc *sc = container_of(work, struct ath_softc,
1034 hw_pll_work.work);
1035 u32 pll_sqsum;
1036
1037 if (AR_SREV_9485(sc->sc_ah)) {
1038
1039 ath9k_ps_wakeup(sc);
1040 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1041 ath9k_ps_restore(sc);
1042
1043 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1044
1045 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1046 }
1047}
1048
ff37e337
S
1049/**********************/
1050/* mac80211 callbacks */
1051/**********************/
1052
8feceb67 1053static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1054{
9ac58615 1055 struct ath_softc *sc = hw->priv;
af03abec 1056 struct ath_hw *ah = sc->sc_ah;
c46917bb 1057 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1058 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1059 struct ath9k_channel *init_channel;
82880a7c 1060 int r;
f078f209 1061
226afe68
JP
1062 ath_dbg(common, ATH_DBG_CONFIG,
1063 "Starting driver with initial channel: %d MHz\n",
1064 curchan->center_freq);
f078f209 1065
f62d816f
FF
1066 ath9k_ps_wakeup(sc);
1067
141b38b6
S
1068 mutex_lock(&sc->mutex);
1069
8feceb67 1070 /* setup initial channel */
82880a7c 1071 sc->chan_idx = curchan->hw_value;
f078f209 1072
c344c9cb 1073 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1074
1075 /* Reset SERDES registers */
84c87dc8 1076 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
1077
1078 /*
1079 * The basic interface to setting the hardware in a good
1080 * state is ``reset''. On return the hardware is known to
1081 * be powered up and with interrupts disabled. This must
1082 * be followed by initialization of the appropriate bits
1083 * and then setup of the interrupt mask.
1084 */
4bdd1e97 1085 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1086 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1087 if (r) {
3800276a
JP
1088 ath_err(common,
1089 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1090 r, curchan->center_freq);
4bdd1e97 1091 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1092 goto mutex_unlock;
ff37e337 1093 }
ff37e337
S
1094
1095 /*
1096 * This is needed only to setup initial state
1097 * but it's best done after a reset.
1098 */
5048e8c3
RM
1099 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1100 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1101
ff37e337
S
1102 /*
1103 * Setup the hardware after reset:
1104 * The receive engine is set going.
1105 * Frame transmit is handled entirely
1106 * in the frame output path; there's nothing to do
1107 * here except setup the interrupt mask.
1108 */
1109 if (ath_startrecv(sc) != 0) {
3800276a 1110 ath_err(common, "Unable to start recv logic\n");
141b38b6 1111 r = -EIO;
4bdd1e97 1112 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1113 goto mutex_unlock;
f078f209 1114 }
4bdd1e97 1115 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1116
ff37e337 1117 /* Setup our intr mask. */
b5c80475
FF
1118 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1119 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1120 ATH9K_INT_GLOBAL;
1121
1122 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1123 ah->imask |= ATH9K_INT_RXHP |
1124 ATH9K_INT_RXLP |
1125 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1126 else
1127 ah->imask |= ATH9K_INT_RX;
ff37e337 1128
364734fa 1129 ah->imask |= ATH9K_INT_GTT;
ff37e337 1130
af03abec 1131 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1132 ah->imask |= ATH9K_INT_CST;
ff37e337 1133
ff37e337 1134 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1135 sc->sc_ah->is_monitoring = false;
ff37e337
S
1136
1137 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1138 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1139 ath9k_hw_set_interrupts(ah, ah->imask);
b037b693 1140 ath9k_hw_enable_interrupts(ah);
ff37e337 1141
bce048d7 1142 ieee80211_wake_queues(hw);
ff37e337 1143
42935eca 1144 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1145
766ec4a9
LR
1146 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1147 !ah->btcoex_hw.enabled) {
5e197292
LR
1148 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1149 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1150 ath9k_hw_btcoex_enable(ah);
f985ad12 1151
766ec4a9 1152 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1153 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1154 }
1155
8060e169
VT
1156 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1157 common->bus_ops->extn_synch_en(common);
1158
141b38b6
S
1159mutex_unlock:
1160 mutex_unlock(&sc->mutex);
1161
f62d816f
FF
1162 ath9k_ps_restore(sc);
1163
ae8d2858 1164 return r;
f078f209
LR
1165}
1166
7bb45683 1167static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1168{
9ac58615 1169 struct ath_softc *sc = hw->priv;
c46917bb 1170 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1171 struct ath_tx_control txctl;
1bc14880 1172 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1173
96148326 1174 if (sc->ps_enabled) {
dc8c4585
JM
1175 /*
1176 * mac80211 does not set PM field for normal data frames, so we
1177 * need to update that based on the current PS mode.
1178 */
1179 if (ieee80211_is_data(hdr->frame_control) &&
1180 !ieee80211_is_nullfunc(hdr->frame_control) &&
1181 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1182 ath_dbg(common, ATH_DBG_PS,
1183 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1184 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1185 }
1186 }
1187
9a23f9ca
JM
1188 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1189 /*
1190 * We are using PS-Poll and mac80211 can request TX while in
1191 * power save mode. Need to wake up hardware for the TX to be
1192 * completed and if needed, also for RX of buffered frames.
1193 */
9a23f9ca 1194 ath9k_ps_wakeup(sc);
fdf76622
VT
1195 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1196 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1197 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1198 ath_dbg(common, ATH_DBG_PS,
1199 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1200 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1201 } else {
226afe68
JP
1202 ath_dbg(common, ATH_DBG_PS,
1203 "Wake up to complete TX\n");
1b04b930 1204 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1205 }
1206 /*
1207 * The actual restore operation will happen only after
1208 * the sc_flags bit is cleared. We are just dropping
1209 * the ps_usecount here.
1210 */
1211 ath9k_ps_restore(sc);
1212 }
1213
528f0c6b 1214 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1215 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1216
226afe68 1217 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1218
c52f33d0 1219 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1220 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1221 goto exit;
8feceb67
VT
1222 }
1223
7bb45683 1224 return;
528f0c6b
S
1225exit:
1226 dev_kfree_skb_any(skb);
f078f209
LR
1227}
1228
8feceb67 1229static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1230{
9ac58615 1231 struct ath_softc *sc = hw->priv;
af03abec 1232 struct ath_hw *ah = sc->sc_ah;
c46917bb 1233 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1234
4c483817
S
1235 mutex_lock(&sc->mutex);
1236
c94dbff7 1237 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1238 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1239 cancel_work_sync(&sc->paprd_work);
347809fc 1240 cancel_work_sync(&sc->hw_check_work);
236de514 1241 cancel_work_sync(&sc->hw_reset_work);
c94dbff7 1242
9c84b797 1243 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1244 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1245 mutex_unlock(&sc->mutex);
9c84b797
S
1246 return;
1247 }
8feceb67 1248
3867cf6a
S
1249 /* Ensure HW is awake when we try to shut it down. */
1250 ath9k_ps_wakeup(sc);
1251
766ec4a9 1252 if (ah->btcoex_hw.enabled) {
af03abec 1253 ath9k_hw_btcoex_disable(ah);
766ec4a9 1254 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1255 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1256 }
1257
6a6733f2
LR
1258 spin_lock_bh(&sc->sc_pcu_lock);
1259
203043f5
SG
1260 /* prevent tasklets to enable interrupts once we disable them */
1261 ah->imask &= ~ATH9K_INT_GLOBAL;
1262
ff37e337
S
1263 /* make sure h/w will not generate any interrupt
1264 * before setting the invalid flag. */
4df3071e 1265 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1266
1267 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1268 ath_drain_all_txq(sc, false);
ff37e337 1269 ath_stoprecv(sc);
af03abec 1270 ath9k_hw_phy_disable(ah);
6a6733f2 1271 } else
b77f483f 1272 sc->rx.rxlink = NULL;
ff37e337 1273
0d95521e
FF
1274 if (sc->rx.frag) {
1275 dev_kfree_skb_any(sc->rx.frag);
1276 sc->rx.frag = NULL;
1277 }
1278
ff37e337 1279 /* disable HAL and put h/w to sleep */
af03abec 1280 ath9k_hw_disable(ah);
6a6733f2
LR
1281
1282 spin_unlock_bh(&sc->sc_pcu_lock);
1283
203043f5
SG
1284 /* we can now sync irq and kill any running tasklets, since we already
1285 * disabled interrupts and not holding a spin lock */
1286 synchronize_irq(sc->irq);
1287 tasklet_kill(&sc->intr_tq);
1288 tasklet_kill(&sc->bcon_tasklet);
1289
3867cf6a
S
1290 ath9k_ps_restore(sc);
1291
a08e7ade
LR
1292 sc->ps_idle = true;
1293 ath_radio_disable(sc, hw);
ff37e337
S
1294
1295 sc->sc_flags |= SC_OP_INVALID;
500c064d 1296
141b38b6
S
1297 mutex_unlock(&sc->mutex);
1298
226afe68 1299 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1300}
1301
4801416c
BG
1302bool ath9k_uses_beacons(int type)
1303{
1304 switch (type) {
1305 case NL80211_IFTYPE_AP:
1306 case NL80211_IFTYPE_ADHOC:
1307 case NL80211_IFTYPE_MESH_POINT:
1308 return true;
1309 default:
1310 return false;
1311 }
1312}
1313
1314static void ath9k_reclaim_beacon(struct ath_softc *sc,
1315 struct ieee80211_vif *vif)
f078f209 1316{
1ed32e4f 1317 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1318
014cf3bb 1319 ath9k_set_beaconing_status(sc, false);
4801416c 1320 ath_beacon_return(sc, avp);
014cf3bb 1321 ath9k_set_beaconing_status(sc, true);
4801416c 1322 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1323}
1324
1325static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1326{
1327 struct ath9k_vif_iter_data *iter_data = data;
1328 int i;
1329
1330 if (iter_data->hw_macaddr)
1331 for (i = 0; i < ETH_ALEN; i++)
1332 iter_data->mask[i] &=
1333 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1334
1ed32e4f 1335 switch (vif->type) {
4801416c
BG
1336 case NL80211_IFTYPE_AP:
1337 iter_data->naps++;
f078f209 1338 break;
4801416c
BG
1339 case NL80211_IFTYPE_STATION:
1340 iter_data->nstations++;
e51f3eff 1341 break;
05c914fe 1342 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1343 iter_data->nadhocs++;
1344 break;
9cb5412b 1345 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1346 iter_data->nmeshes++;
1347 break;
1348 case NL80211_IFTYPE_WDS:
1349 iter_data->nwds++;
f078f209
LR
1350 break;
1351 default:
4801416c
BG
1352 iter_data->nothers++;
1353 break;
f078f209 1354 }
4801416c 1355}
f078f209 1356
4801416c
BG
1357/* Called with sc->mutex held. */
1358void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1359 struct ieee80211_vif *vif,
1360 struct ath9k_vif_iter_data *iter_data)
1361{
9ac58615 1362 struct ath_softc *sc = hw->priv;
4801416c
BG
1363 struct ath_hw *ah = sc->sc_ah;
1364 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1365
4801416c
BG
1366 /*
1367 * Use the hardware MAC address as reference, the hardware uses it
1368 * together with the BSSID mask when matching addresses.
1369 */
1370 memset(iter_data, 0, sizeof(*iter_data));
1371 iter_data->hw_macaddr = common->macaddr;
1372 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1373
4801416c
BG
1374 if (vif)
1375 ath9k_vif_iter(iter_data, vif->addr, vif);
1376
1377 /* Get list of all active MAC addresses */
4801416c
BG
1378 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1379 iter_data);
4801416c 1380}
8ca21f01 1381
4801416c
BG
1382/* Called with sc->mutex held. */
1383static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1384 struct ieee80211_vif *vif)
1385{
9ac58615 1386 struct ath_softc *sc = hw->priv;
4801416c
BG
1387 struct ath_hw *ah = sc->sc_ah;
1388 struct ath_common *common = ath9k_hw_common(ah);
1389 struct ath9k_vif_iter_data iter_data;
8ca21f01 1390
4801416c 1391 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1392
4801416c
BG
1393 /* Set BSSID mask. */
1394 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1395 ath_hw_setbssidmask(common);
1396
1397 /* Set op-mode & TSF */
1398 if (iter_data.naps > 0) {
3069168c 1399 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1400 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1401 ah->opmode = NL80211_IFTYPE_AP;
1402 } else {
1403 ath9k_hw_set_tsfadjust(ah, 0);
1404 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1405
fd5999cf
JC
1406 if (iter_data.nmeshes)
1407 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1408 else if (iter_data.nwds)
4801416c
BG
1409 ah->opmode = NL80211_IFTYPE_AP;
1410 else if (iter_data.nadhocs)
1411 ah->opmode = NL80211_IFTYPE_ADHOC;
1412 else
1413 ah->opmode = NL80211_IFTYPE_STATION;
1414 }
5640b08e 1415
4e30ffa2
VN
1416 /*
1417 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1418 */
4801416c 1419 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1420 if (ah->config.enable_ani)
1421 ah->imask |= ATH9K_INT_MIB;
3069168c 1422 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1423 } else {
1424 ah->imask &= ~ATH9K_INT_MIB;
1425 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1426 }
1427
3069168c 1428 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1429
4801416c 1430 /* Set up ANI */
2e5ef459 1431 if (iter_data.naps > 0) {
729da390 1432 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1433
1434 if (!common->disable_ani) {
1435 sc->sc_flags |= SC_OP_ANI_RUN;
1436 ath_start_ani(common);
1437 }
1438
f60c49b6
RM
1439 } else {
1440 sc->sc_flags &= ~SC_OP_ANI_RUN;
1441 del_timer_sync(&common->ani.timer);
6c3118e2 1442 }
4801416c 1443}
6f255425 1444
4801416c
BG
1445/* Called with sc->mutex held, vif counts set up properly. */
1446static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1447 struct ieee80211_vif *vif)
1448{
9ac58615 1449 struct ath_softc *sc = hw->priv;
4801416c
BG
1450
1451 ath9k_calculate_summary_state(hw, vif);
1452
1453 if (ath9k_uses_beacons(vif->type)) {
1454 int error;
4801416c
BG
1455 /* This may fail because upper levels do not have beacons
1456 * properly configured yet. That's OK, we assume it
1457 * will be properly configured and then we will be notified
1458 * in the info_changed method and set up beacons properly
1459 * there.
1460 */
014cf3bb 1461 ath9k_set_beaconing_status(sc, false);
9ac58615 1462 error = ath_beacon_alloc(sc, vif);
391bd1c4 1463 if (!error)
4801416c 1464 ath_beacon_config(sc, vif);
014cf3bb 1465 ath9k_set_beaconing_status(sc, true);
4801416c 1466 }
f078f209
LR
1467}
1468
4801416c
BG
1469
1470static int ath9k_add_interface(struct ieee80211_hw *hw,
1471 struct ieee80211_vif *vif)
6b3b991d 1472{
9ac58615 1473 struct ath_softc *sc = hw->priv;
4801416c
BG
1474 struct ath_hw *ah = sc->sc_ah;
1475 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1476 int ret = 0;
6b3b991d 1477
96f372c9 1478 ath9k_ps_wakeup(sc);
4801416c 1479 mutex_lock(&sc->mutex);
6b3b991d 1480
4801416c
BG
1481 switch (vif->type) {
1482 case NL80211_IFTYPE_STATION:
1483 case NL80211_IFTYPE_WDS:
1484 case NL80211_IFTYPE_ADHOC:
1485 case NL80211_IFTYPE_AP:
1486 case NL80211_IFTYPE_MESH_POINT:
1487 break;
1488 default:
1489 ath_err(common, "Interface type %d not yet supported\n",
1490 vif->type);
1491 ret = -EOPNOTSUPP;
1492 goto out;
1493 }
6b3b991d 1494
4801416c
BG
1495 if (ath9k_uses_beacons(vif->type)) {
1496 if (sc->nbcnvifs >= ATH_BCBUF) {
1497 ath_err(common, "Not enough beacon buffers when adding"
1498 " new interface of type: %i\n",
1499 vif->type);
1500 ret = -ENOBUFS;
1501 goto out;
1502 }
1503 }
1504
59575d1c
RM
1505 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1506 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1507 sc->nvifs > 0)) {
4801416c
BG
1508 ath_err(common, "Cannot create ADHOC interface when other"
1509 " interfaces already exist.\n");
1510 ret = -EINVAL;
1511 goto out;
6b3b991d 1512 }
4801416c
BG
1513
1514 ath_dbg(common, ATH_DBG_CONFIG,
1515 "Attach a VIF of type: %d\n", vif->type);
1516
4801416c
BG
1517 sc->nvifs++;
1518
1519 ath9k_do_vif_add_setup(hw, vif);
1520out:
1521 mutex_unlock(&sc->mutex);
96f372c9 1522 ath9k_ps_restore(sc);
4801416c 1523 return ret;
6b3b991d
RM
1524}
1525
1526static int ath9k_change_interface(struct ieee80211_hw *hw,
1527 struct ieee80211_vif *vif,
1528 enum nl80211_iftype new_type,
1529 bool p2p)
1530{
9ac58615 1531 struct ath_softc *sc = hw->priv;
6b3b991d 1532 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1533 int ret = 0;
6b3b991d
RM
1534
1535 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1536 mutex_lock(&sc->mutex);
96f372c9 1537 ath9k_ps_wakeup(sc);
6b3b991d 1538
4801416c
BG
1539 /* See if new interface type is valid. */
1540 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1541 (sc->nvifs > 1)) {
1542 ath_err(common, "When using ADHOC, it must be the only"
1543 " interface.\n");
1544 ret = -EINVAL;
1545 goto out;
1546 }
1547
1548 if (ath9k_uses_beacons(new_type) &&
1549 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1550 if (sc->nbcnvifs >= ATH_BCBUF) {
1551 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1552 ret = -ENOBUFS;
1553 goto out;
6b3b991d 1554 }
6b3b991d 1555 }
4801416c
BG
1556
1557 /* Clean up old vif stuff */
1558 if (ath9k_uses_beacons(vif->type))
1559 ath9k_reclaim_beacon(sc, vif);
1560
1561 /* Add new settings */
6b3b991d
RM
1562 vif->type = new_type;
1563 vif->p2p = p2p;
1564
4801416c 1565 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1566out:
96f372c9 1567 ath9k_ps_restore(sc);
6b3b991d 1568 mutex_unlock(&sc->mutex);
6dab55bf 1569 return ret;
6b3b991d
RM
1570}
1571
8feceb67 1572static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1573 struct ieee80211_vif *vif)
f078f209 1574{
9ac58615 1575 struct ath_softc *sc = hw->priv;
c46917bb 1576 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1577
226afe68 1578 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1579
96f372c9 1580 ath9k_ps_wakeup(sc);
141b38b6
S
1581 mutex_lock(&sc->mutex);
1582
4801416c 1583 sc->nvifs--;
580f0b8a 1584
8feceb67 1585 /* Reclaim beacon resources */
4801416c 1586 if (ath9k_uses_beacons(vif->type))
6b3b991d 1587 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1588
4801416c 1589 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1590
1591 mutex_unlock(&sc->mutex);
96f372c9 1592 ath9k_ps_restore(sc);
f078f209
LR
1593}
1594
fbab7390 1595static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1596{
3069168c
PR
1597 struct ath_hw *ah = sc->sc_ah;
1598
3f7c5c10 1599 sc->ps_enabled = true;
3069168c
PR
1600 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1601 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1602 ah->imask |= ATH9K_INT_TIM_TIMER;
1603 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1604 }
fdf76622 1605 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1606 }
3f7c5c10
SB
1607}
1608
845d708e
SB
1609static void ath9k_disable_ps(struct ath_softc *sc)
1610{
1611 struct ath_hw *ah = sc->sc_ah;
1612
1613 sc->ps_enabled = false;
1614 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1615 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1616 ath9k_hw_setrxabort(ah, 0);
1617 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1618 PS_WAIT_FOR_CAB |
1619 PS_WAIT_FOR_PSPOLL_DATA |
1620 PS_WAIT_FOR_TX_ACK);
1621 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1622 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1623 ath9k_hw_set_interrupts(ah, ah->imask);
1624 }
1625 }
1626
1627}
1628
e8975581 1629static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1630{
9ac58615 1631 struct ath_softc *sc = hw->priv;
3430098a
FF
1632 struct ath_hw *ah = sc->sc_ah;
1633 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1634 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1635 bool disable_radio = false;
f078f209 1636
aa33de09 1637 mutex_lock(&sc->mutex);
141b38b6 1638
194b7c13
LR
1639 /*
1640 * Leave this as the first check because we need to turn on the
1641 * radio if it was disabled before prior to processing the rest
1642 * of the changes. Likewise we must only disable the radio towards
1643 * the end.
1644 */
64839170 1645 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1646 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1647 if (!sc->ps_idle) {
68a89116 1648 ath_radio_enable(sc, hw);
226afe68
JP
1649 ath_dbg(common, ATH_DBG_CONFIG,
1650 "not-idle: enabling radio\n");
7545daf4
FF
1651 } else {
1652 disable_radio = true;
64839170
LR
1653 }
1654 }
1655
e7824a50
LR
1656 /*
1657 * We just prepare to enable PS. We have to wait until our AP has
1658 * ACK'd our null data frame to disable RX otherwise we'll ignore
1659 * those ACKs and end up retransmitting the same null data frames.
1660 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1661 */
3cbb5dd7 1662 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1663 unsigned long flags;
1664 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1665 if (conf->flags & IEEE80211_CONF_PS)
1666 ath9k_enable_ps(sc);
845d708e
SB
1667 else
1668 ath9k_disable_ps(sc);
8ab2cd09 1669 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1670 }
1671
199afd9d
S
1672 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1673 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1674 ath_dbg(common, ATH_DBG_CONFIG,
1675 "Monitor mode is enabled\n");
5f841b41
RM
1676 sc->sc_ah->is_monitoring = true;
1677 } else {
226afe68
JP
1678 ath_dbg(common, ATH_DBG_CONFIG,
1679 "Monitor mode is disabled\n");
5f841b41 1680 sc->sc_ah->is_monitoring = false;
199afd9d
S
1681 }
1682 }
1683
4797938c 1684 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1685 struct ieee80211_channel *curchan = hw->conf.channel;
e338a85e 1686 struct ath9k_channel old_chan;
5f8e077c 1687 int pos = curchan->hw_value;
3430098a
FF
1688 int old_pos = -1;
1689 unsigned long flags;
1690
1691 if (ah->curchan)
1692 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1693
5ee08656
FF
1694 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1695 sc->sc_flags |= SC_OP_OFFCHANNEL;
1696 else
1697 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1698
8c79a610
BG
1699 ath_dbg(common, ATH_DBG_CONFIG,
1700 "Set channel: %d MHz type: %d\n",
1701 curchan->center_freq, conf->channel_type);
f078f209 1702
3430098a
FF
1703 /* update survey stats for the old channel before switching */
1704 spin_lock_irqsave(&common->cc_lock, flags);
1705 ath_update_survey_stats(sc);
1706 spin_unlock_irqrestore(&common->cc_lock, flags);
1707
e338a85e
RM
1708 /*
1709 * Preserve the current channel values, before updating
1710 * the same channel
1711 */
1712 if (old_pos == pos) {
1713 memcpy(&old_chan, &sc->sc_ah->channels[pos],
1714 sizeof(struct ath9k_channel));
1715 ah->curchan = &old_chan;
1716 }
1717
1718 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1719 curchan, conf->channel_type);
1720
3430098a
FF
1721 /*
1722 * If the operating channel changes, change the survey in-use flags
1723 * along with it.
1724 * Reset the survey data for the new channel, unless we're switching
1725 * back to the operating channel from an off-channel operation.
1726 */
1727 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1728 sc->cur_survey != &sc->survey[pos]) {
1729
1730 if (sc->cur_survey)
1731 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1732
1733 sc->cur_survey = &sc->survey[pos];
1734
1735 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1736 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1737 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1738 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1739 }
1740
0e2dedf9 1741 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1742 ath_err(common, "Unable to set channel\n");
aa33de09 1743 mutex_unlock(&sc->mutex);
e11602b7
S
1744 return -EINVAL;
1745 }
3430098a
FF
1746
1747 /*
1748 * The most recent snapshot of channel->noisefloor for the old
1749 * channel is only available after the hardware reset. Copy it to
1750 * the survey stats now.
1751 */
1752 if (old_pos >= 0)
1753 ath_update_survey_nf(sc, old_pos);
094d05dc 1754 }
f078f209 1755
c9f6a656 1756 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1757 ath_dbg(common, ATH_DBG_CONFIG,
1758 "Set power: %d\n", conf->power_level);
17d7904d 1759 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1760 ath9k_ps_wakeup(sc);
5048e8c3
RM
1761 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1762 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1763 ath9k_ps_restore(sc);
c9f6a656 1764 }
f078f209 1765
64839170 1766 if (disable_radio) {
226afe68 1767 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1768 ath_radio_disable(sc, hw);
64839170
LR
1769 }
1770
aa33de09 1771 mutex_unlock(&sc->mutex);
141b38b6 1772
f078f209
LR
1773 return 0;
1774}
1775
8feceb67
VT
1776#define SUPPORTED_FILTERS \
1777 (FIF_PROMISC_IN_BSS | \
1778 FIF_ALLMULTI | \
1779 FIF_CONTROL | \
af6a3fc7 1780 FIF_PSPOLL | \
8feceb67
VT
1781 FIF_OTHER_BSS | \
1782 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1783 FIF_PROBE_REQ | \
8feceb67 1784 FIF_FCSFAIL)
c83be688 1785
8feceb67
VT
1786/* FIXME: sc->sc_full_reset ? */
1787static void ath9k_configure_filter(struct ieee80211_hw *hw,
1788 unsigned int changed_flags,
1789 unsigned int *total_flags,
3ac64bee 1790 u64 multicast)
8feceb67 1791{
9ac58615 1792 struct ath_softc *sc = hw->priv;
8feceb67 1793 u32 rfilt;
f078f209 1794
8feceb67
VT
1795 changed_flags &= SUPPORTED_FILTERS;
1796 *total_flags &= SUPPORTED_FILTERS;
f078f209 1797
b77f483f 1798 sc->rx.rxfilter = *total_flags;
aa68aeaa 1799 ath9k_ps_wakeup(sc);
8feceb67
VT
1800 rfilt = ath_calcrxfilter(sc);
1801 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1802 ath9k_ps_restore(sc);
f078f209 1803
226afe68
JP
1804 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1805 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1806}
f078f209 1807
4ca77860
JB
1808static int ath9k_sta_add(struct ieee80211_hw *hw,
1809 struct ieee80211_vif *vif,
1810 struct ieee80211_sta *sta)
8feceb67 1811{
9ac58615 1812 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1813 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1814 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1815 struct ieee80211_key_conf ps_key = { };
f078f209 1816
4ca77860 1817 ath_node_attach(sc, sta);
f59a59fe
FF
1818
1819 if (vif->type != NL80211_IFTYPE_AP &&
1820 vif->type != NL80211_IFTYPE_AP_VLAN)
1821 return 0;
1822
93ae2dd2 1823 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1824
1825 return 0;
1826}
1827
93ae2dd2
FF
1828static void ath9k_del_ps_key(struct ath_softc *sc,
1829 struct ieee80211_vif *vif,
1830 struct ieee80211_sta *sta)
1831{
1832 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1833 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1834 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1835
1836 if (!an->ps_key)
1837 return;
1838
1839 ath_key_delete(common, &ps_key);
1840}
1841
4ca77860
JB
1842static int ath9k_sta_remove(struct ieee80211_hw *hw,
1843 struct ieee80211_vif *vif,
1844 struct ieee80211_sta *sta)
1845{
9ac58615 1846 struct ath_softc *sc = hw->priv;
4ca77860 1847
93ae2dd2 1848 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1849 ath_node_detach(sc, sta);
1850
1851 return 0;
f078f209
LR
1852}
1853
5519541d
FF
1854static void ath9k_sta_notify(struct ieee80211_hw *hw,
1855 struct ieee80211_vif *vif,
1856 enum sta_notify_cmd cmd,
1857 struct ieee80211_sta *sta)
1858{
1859 struct ath_softc *sc = hw->priv;
1860 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1861
1862 switch (cmd) {
1863 case STA_NOTIFY_SLEEP:
1864 an->sleeping = true;
1865 if (ath_tx_aggr_sleep(sc, an))
1866 ieee80211_sta_set_tim(sta);
1867 break;
1868 case STA_NOTIFY_AWAKE:
1869 an->sleeping = false;
1870 ath_tx_aggr_wakeup(sc, an);
1871 break;
1872 }
1873}
1874
141b38b6 1875static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1876 const struct ieee80211_tx_queue_params *params)
f078f209 1877{
9ac58615 1878 struct ath_softc *sc = hw->priv;
c46917bb 1879 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1880 struct ath_txq *txq;
8feceb67 1881 struct ath9k_tx_queue_info qi;
066dae93 1882 int ret = 0;
f078f209 1883
8feceb67
VT
1884 if (queue >= WME_NUM_AC)
1885 return 0;
f078f209 1886
066dae93
FF
1887 txq = sc->tx.txq_map[queue];
1888
96f372c9 1889 ath9k_ps_wakeup(sc);
141b38b6
S
1890 mutex_lock(&sc->mutex);
1891
1ffb0610
S
1892 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1893
8feceb67
VT
1894 qi.tqi_aifs = params->aifs;
1895 qi.tqi_cwmin = params->cw_min;
1896 qi.tqi_cwmax = params->cw_max;
1897 qi.tqi_burstTime = params->txop;
f078f209 1898
226afe68
JP
1899 ath_dbg(common, ATH_DBG_CONFIG,
1900 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1901 queue, txq->axq_qnum, params->aifs, params->cw_min,
1902 params->cw_max, params->txop);
f078f209 1903
066dae93 1904 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1905 if (ret)
3800276a 1906 ath_err(common, "TXQ Update failed\n");
f078f209 1907
94db2936 1908 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1909 if (queue == WME_AC_BE && !ret)
94db2936
VN
1910 ath_beaconq_config(sc);
1911
141b38b6 1912 mutex_unlock(&sc->mutex);
96f372c9 1913 ath9k_ps_restore(sc);
141b38b6 1914
8feceb67
VT
1915 return ret;
1916}
f078f209 1917
8feceb67
VT
1918static int ath9k_set_key(struct ieee80211_hw *hw,
1919 enum set_key_cmd cmd,
dc822b5d
JB
1920 struct ieee80211_vif *vif,
1921 struct ieee80211_sta *sta,
8feceb67
VT
1922 struct ieee80211_key_conf *key)
1923{
9ac58615 1924 struct ath_softc *sc = hw->priv;
c46917bb 1925 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1926 int ret = 0;
f078f209 1927
3e6109c5 1928 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1929 return -ENOSPC;
1930
cfdc9a8b
JM
1931 if (vif->type == NL80211_IFTYPE_ADHOC &&
1932 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1933 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1934 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1935 /*
1936 * For now, disable hw crypto for the RSN IBSS group keys. This
1937 * could be optimized in the future to use a modified key cache
1938 * design to support per-STA RX GTK, but until that gets
1939 * implemented, use of software crypto for group addressed
1940 * frames is a acceptable to allow RSN IBSS to be used.
1941 */
1942 return -EOPNOTSUPP;
1943 }
1944
141b38b6 1945 mutex_lock(&sc->mutex);
3cbb5dd7 1946 ath9k_ps_wakeup(sc);
226afe68 1947 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1948
8feceb67
VT
1949 switch (cmd) {
1950 case SET_KEY:
93ae2dd2
FF
1951 if (sta)
1952 ath9k_del_ps_key(sc, vif, sta);
1953
040e539e 1954 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1955 if (ret >= 0) {
1956 key->hw_key_idx = ret;
8feceb67
VT
1957 /* push IV and Michael MIC generation to stack */
1958 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1959 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1960 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1961 if (sc->sc_ah->sw_mgmt_crypto &&
1962 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1963 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1964 ret = 0;
8feceb67
VT
1965 }
1966 break;
1967 case DISABLE_KEY:
040e539e 1968 ath_key_delete(common, key);
8feceb67
VT
1969 break;
1970 default:
1971 ret = -EINVAL;
1972 }
f078f209 1973
3cbb5dd7 1974 ath9k_ps_restore(sc);
141b38b6
S
1975 mutex_unlock(&sc->mutex);
1976
8feceb67
VT
1977 return ret;
1978}
4f5ef75b
RM
1979static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1980{
1981 struct ath_softc *sc = data;
1982 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1983 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1984 struct ath_vif *avp = (void *)vif->drv_priv;
1985
2e5ef459
RM
1986 /*
1987 * Skip iteration if primary station vif's bss info
1988 * was not changed
1989 */
1990 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1991 return;
1992
1993 if (bss_conf->assoc) {
1994 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1995 avp->primary_sta_vif = true;
4f5ef75b
RM
1996 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1997 common->curaid = bss_conf->aid;
1998 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1999 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
2000 "Bss Info ASSOC %d, bssid: %pM\n",
2001 bss_conf->aid, common->curbssid);
2e5ef459
RM
2002 ath_beacon_config(sc, vif);
2003 /*
2004 * Request a re-configuration of Beacon related timers
2005 * on the receipt of the first Beacon frame (i.e.,
2006 * after time sync with the AP).
2007 */
2008 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
2009 /* Reset rssi stats */
2010 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
2011 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 2012
05c0be2f
MSS
2013 if (!common->disable_ani) {
2014 sc->sc_flags |= SC_OP_ANI_RUN;
2015 ath_start_ani(common);
2016 }
2017
4f5ef75b
RM
2018 }
2019}
2020
2021static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2022{
2023 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2024 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2025 struct ath_vif *avp = (void *)vif->drv_priv;
2026
2e5ef459
RM
2027 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2028 return;
2029
4f5ef75b
RM
2030 /* Reconfigure bss info */
2031 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
2032 ath_dbg(common, ATH_DBG_CONFIG,
2033 "Bss Info DISASSOC %d, bssid %pM\n",
2034 common->curaid, common->curbssid);
2035 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2036 avp->primary_sta_vif = false;
2037 memset(common->curbssid, 0, ETH_ALEN);
2038 common->curaid = 0;
2039 }
2040
2041 ieee80211_iterate_active_interfaces_atomic(
2042 sc->hw, ath9k_bss_iter, sc);
2043
2044 /*
2045 * None of station vifs are associated.
2046 * Clear bssid & aid
2047 */
2e5ef459 2048 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2049 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2050 /* Stop ANI */
2051 sc->sc_flags &= ~SC_OP_ANI_RUN;
2052 del_timer_sync(&common->ani.timer);
2053 }
4f5ef75b 2054}
f078f209 2055
8feceb67
VT
2056static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2057 struct ieee80211_vif *vif,
2058 struct ieee80211_bss_conf *bss_conf,
2059 u32 changed)
2060{
9ac58615 2061 struct ath_softc *sc = hw->priv;
2d0ddec5 2062 struct ath_hw *ah = sc->sc_ah;
1510718d 2063 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2064 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2065 int slottime;
c6089ccc 2066 int error;
f078f209 2067
96f372c9 2068 ath9k_ps_wakeup(sc);
141b38b6
S
2069 mutex_lock(&sc->mutex);
2070
c6089ccc 2071 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2072 ath9k_config_bss(sc, vif);
2d0ddec5 2073
226afe68
JP
2074 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2075 common->curbssid, common->curaid);
c6089ccc 2076 }
2d0ddec5 2077
2e5ef459
RM
2078 if (changed & BSS_CHANGED_IBSS) {
2079 /* There can be only one vif available */
2080 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2081 common->curaid = bss_conf->aid;
2082 ath9k_hw_write_associd(sc->sc_ah);
2083
2084 if (bss_conf->ibss_joined) {
2085 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2086
2087 if (!common->disable_ani) {
2088 sc->sc_flags |= SC_OP_ANI_RUN;
2089 ath_start_ani(common);
2090 }
2091
2e5ef459
RM
2092 } else {
2093 sc->sc_flags &= ~SC_OP_ANI_RUN;
2094 del_timer_sync(&common->ani.timer);
2095 }
2096 }
2097
c6089ccc
S
2098 /* Enable transmission of beacons (AP, IBSS, MESH) */
2099 if ((changed & BSS_CHANGED_BEACON) ||
2100 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2101 ath9k_set_beaconing_status(sc, false);
9ac58615 2102 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2103 if (!error)
2104 ath_beacon_config(sc, vif);
014cf3bb 2105 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2106 }
2107
2108 if (changed & BSS_CHANGED_ERP_SLOT) {
2109 if (bss_conf->use_short_slot)
2110 slottime = 9;
2111 else
2112 slottime = 20;
2113 if (vif->type == NL80211_IFTYPE_AP) {
2114 /*
2115 * Defer update, so that connected stations can adjust
2116 * their settings at the same time.
2117 * See beacon.c for more details
2118 */
2119 sc->beacon.slottime = slottime;
2120 sc->beacon.updateslot = UPDATE;
2121 } else {
2122 ah->slottime = slottime;
2123 ath9k_hw_init_global_settings(ah);
2124 }
2d0ddec5
JB
2125 }
2126
c6089ccc 2127 /* Disable transmission of beacons */
014cf3bb
RM
2128 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2129 !bss_conf->enable_beacon) {
2130 ath9k_set_beaconing_status(sc, false);
2131 avp->is_bslot_active = false;
2132 ath9k_set_beaconing_status(sc, true);
2133 }
2d0ddec5 2134
c6089ccc 2135 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2136 /*
2137 * In case of AP mode, the HW TSF has to be reset
2138 * when the beacon interval changes.
2139 */
2140 if (vif->type == NL80211_IFTYPE_AP) {
2141 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2142 ath9k_set_beaconing_status(sc, false);
9ac58615 2143 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2144 if (!error)
2145 ath_beacon_config(sc, vif);
014cf3bb 2146 ath9k_set_beaconing_status(sc, true);
99e4d43a 2147 } else
c6089ccc 2148 ath_beacon_config(sc, vif);
2d0ddec5
JB
2149 }
2150
8feceb67 2151 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2152 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2153 bss_conf->use_short_preamble);
8feceb67
VT
2154 if (bss_conf->use_short_preamble)
2155 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2156 else
2157 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2158 }
f078f209 2159
8feceb67 2160 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2161 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2162 bss_conf->use_cts_prot);
8feceb67
VT
2163 if (bss_conf->use_cts_prot &&
2164 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2165 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2166 else
2167 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2168 }
f078f209 2169
141b38b6 2170 mutex_unlock(&sc->mutex);
96f372c9 2171 ath9k_ps_restore(sc);
8feceb67 2172}
f078f209 2173
8feceb67
VT
2174static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2175{
9ac58615 2176 struct ath_softc *sc = hw->priv;
8feceb67 2177 u64 tsf;
f078f209 2178
141b38b6 2179 mutex_lock(&sc->mutex);
9abbfb27 2180 ath9k_ps_wakeup(sc);
141b38b6 2181 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2182 ath9k_ps_restore(sc);
141b38b6 2183 mutex_unlock(&sc->mutex);
f078f209 2184
8feceb67
VT
2185 return tsf;
2186}
f078f209 2187
3b5d665b
AF
2188static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2189{
9ac58615 2190 struct ath_softc *sc = hw->priv;
3b5d665b 2191
141b38b6 2192 mutex_lock(&sc->mutex);
9abbfb27 2193 ath9k_ps_wakeup(sc);
141b38b6 2194 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2195 ath9k_ps_restore(sc);
141b38b6 2196 mutex_unlock(&sc->mutex);
3b5d665b
AF
2197}
2198
8feceb67
VT
2199static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2200{
9ac58615 2201 struct ath_softc *sc = hw->priv;
c83be688 2202
141b38b6 2203 mutex_lock(&sc->mutex);
21526d57
LR
2204
2205 ath9k_ps_wakeup(sc);
141b38b6 2206 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2207 ath9k_ps_restore(sc);
2208
141b38b6 2209 mutex_unlock(&sc->mutex);
8feceb67 2210}
f078f209 2211
8feceb67 2212static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2213 struct ieee80211_vif *vif,
141b38b6
S
2214 enum ieee80211_ampdu_mlme_action action,
2215 struct ieee80211_sta *sta,
0b01f030 2216 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2217{
9ac58615 2218 struct ath_softc *sc = hw->priv;
8feceb67 2219 int ret = 0;
f078f209 2220
85ad181e
JB
2221 local_bh_disable();
2222
8feceb67
VT
2223 switch (action) {
2224 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2225 if (!(sc->sc_flags & SC_OP_RXAGGR))
2226 ret = -ENOTSUPP;
8feceb67
VT
2227 break;
2228 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2229 break;
2230 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2231 if (!(sc->sc_flags & SC_OP_TXAGGR))
2232 return -EOPNOTSUPP;
2233
8b685ba9 2234 ath9k_ps_wakeup(sc);
231c3a1f
FF
2235 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2236 if (!ret)
2237 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2238 ath9k_ps_restore(sc);
8feceb67
VT
2239 break;
2240 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2241 ath9k_ps_wakeup(sc);
f83da965 2242 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2243 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2244 ath9k_ps_restore(sc);
8feceb67 2245 break;
b1720231 2246 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2247 ath9k_ps_wakeup(sc);
8469cdef 2248 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2249 ath9k_ps_restore(sc);
8469cdef 2250 break;
8feceb67 2251 default:
3800276a 2252 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2253 }
2254
85ad181e
JB
2255 local_bh_enable();
2256
8feceb67 2257 return ret;
f078f209
LR
2258}
2259
62dad5b0
BP
2260static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2261 struct survey_info *survey)
2262{
9ac58615 2263 struct ath_softc *sc = hw->priv;
3430098a 2264 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2265 struct ieee80211_supported_band *sband;
3430098a
FF
2266 struct ieee80211_channel *chan;
2267 unsigned long flags;
2268 int pos;
2269
2270 spin_lock_irqsave(&common->cc_lock, flags);
2271 if (idx == 0)
2272 ath_update_survey_stats(sc);
39162dbe
FF
2273
2274 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2275 if (sband && idx >= sband->n_channels) {
2276 idx -= sband->n_channels;
2277 sband = NULL;
2278 }
62dad5b0 2279
39162dbe
FF
2280 if (!sband)
2281 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2282
3430098a
FF
2283 if (!sband || idx >= sband->n_channels) {
2284 spin_unlock_irqrestore(&common->cc_lock, flags);
2285 return -ENOENT;
4f1a5a4b 2286 }
62dad5b0 2287
3430098a
FF
2288 chan = &sband->channels[idx];
2289 pos = chan->hw_value;
2290 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2291 survey->channel = chan;
2292 spin_unlock_irqrestore(&common->cc_lock, flags);
2293
62dad5b0
BP
2294 return 0;
2295}
2296
e239d859
FF
2297static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2298{
9ac58615 2299 struct ath_softc *sc = hw->priv;
e239d859
FF
2300 struct ath_hw *ah = sc->sc_ah;
2301
2302 mutex_lock(&sc->mutex);
2303 ah->coverage_class = coverage_class;
2304 ath9k_hw_init_global_settings(ah);
2305 mutex_unlock(&sc->mutex);
2306}
2307
69081624
VT
2308static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2309{
69081624 2310 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2311 struct ath_hw *ah = sc->sc_ah;
2312 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2313 int timeout = 200; /* ms */
2314 int i, j;
2f6fc351 2315 bool drain_txq;
69081624
VT
2316
2317 mutex_lock(&sc->mutex);
69081624
VT
2318 cancel_delayed_work_sync(&sc->tx_complete_work);
2319
99aa55b6
MSS
2320 if (sc->sc_flags & SC_OP_INVALID) {
2321 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2322 mutex_unlock(&sc->mutex);
2323 return;
2324 }
2325
86271e46
FF
2326 if (drop)
2327 timeout = 1;
69081624 2328
86271e46 2329 for (j = 0; j < timeout; j++) {
108697c4 2330 bool npend = false;
86271e46
FF
2331
2332 if (j)
2333 usleep_range(1000, 2000);
69081624 2334
86271e46
FF
2335 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2336 if (!ATH_TXQ_SETUP(sc, i))
2337 continue;
2338
108697c4
MSS
2339 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2340
2341 if (npend)
2342 break;
69081624 2343 }
86271e46
FF
2344
2345 if (!npend)
2346 goto out;
69081624
VT
2347 }
2348
51513906 2349 ath9k_ps_wakeup(sc);
2f6fc351
RM
2350 spin_lock_bh(&sc->sc_pcu_lock);
2351 drain_txq = ath_drain_all_txq(sc, false);
2f6fc351 2352 if (!drain_txq)
69081624 2353 ath_reset(sc, false);
f6b4e4d4 2354 spin_unlock_bh(&sc->sc_pcu_lock);
51513906 2355 ath9k_ps_restore(sc);
d78f4b3e
SB
2356 ieee80211_wake_queues(hw);
2357
86271e46 2358out:
69081624
VT
2359 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2360 mutex_unlock(&sc->mutex);
2361}
2362
15b91e83
VN
2363static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2364{
2365 struct ath_softc *sc = hw->priv;
2366 int i;
2367
2368 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2369 if (!ATH_TXQ_SETUP(sc, i))
2370 continue;
2371
2372 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2373 return true;
2374 }
2375 return false;
2376}
2377
5595f119 2378static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2379{
2380 struct ath_softc *sc = hw->priv;
2381 struct ath_hw *ah = sc->sc_ah;
2382 struct ieee80211_vif *vif;
2383 struct ath_vif *avp;
2384 struct ath_buf *bf;
2385 struct ath_tx_status ts;
2386 int status;
2387
2388 vif = sc->beacon.bslot[0];
2389 if (!vif)
2390 return 0;
2391
2392 avp = (void *)vif->drv_priv;
2393 if (!avp->is_bslot_active)
2394 return 0;
2395
2396 if (!sc->beacon.tx_processed) {
2397 tasklet_disable(&sc->bcon_tasklet);
2398
2399 bf = avp->av_bcbuf;
2400 if (!bf || !bf->bf_mpdu)
2401 goto skip;
2402
2403 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2404 if (status == -EINPROGRESS)
2405 goto skip;
2406
2407 sc->beacon.tx_processed = true;
2408 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2409
2410skip:
2411 tasklet_enable(&sc->bcon_tasklet);
2412 }
2413
2414 return sc->beacon.tx_last;
2415}
2416
52c94f41
MSS
2417static int ath9k_get_stats(struct ieee80211_hw *hw,
2418 struct ieee80211_low_level_stats *stats)
2419{
2420 struct ath_softc *sc = hw->priv;
2421 struct ath_hw *ah = sc->sc_ah;
2422 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2423
2424 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2425 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2426 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2427 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2428 return 0;
2429}
2430
6baff7f9 2431struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2432 .tx = ath9k_tx,
2433 .start = ath9k_start,
2434 .stop = ath9k_stop,
2435 .add_interface = ath9k_add_interface,
6b3b991d 2436 .change_interface = ath9k_change_interface,
8feceb67
VT
2437 .remove_interface = ath9k_remove_interface,
2438 .config = ath9k_config,
8feceb67 2439 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2440 .sta_add = ath9k_sta_add,
2441 .sta_remove = ath9k_sta_remove,
5519541d 2442 .sta_notify = ath9k_sta_notify,
8feceb67 2443 .conf_tx = ath9k_conf_tx,
8feceb67 2444 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2445 .set_key = ath9k_set_key,
8feceb67 2446 .get_tsf = ath9k_get_tsf,
3b5d665b 2447 .set_tsf = ath9k_set_tsf,
8feceb67 2448 .reset_tsf = ath9k_reset_tsf,
4233df6b 2449 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2450 .get_survey = ath9k_get_survey,
3b319aae 2451 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2452 .set_coverage_class = ath9k_set_coverage_class,
69081624 2453 .flush = ath9k_flush,
15b91e83 2454 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2455 .tx_last_beacon = ath9k_tx_last_beacon,
2456 .get_stats = ath9k_get_stats,
8feceb67 2457};