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ath9k: make sure main_rssi is positive
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S		 22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT		 57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
65 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
66 pending = !list_empty(&txq->txq_fifo_pending);
67
68 spin_unlock_bh(&txq->axq_lock);
69 return pending;
70}
71
55624204 72bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 73{
74 unsigned long flags;
75 bool ret;
76
9ecdef4b
LR		 77 spin_lock_irqsave(&sc->sc_pm_lock, flags);
78 ret = ath9k_hw_setpower(sc->sc_ah, mode);
79 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 80
81 return ret;
82}
83
a91d75ae
LR		 84void ath9k_ps_wakeup(struct ath_softc *sc)
85{
898c914a 86 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 87 unsigned long flags;
fbb078fc 88 enum ath9k_power_mode power_mode;
a91d75ae
LR		 89
90 spin_lock_irqsave(&sc->sc_pm_lock, flags);
91 if (++sc->ps_usecount != 1)
92 goto unlock;
93
fbb078fc 94 power_mode = sc->sc_ah->power_mode;
9ecdef4b 95 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 96
898c914a
FF		 97 /*
98 * While the hardware is asleep, the cycle counters contain no
99 * useful data. Better clear them now so that they don't mess up
100 * survey data results.
101 */
fbb078fc
FF		 102 if (power_mode != ATH9K_PM_AWAKE) {
103 spin_lock(&common->cc_lock);
104 ath_hw_cycle_counters_update(common);
105 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
106 spin_unlock(&common->cc_lock);
107 }
898c914a 108
a91d75ae
LR		 109 unlock:
110 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
111}
112
113void ath9k_ps_restore(struct ath_softc *sc)
114{
898c914a 115 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR		 116 unsigned long flags;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (--sc->ps_usecount != 0)
120 goto unlock;
121
898c914a
FF		 122 spin_lock(&common->cc_lock);
123 ath_hw_cycle_counters_update(common);
124 spin_unlock(&common->cc_lock);
125
1dbfd9d4
VN		 126 if (sc->ps_idle)
127 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
128 else if (sc->ps_enabled &&
129 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S		 130 PS_WAIT_FOR_CAB |
131 PS_WAIT_FOR_PSPOLL_DATA |
132 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 133 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 134
135 unlock:
136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
137}
138
5ee08656
FF		 139static void ath_start_ani(struct ath_common *common)
140{
141 struct ath_hw *ah = common->ah;
142 unsigned long timestamp = jiffies_to_msecs(jiffies);
143 struct ath_softc *sc = (struct ath_softc *) common->priv;
144
145 if (!(sc->sc_flags & SC_OP_ANI_RUN))
146 return;
147
148 if (sc->sc_flags & SC_OP_OFFCHANNEL)
149 return;
150
151 common->ani.longcal_timer = timestamp;
152 common->ani.shortcal_timer = timestamp;
153 common->ani.checkani_timer = timestamp;
154
155 mod_timer(&common->ani.timer,
156 jiffies +
157 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
158}
159
3430098a
FF		 160static void ath_update_survey_nf(struct ath_softc *sc, int channel)
161{
162 struct ath_hw *ah = sc->sc_ah;
163 struct ath9k_channel *chan = &ah->channels[channel];
164 struct survey_info *survey = &sc->survey[channel];
165
166 if (chan->noisefloor) {
167 survey->filled |= SURVEY_INFO_NOISE_DBM;
168 survey->noise = chan->noisefloor;
169 }
170}
171
cb8d61de
FF		 172/*
173 * Updates the survey statistics and returns the busy time since last
174 * update in %, if the measurement duration was long enough for the
175 * result to be useful, -1 otherwise.
176 */
177static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF		 178{
179 struct ath_hw *ah = sc->sc_ah;
180 struct ath_common *common = ath9k_hw_common(ah);
181 int pos = ah->curchan - &ah->channels[0];
182 struct survey_info *survey = &sc->survey[pos];
183 struct ath_cycle_counters *cc = &common->cc_survey;
184 unsigned int div = common->clockrate * 1000;
cb8d61de 185 int ret = 0;
3430098a 186
0845735e 187 if (!ah->curchan)
cb8d61de 188 return -1;
0845735e 189
898c914a
FF		 190 if (ah->power_mode == ATH9K_PM_AWAKE)
191 ath_hw_cycle_counters_update(common);
3430098a
FF		 192
193 if (cc->cycles > 0) {
194 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
195 SURVEY_INFO_CHANNEL_TIME_BUSY |
196 SURVEY_INFO_CHANNEL_TIME_RX |
197 SURVEY_INFO_CHANNEL_TIME_TX;
198 survey->channel_time += cc->cycles / div;
199 survey->channel_time_busy += cc->rx_busy / div;
200 survey->channel_time_rx += cc->rx_frame / div;
201 survey->channel_time_tx += cc->tx_frame / div;
202 }
cb8d61de
FF		 203
204 if (cc->cycles < div)
205 return -1;
206
207 if (cc->cycles > 0)
208 ret = cc->rx_busy * 100 / cc->cycles;
209
3430098a
FF		 210 memset(cc, 0, sizeof(*cc));
211
212 ath_update_survey_nf(sc, pos);
cb8d61de
FF		 213
214 return ret;
3430098a
FF		 215}
216
ff37e337
S		 217/*
218 * Set/change channels. If the channel is really being changed, it's done
219 * by reseting the chip. To accomplish this we must first cleanup any pending
220 * DMA, then restart stuff.
221*/
0e2dedf9
JM		 222int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
223 struct ath9k_channel *hchan)
ff37e337 224{
cbe61d8a 225 struct ath_hw *ah = sc->sc_ah;
c46917bb 226 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 227 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 228 bool fastcc = true, stopped;
ae8d2858 229 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 230 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 231 int r;
ff37e337
S		 232
233 if (sc->sc_flags & SC_OP_INVALID)
234 return -EIO;
235
cb8d61de
FF		 236 sc->hw_busy_count = 0;
237
5ee08656
FF		 238 del_timer_sync(&common->ani.timer);
239 cancel_work_sync(&sc->paprd_work);
240 cancel_work_sync(&sc->hw_check_work);
241 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 242 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 243
3cbb5dd7
VN		 244 ath9k_ps_wakeup(sc);
245
6a6733f2
LR		 246 spin_lock_bh(&sc->sc_pcu_lock);
247
c0d7c7af
LR		 248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
4df3071e 257 ath9k_hw_disable_interrupts(ah);
080e1a25 258 stopped = ath_drain_all_txq(sc, false);
5e848f78 259
080e1a25
FF		 260 if (!ath_stoprecv(sc))
261 stopped = false;
ff37e337 262
8b3f4616
FF		 263 if (!ath9k_hw_check_alive(ah))
264 stopped = false;
265
c0d7c7af
LR		 266 /* XXX: do not flush receive queue here. We don't want
267 * to flush data frames already in queue because of
268 * changing channel. */
ff37e337 269
5ee08656 270 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR		 271 fastcc = false;
272
20bd2a09 273 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 274 caldata = &sc->caldata;
20bd2a09 275
226afe68
JP		 276 ath_dbg(common, ATH_DBG_CONFIG,
277 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
278 sc->sc_ah->curchan->channel,
279 channel->center_freq, conf_is_ht40(conf),
280 fastcc);
ff37e337 281
20bd2a09 282 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 283 if (r) {
3800276a
JP		 284 ath_err(common,
285 "Unable to reset channel (%u MHz), reset status %d\n",
286 channel->center_freq, r);
3989279c 287 goto ps_restore;
ff37e337 288 }
c0d7c7af 289
c0d7c7af 290 if (ath_startrecv(sc) != 0) {
3800276a 291 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ		 292 r = -EIO;
293 goto ps_restore;
c0d7c7af
LR		 294 }
295
5048e8c3
RM		 296 ath9k_cmn_update_txpow(ah, sc->curtxpow,
297 sc->config.txpowlimit, &sc->curtxpow);
3069168c 298 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 299
48a6a468 300 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b 301 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 302 ath_set_beacon(sc);
5ee08656 303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
48a6a468 305 ath_start_ani(common);
5ee08656
FF		 306 }
307
3989279c 308 ps_restore:
92460412
FF		 309 ieee80211_wake_queues(hw);
310
6a6733f2
LR		 311 spin_unlock_bh(&sc->sc_pcu_lock);
312
3cbb5dd7 313 ath9k_ps_restore(sc);
3989279c 314 return r;
ff37e337
S		 315}
316
9f42c2b6
FF		 317static void ath_paprd_activate(struct ath_softc *sc)
318{
319 struct ath_hw *ah = sc->sc_ah;
20bd2a09 320 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 321 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF		 322 int chain;
323
20bd2a09 324 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF		 325 return;
326
327 ath9k_ps_wakeup(sc);
ddfef792 328 ar9003_paprd_enable(ah, false);
9f42c2b6 329 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 330 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 331 continue;
332
20bd2a09 333 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF		 334 }
335
336 ar9003_paprd_enable(ah, true);
337 ath9k_ps_restore(sc);
338}
339
7607cbe2
FF		 340static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
341{
342 struct ieee80211_hw *hw = sc->hw;
343 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS		 344 struct ath_hw *ah = sc->sc_ah;
345 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF		 346 struct ath_tx_control txctl;
347 int time_left;
348
349 memset(&txctl, 0, sizeof(txctl));
350 txctl.txq = sc->tx.txq_map[WME_AC_BE];
351
352 memset(tx_info, 0, sizeof(*tx_info));
353 tx_info->band = hw->conf.channel->band;
354 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
355 tx_info->control.rates[0].idx = 0;
356 tx_info->control.rates[0].count = 1;
357 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
358 tx_info->control.rates[1].idx = -1;
359
360 init_completion(&sc->paprd_complete);
7607cbe2 361 txctl.paprd = BIT(chain);
47960077
MSS		 362
363 if (ath_tx_start(hw, skb, &txctl) != 0) {
364 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
365 dev_kfree_skb_any(skb);
7607cbe2 366 return false;
47960077 367 }
7607cbe2
FF		 368
369 time_left = wait_for_completion_timeout(&sc->paprd_complete,
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF		 371
372 if (!time_left)
373 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
374 "Timeout waiting for paprd training on TX chain %d\n",
375 chain);
376
377 return !!time_left;
378}
379
9f42c2b6
FF		 380void ath_paprd_calibrate(struct work_struct *work)
381{
382 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
383 struct ieee80211_hw *hw = sc->hw;
384 struct ath_hw *ah = sc->sc_ah;
385 struct ieee80211_hdr *hdr;
386 struct sk_buff *skb = NULL;
20bd2a09 387 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 388 struct ath_common *common = ath9k_hw_common(ah);
066dae93 389 int ftype;
9f42c2b6
FF		 390 int chain_ok = 0;
391 int chain;
392 int len = 1800;
9f42c2b6 393
20bd2a09
FF		 394 if (!caldata)
395 return;
396
1bf38661
FF		 397 if (ar9003_paprd_init_table(ah) < 0)
398 return;
399
9f42c2b6
FF		 400 skb = alloc_skb(len, GFP_KERNEL);
401 if (!skb)
402 return;
403
9f42c2b6
FF		 404 skb_put(skb, len);
405 memset(skb->data, 0, len);
406 hdr = (struct ieee80211_hdr *)skb->data;
407 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
408 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 409 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF		 410 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
413
47399f1a 414 ath9k_ps_wakeup(sc);
9f42c2b6 415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 416 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF		 417 continue;
418
419 chain_ok = 0;
9f42c2b6 420
7607cbe2
FF		 421 ath_dbg(common, ATH_DBG_CALIBRATE,
422 "Sending PAPRD frame for thermal measurement "
423 "on chain %d\n", chain);
424 if (!ath_paprd_send_frame(sc, skb, chain))
425 goto fail_paprd;
9f42c2b6 426
9f42c2b6 427 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 428
7607cbe2
FF		 429 ath_dbg(common, ATH_DBG_CALIBRATE,
430 "Sending PAPRD training frame on chain %d\n", chain);
431 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 432 goto fail_paprd;
9f42c2b6
FF		 433
434 if (!ar9003_paprd_is_done(ah))
435 break;
436
20bd2a09 437 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF		 438 break;
439
440 chain_ok = 1;
441 }
442 kfree_skb(skb);
443
444 if (chain_ok) {
20bd2a09 445 caldata->paprd_done = true;
9f42c2b6
FF		 446 ath_paprd_activate(sc);
447 }
448
ca369eb4 449fail_paprd:
9f42c2b6
FF		 450 ath9k_ps_restore(sc);
451}
452
ff37e337
S		 453/*
454 * This routine performs the periodic noise floor calibration function
455 * that is used to adjust and optimize the chip performance. This
456 * takes environmental changes (location, temperature) into account.
457 * When the task is complete, it reschedules itself depending on the
458 * appropriate interval that was calculated.
459 */
55624204 460void ath_ani_calibrate(unsigned long data)
ff37e337 461{
20977d3e
S		 462 struct ath_softc *sc = (struct ath_softc *)data;
463 struct ath_hw *ah = sc->sc_ah;
c46917bb 464 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 465 bool longcal = false;
466 bool shortcal = false;
467 bool aniflag = false;
468 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 469 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 470 unsigned long flags;
6044474e
FF		 471
472 if (ah->caldata && ah->caldata->nfcal_interference)
473 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
474 else
475 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 476
20977d3e
S		 477 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
478 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 479
1ffc1c61
JM		 480 /* Only calibrate if awake */
481 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
482 goto set_timer;
483
484 ath9k_ps_wakeup(sc);
485
ff37e337 486 /* Long calibration runs independently of short calibration. */
6044474e 487 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 488 longcal = true;
226afe68 489 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 490 common->ani.longcal_timer = timestamp;
ff37e337
S		 491 }
492
17d7904d 493 /* Short calibration applies only while caldone is false */
3d536acf
LR		 494 if (!common->ani.caldone) {
495 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 496 shortcal = true;
226afe68
JP		 497 ath_dbg(common, ATH_DBG_ANI,
498 "shortcal @%lu\n", jiffies);
3d536acf
LR		 499 common->ani.shortcal_timer = timestamp;
500 common->ani.resetcal_timer = timestamp;
ff37e337
S		 501 }
502 } else {
3d536acf 503 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 504 ATH_RESTART_CALINTERVAL) {
3d536acf
LR		 505 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
506 if (common->ani.caldone)
507 common->ani.resetcal_timer = timestamp;
ff37e337
S		 508 }
509 }
510
511 /* Verify whether we must check ANI */
e36b27af
LR		 512 if ((timestamp - common->ani.checkani_timer) >=
513 ah->config.ani_poll_interval) {
ff37e337 514 aniflag = true;
3d536acf 515 common->ani.checkani_timer = timestamp;
ff37e337
S		 516 }
517
518 /* Skip all processing if there's nothing to do. */
519 if (longcal || shortcal || aniflag) {
520 /* Call ANI routine if necessary */
b5bfc568
FF		 521 if (aniflag) {
522 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 523 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 524 ath_update_survey_stats(sc);
b5bfc568
FF		 525 spin_unlock_irqrestore(&common->cc_lock, flags);
526 }
ff37e337
S		 527
528 /* Perform calibration if necessary */
529 if (longcal || shortcal) {
3d536acf 530 common->ani.caldone =
43c27613
LR		 531 ath9k_hw_calibrate(ah,
532 ah->curchan,
533 common->rx_chainmask,
534 longcal);
ff37e337
S		 535 }
536 }
537
1ffc1c61
JM		 538 ath9k_ps_restore(sc);
539
20977d3e 540set_timer:
ff37e337
S		 541 /*
542 * Set timer interval based on previous results.
543 * The interval must be the shortest necessary to satisfy ANI,
544 * short calibration and long calibration.
545 */
aac9207e 546 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 547 if (sc->sc_ah->config.enable_ani)
e36b27af
LR		 548 cal_interval = min(cal_interval,
549 (u32)ah->config.ani_poll_interval);
3d536acf 550 if (!common->ani.caldone)
20977d3e 551 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 552
3d536acf 553 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF		 554 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
555 if (!ah->caldata->paprd_done)
9f42c2b6 556 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 557 else if (!ah->paprd_table_write_done)
9f42c2b6
FF		 558 ath_paprd_activate(sc);
559 }
ff37e337
S		 560}
561
ff37e337
S		 562static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
563{
564 struct ath_node *an;
ea066d5a 565 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 566 an = (struct ath_node *)sta->drv_priv;
567
7f010c93
BG		 568#ifdef CONFIG_ATH9K_DEBUGFS
569 spin_lock(&sc->nodes_lock);
570 list_add(&an->list, &sc->nodes);
571 spin_unlock(&sc->nodes_lock);
572 an->sta = sta;
573#endif
ea066d5a
MSS		 574 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
575 sc->sc_flags |= SC_OP_ENABLE_APM;
576
87792efc 577 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 578 ath_tx_node_init(sc, an);
9e98ac65 579 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 580 sta->ht_cap.ampdu_factor);
581 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
582 }
ff37e337
S		 583}
584
585static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
586{
587 struct ath_node *an = (struct ath_node *)sta->drv_priv;
588
7f010c93
BG		 589#ifdef CONFIG_ATH9K_DEBUGFS
590 spin_lock(&sc->nodes_lock);
591 list_del(&an->list);
592 spin_unlock(&sc->nodes_lock);
593 an->sta = NULL;
594#endif
595
ff37e337
S		 596 if (sc->sc_flags & SC_OP_TXAGGR)
597 ath_tx_node_cleanup(sc, an);
598}
599
347809fc
FF		 600void ath_hw_check(struct work_struct *work)
601{
602 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
cb8d61de
FF		 603 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
604 unsigned long flags;
605 int busy;
347809fc
FF		 606
607 ath9k_ps_wakeup(sc);
cb8d61de
FF		 608 if (ath9k_hw_check_alive(sc->sc_ah))
609 goto out;
347809fc 610
cb8d61de
FF		 611 spin_lock_irqsave(&common->cc_lock, flags);
612 busy = ath_update_survey_stats(sc);
613 spin_unlock_irqrestore(&common->cc_lock, flags);
347809fc 614
cb8d61de
FF		 615 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
616 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
617 if (busy >= 99) {
618 if (++sc->hw_busy_count >= 3)
619 ath_reset(sc, true);
620 } else if (busy >= 0)
621 sc->hw_busy_count = 0;
347809fc
FF		 622
623out:
624 ath9k_ps_restore(sc);
625}
626
b84628eb
SB		 627static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
628{
629 static int count;
630 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
631
632 if (pll_sqsum >= 0x40000) {
633 count++;
634 if (count == 3) {
635 /* Rx is hung for more than 500ms. Reset it */
636 ath_dbg(common, ATH_DBG_RESET,
637 "Possible RX hang, resetting");
638 ath_reset(sc, true);
639 count = 0;
640 }
641 } else
642 count = 0;
643}
644
9eab61c2
SB		 645void ath_hw_pll_work(struct work_struct *work)
646{
647 struct ath_softc *sc = container_of(work, struct ath_softc,
648 hw_pll_work.work);
b84628eb 649 u32 pll_sqsum;
9eab61c2
SB		 650
651 if (AR_SREV_9485(sc->sc_ah)) {
b84628eb
SB		 652
653 ath9k_ps_wakeup(sc);
654 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
655 ath9k_ps_restore(sc);
656
657 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
9eab61c2
SB		 658
659 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
660 }
661}
662
663
55624204 664void ath9k_tasklet(unsigned long data)
ff37e337
S		 665{
666 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 667 struct ath_hw *ah = sc->sc_ah;
c46917bb 668 struct ath_common *common = ath9k_hw_common(ah);
af03abec 669
17d7904d 670 u32 status = sc->intrstatus;
b5c80475 671 u32 rxmask;
ff37e337 672
347809fc 673 if (status & ATH9K_INT_FATAL) {
fac6b6a0 674 ath_reset(sc, true);
ff37e337 675 return;
063d8be3 676 }
ff37e337 677
783cd01e 678 ath9k_ps_wakeup(sc);
52671e43 679 spin_lock(&sc->sc_pcu_lock);
6a6733f2 680
8b3f4616
FF		 681 /*
682 * Only run the baseband hang check if beacons stop working in AP or
683 * IBSS mode, because it has a high false positive rate. For station
684 * mode it should not be necessary, since the upper layers will detect
685 * this through a beacon miss automatically and the following channel
686 * change will trigger a hardware reset anyway
687 */
688 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
689 !ath9k_hw_check_alive(ah))
347809fc
FF		 690 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
691
4105f807
RM		 692 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
693 /*
694 * TSF sync does not look correct; remain awake to sync with
695 * the next Beacon.
696 */
697 ath_dbg(common, ATH_DBG_PS,
698 "TSFOOR - Sync with next Beacon\n");
699 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
700 PS_TSFOOR_SYNC;
701 }
702
b5c80475
FF		 703 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
704 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
705 ATH9K_INT_RXORN);
706 else
707 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
708
709 if (status & rxmask) {
b5c80475
FF		 710 /* Check for high priority Rx first */
711 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
712 (status & ATH9K_INT_RXHP))
713 ath_rx_tasklet(sc, 0, true);
714
715 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 716 }
717
e5003249
VT		 718 if (status & ATH9K_INT_TX) {
719 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
720 ath_tx_edma_tasklet(sc);
721 else
722 ath_tx_tasklet(sc);
723 }
063d8be3 724
766ec4a9 725 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 726 if (status & ATH9K_INT_GENTIMER)
727 ath_gen_timer_isr(sc->sc_ah);
728
ff37e337 729 /* re-enable hardware interrupt */
4df3071e 730 ath9k_hw_enable_interrupts(ah);
6a6733f2 731
52671e43 732 spin_unlock(&sc->sc_pcu_lock);
153e080d 733 ath9k_ps_restore(sc);
ff37e337
S		 734}
735
6baff7f9 736irqreturn_t ath_isr(int irq, void *dev)
ff37e337 737{
063d8be3
S		 738#define SCHED_INTR ( \
739 ATH9K_INT_FATAL | \
740 ATH9K_INT_RXORN | \
741 ATH9K_INT_RXEOL | \
742 ATH9K_INT_RX | \
b5c80475
FF		 743 ATH9K_INT_RXLP | \
744 ATH9K_INT_RXHP | \
063d8be3
S		 745 ATH9K_INT_TX | \
746 ATH9K_INT_BMISS | \
747 ATH9K_INT_CST | \
ebb8e1d7
VT		 748 ATH9K_INT_TSFOOR | \
749 ATH9K_INT_GENTIMER)
063d8be3 750
ff37e337 751 struct ath_softc *sc = dev;
cbe61d8a 752 struct ath_hw *ah = sc->sc_ah;
b5bfc568 753 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 754 enum ath9k_int status;
755 bool sched = false;
756
063d8be3
S		 757 /*
758 * The hardware is not ready/present, don't
759 * touch anything. Note this can happen early
760 * on if the IRQ is shared.
761 */
762 if (sc->sc_flags & SC_OP_INVALID)
763 return IRQ_NONE;
ff37e337 764
063d8be3
S		 765
766 /* shared irq, not for us */
767
153e080d 768 if (!ath9k_hw_intrpend(ah))
063d8be3 769 return IRQ_NONE;
063d8be3
S		 770
771 /*
772 * Figure out the reason(s) for the interrupt. Note
773 * that the hal returns a pseudo-ISR that may include
774 * bits we haven't explicitly enabled so we mask the
775 * value to insure we only process bits we requested.
776 */
777 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 778 status &= ah->imask; /* discard unasked-for bits */
ff37e337 779
063d8be3
S		 780 /*
781 * If there are no status bits set, then this interrupt was not
782 * for me (should have been caught above).
783 */
153e080d 784 if (!status)
063d8be3 785 return IRQ_NONE;
ff37e337 786
063d8be3
S		 787 /* Cache the status */
788 sc->intrstatus = status;
789
790 if (status & SCHED_INTR)
791 sched = true;
792
793 /*
794 * If a FATAL or RXORN interrupt is received, we have to reset the
795 * chip immediately.
796 */
b5c80475
FF		 797 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
798 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 799 goto chip_reset;
800
08578b8f
LR		 801 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
802 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF		 803
804 spin_lock(&common->cc_lock);
805 ath_hw_cycle_counters_update(common);
08578b8f 806 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF		 807 spin_unlock(&common->cc_lock);
808
08578b8f
LR		 809 goto chip_reset;
810 }
811
063d8be3
S		 812 if (status & ATH9K_INT_SWBA)
813 tasklet_schedule(&sc->bcon_tasklet);
814
815 if (status & ATH9K_INT_TXURN)
816 ath9k_hw_updatetxtriglevel(ah, true);
817
b5c80475
FF		 818 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
819 if (status & ATH9K_INT_RXEOL) {
820 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
821 ath9k_hw_set_interrupts(ah, ah->imask);
822 }
823 }
824
063d8be3 825 if (status & ATH9K_INT_MIB) {
ff37e337 826 /*
063d8be3
S		 827 * Disable interrupts until we service the MIB
828 * interrupt; otherwise it will continue to
829 * fire.
ff37e337 830 */
4df3071e 831 ath9k_hw_disable_interrupts(ah);
063d8be3
S		 832 /*
833 * Let the hal handle the event. We assume
834 * it will clear whatever condition caused
835 * the interrupt.
836 */
88eac2da 837 spin_lock(&common->cc_lock);
bfc472bb 838 ath9k_hw_proc_mib_event(ah);
88eac2da 839 spin_unlock(&common->cc_lock);
4df3071e 840 ath9k_hw_enable_interrupts(ah);
063d8be3 841 }
ff37e337 842
153e080d
VT		 843 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
844 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 845 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
846 goto chip_reset;
063d8be3
S		 847 /* Clear RxAbort bit so that we can
848 * receive frames */
9ecdef4b 849 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 850 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 851 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 852 }
063d8be3
S		 853
854chip_reset:
ff37e337 855
817e11de
S		 856 ath_debug_stat_interrupt(sc, status);
857
ff37e337 858 if (sched) {
4df3071e
FF		 859 /* turn off every interrupt */
860 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 861 tasklet_schedule(&sc->intr_tq);
862 }
863
864 return IRQ_HANDLED;
063d8be3
S		 865
866#undef SCHED_INTR
ff37e337
S		 867}
868
68a89116 869void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 870{
cbe61d8a 871 struct ath_hw *ah = sc->sc_ah;
c46917bb 872 struct ath_common *common = ath9k_hw_common(ah);
68a89116 873 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 874 int r;
500c064d 875
3cbb5dd7 876 ath9k_ps_wakeup(sc);
6a6733f2
LR		 877 spin_lock_bh(&sc->sc_pcu_lock);
878
93b1b37f 879 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 880
159cd468 881 if (!ah->curchan)
c344c9cb 882 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 883
20bd2a09 884 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 885 if (r) {
3800276a
JP		 886 ath_err(common,
887 "Unable to reset channel (%u MHz), reset status %d\n",
888 channel->center_freq, r);
500c064d 889 }
500c064d 890
5048e8c3
RM		 891 ath9k_cmn_update_txpow(ah, sc->curtxpow,
892 sc->config.txpowlimit, &sc->curtxpow);
500c064d 893 if (ath_startrecv(sc) != 0) {
3800276a 894 ath_err(common, "Unable to restart recv logic\n");
c2731b81 895 goto out;
500c064d 896 }
500c064d 897 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 898 ath_set_beacon(sc); /* restart beacons */
500c064d
VT		 899
900 /* Re-Enable interrupts */
3069168c 901 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT		 902
903 /* Enable LED */
08fc5c1b 904 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 905 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 906 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 907
68a89116 908 ieee80211_wake_queues(hw);
7e3514fd
VN		 909 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
910
c2731b81 911out:
6a6733f2
LR		 912 spin_unlock_bh(&sc->sc_pcu_lock);
913
3cbb5dd7 914 ath9k_ps_restore(sc);
500c064d
VT		 915}
916
68a89116 917void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 918{
cbe61d8a 919 struct ath_hw *ah = sc->sc_ah;
68a89116 920 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 921 int r;
500c064d 922
3cbb5dd7 923 ath9k_ps_wakeup(sc);
7e3514fd
VN		 924 cancel_delayed_work_sync(&sc->hw_pll_work);
925
6a6733f2
LR		 926 spin_lock_bh(&sc->sc_pcu_lock);
927
68a89116 928 ieee80211_stop_queues(hw);
500c064d 929
982723df
VN		 930 /*
931 * Keep the LED on when the radio is disabled
932 * during idle unassociated state.
933 */
934 if (!sc->ps_idle) {
935 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
936 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
937 }
500c064d
VT		 938
939 /* Disable interrupts */
4df3071e 940 ath9k_hw_disable_interrupts(ah);
500c064d 941
043a0405 942 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 943
500c064d
VT		 944 ath_stoprecv(sc); /* turn off frame recv */
945 ath_flushrecv(sc); /* flush recv queue */
946
159cd468 947 if (!ah->curchan)
c344c9cb 948 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 949
20bd2a09 950 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 951 if (r) {
3800276a
JP		 952 ath_err(ath9k_hw_common(sc->sc_ah),
953 "Unable to reset channel (%u MHz), reset status %d\n",
954 channel->center_freq, r);
500c064d 955 }
500c064d
VT		 956
957 ath9k_hw_phy_disable(ah);
5e848f78 958
93b1b37f 959 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 960
961 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 962 ath9k_ps_restore(sc);
500c064d
VT		 963}
964
ff37e337
S		 965int ath_reset(struct ath_softc *sc, bool retry_tx)
966{
cbe61d8a 967 struct ath_hw *ah = sc->sc_ah;
c46917bb 968 struct ath_common *common = ath9k_hw_common(ah);
030bb495 969 struct ieee80211_hw *hw = sc->hw;
ae8d2858 970 int r;
ff37e337 971
cb8d61de
FF		 972 sc->hw_busy_count = 0;
973
2ab81d4a
S		 974 /* Stop ANI */
975 del_timer_sync(&common->ani.timer);
976
783cd01e 977 ath9k_ps_wakeup(sc);
6a6733f2
LR		 978 spin_lock_bh(&sc->sc_pcu_lock);
979
cc9c378a
S		 980 ieee80211_stop_queues(hw);
981
4df3071e 982 ath9k_hw_disable_interrupts(ah);
043a0405 983 ath_drain_all_txq(sc, retry_tx);
5e848f78 984
ff37e337
S		 985 ath_stoprecv(sc);
986 ath_flushrecv(sc);
987
20bd2a09 988 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 989 if (r)
3800276a
JP		 990 ath_err(common,
991 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 992
993 if (ath_startrecv(sc) != 0)
3800276a 994 ath_err(common, "Unable to start recv logic\n");
ff37e337
S		 995
996 /*
997 * We may be doing a reset in response to a request
998 * that changes the channel so update any state that
999 * might change as a result.
1000 */
5048e8c3
RM		 1001 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1002 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 1003
52b8ac92 1004 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
99e4d43a 1005 ath_set_beacon(sc); /* restart beacons */
ff37e337 1006
3069168c 1007 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S		 1008
1009 if (retry_tx) {
1010 int i;
1011 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1012 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1013 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1014 ath_txq_schedule(sc, &sc->tx.txq[i]);
1015 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1016 }
1017 }
1018 }
1019
cc9c378a 1020 ieee80211_wake_queues(hw);
6a6733f2 1021 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1022
2ab81d4a
S		 1023 /* Start ANI */
1024 ath_start_ani(common);
783cd01e 1025 ath9k_ps_restore(sc);
2ab81d4a 1026
ae8d2858 1027 return r;
ff37e337
S		 1028}
1029
ff37e337
S		 1030/**********************/
1031/* mac80211 callbacks */
1032/**********************/
1033
8feceb67 1034static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1035{
9ac58615 1036 struct ath_softc *sc = hw->priv;
af03abec 1037 struct ath_hw *ah = sc->sc_ah;
c46917bb 1038 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1039 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1040 struct ath9k_channel *init_channel;
82880a7c 1041 int r;
f078f209 1042
226afe68
JP		 1043 ath_dbg(common, ATH_DBG_CONFIG,
1044 "Starting driver with initial channel: %d MHz\n",
1045 curchan->center_freq);
f078f209 1046
f62d816f
FF		 1047 ath9k_ps_wakeup(sc);
1048
141b38b6
S		 1049 mutex_lock(&sc->mutex);
1050
8feceb67 1051 /* setup initial channel */
82880a7c 1052 sc->chan_idx = curchan->hw_value;
f078f209 1053
c344c9cb 1054 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S		 1055
1056 /* Reset SERDES registers */
af03abec 1057 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 1058
1059 /*
1060 * The basic interface to setting the hardware in a good
1061 * state is ``reset''. On return the hardware is known to
1062 * be powered up and with interrupts disabled. This must
1063 * be followed by initialization of the appropriate bits
1064 * and then setup of the interrupt mask.
1065 */
4bdd1e97 1066 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1067 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1068 if (r) {
3800276a
JP		 1069 ath_err(common,
1070 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1071 r, curchan->center_freq);
4bdd1e97 1072 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1073 goto mutex_unlock;
ff37e337 1074 }
ff37e337
S		 1075
1076 /*
1077 * This is needed only to setup initial state
1078 * but it's best done after a reset.
1079 */
5048e8c3
RM		 1080 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1081 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1082
ff37e337
S		 1083 /*
1084 * Setup the hardware after reset:
1085 * The receive engine is set going.
1086 * Frame transmit is handled entirely
1087 * in the frame output path; there's nothing to do
1088 * here except setup the interrupt mask.
1089 */
1090 if (ath_startrecv(sc) != 0) {
3800276a 1091 ath_err(common, "Unable to start recv logic\n");
141b38b6 1092 r = -EIO;
4bdd1e97 1093 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1094 goto mutex_unlock;
f078f209 1095 }
4bdd1e97 1096 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1097
ff37e337 1098 /* Setup our intr mask. */
b5c80475
FF		 1099 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1100 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1101 ATH9K_INT_GLOBAL;
1102
1103 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR		 1104 ah->imask |= ATH9K_INT_RXHP |
1105 ATH9K_INT_RXLP |
1106 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF		 1107 else
1108 ah->imask |= ATH9K_INT_RX;
ff37e337 1109
364734fa 1110 ah->imask |= ATH9K_INT_GTT;
ff37e337 1111
af03abec 1112 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1113 ah->imask |= ATH9K_INT_CST;
ff37e337 1114
ff37e337 1115 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1116 sc->sc_ah->is_monitoring = false;
ff37e337
S		 1117
1118 /* Disable BMISS interrupt when we're not associated */
3069168c
PR		 1119 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1120 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1121
bce048d7 1122 ieee80211_wake_queues(hw);
ff37e337 1123
42935eca 1124 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1125
766ec4a9
LR		 1126 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1127 !ah->btcoex_hw.enabled) {
5e197292
LR		 1128 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1129 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1130 ath9k_hw_btcoex_enable(ah);
f985ad12 1131
5bb12791
LR		 1132 if (common->bus_ops->bt_coex_prep)
1133 common->bus_ops->bt_coex_prep(common);
766ec4a9 1134 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1135 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 1136 }
1137
8060e169
VT		 1138 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1139 common->bus_ops->extn_synch_en(common);
1140
141b38b6
S		 1141mutex_unlock:
1142 mutex_unlock(&sc->mutex);
1143
f62d816f
FF		 1144 ath9k_ps_restore(sc);
1145
ae8d2858 1146 return r;
f078f209
LR		 1147}
1148
7bb45683 1149static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1150{
9ac58615 1151 struct ath_softc *sc = hw->priv;
c46917bb 1152 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1153 struct ath_tx_control txctl;
1bc14880 1154 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1155
96148326 1156 if (sc->ps_enabled) {
dc8c4585
JM		 1157 /*
1158 * mac80211 does not set PM field for normal data frames, so we
1159 * need to update that based on the current PS mode.
1160 */
1161 if (ieee80211_is_data(hdr->frame_control) &&
1162 !ieee80211_is_nullfunc(hdr->frame_control) &&
1163 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP		 1164 ath_dbg(common, ATH_DBG_PS,
1165 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 1166 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1167 }
1168 }
1169
9a23f9ca
JM		 1170 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1171 /*
1172 * We are using PS-Poll and mac80211 can request TX while in
1173 * power save mode. Need to wake up hardware for the TX to be
1174 * completed and if needed, also for RX of buffered frames.
1175 */
9a23f9ca 1176 ath9k_ps_wakeup(sc);
fdf76622
VT		 1177 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1178 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1179 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP		 1180 ath_dbg(common, ATH_DBG_PS,
1181 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1182 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1183 } else {
226afe68
JP		 1184 ath_dbg(common, ATH_DBG_PS,
1185 "Wake up to complete TX\n");
1b04b930 1186 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 1187 }
1188 /*
1189 * The actual restore operation will happen only after
1190 * the sc_flags bit is cleared. We are just dropping
1191 * the ps_usecount here.
1192 */
1193 ath9k_ps_restore(sc);
1194 }
1195
528f0c6b 1196 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1197 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1198
226afe68 1199 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1200
c52f33d0 1201 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1202 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1203 goto exit;
8feceb67
VT		 1204 }
1205
7bb45683 1206 return;
528f0c6b
S		 1207exit:
1208 dev_kfree_skb_any(skb);
f078f209
LR		 1209}
1210
8feceb67 1211static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1212{
9ac58615 1213 struct ath_softc *sc = hw->priv;
af03abec 1214 struct ath_hw *ah = sc->sc_ah;
c46917bb 1215 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1216
4c483817
S		 1217 mutex_lock(&sc->mutex);
1218
c94dbff7 1219 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1220 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1221 cancel_work_sync(&sc->paprd_work);
347809fc 1222 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1223
9c84b797 1224 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1225 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1226 mutex_unlock(&sc->mutex);
9c84b797
S		 1227 return;
1228 }
8feceb67 1229
3867cf6a
S		 1230 /* Ensure HW is awake when we try to shut it down. */
1231 ath9k_ps_wakeup(sc);
1232
766ec4a9 1233 if (ah->btcoex_hw.enabled) {
af03abec 1234 ath9k_hw_btcoex_disable(ah);
766ec4a9 1235 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1236 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 1237 }
1238
6a6733f2
LR		 1239 spin_lock_bh(&sc->sc_pcu_lock);
1240
203043f5
SG		 1241 /* prevent tasklets to enable interrupts once we disable them */
1242 ah->imask &= ~ATH9K_INT_GLOBAL;
1243
ff37e337
S		 1244 /* make sure h/w will not generate any interrupt
1245 * before setting the invalid flag. */
4df3071e 1246 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 1247
1248 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1249 ath_drain_all_txq(sc, false);
ff37e337 1250 ath_stoprecv(sc);
af03abec 1251 ath9k_hw_phy_disable(ah);
6a6733f2 1252 } else
b77f483f 1253 sc->rx.rxlink = NULL;
ff37e337 1254
0d95521e
FF		 1255 if (sc->rx.frag) {
1256 dev_kfree_skb_any(sc->rx.frag);
1257 sc->rx.frag = NULL;
1258 }
1259
ff37e337 1260 /* disable HAL and put h/w to sleep */
af03abec
LR		 1261 ath9k_hw_disable(ah);
1262 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR		 1263
1264 spin_unlock_bh(&sc->sc_pcu_lock);
1265
203043f5
SG		 1266 /* we can now sync irq and kill any running tasklets, since we already
1267 * disabled interrupts and not holding a spin lock */
1268 synchronize_irq(sc->irq);
1269 tasklet_kill(&sc->intr_tq);
1270 tasklet_kill(&sc->bcon_tasklet);
1271
3867cf6a
S		 1272 ath9k_ps_restore(sc);
1273
a08e7ade
LR		 1274 sc->ps_idle = true;
1275 ath_radio_disable(sc, hw);
ff37e337
S		 1276
1277 sc->sc_flags |= SC_OP_INVALID;
500c064d 1278
141b38b6
S		 1279 mutex_unlock(&sc->mutex);
1280
226afe68 1281 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 1282}
1283
4801416c
BG		 1284bool ath9k_uses_beacons(int type)
1285{
1286 switch (type) {
1287 case NL80211_IFTYPE_AP:
1288 case NL80211_IFTYPE_ADHOC:
1289 case NL80211_IFTYPE_MESH_POINT:
1290 return true;
1291 default:
1292 return false;
1293 }
1294}
1295
1296static void ath9k_reclaim_beacon(struct ath_softc *sc,
1297 struct ieee80211_vif *vif)
f078f209 1298{
1ed32e4f 1299 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1300
014cf3bb 1301 ath9k_set_beaconing_status(sc, false);
4801416c 1302 ath_beacon_return(sc, avp);
014cf3bb 1303 ath9k_set_beaconing_status(sc, true);
4801416c 1304 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG		 1305}
1306
1307static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1308{
1309 struct ath9k_vif_iter_data *iter_data = data;
1310 int i;
1311
1312 if (iter_data->hw_macaddr)
1313 for (i = 0; i < ETH_ALEN; i++)
1314 iter_data->mask[i] &=
1315 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1316
1ed32e4f 1317 switch (vif->type) {
4801416c
BG		 1318 case NL80211_IFTYPE_AP:
1319 iter_data->naps++;
f078f209 1320 break;
4801416c
BG		 1321 case NL80211_IFTYPE_STATION:
1322 iter_data->nstations++;
e51f3eff 1323 break;
05c914fe 1324 case NL80211_IFTYPE_ADHOC:
4801416c
BG		 1325 iter_data->nadhocs++;
1326 break;
9cb5412b 1327 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG		 1328 iter_data->nmeshes++;
1329 break;
1330 case NL80211_IFTYPE_WDS:
1331 iter_data->nwds++;
f078f209
LR		 1332 break;
1333 default:
4801416c
BG		 1334 iter_data->nothers++;
1335 break;
f078f209 1336 }
4801416c 1337}
f078f209 1338
4801416c
BG		 1339/* Called with sc->mutex held. */
1340void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1341 struct ieee80211_vif *vif,
1342 struct ath9k_vif_iter_data *iter_data)
1343{
9ac58615 1344 struct ath_softc *sc = hw->priv;
4801416c
BG		 1345 struct ath_hw *ah = sc->sc_ah;
1346 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1347
4801416c
BG		 1348 /*
1349 * Use the hardware MAC address as reference, the hardware uses it
1350 * together with the BSSID mask when matching addresses.
1351 */
1352 memset(iter_data, 0, sizeof(*iter_data));
1353 iter_data->hw_macaddr = common->macaddr;
1354 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1355
4801416c
BG		 1356 if (vif)
1357 ath9k_vif_iter(iter_data, vif->addr, vif);
1358
1359 /* Get list of all active MAC addresses */
4801416c
BG		 1360 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1361 iter_data);
4801416c 1362}
8ca21f01 1363
4801416c
BG		 1364/* Called with sc->mutex held. */
1365static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1366 struct ieee80211_vif *vif)
1367{
9ac58615 1368 struct ath_softc *sc = hw->priv;
4801416c
BG		 1369 struct ath_hw *ah = sc->sc_ah;
1370 struct ath_common *common = ath9k_hw_common(ah);
1371 struct ath9k_vif_iter_data iter_data;
8ca21f01 1372
4801416c 1373 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1374
4801416c
BG		 1375 /* Set BSSID mask. */
1376 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1377 ath_hw_setbssidmask(common);
1378
1379 /* Set op-mode & TSF */
1380 if (iter_data.naps > 0) {
3069168c 1381 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1382 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG		 1383 ah->opmode = NL80211_IFTYPE_AP;
1384 } else {
1385 ath9k_hw_set_tsfadjust(ah, 0);
1386 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1387
fd5999cf
JC		 1388 if (iter_data.nmeshes)
1389 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1390 else if (iter_data.nwds)
4801416c
BG		 1391 ah->opmode = NL80211_IFTYPE_AP;
1392 else if (iter_data.nadhocs)
1393 ah->opmode = NL80211_IFTYPE_ADHOC;
1394 else
1395 ah->opmode = NL80211_IFTYPE_STATION;
1396 }
5640b08e 1397
4e30ffa2
VN		 1398 /*
1399 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1400 */
4801416c 1401 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR		 1402 if (ah->config.enable_ani)
1403 ah->imask |= ATH9K_INT_MIB;
3069168c 1404 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG		 1405 } else {
1406 ah->imask &= ~ATH9K_INT_MIB;
1407 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S		 1408 }
1409
3069168c 1410 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1411
4801416c
BG		 1412 /* Set up ANI */
1413 if ((iter_data.naps + iter_data.nadhocs) > 0) {
729da390 1414 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
6c3118e2 1415 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1416 ath_start_ani(common);
f60c49b6
RM		 1417 } else {
1418 sc->sc_flags &= ~SC_OP_ANI_RUN;
1419 del_timer_sync(&common->ani.timer);
6c3118e2 1420 }
4801416c 1421}
6f255425 1422
4801416c
BG		 1423/* Called with sc->mutex held, vif counts set up properly. */
1424static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1425 struct ieee80211_vif *vif)
1426{
9ac58615 1427 struct ath_softc *sc = hw->priv;
4801416c
BG		 1428
1429 ath9k_calculate_summary_state(hw, vif);
1430
1431 if (ath9k_uses_beacons(vif->type)) {
1432 int error;
4801416c
BG		 1433 /* This may fail because upper levels do not have beacons
1434 * properly configured yet. That's OK, we assume it
1435 * will be properly configured and then we will be notified
1436 * in the info_changed method and set up beacons properly
1437 * there.
1438 */
014cf3bb 1439 ath9k_set_beaconing_status(sc, false);
9ac58615 1440 error = ath_beacon_alloc(sc, vif);
391bd1c4 1441 if (!error)
4801416c 1442 ath_beacon_config(sc, vif);
014cf3bb 1443 ath9k_set_beaconing_status(sc, true);
4801416c 1444 }
f078f209
LR		 1445}
1446
4801416c
BG		 1447
1448static int ath9k_add_interface(struct ieee80211_hw *hw,
1449 struct ieee80211_vif *vif)
6b3b991d 1450{
9ac58615 1451 struct ath_softc *sc = hw->priv;
4801416c
BG		 1452 struct ath_hw *ah = sc->sc_ah;
1453 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1454 int ret = 0;
6b3b991d 1455
96f372c9 1456 ath9k_ps_wakeup(sc);
4801416c 1457 mutex_lock(&sc->mutex);
6b3b991d 1458
4801416c
BG		 1459 switch (vif->type) {
1460 case NL80211_IFTYPE_STATION:
1461 case NL80211_IFTYPE_WDS:
1462 case NL80211_IFTYPE_ADHOC:
1463 case NL80211_IFTYPE_AP:
1464 case NL80211_IFTYPE_MESH_POINT:
1465 break;
1466 default:
1467 ath_err(common, "Interface type %d not yet supported\n",
1468 vif->type);
1469 ret = -EOPNOTSUPP;
1470 goto out;
1471 }
6b3b991d 1472
4801416c
BG		 1473 if (ath9k_uses_beacons(vif->type)) {
1474 if (sc->nbcnvifs >= ATH_BCBUF) {
1475 ath_err(common, "Not enough beacon buffers when adding"
1476 " new interface of type: %i\n",
1477 vif->type);
1478 ret = -ENOBUFS;
1479 goto out;
1480 }
1481 }
1482
59575d1c
RM		 1483 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1484 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1485 sc->nvifs > 0)) {
4801416c
BG		 1486 ath_err(common, "Cannot create ADHOC interface when other"
1487 " interfaces already exist.\n");
1488 ret = -EINVAL;
1489 goto out;
6b3b991d 1490 }
4801416c
BG		 1491
1492 ath_dbg(common, ATH_DBG_CONFIG,
1493 "Attach a VIF of type: %d\n", vif->type);
1494
4801416c
BG		 1495 sc->nvifs++;
1496
1497 ath9k_do_vif_add_setup(hw, vif);
1498out:
1499 mutex_unlock(&sc->mutex);
96f372c9 1500 ath9k_ps_restore(sc);
4801416c 1501 return ret;
6b3b991d
RM		 1502}
1503
1504static int ath9k_change_interface(struct ieee80211_hw *hw,
1505 struct ieee80211_vif *vif,
1506 enum nl80211_iftype new_type,
1507 bool p2p)
1508{
9ac58615 1509 struct ath_softc *sc = hw->priv;
6b3b991d 1510 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1511 int ret = 0;
6b3b991d
RM		 1512
1513 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1514 mutex_lock(&sc->mutex);
96f372c9 1515 ath9k_ps_wakeup(sc);
6b3b991d 1516
4801416c
BG		 1517 /* See if new interface type is valid. */
1518 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1519 (sc->nvifs > 1)) {
1520 ath_err(common, "When using ADHOC, it must be the only"
1521 " interface.\n");
1522 ret = -EINVAL;
1523 goto out;
1524 }
1525
1526 if (ath9k_uses_beacons(new_type) &&
1527 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM		 1528 if (sc->nbcnvifs >= ATH_BCBUF) {
1529 ath_err(common, "No beacon slot available\n");
6dab55bf
DC		 1530 ret = -ENOBUFS;
1531 goto out;
6b3b991d 1532 }
6b3b991d 1533 }
4801416c
BG		 1534
1535 /* Clean up old vif stuff */
1536 if (ath9k_uses_beacons(vif->type))
1537 ath9k_reclaim_beacon(sc, vif);
1538
1539 /* Add new settings */
6b3b991d
RM		 1540 vif->type = new_type;
1541 vif->p2p = p2p;
1542
4801416c 1543 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1544out:
96f372c9 1545 ath9k_ps_restore(sc);
6b3b991d 1546 mutex_unlock(&sc->mutex);
6dab55bf 1547 return ret;
6b3b991d
RM		 1548}
1549
8feceb67 1550static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1551 struct ieee80211_vif *vif)
f078f209 1552{
9ac58615 1553 struct ath_softc *sc = hw->priv;
c46917bb 1554 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1555
226afe68 1556 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1557
96f372c9 1558 ath9k_ps_wakeup(sc);
141b38b6
S		 1559 mutex_lock(&sc->mutex);
1560
4801416c 1561 sc->nvifs--;
580f0b8a 1562
8feceb67 1563 /* Reclaim beacon resources */
4801416c 1564 if (ath9k_uses_beacons(vif->type))
6b3b991d 1565 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1566
4801416c 1567 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S		 1568
1569 mutex_unlock(&sc->mutex);
96f372c9 1570 ath9k_ps_restore(sc);
f078f209
LR		 1571}
1572
fbab7390 1573static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1574{
3069168c
PR		 1575 struct ath_hw *ah = sc->sc_ah;
1576
3f7c5c10 1577 sc->ps_enabled = true;
3069168c
PR		 1578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1579 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1580 ah->imask |= ATH9K_INT_TIM_TIMER;
1581 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1582 }
fdf76622 1583 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1584 }
3f7c5c10
SB		 1585}
1586
845d708e
SB		 1587static void ath9k_disable_ps(struct ath_softc *sc)
1588{
1589 struct ath_hw *ah = sc->sc_ah;
1590
1591 sc->ps_enabled = false;
1592 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1593 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1594 ath9k_hw_setrxabort(ah, 0);
1595 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1596 PS_WAIT_FOR_CAB |
1597 PS_WAIT_FOR_PSPOLL_DATA |
1598 PS_WAIT_FOR_TX_ACK);
1599 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1600 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1601 ath9k_hw_set_interrupts(ah, ah->imask);
1602 }
1603 }
1604
1605}
1606
e8975581 1607static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1608{
9ac58615 1609 struct ath_softc *sc = hw->priv;
3430098a
FF		 1610 struct ath_hw *ah = sc->sc_ah;
1611 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1612 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1613 bool disable_radio = false;
f078f209 1614
aa33de09 1615 mutex_lock(&sc->mutex);
141b38b6 1616
194b7c13
LR		 1617 /*
1618 * Leave this as the first check because we need to turn on the
1619 * radio if it was disabled before prior to processing the rest
1620 * of the changes. Likewise we must only disable the radio towards
1621 * the end.
1622 */
64839170 1623 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF		 1624 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1625 if (!sc->ps_idle) {
68a89116 1626 ath_radio_enable(sc, hw);
226afe68
JP		 1627 ath_dbg(common, ATH_DBG_CONFIG,
1628 "not-idle: enabling radio\n");
7545daf4
FF		 1629 } else {
1630 disable_radio = true;
64839170
LR		 1631 }
1632 }
1633
e7824a50
LR		 1634 /*
1635 * We just prepare to enable PS. We have to wait until our AP has
1636 * ACK'd our null data frame to disable RX otherwise we'll ignore
1637 * those ACKs and end up retransmitting the same null data frames.
1638 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1639 */
3cbb5dd7 1640 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1641 unsigned long flags;
1642 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1643 if (conf->flags & IEEE80211_CONF_PS)
1644 ath9k_enable_ps(sc);
845d708e
SB		 1645 else
1646 ath9k_disable_ps(sc);
8ab2cd09 1647 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1648 }
1649
199afd9d
S		 1650 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1651 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP		 1652 ath_dbg(common, ATH_DBG_CONFIG,
1653 "Monitor mode is enabled\n");
5f841b41
RM		 1654 sc->sc_ah->is_monitoring = true;
1655 } else {
226afe68
JP		 1656 ath_dbg(common, ATH_DBG_CONFIG,
1657 "Monitor mode is disabled\n");
5f841b41 1658 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1659 }
1660 }
1661
4797938c 1662 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1663 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1664 int pos = curchan->hw_value;
3430098a
FF		 1665 int old_pos = -1;
1666 unsigned long flags;
1667
1668 if (ah->curchan)
1669 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1670
5ee08656
FF		 1671 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1672 sc->sc_flags |= SC_OP_OFFCHANNEL;
1673 else
1674 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1675
8c79a610
BG		 1676 ath_dbg(common, ATH_DBG_CONFIG,
1677 "Set channel: %d MHz type: %d\n",
1678 curchan->center_freq, conf->channel_type);
f078f209 1679
de87f736
RM		 1680 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1681 curchan, conf->channel_type);
e11602b7 1682
3430098a
FF		 1683 /* update survey stats for the old channel before switching */
1684 spin_lock_irqsave(&common->cc_lock, flags);
1685 ath_update_survey_stats(sc);
1686 spin_unlock_irqrestore(&common->cc_lock, flags);
1687
1688 /*
1689 * If the operating channel changes, change the survey in-use flags
1690 * along with it.
1691 * Reset the survey data for the new channel, unless we're switching
1692 * back to the operating channel from an off-channel operation.
1693 */
1694 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1695 sc->cur_survey != &sc->survey[pos]) {
1696
1697 if (sc->cur_survey)
1698 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1699
1700 sc->cur_survey = &sc->survey[pos];
1701
1702 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1703 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1704 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1705 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1706 }
1707
0e2dedf9 1708 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1709 ath_err(common, "Unable to set channel\n");
aa33de09 1710 mutex_unlock(&sc->mutex);
e11602b7
S		 1711 return -EINVAL;
1712 }
3430098a
FF		 1713
1714 /*
1715 * The most recent snapshot of channel->noisefloor for the old
1716 * channel is only available after the hardware reset. Copy it to
1717 * the survey stats now.
1718 */
1719 if (old_pos >= 0)
1720 ath_update_survey_nf(sc, old_pos);
094d05dc 1721 }
f078f209 1722
c9f6a656 1723 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG		 1724 ath_dbg(common, ATH_DBG_CONFIG,
1725 "Set power: %d\n", conf->power_level);
17d7904d 1726 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1727 ath9k_ps_wakeup(sc);
5048e8c3
RM		 1728 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1729 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1730 ath9k_ps_restore(sc);
c9f6a656 1731 }
f078f209 1732
64839170 1733 if (disable_radio) {
226afe68 1734 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1735 ath_radio_disable(sc, hw);
64839170
LR		 1736 }
1737
aa33de09 1738 mutex_unlock(&sc->mutex);
141b38b6 1739
f078f209
LR		 1740 return 0;
1741}
1742
8feceb67
VT		 1743#define SUPPORTED_FILTERS \
1744 (FIF_PROMISC_IN_BSS | \
1745 FIF_ALLMULTI | \
1746 FIF_CONTROL | \
af6a3fc7 1747 FIF_PSPOLL | \
8feceb67
VT		 1748 FIF_OTHER_BSS | \
1749 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1750 FIF_PROBE_REQ | \
8feceb67 1751 FIF_FCSFAIL)
c83be688 1752
8feceb67
VT		 1753/* FIXME: sc->sc_full_reset ? */
1754static void ath9k_configure_filter(struct ieee80211_hw *hw,
1755 unsigned int changed_flags,
1756 unsigned int *total_flags,
3ac64bee 1757 u64 multicast)
8feceb67 1758{
9ac58615 1759 struct ath_softc *sc = hw->priv;
8feceb67 1760 u32 rfilt;
f078f209 1761
8feceb67
VT		 1762 changed_flags &= SUPPORTED_FILTERS;
1763 *total_flags &= SUPPORTED_FILTERS;
f078f209 1764
b77f483f 1765 sc->rx.rxfilter = *total_flags;
aa68aeaa 1766 ath9k_ps_wakeup(sc);
8feceb67
VT		 1767 rfilt = ath_calcrxfilter(sc);
1768 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1769 ath9k_ps_restore(sc);
f078f209 1770
226afe68
JP		 1771 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1772 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1773}
f078f209 1774
4ca77860
JB		 1775static int ath9k_sta_add(struct ieee80211_hw *hw,
1776 struct ieee80211_vif *vif,
1777 struct ieee80211_sta *sta)
8feceb67 1778{
9ac58615 1779 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1781 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1782 struct ieee80211_key_conf ps_key = { };
f078f209 1783
4ca77860 1784 ath_node_attach(sc, sta);
f59a59fe
FF		 1785
1786 if (vif->type != NL80211_IFTYPE_AP &&
1787 vif->type != NL80211_IFTYPE_AP_VLAN)
1788 return 0;
1789
93ae2dd2 1790 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB		 1791
1792 return 0;
1793}
1794
93ae2dd2
FF		 1795static void ath9k_del_ps_key(struct ath_softc *sc,
1796 struct ieee80211_vif *vif,
1797 struct ieee80211_sta *sta)
1798{
1799 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1800 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1801 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1802
1803 if (!an->ps_key)
1804 return;
1805
1806 ath_key_delete(common, &ps_key);
1807}
1808
4ca77860
JB		 1809static int ath9k_sta_remove(struct ieee80211_hw *hw,
1810 struct ieee80211_vif *vif,
1811 struct ieee80211_sta *sta)
1812{
9ac58615 1813 struct ath_softc *sc = hw->priv;
4ca77860 1814
93ae2dd2 1815 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1816 ath_node_detach(sc, sta);
1817
1818 return 0;
f078f209
LR		 1819}
1820
5519541d
FF		 1821static void ath9k_sta_notify(struct ieee80211_hw *hw,
1822 struct ieee80211_vif *vif,
1823 enum sta_notify_cmd cmd,
1824 struct ieee80211_sta *sta)
1825{
1826 struct ath_softc *sc = hw->priv;
1827 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1828
1829 switch (cmd) {
1830 case STA_NOTIFY_SLEEP:
1831 an->sleeping = true;
1832 if (ath_tx_aggr_sleep(sc, an))
1833 ieee80211_sta_set_tim(sta);
1834 break;
1835 case STA_NOTIFY_AWAKE:
1836 an->sleeping = false;
1837 ath_tx_aggr_wakeup(sc, an);
1838 break;
1839 }
1840}
1841
141b38b6 1842static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1843 const struct ieee80211_tx_queue_params *params)
f078f209 1844{
9ac58615 1845 struct ath_softc *sc = hw->priv;
c46917bb 1846 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1847 struct ath_txq *txq;
8feceb67 1848 struct ath9k_tx_queue_info qi;
066dae93 1849 int ret = 0;
f078f209 1850
8feceb67
VT		 1851 if (queue >= WME_NUM_AC)
1852 return 0;
f078f209 1853
066dae93
FF		 1854 txq = sc->tx.txq_map[queue];
1855
96f372c9 1856 ath9k_ps_wakeup(sc);
141b38b6
S		 1857 mutex_lock(&sc->mutex);
1858
1ffb0610
S		 1859 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1860
8feceb67
VT		 1861 qi.tqi_aifs = params->aifs;
1862 qi.tqi_cwmin = params->cw_min;
1863 qi.tqi_cwmax = params->cw_max;
1864 qi.tqi_burstTime = params->txop;
f078f209 1865
226afe68
JP		 1866 ath_dbg(common, ATH_DBG_CONFIG,
1867 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1868 queue, txq->axq_qnum, params->aifs, params->cw_min,
1869 params->cw_max, params->txop);
f078f209 1870
066dae93 1871 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1872 if (ret)
3800276a 1873 ath_err(common, "TXQ Update failed\n");
f078f209 1874
94db2936 1875 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1876 if (queue == WME_AC_BE && !ret)
94db2936
VN		 1877 ath_beaconq_config(sc);
1878
141b38b6 1879 mutex_unlock(&sc->mutex);
96f372c9 1880 ath9k_ps_restore(sc);
141b38b6 1881
8feceb67
VT		 1882 return ret;
1883}
f078f209 1884
8feceb67
VT		 1885static int ath9k_set_key(struct ieee80211_hw *hw,
1886 enum set_key_cmd cmd,
dc822b5d
JB		 1887 struct ieee80211_vif *vif,
1888 struct ieee80211_sta *sta,
8feceb67
VT		 1889 struct ieee80211_key_conf *key)
1890{
9ac58615 1891 struct ath_softc *sc = hw->priv;
c46917bb 1892 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1893 int ret = 0;
f078f209 1894
3e6109c5 1895 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1896 return -ENOSPC;
1897
cfdc9a8b
JM		 1898 if (vif->type == NL80211_IFTYPE_ADHOC &&
1899 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1900 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1901 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1902 /*
1903 * For now, disable hw crypto for the RSN IBSS group keys. This
1904 * could be optimized in the future to use a modified key cache
1905 * design to support per-STA RX GTK, but until that gets
1906 * implemented, use of software crypto for group addressed
1907 * frames is a acceptable to allow RSN IBSS to be used.
1908 */
1909 return -EOPNOTSUPP;
1910 }
1911
141b38b6 1912 mutex_lock(&sc->mutex);
3cbb5dd7 1913 ath9k_ps_wakeup(sc);
226afe68 1914 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1915
8feceb67
VT		 1916 switch (cmd) {
1917 case SET_KEY:
93ae2dd2
FF		 1918 if (sta)
1919 ath9k_del_ps_key(sc, vif, sta);
1920
040e539e 1921 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1922 if (ret >= 0) {
1923 key->hw_key_idx = ret;
8feceb67
VT		 1924 /* push IV and Michael MIC generation to stack */
1925 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1926 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1927 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1928 if (sc->sc_ah->sw_mgmt_crypto &&
1929 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1930 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1931 ret = 0;
8feceb67
VT		 1932 }
1933 break;
1934 case DISABLE_KEY:
040e539e 1935 ath_key_delete(common, key);
8feceb67
VT		 1936 break;
1937 default:
1938 ret = -EINVAL;
1939 }
f078f209 1940
3cbb5dd7 1941 ath9k_ps_restore(sc);
141b38b6
S		 1942 mutex_unlock(&sc->mutex);
1943
8feceb67
VT		 1944 return ret;
1945}
4f5ef75b
RM		 1946static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1947{
1948 struct ath_softc *sc = data;
1949 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1950 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1951 struct ath_vif *avp = (void *)vif->drv_priv;
1952
1953 switch (sc->sc_ah->opmode) {
1954 case NL80211_IFTYPE_ADHOC:
1955 /* There can be only one vif available */
1956 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1957 common->curaid = bss_conf->aid;
1958 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM		 1959 /* configure beacon */
1960 if (bss_conf->enable_beacon)
1961 ath_beacon_config(sc, vif);
4f5ef75b
RM		 1962 break;
1963 case NL80211_IFTYPE_STATION:
1964 /*
1965 * Skip iteration if primary station vif's bss info
1966 * was not changed
1967 */
1968 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1969 break;
1970
1971 if (bss_conf->assoc) {
1972 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1973 avp->primary_sta_vif = true;
1974 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1975 common->curaid = bss_conf->aid;
1976 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM		 1977 ath_dbg(common, ATH_DBG_CONFIG,
1978 "Bss Info ASSOC %d, bssid: %pM\n",
1979 bss_conf->aid, common->curbssid);
1980 ath_beacon_config(sc, vif);
92c6f76c
RM		 1981 /*
1982 * Request a re-configuration of Beacon related timers
1983 * on the receipt of the first Beacon frame (i.e.,
1984 * after time sync with the AP).
1985 */
1986 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
99e4d43a
RM		 1987 /* Reset rssi stats */
1988 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1989 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1990
1991 sc->sc_flags |= SC_OP_ANI_RUN;
1992 ath_start_ani(common);
4f5ef75b
RM		 1993 }
1994 break;
1995 default:
1996 break;
1997 }
1998}
1999
2000static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2001{
2002 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2003 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2004 struct ath_vif *avp = (void *)vif->drv_priv;
2005
2006 /* Reconfigure bss info */
2007 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM		 2008 ath_dbg(common, ATH_DBG_CONFIG,
2009 "Bss Info DISASSOC %d, bssid %pM\n",
2010 common->curaid, common->curbssid);
2011 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM		 2012 avp->primary_sta_vif = false;
2013 memset(common->curbssid, 0, ETH_ALEN);
2014 common->curaid = 0;
2015 }
2016
2017 ieee80211_iterate_active_interfaces_atomic(
2018 sc->hw, ath9k_bss_iter, sc);
2019
2020 /*
2021 * None of station vifs are associated.
2022 * Clear bssid & aid
2023 */
2024 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
99e4d43a 2025 !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2026 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM		 2027 /* Stop ANI */
2028 sc->sc_flags &= ~SC_OP_ANI_RUN;
2029 del_timer_sync(&common->ani.timer);
2030 }
4f5ef75b 2031}
f078f209 2032
8feceb67
VT		 2033static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2034 struct ieee80211_vif *vif,
2035 struct ieee80211_bss_conf *bss_conf,
2036 u32 changed)
2037{
9ac58615 2038 struct ath_softc *sc = hw->priv;
2d0ddec5 2039 struct ath_hw *ah = sc->sc_ah;
1510718d 2040 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2041 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2042 int slottime;
c6089ccc 2043 int error;
f078f209 2044
96f372c9 2045 ath9k_ps_wakeup(sc);
141b38b6
S		 2046 mutex_lock(&sc->mutex);
2047
c6089ccc 2048 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2049 ath9k_config_bss(sc, vif);
2d0ddec5 2050
226afe68
JP		 2051 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2052 common->curbssid, common->curaid);
c6089ccc 2053 }
2d0ddec5 2054
c6089ccc
S		 2055 /* Enable transmission of beacons (AP, IBSS, MESH) */
2056 if ((changed & BSS_CHANGED_BEACON) ||
2057 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2058 ath9k_set_beaconing_status(sc, false);
9ac58615 2059 error = ath_beacon_alloc(sc, vif);
c6089ccc
S		 2060 if (!error)
2061 ath_beacon_config(sc, vif);
014cf3bb 2062 ath9k_set_beaconing_status(sc, true);
0005baf4
FF		 2063 }
2064
2065 if (changed & BSS_CHANGED_ERP_SLOT) {
2066 if (bss_conf->use_short_slot)
2067 slottime = 9;
2068 else
2069 slottime = 20;
2070 if (vif->type == NL80211_IFTYPE_AP) {
2071 /*
2072 * Defer update, so that connected stations can adjust
2073 * their settings at the same time.
2074 * See beacon.c for more details
2075 */
2076 sc->beacon.slottime = slottime;
2077 sc->beacon.updateslot = UPDATE;
2078 } else {
2079 ah->slottime = slottime;
2080 ath9k_hw_init_global_settings(ah);
2081 }
2d0ddec5
JB		 2082 }
2083
c6089ccc 2084 /* Disable transmission of beacons */
014cf3bb
RM		 2085 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2086 !bss_conf->enable_beacon) {
2087 ath9k_set_beaconing_status(sc, false);
2088 avp->is_bslot_active = false;
2089 ath9k_set_beaconing_status(sc, true);
2090 }
2d0ddec5 2091
c6089ccc 2092 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S		 2093 /*
2094 * In case of AP mode, the HW TSF has to be reset
2095 * when the beacon interval changes.
2096 */
2097 if (vif->type == NL80211_IFTYPE_AP) {
2098 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2099 ath9k_set_beaconing_status(sc, false);
9ac58615 2100 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB		 2101 if (!error)
2102 ath_beacon_config(sc, vif);
014cf3bb 2103 ath9k_set_beaconing_status(sc, true);
99e4d43a 2104 } else
c6089ccc 2105 ath_beacon_config(sc, vif);
2d0ddec5
JB		 2106 }
2107
8feceb67 2108 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP		 2109 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2110 bss_conf->use_short_preamble);
8feceb67
VT		 2111 if (bss_conf->use_short_preamble)
2112 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2113 else
2114 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2115 }
f078f209 2116
8feceb67 2117 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP		 2118 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2119 bss_conf->use_cts_prot);
8feceb67
VT		 2120 if (bss_conf->use_cts_prot &&
2121 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2122 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2123 else
2124 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2125 }
f078f209 2126
141b38b6 2127 mutex_unlock(&sc->mutex);
96f372c9 2128 ath9k_ps_restore(sc);
8feceb67 2129}
f078f209 2130
8feceb67
VT		 2131static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2132{
9ac58615 2133 struct ath_softc *sc = hw->priv;
8feceb67 2134 u64 tsf;
f078f209 2135
141b38b6 2136 mutex_lock(&sc->mutex);
9abbfb27 2137 ath9k_ps_wakeup(sc);
141b38b6 2138 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2139 ath9k_ps_restore(sc);
141b38b6 2140 mutex_unlock(&sc->mutex);
f078f209 2141
8feceb67
VT		 2142 return tsf;
2143}
f078f209 2144
3b5d665b
AF		 2145static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2146{
9ac58615 2147 struct ath_softc *sc = hw->priv;
3b5d665b 2148
141b38b6 2149 mutex_lock(&sc->mutex);
9abbfb27 2150 ath9k_ps_wakeup(sc);
141b38b6 2151 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2152 ath9k_ps_restore(sc);
141b38b6 2153 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2154}
2155
8feceb67
VT		 2156static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2157{
9ac58615 2158 struct ath_softc *sc = hw->priv;
c83be688 2159
141b38b6 2160 mutex_lock(&sc->mutex);
21526d57
LR		 2161
2162 ath9k_ps_wakeup(sc);
141b38b6 2163 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 2164 ath9k_ps_restore(sc);
2165
141b38b6 2166 mutex_unlock(&sc->mutex);
8feceb67 2167}
f078f209 2168
8feceb67 2169static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2170 struct ieee80211_vif *vif,
141b38b6
S		 2171 enum ieee80211_ampdu_mlme_action action,
2172 struct ieee80211_sta *sta,
0b01f030 2173 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2174{
9ac58615 2175 struct ath_softc *sc = hw->priv;
8feceb67 2176 int ret = 0;
f078f209 2177
85ad181e
JB		 2178 local_bh_disable();
2179
8feceb67
VT		 2180 switch (action) {
2181 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2182 if (!(sc->sc_flags & SC_OP_RXAGGR))
2183 ret = -ENOTSUPP;
8feceb67
VT		 2184 break;
2185 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2186 break;
2187 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF		 2188 if (!(sc->sc_flags & SC_OP_TXAGGR))
2189 return -EOPNOTSUPP;
2190
8b685ba9 2191 ath9k_ps_wakeup(sc);
231c3a1f
FF		 2192 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2193 if (!ret)
2194 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2195 ath9k_ps_restore(sc);
8feceb67
VT		 2196 break;
2197 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2198 ath9k_ps_wakeup(sc);
f83da965 2199 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2200 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2201 ath9k_ps_restore(sc);
8feceb67 2202 break;
b1720231 2203 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2204 ath9k_ps_wakeup(sc);
8469cdef 2205 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2206 ath9k_ps_restore(sc);
8469cdef 2207 break;
8feceb67 2208 default:
3800276a 2209 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 2210 }
2211
85ad181e
JB		 2212 local_bh_enable();
2213
8feceb67 2214 return ret;
f078f209
LR		 2215}
2216
62dad5b0
BP		 2217static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2218 struct survey_info *survey)
2219{
9ac58615 2220 struct ath_softc *sc = hw->priv;
3430098a 2221 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2222 struct ieee80211_supported_band *sband;
3430098a
FF		 2223 struct ieee80211_channel *chan;
2224 unsigned long flags;
2225 int pos;
2226
2227 spin_lock_irqsave(&common->cc_lock, flags);
2228 if (idx == 0)
2229 ath_update_survey_stats(sc);
39162dbe
FF		 2230
2231 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2232 if (sband && idx >= sband->n_channels) {
2233 idx -= sband->n_channels;
2234 sband = NULL;
2235 }
62dad5b0 2236
39162dbe
FF		 2237 if (!sband)
2238 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2239
3430098a
FF		 2240 if (!sband || idx >= sband->n_channels) {
2241 spin_unlock_irqrestore(&common->cc_lock, flags);
2242 return -ENOENT;
4f1a5a4b 2243 }
62dad5b0 2244
3430098a
FF		 2245 chan = &sband->channels[idx];
2246 pos = chan->hw_value;
2247 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2248 survey->channel = chan;
2249 spin_unlock_irqrestore(&common->cc_lock, flags);
2250
62dad5b0
BP		 2251 return 0;
2252}
2253
e239d859
FF		 2254static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2255{
9ac58615 2256 struct ath_softc *sc = hw->priv;
e239d859
FF		 2257 struct ath_hw *ah = sc->sc_ah;
2258
2259 mutex_lock(&sc->mutex);
2260 ah->coverage_class = coverage_class;
2261 ath9k_hw_init_global_settings(ah);
2262 mutex_unlock(&sc->mutex);
2263}
2264
69081624
VT		 2265static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2266{
69081624 2267 struct ath_softc *sc = hw->priv;
86271e46
FF		 2268 int timeout = 200; /* ms */
2269 int i, j;
2f6fc351 2270 bool drain_txq;
69081624
VT		 2271
2272 mutex_lock(&sc->mutex);
69081624
VT		 2273 cancel_delayed_work_sync(&sc->tx_complete_work);
2274
86271e46
FF		 2275 if (drop)
2276 timeout = 1;
69081624 2277
86271e46
FF		 2278 for (j = 0; j < timeout; j++) {
2279 int npend = 0;
2280
2281 if (j)
2282 usleep_range(1000, 2000);
69081624 2283
86271e46
FF		 2284 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2285 if (!ATH_TXQ_SETUP(sc, i))
2286 continue;
2287
2288 npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
69081624 2289 }
86271e46
FF		 2290
2291 if (!npend)
2292 goto out;
69081624
VT		 2293 }
2294
51513906 2295 ath9k_ps_wakeup(sc);
2f6fc351
RM		 2296 spin_lock_bh(&sc->sc_pcu_lock);
2297 drain_txq = ath_drain_all_txq(sc, false);
2298 spin_unlock_bh(&sc->sc_pcu_lock);
2299 if (!drain_txq)
69081624 2300 ath_reset(sc, false);
51513906 2301 ath9k_ps_restore(sc);
d78f4b3e
SB		 2302 ieee80211_wake_queues(hw);
2303
86271e46 2304out:
69081624
VT		 2305 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2306 mutex_unlock(&sc->mutex);
2307}
2308
15b91e83
VN		 2309static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2310{
2311 struct ath_softc *sc = hw->priv;
2312 int i;
2313
2314 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2315 if (!ATH_TXQ_SETUP(sc, i))
2316 continue;
2317
2318 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2319 return true;
2320 }
2321 return false;
2322}
2323
6baff7f9 2324struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2325 .tx = ath9k_tx,
2326 .start = ath9k_start,
2327 .stop = ath9k_stop,
2328 .add_interface = ath9k_add_interface,
6b3b991d 2329 .change_interface = ath9k_change_interface,
8feceb67
VT		 2330 .remove_interface = ath9k_remove_interface,
2331 .config = ath9k_config,
8feceb67 2332 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2333 .sta_add = ath9k_sta_add,
2334 .sta_remove = ath9k_sta_remove,
5519541d 2335 .sta_notify = ath9k_sta_notify,
8feceb67 2336 .conf_tx = ath9k_conf_tx,
8feceb67 2337 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2338 .set_key = ath9k_set_key,
8feceb67 2339 .get_tsf = ath9k_get_tsf,
3b5d665b 2340 .set_tsf = ath9k_set_tsf,
8feceb67 2341 .reset_tsf = ath9k_reset_tsf,
4233df6b 2342 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2343 .get_survey = ath9k_get_survey,
3b319aae 2344 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2345 .set_coverage_class = ath9k_set_coverage_class,
69081624 2346 .flush = ath9k_flush,
15b91e83 2347 .tx_frames_pending = ath9k_tx_frames_pending,
8feceb67 2348};
kernel source for telekom puls (alcatel/mediatek)