[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / ar9003_mac.c

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
#include "hw.h"
#include "ar9003_mac.h"

static void ar9003_hw_rx_enable(struct ath_hw *hw)
{
	REG_WRITE(hw, AR_CR, 0);
}

static void
ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
{
	struct ar9003_txc *ads = ds;
	int checksum = 0;
	u32 val, ctl12, ctl17;

	val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
	      (1 << AR_TxRxDesc_S) |
	      (1 << AR_CtrlStat_S) |
	      (i->qcu << AR_TxQcuNum_S) | 0x17;

	checksum += val;
	ACCESS_ONCE(ads->info) = val;

	checksum += i->link;
	ACCESS_ONCE(ads->link) = i->link;

	checksum += i->buf_addr[0];
	ACCESS_ONCE(ads->data0) = i->buf_addr[0];
	checksum += i->buf_addr[1];
	ACCESS_ONCE(ads->data1) = i->buf_addr[1];
	checksum += i->buf_addr[2];
	ACCESS_ONCE(ads->data2) = i->buf_addr[2];
	checksum += i->buf_addr[3];
	ACCESS_ONCE(ads->data3) = i->buf_addr[3];

	checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen);
	ACCESS_ONCE(ads->ctl3) = val;
	checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen);
	ACCESS_ONCE(ads->ctl5) = val;
	checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen);
	ACCESS_ONCE(ads->ctl7) = val;
	checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen);
	ACCESS_ONCE(ads->ctl9) = val;

	checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff);
	ACCESS_ONCE(ads->ctl10) = checksum;

	if (i->is_first || i->is_last) {
		ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0)
			| set11nTries(i->rates, 1)
			| set11nTries(i->rates, 2)
			| set11nTries(i->rates, 3)
			| (i->dur_update ? AR_DurUpdateEna : 0)
			| SM(0, AR_BurstDur);

		ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0)
			| set11nRate(i->rates, 1)
			| set11nRate(i->rates, 2)
			| set11nRate(i->rates, 3);
	} else {
		ACCESS_ONCE(ads->ctl13) = 0;
		ACCESS_ONCE(ads->ctl14) = 0;
	}

	ads->ctl20 = 0;
	ads->ctl21 = 0;
	ads->ctl22 = 0;

	ctl17 = SM(i->keytype, AR_EncrType);
	if (!i->is_first) {
		ACCESS_ONCE(ads->ctl11) = 0;
		ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore;
		ACCESS_ONCE(ads->ctl15) = 0;
		ACCESS_ONCE(ads->ctl16) = 0;
		ACCESS_ONCE(ads->ctl17) = ctl17;
		ACCESS_ONCE(ads->ctl18) = 0;
		ACCESS_ONCE(ads->ctl19) = 0;
		return;
	}

	ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen)
		| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
		| SM(i->txpower, AR_XmitPower)
		| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
		| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
		| (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0)
		| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
		| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
		   (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));

	ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ?
		 SM(i->keyix, AR_DestIdx) : 0)
		| SM(i->type, AR_FrameType)
		| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
		| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
		| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);

	ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
	switch (i->aggr) {
	case AGGR_BUF_FIRST:
		ctl17 |= SM(i->aggr_len, AR_AggrLen);
		/* fall through */
	case AGGR_BUF_MIDDLE:
		ctl12 |= AR_IsAggr | AR_MoreAggr;
		ctl17 |= SM(i->ndelim, AR_PadDelim);
		break;
	case AGGR_BUF_LAST:
		ctl12 |= AR_IsAggr;
		break;
	case AGGR_BUF_NONE:
		break;
	}

	val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S;
	ctl12 |= SM(val, AR_PAPRDChainMask);

	ACCESS_ONCE(ads->ctl12) = ctl12;
	ACCESS_ONCE(ads->ctl17) = ctl17;

	ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0)
		| set11nPktDurRTSCTS(i->rates, 1);

	ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2)
		| set11nPktDurRTSCTS(i->rates, 3);

	ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0)
		| set11nRateFlags(i->rates, 1)
		| set11nRateFlags(i->rates, 2)
		| set11nRateFlags(i->rates, 3)
		| SM(i->rtscts_rate, AR_RTSCTSRate);

	ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding;
}

static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
{
	int checksum;

	checksum = ads->info + ads->link
		+ ads->data0 + ads->ctl3
		+ ads->data1 + ads->ctl5
		+ ads->data2 + ads->ctl7
		+ ads->data3 + ads->ctl9;

	return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
}

static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
{
	struct ar9003_txc *ads = ds;

	ads->link = ds_link;
	ads->ctl10 &= ~AR_TxPtrChkSum;
	ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
}

static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
{
	u32 isr = 0;
	u32 mask2 = 0;
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u32 sync_cause = 0;
	struct ath_common *common = ath9k_hw_common(ah);

	if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
		if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
				== AR_RTC_STATUS_ON)
			isr = REG_READ(ah, AR_ISR);
	}

	sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;

	*masked = 0;

	if (!isr && !sync_cause)
		return false;

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);

			mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
				  MAP_ISR_S2_TIM);
			mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
				  MAP_ISR_S2_DTIM);
			mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
				  MAP_ISR_S2_DTIMSYNC);
			mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
				  MAP_ISR_S2_CABEND);
			mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
				  MAP_ISR_S2_GTT);
			mask2 |= ((isr2 & AR_ISR_S2_CST) <<
				  MAP_ISR_S2_CST);
			mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
				  MAP_ISR_S2_TSFOOR);
			mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
				  MAP_ISR_S2_BB_WATCHDOG);

			if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
				REG_WRITE(ah, AR_ISR_S2, isr2);
				isr &= ~AR_ISR_BCNMISC;
			}
		}

		if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
			isr = REG_READ(ah, AR_ISR_RAC);

		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

		if (ah->config.rx_intr_mitigation)
			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
				*masked |= ATH9K_INT_RXLP;

		if (ah->config.tx_intr_mitigation)
			if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
				*masked |= ATH9K_INT_TX;

		if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RXLP;

		if (isr & AR_ISR_HP_RXOK)
			*masked |= ATH9K_INT_RXHP;

		if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
			*masked |= ATH9K_INT_TX;

			if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
				u32 s0, s1;
				s0 = REG_READ(ah, AR_ISR_S0);
				REG_WRITE(ah, AR_ISR_S0, s0);
				s1 = REG_READ(ah, AR_ISR_S1);
				REG_WRITE(ah, AR_ISR_S1, s1);

				isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
					 AR_ISR_TXEOL);
			}
		}

		if (isr & AR_ISR_GENTMR) {
			u32 s5;

			if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
				s5 = REG_READ(ah, AR_ISR_S5_S);
			else
				s5 = REG_READ(ah, AR_ISR_S5);

			ah->intr_gen_timer_trigger =
				MS(s5, AR_ISR_S5_GENTIMER_TRIG);

			ah->intr_gen_timer_thresh =
				MS(s5, AR_ISR_S5_GENTIMER_THRESH);

			if (ah->intr_gen_timer_trigger)
				*masked |= ATH9K_INT_GENTIMER;

			if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
				REG_WRITE(ah, AR_ISR_S5, s5);
				isr &= ~AR_ISR_GENTMR;
			}

		}

		*masked |= mask2;

		if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
			REG_WRITE(ah, AR_ISR, isr);

			(void) REG_READ(ah, AR_ISR);
		}

		if (*masked & ATH9K_INT_BB_WATCHDOG)
			ar9003_hw_bb_watchdog_read(ah);
	}

	if (sync_cause) {
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}

		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
			ath_dbg(common, ATH_DBG_INTERRUPT,
				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);

	}
	return true;
}

static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
				 struct ath_tx_status *ts)
{
	struct ar9003_txc *txc = (struct ar9003_txc *) ds;
	struct ar9003_txs *ads;
	u32 status;

	ads = &ah->ts_ring[ah->ts_tail];

	status = ACCESS_ONCE(ads->status8);
	if ((status & AR_TxDone) == 0)
		return -EINPROGRESS;

	ts->qid = MS(ads->ds_info, AR_TxQcuNum);
	if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid))
		ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
	else
		return -ENOENT;

	if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
	    (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
			"Tx Descriptor error %x\n", ads->ds_info);
		memset(ads, 0, sizeof(*ads));
		return -EIO;
	}

	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	ts->ts_seqnum = MS(status, AR_SeqNum);
	ts->tid = MS(status, AR_TxTid);

	ts->desc_id = MS(ads->status1, AR_TxDescId);
	ts->ts_tstamp = ads->status4;
	ts->ts_status = 0;
	ts->ts_flags  = 0;

	if (status & AR_TxOpExceeded)
		ts->ts_status |= ATH9K_TXERR_XTXOP;
	status = ACCESS_ONCE(ads->status2);
	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	if (status & AR_TxBaStatus) {
		ts->ts_flags |= ATH9K_TX_BA;
		ts->ba_low = ads->status5;
		ts->ba_high = ads->status6;
	}

	status = ACCESS_ONCE(ads->status3);
	if (status & AR_ExcessiveRetries)
		ts->ts_status |= ATH9K_TXERR_XRETRY;
	if (status & AR_Filtered)
		ts->ts_status |= ATH9K_TXERR_FILT;
	if (status & AR_FIFOUnderrun) {
		ts->ts_status |= ATH9K_TXERR_FIFO;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	if (status & AR_TxTimerExpired)
		ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
	if (status & AR_DescCfgErr)
		ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
	if (status & AR_TxDataUnderrun) {
		ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	if (status & AR_TxDelimUnderrun) {
		ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	ts->ts_longretry = MS(status, AR_DataFailCnt);
	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);

	status = ACCESS_ONCE(ads->status7);
	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);

	memset(ads, 0, sizeof(*ads));

	return 0;
}

void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
{
	struct ath_hw_ops *ops = ath9k_hw_ops(hw);

	ops->rx_enable = ar9003_hw_rx_enable;
	ops->set_desc_link = ar9003_hw_set_desc_link;
	ops->get_isr = ar9003_hw_get_isr;
	ops->set_txdesc = ar9003_set_txdesc;
	ops->proc_txdesc = ar9003_hw_proc_txdesc;
}

void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
{
	REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
}
EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);

void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
			    enum ath9k_rx_qtype qtype)
{
	if (qtype == ATH9K_RX_QUEUE_HP)
		REG_WRITE(ah, AR_HP_RXDP, rxdp);
	else
		REG_WRITE(ah, AR_LP_RXDP, rxdp);
}
EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);

int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
				 void *buf_addr)
{
	struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
	unsigned int phyerr;

	/* TODO: byte swap on big endian for ar9300_10 */

	if (!rxs) {
		if ((rxsp->status11 & AR_RxDone) == 0)
			return -EINPROGRESS;

		if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
			return -EINVAL;

		if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
			return -EINPROGRESS;

		return 0;
	}

	rxs->rs_status = 0;
	rxs->rs_flags =  0;

	rxs->rs_datalen = rxsp->status2 & AR_DataLen;
	rxs->rs_tstamp =  rxsp->status3;

	/* XXX: Keycache */
	rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
	rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
	rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
	rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
	rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
	rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
	rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);

	if (rxsp->status11 & AR_RxKeyIdxValid)
		rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
	else
		rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;

	rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
	rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;

	rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
	rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
	rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
	rxs->rs_flags  = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
	rxs->rs_flags  |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;

	rxs->evm0 = rxsp->status6;
	rxs->evm1 = rxsp->status7;
	rxs->evm2 = rxsp->status8;
	rxs->evm3 = rxsp->status9;
	rxs->evm4 = (rxsp->status10 & 0xffff);

	if (rxsp->status11 & AR_PreDelimCRCErr)
		rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;

	if (rxsp->status11 & AR_PostDelimCRCErr)
		rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;

	if (rxsp->status11 & AR_DecryptBusyErr)
		rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;

	if ((rxsp->status11 & AR_RxFrameOK) == 0) {
		/*
		 * AR_CRCErr will bet set to true if we're on the last
		 * subframe and the AR_PostDelimCRCErr is caught.
		 * In a way this also gives us a guarantee that when
		 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
		 * possibly be reviewing the last subframe. AR_CRCErr
		 * is the CRC of the actual data.
		 */
		if (rxsp->status11 & AR_CRCErr)
			rxs->rs_status |= ATH9K_RXERR_CRC;
		else if (rxsp->status11 & AR_PHYErr) {
			phyerr = MS(rxsp->status11, AR_PHYErrCode);
			/*
			 * If we reach a point here where AR_PostDelimCRCErr is
			 * true it implies we're *not* on the last subframe. In
			 * in that case that we know already that the CRC of
			 * the frame was OK, and MAC would send an ACK for that
			 * subframe, even if we did get a phy error of type
			 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
			 * to frame that are prior to the last subframe.
			 * The AR_PostDelimCRCErr is the CRC for the MPDU
			 * delimiter, which contains the 4 reserved bits,
			 * the MPDU length (12 bits), and follows the MPDU
			 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
			 */
			if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
			    (rxsp->status11 & AR_PostDelimCRCErr)) {
				rxs->rs_phyerr = 0;
			} else {
				rxs->rs_status |= ATH9K_RXERR_PHY;
				rxs->rs_phyerr = phyerr;
			}

		} else if (rxsp->status11 & AR_DecryptCRCErr)
			rxs->rs_status |= ATH9K_RXERR_DECRYPT;
		else if (rxsp->status11 & AR_MichaelErr)
			rxs->rs_status |= ATH9K_RXERR_MIC;
		else if (rxsp->status11 & AR_KeyMiss)
			rxs->rs_status |= ATH9K_RXERR_DECRYPT;
	}

	return 0;
}
EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);

void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
{
	ah->ts_tail = 0;

	memset((void *) ah->ts_ring, 0,
		ah->ts_size * sizeof(struct ar9003_txs));

	ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
		"TS Start 0x%x End 0x%x Virt %p, Size %d\n",
		ah->ts_paddr_start, ah->ts_paddr_end,
		ah->ts_ring, ah->ts_size);

	REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
	REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
}

void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
			       u32 ts_paddr_start,
			       u8 size)
{

	ah->ts_paddr_start = ts_paddr_start;
	ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
	ah->ts_size = size;
	ah->ts_ring = (struct ar9003_txs *) ts_start;

	ath9k_hw_reset_txstatus_ring(ah);
}
EXPORT_SYMBOL(ath9k_hw_setup_statusring);
Commit	Line	Data
ae3bb6d4	1	/*
5b68138e	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
ae3bb6d4 VT	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16	#include "hw.h"
b622a720	17	#include "ar9003_mac.h"
ae3bb6d4 VT	18
	19	static void ar9003_hw_rx_enable(struct ath_hw *hw)
	20	{
	21	REG_WRITE(hw, AR_CR, 0);
	22	}
	23
2b63a41d FF	24	static void
	25	ar9003_set_txdesc(struct ath_hw ah, void ds, struct ath_tx_info *i)
	26	{
	27	struct ar9003_txc *ads = ds;
	28	int checksum = 0;
	29	u32 val, ctl12, ctl17;
	30
	31	val = (ATHEROS_VENDOR_ID << AR_DescId_S) \|
	32	(1 << AR_TxRxDesc_S) \|
	33	(1 << AR_CtrlStat_S) \|
	34	(i->qcu << AR_TxQcuNum_S) \| 0x17;
	35
	36	checksum += val;
	37	ACCESS_ONCE(ads->info) = val;
	38
	39	checksum += i->link;
	40	ACCESS_ONCE(ads->link) = i->link;
	41
	42	checksum += i->buf_addr[0];
	43	ACCESS_ONCE(ads->data0) = i->buf_addr[0];
	44	checksum += i->buf_addr[1];
	45	ACCESS_ONCE(ads->data1) = i->buf_addr[1];
	46	checksum += i->buf_addr[2];
	47	ACCESS_ONCE(ads->data2) = i->buf_addr[2];
	48	checksum += i->buf_addr[3];
	49	ACCESS_ONCE(ads->data3) = i->buf_addr[3];
	50
	51	checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen);
	52	ACCESS_ONCE(ads->ctl3) = val;
	53	checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen);
	54	ACCESS_ONCE(ads->ctl5) = val;
	55	checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen);
	56	ACCESS_ONCE(ads->ctl7) = val;
	57	checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen);
	58	ACCESS_ONCE(ads->ctl9) = val;
	59
	60	checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff);
	61	ACCESS_ONCE(ads->ctl10) = checksum;
	62
	63	if (i->is_first \|\| i->is_last) {
	64	ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0)
	65	\| set11nTries(i->rates, 1)
	66	\| set11nTries(i->rates, 2)
	67	\| set11nTries(i->rates, 3)
	68	\| (i->dur_update ? AR_DurUpdateEna : 0)
	69	\| SM(0, AR_BurstDur);
	70
	71	ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0)
	72	\| set11nRate(i->rates, 1)
	73	\| set11nRate(i->rates, 2)
	74	\| set11nRate(i->rates, 3);
	75	} else {
	76	ACCESS_ONCE(ads->ctl13) = 0;
	77	ACCESS_ONCE(ads->ctl14) = 0;
	78	}
	79
	80	ads->ctl20 = 0;
	81	ads->ctl21 = 0;
	82	ads->ctl22 = 0;
	83
	84	ctl17 = SM(i->keytype, AR_EncrType);
	85	if (!i->is_first) {
	86	ACCESS_ONCE(ads->ctl11) = 0;
	87	ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore;
88	ACCESS_ONCE(ads->ctl15) = 0;
89	ACCESS_ONCE(ads->ctl16) = 0;
90	ACCESS_ONCE(ads->ctl17) = ctl17;
91	ACCESS_ONCE(ads->ctl18) = 0;
92	ACCESS_ONCE(ads->ctl19) = 0;
93	return;
94	}
95
96	ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen)
97	\| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
98	\| SM(i->txpower, AR_XmitPower)
99	\| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
100	\| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
101	\| (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0)
102	\| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
103	\| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
104	(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
105
106	ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ?
107	SM(i->keyix, AR_DestIdx) : 0)
108	\| SM(i->type, AR_FrameType)
109	\| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
110	\| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
111	\| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
112
113	ctl17 \|= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
114	switch (i->aggr) {
115	case AGGR_BUF_FIRST:
116	ctl17 \|= SM(i->aggr_len, AR_AggrLen);
117	/* fall through */
118	case AGGR_BUF_MIDDLE:
119	ctl12 \|= AR_IsAggr \| AR_MoreAggr;
120	ctl17 \|= SM(i->ndelim, AR_PadDelim);
121	break;
122	case AGGR_BUF_LAST:
123	ctl12 \|= AR_IsAggr;
124	break;
125	case AGGR_BUF_NONE:
126	break;
127	}
128
129	val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S;
130	ctl12 \|= SM(val, AR_PAPRDChainMask);
131
132	ACCESS_ONCE(ads->ctl12) = ctl12;
133	ACCESS_ONCE(ads->ctl17) = ctl17;
134
135	ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0)
136	\| set11nPktDurRTSCTS(i->rates, 1);
137
138	ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2)
139	\| set11nPktDurRTSCTS(i->rates, 3);
140
141	ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0)
142	\| set11nRateFlags(i->rates, 1)
143	\| set11nRateFlags(i->rates, 2)
144	\| set11nRateFlags(i->rates, 3)
145	\| SM(i->rtscts_rate, AR_RTSCTSRate);
146
147	ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding;
148	}
149
eb823253 VT	150	static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
	151	{
	152	int checksum;
	153
	154	checksum = ads->info + ads->link
	155	+ ads->data0 + ads->ctl3
	156	+ ads->data1 + ads->ctl5
	157	+ ads->data2 + ads->ctl7
	158	+ ads->data3 + ads->ctl9;
	159
	160	return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
	161	}
	162
87d5efbb VT	163	static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
87d5efbb VT	164	{
eb823253 VT	165	struct ar9003_txc *ads = ds;
	166
	167	ads->link = ds_link;
	168	ads->ctl10 &= ~AR_TxPtrChkSum;
	169	ads->ctl10 \|= ar9003_calc_ptr_chksum(ads);
87d5efbb VT	170	}
87d5efbb VT	171
55e82df4 VT	172	static bool ar9003_hw_get_isr(struct ath_hw ah, enum ath9k_int masked)
55e82df4 VT	173	{
6c84ce08 VT	174	u32 isr = 0;
	175	u32 mask2 = 0;
	176	struct ath9k_hw_capabilities *pCap = &ah->caps;
	177	u32 sync_cause = 0;
	178	struct ath_common *common = ath9k_hw_common(ah);
	179
	180	if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
	181	if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
	182	== AR_RTC_STATUS_ON)
	183	isr = REG_READ(ah, AR_ISR);
	184	}
	185
	186	sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
	187
	188	*masked = 0;
	189
	190	if (!isr && !sync_cause)
	191	return false;
	192
	193	if (isr) {
	194	if (isr & AR_ISR_BCNMISC) {
	195	u32 isr2;
	196	isr2 = REG_READ(ah, AR_ISR_S2);
	197
	198	mask2 \|= ((isr2 & AR_ISR_S2_TIM) >>
	199	MAP_ISR_S2_TIM);
	200	mask2 \|= ((isr2 & AR_ISR_S2_DTIM) >>
	201	MAP_ISR_S2_DTIM);
	202	mask2 \|= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
	203	MAP_ISR_S2_DTIMSYNC);
	204	mask2 \|= ((isr2 & AR_ISR_S2_CABEND) >>
	205	MAP_ISR_S2_CABEND);
	206	mask2 \|= ((isr2 & AR_ISR_S2_GTT) <<
	207	MAP_ISR_S2_GTT);
	208	mask2 \|= ((isr2 & AR_ISR_S2_CST) <<
	209	MAP_ISR_S2_CST);
	210	mask2 \|= ((isr2 & AR_ISR_S2_TSFOOR) >>
	211	MAP_ISR_S2_TSFOOR);
aea702b7 LR	212	mask2 \|= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
aea702b7 LR	213	MAP_ISR_S2_BB_WATCHDOG);
6c84ce08 VT	214
	215	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
	216	REG_WRITE(ah, AR_ISR_S2, isr2);
	217	isr &= ~AR_ISR_BCNMISC;
	218	}
	219	}
	220
	221	if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
	222	isr = REG_READ(ah, AR_ISR_RAC);
	223
	224	if (isr == 0xffffffff) {
	225	*masked = 0;
	226	return false;
	227	}
	228
	229	*masked = isr & ATH9K_INT_COMMON;
	230
	231	if (ah->config.rx_intr_mitigation)
	232	if (isr & (AR_ISR_RXMINTR \| AR_ISR_RXINTM))
	233	*masked \|= ATH9K_INT_RXLP;
	234
	235	if (ah->config.tx_intr_mitigation)
	236	if (isr & (AR_ISR_TXMINTR \| AR_ISR_TXINTM))
	237	*masked \|= ATH9K_INT_TX;
	238
	239	if (isr & (AR_ISR_LP_RXOK \| AR_ISR_RXERR))
	240	*masked \|= ATH9K_INT_RXLP;
	241
	242	if (isr & AR_ISR_HP_RXOK)
	243	*masked \|= ATH9K_INT_RXHP;
	244
	245	if (isr & (AR_ISR_TXOK \| AR_ISR_TXERR \| AR_ISR_TXEOL)) {
	246	*masked \|= ATH9K_INT_TX;
	247
	248	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
	249	u32 s0, s1;
	250	s0 = REG_READ(ah, AR_ISR_S0);
	251	REG_WRITE(ah, AR_ISR_S0, s0);
	252	s1 = REG_READ(ah, AR_ISR_S1);
	253	REG_WRITE(ah, AR_ISR_S1, s1);
	254
	255	isr &= ~(AR_ISR_TXOK \| AR_ISR_TXERR \|
	256	AR_ISR_TXEOL);
	257	}
	258	}
	259
	260	if (isr & AR_ISR_GENTMR) {
	261	u32 s5;
	262
	263	if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
	264	s5 = REG_READ(ah, AR_ISR_S5_S);
	265	else
	266	s5 = REG_READ(ah, AR_ISR_S5);
	267
	268	ah->intr_gen_timer_trigger =
	269	MS(s5, AR_ISR_S5_GENTIMER_TRIG);
	270
	271	ah->intr_gen_timer_thresh =
	272	MS(s5, AR_ISR_S5_GENTIMER_THRESH);
	273
	274	if (ah->intr_gen_timer_trigger)
	275	*masked \|= ATH9K_INT_GENTIMER;
	276
	277	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
278	REG_WRITE(ah, AR_ISR_S5, s5);
279	isr &= ~AR_ISR_GENTMR;
280	}
281
282	}
283
284	*masked \|= mask2;
285
286	if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
287	REG_WRITE(ah, AR_ISR, isr);
288
289	(void) REG_READ(ah, AR_ISR);
290	}
aea702b7 LR	291
	292	if (*masked & ATH9K_INT_BB_WATCHDOG)
	293	ar9003_hw_bb_watchdog_read(ah);
6c84ce08 VT	294	}
	295
	296	if (sync_cause) {
	297	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
	298	REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
	299	REG_WRITE(ah, AR_RC, 0);
	300	*masked \|= ATH9K_INT_FATAL;
	301	}
	302
	303	if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
226afe68 JP	304	ath_dbg(common, ATH_DBG_INTERRUPT,
226afe68 JP	305	"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
6c84ce08	306
6fe14002	307	REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6c84ce08 VT	308	(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	309
	310	}
55e82df4 VT	311	return true;
	312	}
	313
cc610ac0 VT	314	static int ar9003_hw_proc_txdesc(struct ath_hw ah, void ds,
	315	struct ath_tx_status *ts)
	316	{
dcfcbd59	317	struct ar9003_txc txc = (struct ar9003_txc ) ds;
994089db	318	struct ar9003_txs *ads;
e0e9bc82	319	u32 status;
994089db VT	320
	321	ads = &ah->ts_ring[ah->ts_tail];
	322
e0e9bc82 FF	323	status = ACCESS_ONCE(ads->status8);
e0e9bc82 FF	324	if ((status & AR_TxDone) == 0)
994089db VT	325	return -EINPROGRESS;
994089db VT	326
dcfcbd59 RM	327	ts->qid = MS(ads->ds_info, AR_TxQcuNum);
	328	if (!txc \|\| (MS(txc->info, AR_TxQcuNum) == ts->qid))
	329	ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
	330	else
	331	return -ENOENT;
994089db VT	332
	333	if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) \|\|
	334	(MS(ads->ds_info, AR_TxRxDesc) != 1)) {
226afe68 JP	335	ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
226afe68 JP	336	"Tx Descriptor error %x\n", ads->ds_info);
994089db VT	337	memset(ads, 0, sizeof(*ads));
	338	return -EIO;
	339	}
	340
e0e9bc82 FF	341	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	342	ts->ts_seqnum = MS(status, AR_SeqNum);
	343	ts->tid = MS(status, AR_TxTid);
	344
994089db	345	ts->desc_id = MS(ads->status1, AR_TxDescId);
994089db VT	346	ts->ts_tstamp = ads->status4;
	347	ts->ts_status = 0;
	348	ts->ts_flags = 0;
	349
2a15b394 RM	350	if (status & AR_TxOpExceeded)
2a15b394 RM	351	ts->ts_status \|= ATH9K_TXERR_XTXOP;
e0e9bc82 FF	352	status = ACCESS_ONCE(ads->status2);
	353	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	354	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	355	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	356	if (status & AR_TxBaStatus) {
	357	ts->ts_flags \|= ATH9K_TX_BA;
	358	ts->ba_low = ads->status5;
	359	ts->ba_high = ads->status6;
	360	}
	361
	362	status = ACCESS_ONCE(ads->status3);
	363	if (status & AR_ExcessiveRetries)
994089db	364	ts->ts_status \|= ATH9K_TXERR_XRETRY;
e0e9bc82	365	if (status & AR_Filtered)
994089db	366	ts->ts_status \|= ATH9K_TXERR_FILT;
e0e9bc82	367	if (status & AR_FIFOUnderrun) {
994089db VT	368	ts->ts_status \|= ATH9K_TXERR_FIFO;
	369	ath9k_hw_updatetxtriglevel(ah, true);
	370	}
e0e9bc82	371	if (status & AR_TxTimerExpired)
994089db	372	ts->ts_status \|= ATH9K_TXERR_TIMER_EXPIRED;
e0e9bc82	373	if (status & AR_DescCfgErr)
994089db	374	ts->ts_flags \|= ATH9K_TX_DESC_CFG_ERR;
e0e9bc82	375	if (status & AR_TxDataUnderrun) {
994089db VT	376	ts->ts_flags \|= ATH9K_TX_DATA_UNDERRUN;
	377	ath9k_hw_updatetxtriglevel(ah, true);
	378	}
e0e9bc82	379	if (status & AR_TxDelimUnderrun) {
994089db VT	380	ts->ts_flags \|= ATH9K_TX_DELIM_UNDERRUN;
	381	ath9k_hw_updatetxtriglevel(ah, true);
	382	}
e0e9bc82 FF	383	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	384	ts->ts_longretry = MS(status, AR_DataFailCnt);
	385	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
	386
	387	status = ACCESS_ONCE(ads->status7);
	388	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	389	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	390	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	391	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
994089db VT	392
	393	memset(ads, 0, sizeof(*ads));
	394
cc610ac0 VT	395	return 0;
cc610ac0 VT	396	}
994089db	397
ae3bb6d4 VT	398	void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
	399	{
	400	struct ath_hw_ops *ops = ath9k_hw_ops(hw);
	401
	402	ops->rx_enable = ar9003_hw_rx_enable;
87d5efbb	403	ops->set_desc_link = ar9003_hw_set_desc_link;
55e82df4	404	ops->get_isr = ar9003_hw_get_isr;
2b63a41d	405	ops->set_txdesc = ar9003_set_txdesc;
cc610ac0	406	ops->proc_txdesc = ar9003_hw_proc_txdesc;
ae3bb6d4	407	}
ad7b8060 VT	408
	409	void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
	410	{
	411	REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
	412	}
	413	EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
	414
	415	void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
	416	enum ath9k_rx_qtype qtype)
	417	{
	418	if (qtype == ATH9K_RX_QUEUE_HP)
	419	REG_WRITE(ah, AR_HP_RXDP, rxdp);
	420	else
	421	REG_WRITE(ah, AR_LP_RXDP, rxdp);
	422	}
	423	EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
	424
	425	int ath9k_hw_process_rxdesc_edma(struct ath_hw ah, struct ath_rx_status rxs,
	426	void *buf_addr)
	427	{
	428	struct ar9003_rxs rxsp = (struct ar9003_rxs ) buf_addr;
	429	unsigned int phyerr;
	430
	431	/* TODO: byte swap on big endian for ar9300_10 */
	432
cca1fe1a RM	433	if (!rxs) {
	434	if ((rxsp->status11 & AR_RxDone) == 0)
	435	return -EINPROGRESS;
ad7b8060	436
cca1fe1a RM	437	if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
cca1fe1a RM	438	return -EINVAL;
ad7b8060	439
cca1fe1a RM	440	if ((rxsp->ds_info & (AR_TxRxDesc \| AR_CtrlStat)) != 0)
cca1fe1a RM	441	return -EINPROGRESS;
ad7b8060	442
b5c80475	443	return 0;
cca1fe1a	444	}
b5c80475	445
ad7b8060 VT	446	rxs->rs_status = 0;
	447	rxs->rs_flags = 0;
	448
	449	rxs->rs_datalen = rxsp->status2 & AR_DataLen;
	450	rxs->rs_tstamp = rxsp->status3;
	451
	452	/* XXX: Keycache */
	453	rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
	454	rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
	455	rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
	456	rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
	457	rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
	458	rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
	459	rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
	460
	461	if (rxsp->status11 & AR_RxKeyIdxValid)
	462	rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
	463	else
	464	rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
	465
	466	rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
	467	rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
	468
	469	rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
	470	rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
	471	rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
	472	rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
	473	rxs->rs_flags \|= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
	474
	475	rxs->evm0 = rxsp->status6;
	476	rxs->evm1 = rxsp->status7;
	477	rxs->evm2 = rxsp->status8;
	478	rxs->evm3 = rxsp->status9;
	479	rxs->evm4 = (rxsp->status10 & 0xffff);
	480
	481	if (rxsp->status11 & AR_PreDelimCRCErr)
	482	rxs->rs_flags \|= ATH9K_RX_DELIM_CRC_PRE;
	483
	484	if (rxsp->status11 & AR_PostDelimCRCErr)
	485	rxs->rs_flags \|= ATH9K_RX_DELIM_CRC_POST;
	486
	487	if (rxsp->status11 & AR_DecryptBusyErr)
	488	rxs->rs_flags \|= ATH9K_RX_DECRYPT_BUSY;
	489
	490	if ((rxsp->status11 & AR_RxFrameOK) == 0) {
9171acc7 LR	491	/*
	492	* AR_CRCErr will bet set to true if we're on the last
	493	* subframe and the AR_PostDelimCRCErr is caught.
	494	* In a way this also gives us a guarantee that when
	495	* (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
	496	* possibly be reviewing the last subframe. AR_CRCErr
	497	* is the CRC of the actual data.
	498	*/
1c30cc19	499	if (rxsp->status11 & AR_CRCErr)
ad7b8060	500	rxs->rs_status \|= ATH9K_RXERR_CRC;
115dad7a	501	else if (rxsp->status11 & AR_PHYErr) {
ad7b8060	502	phyerr = MS(rxsp->status11, AR_PHYErrCode);
9171acc7 LR	503	/*
	504	* If we reach a point here where AR_PostDelimCRCErr is
	505	* true it implies we're not on the last subframe. In
	506	* in that case that we know already that the CRC of
	507	* the frame was OK, and MAC would send an ACK for that
	508	* subframe, even if we did get a phy error of type
	509	* ATH9K_PHYERR_OFDM_RESTART. This is only applicable
	510	* to frame that are prior to the last subframe.
	511	* The AR_PostDelimCRCErr is the CRC for the MPDU
	512	* delimiter, which contains the 4 reserved bits,
	513	* the MPDU length (12 bits), and follows the MPDU
	514	* delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
	515	*/
	516	if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
	517	(rxsp->status11 & AR_PostDelimCRCErr)) {
	518	rxs->rs_phyerr = 0;
	519	} else {
	520	rxs->rs_status \|= ATH9K_RXERR_PHY;
	521	rxs->rs_phyerr = phyerr;
	522	}
	523
115dad7a	524	} else if (rxsp->status11 & AR_DecryptCRCErr)
ad7b8060	525	rxs->rs_status \|= ATH9K_RXERR_DECRYPT;
115dad7a	526	else if (rxsp->status11 & AR_MichaelErr)
ad7b8060	527	rxs->rs_status \|= ATH9K_RXERR_MIC;
0472ade0	528	else if (rxsp->status11 & AR_KeyMiss)
3ae74c33	529	rxs->rs_status \|= ATH9K_RXERR_DECRYPT;
ad7b8060 VT	530	}
	531
	532	return 0;
	533	}
	534	EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
744d4025 VT	535
	536	void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
	537	{
	538	ah->ts_tail = 0;
	539
	540	memset((void *) ah->ts_ring, 0,
	541	ah->ts_size * sizeof(struct ar9003_txs));
	542
226afe68 JP	543	ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
	544	"TS Start 0x%x End 0x%x Virt %p, Size %d\n",
	545	ah->ts_paddr_start, ah->ts_paddr_end,
	546	ah->ts_ring, ah->ts_size);
744d4025 VT	547
	548	REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
	549	REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
	550	}
	551
	552	void ath9k_hw_setup_statusring(struct ath_hw ah, void ts_start,
	553	u32 ts_paddr_start,
	554	u8 size)
	555	{
	556
	557	ah->ts_paddr_start = ts_paddr_start;
	558	ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
	559	ah->ts_size = size;
	560	ah->ts_ring = (struct ar9003_txs *) ts_start;
	561
	562	ath9k_hw_reset_txstatus_ring(ah);
	563	}
	564	EXPORT_SYMBOL(ath9k_hw_setup_statusring);