[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / ar9002_mac.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"

#define AR_BufLen           0x00000fff

static void ar9002_hw_rx_enable(struct ath_hw *ah)
{
	REG_WRITE(ah, AR_CR, AR_CR_RXE);
}

static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
{
	((struct ath_desc*) ds)->ds_link = ds_link;
}

static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
{
	u32 isr = 0;
	u32 mask2 = 0;
	struct ath9k_hw_capabilities *pCap = &ah->caps;
	u32 sync_cause = 0;
	bool fatal_int = false;
	struct ath_common *common = ath9k_hw_common(ah);

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
			   AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;

		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);

			s1_s = REG_READ(ah, AR_ISR_S1_S);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
		}

		if (isr & AR_ISR_RXORN) {
			ath_dbg(common, ATH_DBG_INTERRUPT,
				"receive FIFO overrun interrupt\n");
		}

		*masked |= mask2;
	}

	if (AR_SREV_9100(ah))
		return true;

	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

		ah->intr_gen_timer_thresh =
			MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

		if (ah->intr_gen_timer_trigger)
			*masked |= ATH9K_INT_GENTIMER;

		if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
		    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
			*masked |= ATH9K_INT_TIM_TIMER;
	}

	if (sync_cause) {
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
				ath_dbg(common, ATH_DBG_ANY,
					"received PCI FATAL interrupt\n");
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
				ath_dbg(common, ATH_DBG_ANY,
					"received PCI PERR interrupt\n");
			}
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
			ath_dbg(common, ATH_DBG_INTERRUPT,
				"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
			ath_dbg(common, ATH_DBG_INTERRUPT,
				"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}

	return true;
}

static void
ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 ctl1, ctl6;

	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;

	ACCESS_ONCE(ads->ds_link) = i->link;
	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];

	ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore);
	ctl6 = SM(i->keytype, AR_EncrType);

	if (AR_SREV_9285(ah)) {
		ads->ds_ctl8 = 0;
		ads->ds_ctl9 = 0;
		ads->ds_ctl10 = 0;
		ads->ds_ctl11 = 0;
	}

	if ((i->is_first || i->is_last) &&
	    i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
		ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
			| set11nTries(i->rates, 1)
			| set11nTries(i->rates, 2)
			| set11nTries(i->rates, 3)
			| (i->dur_update ? AR_DurUpdateEna : 0)
			| SM(0, AR_BurstDur);

		ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
			| set11nRate(i->rates, 1)
			| set11nRate(i->rates, 2)
			| set11nRate(i->rates, 3);
	} else {
		ACCESS_ONCE(ads->ds_ctl2) = 0;
		ACCESS_ONCE(ads->ds_ctl3) = 0;
	}

	if (!i->is_first) {
		ACCESS_ONCE(ads->ds_ctl0) = 0;
		ACCESS_ONCE(ads->ds_ctl1) = ctl1;
		ACCESS_ONCE(ads->ds_ctl6) = ctl6;
		return;
	}

	ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
		| SM(i->type, AR_FrameType)
		| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
		| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
		| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);

	switch (i->aggr) {
	case AGGR_BUF_FIRST:
		ctl6 |= SM(i->aggr_len, AR_AggrLen);
		/* fall through */
	case AGGR_BUF_MIDDLE:
		ctl1 |= AR_IsAggr | AR_MoreAggr;
		ctl6 |= SM(i->ndelim, AR_PadDelim);
		break;
	case AGGR_BUF_LAST:
		ctl1 |= AR_IsAggr;
		break;
	case AGGR_BUF_NONE:
		break;
	}

	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
		| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
		| SM(i->txpower, AR_XmitPower)
		| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
		| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
		| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
		| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
		| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
		   (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));

	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	ACCESS_ONCE(ads->ds_ctl6) = ctl6;

	if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST)
		return;

	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
		| set11nPktDurRTSCTS(i->rates, 1);

	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
		| set11nPktDurRTSCTS(i->rates, 3);

	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
		| set11nRateFlags(i->rates, 1)
		| set11nRateFlags(i->rates, 2)
		| set11nRateFlags(i->rates, 3)
		| SM(i->rtscts_rate, AR_RTSCTSRate);
}

static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
				 struct ath_tx_status *ts)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	u32 status;

	status = ACCESS_ONCE(ads->ds_txstatus9);
	if ((status & AR_TxDone) == 0)
		return -EINPROGRESS;

	ts->ts_tstamp = ads->AR_SendTimestamp;
	ts->ts_status = 0;
	ts->ts_flags = 0;

	if (status & AR_TxOpExceeded)
		ts->ts_status |= ATH9K_TXERR_XTXOP;
	ts->tid = MS(status, AR_TxTid);
	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	ts->ts_seqnum = MS(status, AR_SeqNum);

	status = ACCESS_ONCE(ads->ds_txstatus0);
	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	if (status & AR_TxBaStatus) {
		ts->ts_flags |= ATH9K_TX_BA;
		ts->ba_low = ads->AR_BaBitmapLow;
		ts->ba_high = ads->AR_BaBitmapHigh;
	}

	status = ACCESS_ONCE(ads->ds_txstatus1);
	if (status & AR_FrmXmitOK)
		ts->ts_status |= ATH9K_TX_ACKED;
	else {
		if (status & AR_ExcessiveRetries)
			ts->ts_status |= ATH9K_TXERR_XRETRY;
		if (status & AR_Filtered)
			ts->ts_status |= ATH9K_TXERR_FILT;
		if (status & AR_FIFOUnderrun) {
			ts->ts_status |= ATH9K_TXERR_FIFO;
			ath9k_hw_updatetxtriglevel(ah, true);
		}
	}
	if (status & AR_TxTimerExpired)
		ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
	if (status & AR_DescCfgErr)
		ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
	if (status & AR_TxDataUnderrun) {
		ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	if (status & AR_TxDelimUnderrun) {
		ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
		ath9k_hw_updatetxtriglevel(ah, true);
	}
	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	ts->ts_longretry = MS(status, AR_DataFailCnt);
	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);

	status = ACCESS_ONCE(ads->ds_txstatus5);
	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);

	ts->evm0 = ads->AR_TxEVM0;
	ts->evm1 = ads->AR_TxEVM1;
	ts->evm2 = ads->AR_TxEVM2;

	return 0;
}

void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
			  u32 size, u32 flags)
{
	struct ar5416_desc *ads = AR5416DESC(ds);
	struct ath9k_hw_capabilities *pCap = &ah->caps;

	ads->ds_ctl1 = size & AR_BufLen;
	if (flags & ATH9K_RXDESC_INTREQ)
		ads->ds_ctl1 |= AR_RxIntrReq;

	ads->ds_rxstatus8 &= ~AR_RxDone;
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
		memset(&(ads->u), 0, sizeof(ads->u));
}
EXPORT_SYMBOL(ath9k_hw_setuprxdesc);

void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
{
	struct ath_hw_ops *ops = ath9k_hw_ops(ah);

	ops->rx_enable = ar9002_hw_rx_enable;
	ops->set_desc_link = ar9002_hw_set_desc_link;
	ops->get_isr = ar9002_hw_get_isr;
	ops->set_txdesc = ar9002_set_txdesc;
	ops->proc_txdesc = ar9002_hw_proc_txdesc;
}
Commit	Line	Data
b622a720	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
b622a720 LR	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include "hw.h"
	18
	19	#define AR_BufLen 0x00000fff
	20
	21	static void ar9002_hw_rx_enable(struct ath_hw *ah)
	22	{
	23	REG_WRITE(ah, AR_CR, AR_CR_RXE);
	24	}
	25
	26	static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
	27	{
	28	((struct ath_desc*) ds)->ds_link = ds_link;
	29	}
	30
b622a720 LR	31	static bool ar9002_hw_get_isr(struct ath_hw ah, enum ath9k_int masked)
	32	{
	33	u32 isr = 0;
	34	u32 mask2 = 0;
	35	struct ath9k_hw_capabilities *pCap = &ah->caps;
	36	u32 sync_cause = 0;
	37	bool fatal_int = false;
	38	struct ath_common *common = ath9k_hw_common(ah);
	39
	40	if (!AR_SREV_9100(ah)) {
	41	if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
	42	if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
	43	== AR_RTC_STATUS_ON) {
	44	isr = REG_READ(ah, AR_ISR);
	45	}
	46	}
	47
	48	sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
	49	AR_INTR_SYNC_DEFAULT;
	50
	51	*masked = 0;
	52
	53	if (!isr && !sync_cause)
	54	return false;
	55	} else {
	56	*masked = 0;
	57	isr = REG_READ(ah, AR_ISR);
	58	}
	59
	60	if (isr) {
	61	if (isr & AR_ISR_BCNMISC) {
	62	u32 isr2;
	63	isr2 = REG_READ(ah, AR_ISR_S2);
	64	if (isr2 & AR_ISR_S2_TIM)
	65	mask2 \|= ATH9K_INT_TIM;
	66	if (isr2 & AR_ISR_S2_DTIM)
	67	mask2 \|= ATH9K_INT_DTIM;
	68	if (isr2 & AR_ISR_S2_DTIMSYNC)
	69	mask2 \|= ATH9K_INT_DTIMSYNC;
	70	if (isr2 & (AR_ISR_S2_CABEND))
	71	mask2 \|= ATH9K_INT_CABEND;
	72	if (isr2 & AR_ISR_S2_GTT)
	73	mask2 \|= ATH9K_INT_GTT;
	74	if (isr2 & AR_ISR_S2_CST)
	75	mask2 \|= ATH9K_INT_CST;
	76	if (isr2 & AR_ISR_S2_TSFOOR)
	77	mask2 \|= ATH9K_INT_TSFOOR;
	78	}
	79
	80	isr = REG_READ(ah, AR_ISR_RAC);
	81	if (isr == 0xffffffff) {
	82	*masked = 0;
	83	return false;
	84	}
	85
	86	*masked = isr & ATH9K_INT_COMMON;
	87
45684c75 FF	88	if (isr & (AR_ISR_RXMINTR \| AR_ISR_RXINTM \|
45684c75 FF	89	AR_ISR_RXOK \| AR_ISR_RXERR))
b622a720	90	*masked \|= ATH9K_INT_RX;
45684c75	91
b622a720 LR	92	if (isr &
	93	(AR_ISR_TXOK \| AR_ISR_TXDESC \| AR_ISR_TXERR \|
	94	AR_ISR_TXEOL)) {
	95	u32 s0_s, s1_s;
	96
	97	*masked \|= ATH9K_INT_TX;
	98
	99	s0_s = REG_READ(ah, AR_ISR_S0_S);
	100	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXOK);
	101	ah->intr_txqs \|= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
	102
	103	s1_s = REG_READ(ah, AR_ISR_S1_S);
	104	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXERR);
	105	ah->intr_txqs \|= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
	106	}
	107
	108	if (isr & AR_ISR_RXORN) {
226afe68 JP	109	ath_dbg(common, ATH_DBG_INTERRUPT,
226afe68 JP	110	"receive FIFO overrun interrupt\n");
b622a720 LR	111	}
b622a720 LR	112
b622a720 LR	113	*masked \|= mask2;
	114	}
	115
	116	if (AR_SREV_9100(ah))
	117	return true;
	118
	119	if (isr & AR_ISR_GENTMR) {
	120	u32 s5_s;
	121
	122	s5_s = REG_READ(ah, AR_ISR_S5_S);
45684c75	123	ah->intr_gen_timer_trigger =
b622a720 LR	124	MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
b622a720 LR	125
45684c75 FF	126	ah->intr_gen_timer_thresh =
45684c75 FF	127	MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
b622a720	128
45684c75 FF	129	if (ah->intr_gen_timer_trigger)
45684c75 FF	130	*masked \|= ATH9K_INT_GENTIMER;
b622a720	131
45684c75 FF	132	if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
	133	!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
	134	*masked \|= ATH9K_INT_TIM_TIMER;
b622a720 LR	135	}
	136
	137	if (sync_cause) {
	138	fatal_int =
	139	(sync_cause &
	140	(AR_INTR_SYNC_HOST1_FATAL \| AR_INTR_SYNC_HOST1_PERR))
	141	? true : false;
	142
	143	if (fatal_int) {
	144	if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
226afe68 JP	145	ath_dbg(common, ATH_DBG_ANY,
226afe68 JP	146	"received PCI FATAL interrupt\n");
b622a720 LR	147	}
b622a720 LR	148	if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
226afe68 JP	149	ath_dbg(common, ATH_DBG_ANY,
226afe68 JP	150	"received PCI PERR interrupt\n");
b622a720 LR	151	}
	152	*masked \|= ATH9K_INT_FATAL;
	153	}
	154	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
226afe68 JP	155	ath_dbg(common, ATH_DBG_INTERRUPT,
226afe68 JP	156	"AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
b622a720 LR	157	REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
	158	REG_WRITE(ah, AR_RC, 0);
	159	*masked \|= ATH9K_INT_FATAL;
	160	}
	161	if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
226afe68 JP	162	ath_dbg(common, ATH_DBG_INTERRUPT,
226afe68 JP	163	"AR_INTR_SYNC_LOCAL_TIMEOUT\n");
b622a720 LR	164	}
	165
	166	REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
	167	(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	168	}
	169
	170	return true;
	171	}
	172
2b63a41d FF	173	static void
	174	ar9002_set_txdesc(struct ath_hw ah, void ds, struct ath_tx_info *i)
	175	{
	176	struct ar5416_desc *ads = AR5416DESC(ds);
	177	u32 ctl1, ctl6;
	178
	179	ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
	180	ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
	181	ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
	182	ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
	183	ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
	184
	185	ACCESS_ONCE(ads->ds_link) = i->link;
	186	ACCESS_ONCE(ads->ds_data) = i->buf_addr[0];
	187
	188	ctl1 = i->buf_len[0] \| (i->is_last ? 0 : AR_TxMore);
	189	ctl6 = SM(i->keytype, AR_EncrType);
	190
	191	if (AR_SREV_9285(ah)) {
	192	ads->ds_ctl8 = 0;
	193	ads->ds_ctl9 = 0;
	194	ads->ds_ctl10 = 0;
	195	ads->ds_ctl11 = 0;
	196	}
	197
	198	if ((i->is_first \|\| i->is_last) &&
	199	i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) {
	200	ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0)
	201	\| set11nTries(i->rates, 1)
	202	\| set11nTries(i->rates, 2)
	203	\| set11nTries(i->rates, 3)
	204	\| (i->dur_update ? AR_DurUpdateEna : 0)
	205	\| SM(0, AR_BurstDur);
	206
	207	ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0)
	208	\| set11nRate(i->rates, 1)
	209	\| set11nRate(i->rates, 2)
	210	\| set11nRate(i->rates, 3);
	211	} else {
	212	ACCESS_ONCE(ads->ds_ctl2) = 0;
	213	ACCESS_ONCE(ads->ds_ctl3) = 0;
	214	}
	215
	216	if (!i->is_first) {
	217	ACCESS_ONCE(ads->ds_ctl0) = 0;
	218	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
	219	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
	220	return;
	221	}
	222
	223	ctl1 \|= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0)
	224	\| SM(i->type, AR_FrameType)
	225	\| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
	226	\| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
	227	\| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
	228
	229	switch (i->aggr) {
	230	case AGGR_BUF_FIRST:
	231	ctl6 \|= SM(i->aggr_len, AR_AggrLen);
	232	/* fall through */
	233	case AGGR_BUF_MIDDLE:
	234	ctl1 \|= AR_IsAggr \| AR_MoreAggr;
	235	ctl6 \|= SM(i->ndelim, AR_PadDelim);
	236	break;
237	case AGGR_BUF_LAST:
238	ctl1 \|= AR_IsAggr;
239	break;
240	case AGGR_BUF_NONE:
241	break;
242	}
243
244	ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen)
245	\| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
246	\| SM(i->txpower, AR_XmitPower)
247	\| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
248	\| (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
249	\| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
250	\| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
251	\| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
252	(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
253
254	ACCESS_ONCE(ads->ds_ctl1) = ctl1;
255	ACCESS_ONCE(ads->ds_ctl6) = ctl6;
256
257	if (i->aggr == AGGR_BUF_MIDDLE \|\| i->aggr == AGGR_BUF_LAST)
258	return;
259
260	ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0)
261	\| set11nPktDurRTSCTS(i->rates, 1);
262
263	ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2)
264	\| set11nPktDurRTSCTS(i->rates, 3);
265
266	ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0)
267	\| set11nRateFlags(i->rates, 1)
268	\| set11nRateFlags(i->rates, 2)
269	\| set11nRateFlags(i->rates, 3)
270	\| SM(i->rtscts_rate, AR_RTSCTSRate);
271	}
272
b622a720 LR	273	static int ar9002_hw_proc_txdesc(struct ath_hw ah, void ds,
	274	struct ath_tx_status *ts)
	275	{
	276	struct ar5416_desc *ads = AR5416DESC(ds);
e0e9bc82	277	u32 status;
b622a720	278
e0e9bc82 FF	279	status = ACCESS_ONCE(ads->ds_txstatus9);
e0e9bc82 FF	280	if ((status & AR_TxDone) == 0)
b622a720 LR	281	return -EINPROGRESS;
b622a720 LR	282
b622a720 LR	283	ts->ts_tstamp = ads->AR_SendTimestamp;
	284	ts->ts_status = 0;
	285	ts->ts_flags = 0;
	286
e0e9bc82 FF	287	if (status & AR_TxOpExceeded)
	288	ts->ts_status \|= ATH9K_TXERR_XTXOP;
	289	ts->tid = MS(status, AR_TxTid);
	290	ts->ts_rateindex = MS(status, AR_FinalTxIdx);
	291	ts->ts_seqnum = MS(status, AR_SeqNum);
	292
	293	status = ACCESS_ONCE(ads->ds_txstatus0);
	294	ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
	295	ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
	296	ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
	297	if (status & AR_TxBaStatus) {
	298	ts->ts_flags \|= ATH9K_TX_BA;
	299	ts->ba_low = ads->AR_BaBitmapLow;
	300	ts->ba_high = ads->AR_BaBitmapHigh;
	301	}
	302
	303	status = ACCESS_ONCE(ads->ds_txstatus1);
	304	if (status & AR_FrmXmitOK)
b622a720	305	ts->ts_status \|= ATH9K_TX_ACKED;
ff32d9cd FF	306	else {
	307	if (status & AR_ExcessiveRetries)
	308	ts->ts_status \|= ATH9K_TXERR_XRETRY;
	309	if (status & AR_Filtered)
	310	ts->ts_status \|= ATH9K_TXERR_FILT;
	311	if (status & AR_FIFOUnderrun) {
	312	ts->ts_status \|= ATH9K_TXERR_FIFO;
	313	ath9k_hw_updatetxtriglevel(ah, true);
	314	}
b622a720	315	}
e0e9bc82	316	if (status & AR_TxTimerExpired)
b622a720	317	ts->ts_status \|= ATH9K_TXERR_TIMER_EXPIRED;
e0e9bc82	318	if (status & AR_DescCfgErr)
b622a720	319	ts->ts_flags \|= ATH9K_TX_DESC_CFG_ERR;
e0e9bc82	320	if (status & AR_TxDataUnderrun) {
b622a720 LR	321	ts->ts_flags \|= ATH9K_TX_DATA_UNDERRUN;
	322	ath9k_hw_updatetxtriglevel(ah, true);
	323	}
e0e9bc82	324	if (status & AR_TxDelimUnderrun) {
b622a720 LR	325	ts->ts_flags \|= ATH9K_TX_DELIM_UNDERRUN;
	326	ath9k_hw_updatetxtriglevel(ah, true);
	327	}
e0e9bc82 FF	328	ts->ts_shortretry = MS(status, AR_RTSFailCnt);
	329	ts->ts_longretry = MS(status, AR_DataFailCnt);
	330	ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
b622a720	331
e0e9bc82 FF	332	status = ACCESS_ONCE(ads->ds_txstatus5);
	333	ts->ts_rssi = MS(status, AR_TxRSSICombined);
	334	ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
	335	ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
	336	ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
b622a720	337
b622a720 LR	338	ts->evm0 = ads->AR_TxEVM0;
	339	ts->evm1 = ads->AR_TxEVM1;
	340	ts->evm2 = ads->AR_TxEVM2;
b622a720 LR	341
	342	return 0;
	343	}
	344
b622a720 LR	345	void ath9k_hw_setuprxdesc(struct ath_hw ah, struct ath_desc ds,
	346	u32 size, u32 flags)
	347	{
	348	struct ar5416_desc *ads = AR5416DESC(ds);
	349	struct ath9k_hw_capabilities *pCap = &ah->caps;
	350
	351	ads->ds_ctl1 = size & AR_BufLen;
	352	if (flags & ATH9K_RXDESC_INTREQ)
	353	ads->ds_ctl1 \|= AR_RxIntrReq;
	354
	355	ads->ds_rxstatus8 &= ~AR_RxDone;
	356	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
	357	memset(&(ads->u), 0, sizeof(ads->u));
	358	}
	359	EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
	360
	361	void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
	362	{
	363	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
	364
	365	ops->rx_enable = ar9002_hw_rx_enable;
	366	ops->set_desc_link = ar9002_hw_set_desc_link;
b622a720	367	ops->get_isr = ar9002_hw_get_isr;
2b63a41d	368	ops->set_txdesc = ar9002_set_txdesc;
b622a720	369	ops->proc_txdesc = ar9002_hw_proc_txdesc;
b622a720	370	}