Commit | Line | Data |
---|---|---|
b622a720 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
b622a720 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
18 | ||
19 | #define AR_BufLen 0x00000fff | |
20 | ||
21 | static void ar9002_hw_rx_enable(struct ath_hw *ah) | |
22 | { | |
23 | REG_WRITE(ah, AR_CR, AR_CR_RXE); | |
24 | } | |
25 | ||
26 | static void ar9002_hw_set_desc_link(void *ds, u32 ds_link) | |
27 | { | |
28 | ((struct ath_desc*) ds)->ds_link = ds_link; | |
29 | } | |
30 | ||
b622a720 LR |
31 | static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) |
32 | { | |
33 | u32 isr = 0; | |
34 | u32 mask2 = 0; | |
35 | struct ath9k_hw_capabilities *pCap = &ah->caps; | |
36 | u32 sync_cause = 0; | |
37 | bool fatal_int = false; | |
38 | struct ath_common *common = ath9k_hw_common(ah); | |
39 | ||
40 | if (!AR_SREV_9100(ah)) { | |
41 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | |
42 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | |
43 | == AR_RTC_STATUS_ON) { | |
44 | isr = REG_READ(ah, AR_ISR); | |
45 | } | |
46 | } | |
47 | ||
48 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & | |
49 | AR_INTR_SYNC_DEFAULT; | |
50 | ||
51 | *masked = 0; | |
52 | ||
53 | if (!isr && !sync_cause) | |
54 | return false; | |
55 | } else { | |
56 | *masked = 0; | |
57 | isr = REG_READ(ah, AR_ISR); | |
58 | } | |
59 | ||
60 | if (isr) { | |
61 | if (isr & AR_ISR_BCNMISC) { | |
62 | u32 isr2; | |
63 | isr2 = REG_READ(ah, AR_ISR_S2); | |
64 | if (isr2 & AR_ISR_S2_TIM) | |
65 | mask2 |= ATH9K_INT_TIM; | |
66 | if (isr2 & AR_ISR_S2_DTIM) | |
67 | mask2 |= ATH9K_INT_DTIM; | |
68 | if (isr2 & AR_ISR_S2_DTIMSYNC) | |
69 | mask2 |= ATH9K_INT_DTIMSYNC; | |
70 | if (isr2 & (AR_ISR_S2_CABEND)) | |
71 | mask2 |= ATH9K_INT_CABEND; | |
72 | if (isr2 & AR_ISR_S2_GTT) | |
73 | mask2 |= ATH9K_INT_GTT; | |
74 | if (isr2 & AR_ISR_S2_CST) | |
75 | mask2 |= ATH9K_INT_CST; | |
76 | if (isr2 & AR_ISR_S2_TSFOOR) | |
77 | mask2 |= ATH9K_INT_TSFOOR; | |
78 | } | |
79 | ||
80 | isr = REG_READ(ah, AR_ISR_RAC); | |
81 | if (isr == 0xffffffff) { | |
82 | *masked = 0; | |
83 | return false; | |
84 | } | |
85 | ||
86 | *masked = isr & ATH9K_INT_COMMON; | |
87 | ||
45684c75 FF |
88 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM | |
89 | AR_ISR_RXOK | AR_ISR_RXERR)) | |
b622a720 | 90 | *masked |= ATH9K_INT_RX; |
45684c75 | 91 | |
b622a720 LR |
92 | if (isr & |
93 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | |
94 | AR_ISR_TXEOL)) { | |
95 | u32 s0_s, s1_s; | |
96 | ||
97 | *masked |= ATH9K_INT_TX; | |
98 | ||
99 | s0_s = REG_READ(ah, AR_ISR_S0_S); | |
100 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); | |
101 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | |
102 | ||
103 | s1_s = REG_READ(ah, AR_ISR_S1_S); | |
104 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); | |
105 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | |
106 | } | |
107 | ||
108 | if (isr & AR_ISR_RXORN) { | |
226afe68 JP |
109 | ath_dbg(common, ATH_DBG_INTERRUPT, |
110 | "receive FIFO overrun interrupt\n"); | |
b622a720 LR |
111 | } |
112 | ||
b622a720 LR |
113 | *masked |= mask2; |
114 | } | |
115 | ||
116 | if (AR_SREV_9100(ah)) | |
117 | return true; | |
118 | ||
119 | if (isr & AR_ISR_GENTMR) { | |
120 | u32 s5_s; | |
121 | ||
122 | s5_s = REG_READ(ah, AR_ISR_S5_S); | |
45684c75 | 123 | ah->intr_gen_timer_trigger = |
b622a720 LR |
124 | MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); |
125 | ||
45684c75 FF |
126 | ah->intr_gen_timer_thresh = |
127 | MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); | |
b622a720 | 128 | |
45684c75 FF |
129 | if (ah->intr_gen_timer_trigger) |
130 | *masked |= ATH9K_INT_GENTIMER; | |
b622a720 | 131 | |
45684c75 FF |
132 | if ((s5_s & AR_ISR_S5_TIM_TIMER) && |
133 | !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | |
134 | *masked |= ATH9K_INT_TIM_TIMER; | |
b622a720 LR |
135 | } |
136 | ||
137 | if (sync_cause) { | |
138 | fatal_int = | |
139 | (sync_cause & | |
140 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | |
141 | ? true : false; | |
142 | ||
143 | if (fatal_int) { | |
144 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | |
226afe68 JP |
145 | ath_dbg(common, ATH_DBG_ANY, |
146 | "received PCI FATAL interrupt\n"); | |
b622a720 LR |
147 | } |
148 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | |
226afe68 JP |
149 | ath_dbg(common, ATH_DBG_ANY, |
150 | "received PCI PERR interrupt\n"); | |
b622a720 LR |
151 | } |
152 | *masked |= ATH9K_INT_FATAL; | |
153 | } | |
154 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | |
226afe68 JP |
155 | ath_dbg(common, ATH_DBG_INTERRUPT, |
156 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); | |
b622a720 LR |
157 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
158 | REG_WRITE(ah, AR_RC, 0); | |
159 | *masked |= ATH9K_INT_FATAL; | |
160 | } | |
161 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | |
226afe68 JP |
162 | ath_dbg(common, ATH_DBG_INTERRUPT, |
163 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | |
b622a720 LR |
164 | } |
165 | ||
166 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | |
167 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | |
168 | } | |
169 | ||
170 | return true; | |
171 | } | |
172 | ||
2b63a41d FF |
173 | static void |
174 | ar9002_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) | |
175 | { | |
176 | struct ar5416_desc *ads = AR5416DESC(ds); | |
177 | u32 ctl1, ctl6; | |
178 | ||
179 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | |
180 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | |
181 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | |
182 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | |
183 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | |
184 | ||
185 | ACCESS_ONCE(ads->ds_link) = i->link; | |
186 | ACCESS_ONCE(ads->ds_data) = i->buf_addr[0]; | |
187 | ||
188 | ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore); | |
189 | ctl6 = SM(i->keytype, AR_EncrType); | |
190 | ||
191 | if (AR_SREV_9285(ah)) { | |
192 | ads->ds_ctl8 = 0; | |
193 | ads->ds_ctl9 = 0; | |
194 | ads->ds_ctl10 = 0; | |
195 | ads->ds_ctl11 = 0; | |
196 | } | |
197 | ||
198 | if ((i->is_first || i->is_last) && | |
199 | i->aggr != AGGR_BUF_MIDDLE && i->aggr != AGGR_BUF_LAST) { | |
200 | ACCESS_ONCE(ads->ds_ctl2) = set11nTries(i->rates, 0) | |
201 | | set11nTries(i->rates, 1) | |
202 | | set11nTries(i->rates, 2) | |
203 | | set11nTries(i->rates, 3) | |
204 | | (i->dur_update ? AR_DurUpdateEna : 0) | |
205 | | SM(0, AR_BurstDur); | |
206 | ||
207 | ACCESS_ONCE(ads->ds_ctl3) = set11nRate(i->rates, 0) | |
208 | | set11nRate(i->rates, 1) | |
209 | | set11nRate(i->rates, 2) | |
210 | | set11nRate(i->rates, 3); | |
211 | } else { | |
212 | ACCESS_ONCE(ads->ds_ctl2) = 0; | |
213 | ACCESS_ONCE(ads->ds_ctl3) = 0; | |
214 | } | |
215 | ||
216 | if (!i->is_first) { | |
217 | ACCESS_ONCE(ads->ds_ctl0) = 0; | |
218 | ACCESS_ONCE(ads->ds_ctl1) = ctl1; | |
219 | ACCESS_ONCE(ads->ds_ctl6) = ctl6; | |
220 | return; | |
221 | } | |
222 | ||
223 | ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) | |
224 | | SM(i->type, AR_FrameType) | |
225 | | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | |
226 | | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | |
227 | | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | |
228 | ||
229 | switch (i->aggr) { | |
230 | case AGGR_BUF_FIRST: | |
231 | ctl6 |= SM(i->aggr_len, AR_AggrLen); | |
232 | /* fall through */ | |
233 | case AGGR_BUF_MIDDLE: | |
234 | ctl1 |= AR_IsAggr | AR_MoreAggr; | |
235 | ctl6 |= SM(i->ndelim, AR_PadDelim); | |
236 | break; | |
237 | case AGGR_BUF_LAST: | |
238 | ctl1 |= AR_IsAggr; | |
239 | break; | |
240 | case AGGR_BUF_NONE: | |
241 | break; | |
242 | } | |
243 | ||
244 | ACCESS_ONCE(ads->ds_ctl0) = (i->pkt_len & AR_FrameLen) | |
245 | | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | |
246 | | SM(i->txpower, AR_XmitPower) | |
247 | | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | |
248 | | (i->flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) | |
249 | | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) | |
250 | | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) | |
251 | | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : | |
252 | (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); | |
253 | ||
254 | ACCESS_ONCE(ads->ds_ctl1) = ctl1; | |
255 | ACCESS_ONCE(ads->ds_ctl6) = ctl6; | |
256 | ||
257 | if (i->aggr == AGGR_BUF_MIDDLE || i->aggr == AGGR_BUF_LAST) | |
258 | return; | |
259 | ||
260 | ACCESS_ONCE(ads->ds_ctl4) = set11nPktDurRTSCTS(i->rates, 0) | |
261 | | set11nPktDurRTSCTS(i->rates, 1); | |
262 | ||
263 | ACCESS_ONCE(ads->ds_ctl5) = set11nPktDurRTSCTS(i->rates, 2) | |
264 | | set11nPktDurRTSCTS(i->rates, 3); | |
265 | ||
266 | ACCESS_ONCE(ads->ds_ctl7) = set11nRateFlags(i->rates, 0) | |
267 | | set11nRateFlags(i->rates, 1) | |
268 | | set11nRateFlags(i->rates, 2) | |
269 | | set11nRateFlags(i->rates, 3) | |
270 | | SM(i->rtscts_rate, AR_RTSCTSRate); | |
271 | } | |
272 | ||
b622a720 LR |
273 | static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen, |
274 | bool is_firstseg, bool is_lastseg, | |
275 | const void *ds0, dma_addr_t buf_addr, | |
276 | unsigned int qcu) | |
277 | { | |
278 | struct ar5416_desc *ads = AR5416DESC(ds); | |
279 | ||
280 | ads->ds_data = buf_addr; | |
281 | ||
282 | if (is_firstseg) { | |
283 | ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore); | |
284 | } else if (is_lastseg) { | |
285 | ads->ds_ctl0 = 0; | |
286 | ads->ds_ctl1 = seglen; | |
287 | ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; | |
288 | ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; | |
289 | } else { | |
290 | ads->ds_ctl0 = 0; | |
291 | ads->ds_ctl1 = seglen | AR_TxMore; | |
292 | ads->ds_ctl2 = 0; | |
293 | ads->ds_ctl3 = 0; | |
294 | } | |
295 | ads->ds_txstatus0 = ads->ds_txstatus1 = 0; | |
296 | ads->ds_txstatus2 = ads->ds_txstatus3 = 0; | |
297 | ads->ds_txstatus4 = ads->ds_txstatus5 = 0; | |
298 | ads->ds_txstatus6 = ads->ds_txstatus7 = 0; | |
299 | ads->ds_txstatus8 = ads->ds_txstatus9 = 0; | |
300 | } | |
301 | ||
302 | static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, | |
303 | struct ath_tx_status *ts) | |
304 | { | |
305 | struct ar5416_desc *ads = AR5416DESC(ds); | |
e0e9bc82 | 306 | u32 status; |
b622a720 | 307 | |
e0e9bc82 FF |
308 | status = ACCESS_ONCE(ads->ds_txstatus9); |
309 | if ((status & AR_TxDone) == 0) | |
b622a720 LR |
310 | return -EINPROGRESS; |
311 | ||
b622a720 LR |
312 | ts->ts_tstamp = ads->AR_SendTimestamp; |
313 | ts->ts_status = 0; | |
314 | ts->ts_flags = 0; | |
315 | ||
e0e9bc82 FF |
316 | if (status & AR_TxOpExceeded) |
317 | ts->ts_status |= ATH9K_TXERR_XTXOP; | |
318 | ts->tid = MS(status, AR_TxTid); | |
319 | ts->ts_rateindex = MS(status, AR_FinalTxIdx); | |
320 | ts->ts_seqnum = MS(status, AR_SeqNum); | |
321 | ||
322 | status = ACCESS_ONCE(ads->ds_txstatus0); | |
323 | ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); | |
324 | ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); | |
325 | ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); | |
326 | if (status & AR_TxBaStatus) { | |
327 | ts->ts_flags |= ATH9K_TX_BA; | |
328 | ts->ba_low = ads->AR_BaBitmapLow; | |
329 | ts->ba_high = ads->AR_BaBitmapHigh; | |
330 | } | |
331 | ||
332 | status = ACCESS_ONCE(ads->ds_txstatus1); | |
333 | if (status & AR_FrmXmitOK) | |
b622a720 | 334 | ts->ts_status |= ATH9K_TX_ACKED; |
ff32d9cd FF |
335 | else { |
336 | if (status & AR_ExcessiveRetries) | |
337 | ts->ts_status |= ATH9K_TXERR_XRETRY; | |
338 | if (status & AR_Filtered) | |
339 | ts->ts_status |= ATH9K_TXERR_FILT; | |
340 | if (status & AR_FIFOUnderrun) { | |
341 | ts->ts_status |= ATH9K_TXERR_FIFO; | |
342 | ath9k_hw_updatetxtriglevel(ah, true); | |
343 | } | |
b622a720 | 344 | } |
e0e9bc82 | 345 | if (status & AR_TxTimerExpired) |
b622a720 | 346 | ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; |
e0e9bc82 | 347 | if (status & AR_DescCfgErr) |
b622a720 | 348 | ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; |
e0e9bc82 | 349 | if (status & AR_TxDataUnderrun) { |
b622a720 LR |
350 | ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; |
351 | ath9k_hw_updatetxtriglevel(ah, true); | |
352 | } | |
e0e9bc82 | 353 | if (status & AR_TxDelimUnderrun) { |
b622a720 LR |
354 | ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; |
355 | ath9k_hw_updatetxtriglevel(ah, true); | |
356 | } | |
e0e9bc82 FF |
357 | ts->ts_shortretry = MS(status, AR_RTSFailCnt); |
358 | ts->ts_longretry = MS(status, AR_DataFailCnt); | |
359 | ts->ts_virtcol = MS(status, AR_VirtRetryCnt); | |
b622a720 | 360 | |
e0e9bc82 FF |
361 | status = ACCESS_ONCE(ads->ds_txstatus5); |
362 | ts->ts_rssi = MS(status, AR_TxRSSICombined); | |
363 | ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); | |
364 | ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); | |
365 | ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); | |
b622a720 | 366 | |
b622a720 LR |
367 | ts->evm0 = ads->AR_TxEVM0; |
368 | ts->evm1 = ads->AR_TxEVM1; | |
369 | ts->evm2 = ads->AR_TxEVM2; | |
b622a720 LR |
370 | |
371 | return 0; | |
372 | } | |
373 | ||
374 | static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds, | |
375 | u32 pktLen, enum ath9k_pkt_type type, | |
a75c0629 | 376 | u32 txPower, u8 keyIx, |
b622a720 LR |
377 | enum ath9k_key_type keyType, u32 flags) |
378 | { | |
379 | struct ar5416_desc *ads = AR5416DESC(ds); | |
380 | ||
b622a720 LR |
381 | if (txPower > 63) |
382 | txPower = 63; | |
383 | ||
384 | ads->ds_ctl0 = (pktLen & AR_FrameLen) | |
385 | | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) | |
386 | | SM(txPower, AR_XmitPower) | |
387 | | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) | |
b622a720 LR |
388 | | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0) |
389 | | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0); | |
390 | ||
391 | ads->ds_ctl1 = | |
392 | (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) | |
393 | | SM(type, AR_FrameType) | |
394 | | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) | |
395 | | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) | |
396 | | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); | |
397 | ||
398 | ads->ds_ctl6 = SM(keyType, AR_EncrType); | |
399 | ||
400 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) { | |
401 | ads->ds_ctl8 = 0; | |
402 | ads->ds_ctl9 = 0; | |
403 | ads->ds_ctl10 = 0; | |
404 | ads->ds_ctl11 = 0; | |
405 | } | |
406 | } | |
407 | ||
5519541d FF |
408 | static void ar9002_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val) |
409 | { | |
410 | struct ar5416_desc *ads = AR5416DESC(ds); | |
411 | ||
412 | if (val) | |
413 | ads->ds_ctl0 |= AR_ClrDestMask; | |
414 | else | |
415 | ads->ds_ctl0 &= ~AR_ClrDestMask; | |
416 | } | |
417 | ||
b622a720 LR |
418 | static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds, |
419 | void *lastds, | |
420 | u32 durUpdateEn, u32 rtsctsRate, | |
421 | u32 rtsctsDuration, | |
422 | struct ath9k_11n_rate_series series[], | |
423 | u32 nseries, u32 flags) | |
424 | { | |
425 | struct ar5416_desc *ads = AR5416DESC(ds); | |
426 | struct ar5416_desc *last_ads = AR5416DESC(lastds); | |
427 | u32 ds_ctl0; | |
428 | ||
429 | if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) { | |
430 | ds_ctl0 = ads->ds_ctl0; | |
431 | ||
432 | if (flags & ATH9K_TXDESC_RTSENA) { | |
433 | ds_ctl0 &= ~AR_CTSEnable; | |
434 | ds_ctl0 |= AR_RTSEnable; | |
435 | } else { | |
436 | ds_ctl0 &= ~AR_RTSEnable; | |
437 | ds_ctl0 |= AR_CTSEnable; | |
438 | } | |
439 | ||
440 | ads->ds_ctl0 = ds_ctl0; | |
441 | } else { | |
442 | ads->ds_ctl0 = | |
443 | (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); | |
444 | } | |
445 | ||
446 | ads->ds_ctl2 = set11nTries(series, 0) | |
447 | | set11nTries(series, 1) | |
448 | | set11nTries(series, 2) | |
449 | | set11nTries(series, 3) | |
450 | | (durUpdateEn ? AR_DurUpdateEna : 0) | |
451 | | SM(0, AR_BurstDur); | |
452 | ||
453 | ads->ds_ctl3 = set11nRate(series, 0) | |
454 | | set11nRate(series, 1) | |
455 | | set11nRate(series, 2) | |
456 | | set11nRate(series, 3); | |
457 | ||
458 | ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) | |
459 | | set11nPktDurRTSCTS(series, 1); | |
460 | ||
461 | ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) | |
462 | | set11nPktDurRTSCTS(series, 3); | |
463 | ||
464 | ads->ds_ctl7 = set11nRateFlags(series, 0) | |
465 | | set11nRateFlags(series, 1) | |
466 | | set11nRateFlags(series, 2) | |
467 | | set11nRateFlags(series, 3) | |
468 | | SM(rtsctsRate, AR_RTSCTSRate); | |
469 | last_ads->ds_ctl2 = ads->ds_ctl2; | |
470 | last_ads->ds_ctl3 = ads->ds_ctl3; | |
471 | } | |
472 | ||
473 | static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds, | |
474 | u32 aggrLen) | |
475 | { | |
476 | struct ar5416_desc *ads = AR5416DESC(ds); | |
477 | ||
478 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | |
479 | ads->ds_ctl6 &= ~AR_AggrLen; | |
480 | ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); | |
481 | } | |
482 | ||
483 | static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds, | |
484 | u32 numDelims) | |
485 | { | |
486 | struct ar5416_desc *ads = AR5416DESC(ds); | |
487 | unsigned int ctl6; | |
488 | ||
489 | ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); | |
490 | ||
491 | ctl6 = ads->ds_ctl6; | |
492 | ctl6 &= ~AR_PadDelim; | |
493 | ctl6 |= SM(numDelims, AR_PadDelim); | |
494 | ads->ds_ctl6 = ctl6; | |
495 | } | |
496 | ||
497 | static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds) | |
498 | { | |
499 | struct ar5416_desc *ads = AR5416DESC(ds); | |
500 | ||
501 | ads->ds_ctl1 |= AR_IsAggr; | |
502 | ads->ds_ctl1 &= ~AR_MoreAggr; | |
503 | ads->ds_ctl6 &= ~AR_PadDelim; | |
504 | } | |
505 | ||
506 | static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds) | |
507 | { | |
508 | struct ar5416_desc *ads = AR5416DESC(ds); | |
509 | ||
510 | ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); | |
511 | } | |
512 | ||
b622a720 LR |
513 | void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, |
514 | u32 size, u32 flags) | |
515 | { | |
516 | struct ar5416_desc *ads = AR5416DESC(ds); | |
517 | struct ath9k_hw_capabilities *pCap = &ah->caps; | |
518 | ||
519 | ads->ds_ctl1 = size & AR_BufLen; | |
520 | if (flags & ATH9K_RXDESC_INTREQ) | |
521 | ads->ds_ctl1 |= AR_RxIntrReq; | |
522 | ||
523 | ads->ds_rxstatus8 &= ~AR_RxDone; | |
524 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | |
525 | memset(&(ads->u), 0, sizeof(ads->u)); | |
526 | } | |
527 | EXPORT_SYMBOL(ath9k_hw_setuprxdesc); | |
528 | ||
529 | void ar9002_hw_attach_mac_ops(struct ath_hw *ah) | |
530 | { | |
531 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); | |
532 | ||
533 | ops->rx_enable = ar9002_hw_rx_enable; | |
534 | ops->set_desc_link = ar9002_hw_set_desc_link; | |
b622a720 | 535 | ops->get_isr = ar9002_hw_get_isr; |
2b63a41d | 536 | ops->set_txdesc = ar9002_set_txdesc; |
b622a720 LR |
537 | ops->fill_txdesc = ar9002_hw_fill_txdesc; |
538 | ops->proc_txdesc = ar9002_hw_proc_txdesc; | |
539 | ops->set11n_txdesc = ar9002_hw_set11n_txdesc; | |
540 | ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario; | |
541 | ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first; | |
542 | ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle; | |
543 | ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last; | |
544 | ops->clr11n_aggr = ar9002_hw_clr11n_aggr; | |
5519541d | 545 | ops->set_clrdmask = ar9002_hw_set_clrdmask; |
b622a720 | 546 | } |