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ath6kl: add ath6kl_bmi_read_hi32()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath6kl / init.c
CommitLineData
bdcd8170
KV		 1
2/*
3 * Copyright (c) 2011 Atheros Communications Inc.
1b2df407 4 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
bdcd8170
KV		 5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
c6efe578 19#include <linux/moduleparam.h>
f7830202 20#include <linux/errno.h>
d6a434d6 21#include <linux/export.h>
92ecbff4 22#include <linux/of.h>
bdcd8170 23#include <linux/mmc/sdio_func.h>
d6a434d6 24
bdcd8170
KV		 25#include "core.h"
26#include "cfg80211.h"
27#include "target.h"
28#include "debug.h"
29#include "hif-ops.h"
30
856f4b31
KV		 31static const struct ath6kl_hw hw_list[] = {
32 {
0d0192ba 33 .id = AR6003_HW_2_0_VERSION,
293badf4 34 .name = "ar6003 hw 2.0",
856f4b31
KV		 35 .dataset_patch_addr = 0x57e884,
36 .app_load_addr = 0x543180,
37 .board_ext_data_addr = 0x57e500,
38 .reserved_ram_size = 6912,
39586bf2
RH		 39 .refclk_hz = 26000000,
40 .uarttx_pin = 8,
856f4b31
KV		 41
42 /* hw2.0 needs override address hardcoded */
43 .app_start_override_addr = 0x944C00,
d1a9421d 44
c0038972
KV		 45 .fw = {
46 .dir = AR6003_HW_2_0_FW_DIR,
47 .otp = AR6003_HW_2_0_OTP_FILE,
48 .fw = AR6003_HW_2_0_FIRMWARE_FILE,
49 .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
50 .patch = AR6003_HW_2_0_PATCH_FILE,
c0038972
KV		 51 },
52
d1a9421d
KV		 53 .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
54 .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
856f4b31
KV		 55 },
56 {
0d0192ba 57 .id = AR6003_HW_2_1_1_VERSION,
293badf4 58 .name = "ar6003 hw 2.1.1",
856f4b31
KV		 59 .dataset_patch_addr = 0x57ff74,
60 .app_load_addr = 0x1234,
61 .board_ext_data_addr = 0x542330,
62 .reserved_ram_size = 512,
39586bf2
RH		 63 .refclk_hz = 26000000,
64 .uarttx_pin = 8,
cd23c1c9 65 .testscript_addr = 0x57ef74,
d1a9421d 66
c0038972
KV		 67 .fw = {
68 .dir = AR6003_HW_2_1_1_FW_DIR,
69 .otp = AR6003_HW_2_1_1_OTP_FILE,
70 .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
71 .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
72 .patch = AR6003_HW_2_1_1_PATCH_FILE,
cd23c1c9
AY		 73 .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
74 .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
c0038972
KV		 75 },
76
d1a9421d
KV		 77 .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
78 .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
856f4b31
KV		 79 },
80 {
0d0192ba 81 .id = AR6004_HW_1_0_VERSION,
293badf4 82 .name = "ar6004 hw 1.0",
856f4b31
KV		 83 .dataset_patch_addr = 0x57e884,
84 .app_load_addr = 0x1234,
85 .board_ext_data_addr = 0x437000,
86 .reserved_ram_size = 19456,
0d4d72bf 87 .board_addr = 0x433900,
39586bf2
RH		 88 .refclk_hz = 26000000,
89 .uarttx_pin = 11,
d1a9421d 90
c0038972
KV		 91 .fw = {
92 .dir = AR6004_HW_1_0_FW_DIR,
93 .fw = AR6004_HW_1_0_FIRMWARE_FILE,
c0038972
KV		 94 },
95
d1a9421d
KV		 96 .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
97 .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
856f4b31
KV		 98 },
99 {
0d0192ba 100 .id = AR6004_HW_1_1_VERSION,
293badf4 101 .name = "ar6004 hw 1.1",
856f4b31
KV		 102 .dataset_patch_addr = 0x57e884,
103 .app_load_addr = 0x1234,
104 .board_ext_data_addr = 0x437000,
105 .reserved_ram_size = 11264,
0d4d72bf 106 .board_addr = 0x43d400,
39586bf2
RH		 107 .refclk_hz = 40000000,
108 .uarttx_pin = 11,
d1a9421d 109
c0038972
KV		 110 .fw = {
111 .dir = AR6004_HW_1_1_FW_DIR,
112 .fw = AR6004_HW_1_1_FIRMWARE_FILE,
c0038972
KV		 113 },
114
d1a9421d
KV		 115 .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
116 .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
856f4b31
KV		 117 },
118};
119
bdcd8170
KV		 120/*
121 * Include definitions here that can be used to tune the WLAN module
122 * behavior. Different customers can tune the behavior as per their needs,
123 * here.
124 */
125
126/*
127 * This configuration item enable/disable keepalive support.
128 * Keepalive support: In the absence of any data traffic to AP, null
129 * frames will be sent to the AP at periodic interval, to keep the association
130 * active. This configuration item defines the periodic interval.
131 * Use value of zero to disable keepalive support
132 * Default: 60 seconds
133 */
134#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
135
136/*
137 * This configuration item sets the value of disconnect timeout
138 * Firmware delays sending the disconnec event to the host for this
139 * timeout after is gets disconnected from the current AP.
140 * If the firmware successly roams within the disconnect timeout
141 * it sends a new connect event
142 */
143#define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
144
bdcd8170 145
bdcd8170
KV		 146#define ATH6KL_DATA_OFFSET 64
147struct sk_buff *ath6kl_buf_alloc(int size)
148{
149 struct sk_buff *skb;
150 u16 reserved;
151
152 /* Add chacheline space at front and back of buffer */
153 reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
1df94a85 154 sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
bdcd8170
KV		 155 skb = dev_alloc_skb(size + reserved);
156
157 if (skb)
158 skb_reserve(skb, reserved - L1_CACHE_BYTES);
159 return skb;
160}
161
e29f25f5 162void ath6kl_init_profile_info(struct ath6kl_vif *vif)
bdcd8170 163{
3450334f
VT		 164 vif->ssid_len = 0;
165 memset(vif->ssid, 0, sizeof(vif->ssid));
166
167 vif->dot11_auth_mode = OPEN_AUTH;
168 vif->auth_mode = NONE_AUTH;
169 vif->prwise_crypto = NONE_CRYPT;
170 vif->prwise_crypto_len = 0;
171 vif->grp_crypto = NONE_CRYPT;
172 vif->grp_crypto_len = 0;
6f2a73f9 173 memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
8c8b65e3
VT		 174 memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
175 memset(vif->bssid, 0, sizeof(vif->bssid));
f74bac54 176 vif->bss_ch = 0;
bdcd8170
KV		 177}
178
bdcd8170
KV		 179static int ath6kl_set_host_app_area(struct ath6kl *ar)
180{
181 u32 address, data;
182 struct host_app_area host_app_area;
183
184 /* Fetch the address of the host_app_area_s
185 * instance in the host interest area */
186 address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
31024d99 187 address = TARG_VTOP(ar->target_type, address);
bdcd8170 188
addb44be 189 if (ath6kl_diag_read32(ar, address, &data))
bdcd8170
KV		 190 return -EIO;
191
31024d99 192 address = TARG_VTOP(ar->target_type, data);
cbf49a6f 193 host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
addb44be
KV		 194 if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
195 sizeof(struct host_app_area)))
bdcd8170
KV		 196 return -EIO;
197
198 return 0;
199}
200
201static inline void set_ac2_ep_map(struct ath6kl *ar,
202 u8 ac,
203 enum htc_endpoint_id ep)
204{
205 ar->ac2ep_map[ac] = ep;
206 ar->ep2ac_map[ep] = ac;
207}
208
209/* connect to a service */
210static int ath6kl_connectservice(struct ath6kl *ar,
211 struct htc_service_connect_req *con_req,
212 char *desc)
213{
214 int status;
215 struct htc_service_connect_resp response;
216
217 memset(&response, 0, sizeof(response));
218
ad226ec2 219 status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
bdcd8170
KV		 220 if (status) {
221 ath6kl_err("failed to connect to %s service status:%d\n",
222 desc, status);
223 return status;
224 }
225
226 switch (con_req->svc_id) {
227 case WMI_CONTROL_SVC:
228 if (test_bit(WMI_ENABLED, &ar->flag))
229 ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
230 ar->ctrl_ep = response.endpoint;
231 break;
232 case WMI_DATA_BE_SVC:
233 set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
234 break;
235 case WMI_DATA_BK_SVC:
236 set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
237 break;
238 case WMI_DATA_VI_SVC:
239 set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
240 break;
241 case WMI_DATA_VO_SVC:
242 set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
243 break;
244 default:
245 ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
246 return -EINVAL;
247 }
248
249 return 0;
250}
251
252static int ath6kl_init_service_ep(struct ath6kl *ar)
253{
254 struct htc_service_connect_req connect;
255
256 memset(&connect, 0, sizeof(connect));
257
258 /* these fields are the same for all service endpoints */
259 connect.ep_cb.rx = ath6kl_rx;
260 connect.ep_cb.rx_refill = ath6kl_rx_refill;
261 connect.ep_cb.tx_full = ath6kl_tx_queue_full;
262
263 /*
264 * Set the max queue depth so that our ath6kl_tx_queue_full handler
265 * gets called.
266 */
267 connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
268 connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
269 if (!connect.ep_cb.rx_refill_thresh)
270 connect.ep_cb.rx_refill_thresh++;
271
272 /* connect to control service */
273 connect.svc_id = WMI_CONTROL_SVC;
274 if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
275 return -EIO;
276
277 connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
278
279 /*
280 * Limit the HTC message size on the send path, although e can
281 * receive A-MSDU frames of 4K, we will only send ethernet-sized
282 * (802.3) frames on the send path.
283 */
284 connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
285
286 /*
287 * To reduce the amount of committed memory for larger A_MSDU
288 * frames, use the recv-alloc threshold mechanism for larger
289 * packets.
290 */
291 connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
292 connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
293
294 /*
295 * For the remaining data services set the connection flag to
296 * reduce dribbling, if configured to do so.
297 */
298 connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
299 connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
300 connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
301
302 connect.svc_id = WMI_DATA_BE_SVC;
303
304 if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
305 return -EIO;
306
307 /* connect to back-ground map this to WMI LOW_PRI */
308 connect.svc_id = WMI_DATA_BK_SVC;
309 if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
310 return -EIO;
311
312 /* connect to Video service, map this to to HI PRI */
313 connect.svc_id = WMI_DATA_VI_SVC;
314 if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
315 return -EIO;
316
317 /*
318 * Connect to VO service, this is currently not mapped to a WMI
319 * priority stream due to historical reasons. WMI originally
320 * defined 3 priorities over 3 mailboxes We can change this when
321 * WMI is reworked so that priorities are not dependent on
322 * mailboxes.
323 */
324 connect.svc_id = WMI_DATA_VO_SVC;
325 if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
326 return -EIO;
327
328 return 0;
329}
330
e29f25f5 331void ath6kl_init_control_info(struct ath6kl_vif *vif)
bdcd8170 332{
e29f25f5 333 ath6kl_init_profile_info(vif);
3450334f 334 vif->def_txkey_index = 0;
6f2a73f9 335 memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
f74bac54 336 vif->ch_hint = 0;
bdcd8170
KV		 337}
338
339/*
340 * Set HTC/Mbox operational parameters, this can only be called when the
341 * target is in the BMI phase.
342 */
343static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
344 u8 htc_ctrl_buf)
345{
346 int status;
347 u32 blk_size;
348
349 blk_size = ar->mbox_info.block_size;
350
351 if (htc_ctrl_buf)
352 blk_size |= ((u32)htc_ctrl_buf) << 16;
353
354 /* set the host interest area for the block size */
24fc32b3 355 status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
bdcd8170
KV		 356 if (status) {
357 ath6kl_err("bmi_write_memory for IO block size failed\n");
358 goto out;
359 }
360
361 ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
362 blk_size,
363 ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
364
365 if (mbox_isr_yield_val) {
366 /* set the host interest area for the mbox ISR yield limit */
24fc32b3
KV		 367 status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
368 mbox_isr_yield_val);
bdcd8170
KV		 369 if (status) {
370 ath6kl_err("bmi_write_memory for yield limit failed\n");
371 goto out;
372 }
373 }
374
375out:
376 return status;
377}
378
0ce59445 379static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
bdcd8170
KV		 380{
381 int status = 0;
4dea08e0 382 int ret;
bdcd8170
KV		 383
384 /*
385 * Configure the device for rx dot11 header rules. "0,0" are the
386 * default values. Required if checksum offload is needed. Set
387 * RxMetaVersion to 2.
388 */
0ce59445 389 if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
bdcd8170
KV		 390 ar->rx_meta_ver, 0, 0)) {
391 ath6kl_err("unable to set the rx frame format\n");
392 status = -EIO;
393 }
394
395 if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
0ce59445 396 if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
bdcd8170
KV		 397 IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
398 ath6kl_err("unable to set power save fail event policy\n");
399 status = -EIO;
400 }
401
402 if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
0ce59445 403 if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
bdcd8170
KV		 404 WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
405 ath6kl_err("unable to set barker preamble policy\n");
406 status = -EIO;
407 }
408
0ce59445 409 if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
96f1fadc 410 WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
bdcd8170
KV		 411 ath6kl_err("unable to set keep alive interval\n");
412 status = -EIO;
413 }
414
0ce59445 415 if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
96f1fadc 416 WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
bdcd8170
KV		 417 ath6kl_err("unable to set disconnect timeout\n");
418 status = -EIO;
419 }
420
421 if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
0ce59445 422 if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
bdcd8170
KV		 423 ath6kl_err("unable to set txop bursting\n");
424 status = -EIO;
425 }
426
b64de356 427 if (ar->p2p && (ar->vif_max == 1 || idx)) {
0ce59445 428 ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
6bbc7c35
JM		 429 P2P_FLAG_CAPABILITIES_REQ |
430 P2P_FLAG_MACADDR_REQ |
431 P2P_FLAG_HMODEL_REQ);
432 if (ret) {
433 ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
434 "capabilities (%d) - assuming P2P not "
435 "supported\n", ret);
3db1cd5c 436 ar->p2p = false;
6bbc7c35
JM		 437 }
438 }
439
b64de356 440 if (ar->p2p && (ar->vif_max == 1 || idx)) {
6bbc7c35 441 /* Enable Probe Request reporting for P2P */
0ce59445 442 ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
6bbc7c35
JM		 443 if (ret) {
444 ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
445 "Request reporting (%d)\n", ret);
446 }
4dea08e0
JM		 447 }
448
bdcd8170
KV		 449 return status;
450}
451
452int ath6kl_configure_target(struct ath6kl *ar)
453{
454 u32 param, ram_reserved_size;
3226f68a 455 u8 fw_iftype, fw_mode = 0, fw_submode = 0;
39586bf2 456 int i, status;
bdcd8170 457
f29af978 458 param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
24fc32b3 459 if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
a10e2f2f
VT		 460 ath6kl_err("bmi_write_memory for uart debug failed\n");
461 return -EIO;
462 }
463
7b85832d
VT		 464 /*
465 * Note: Even though the firmware interface type is
466 * chosen as BSS_STA for all three interfaces, can
467 * be configured to IBSS/AP as long as the fw submode
468 * remains normal mode (0 - AP, STA and IBSS). But
469 * due to an target assert in firmware only one interface is
470 * configured for now.
471 */
dd3751f7 472 fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
bdcd8170 473
71f96ee6 474 for (i = 0; i < ar->vif_max; i++)
7b85832d
VT		 475 fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
476
477 /*
3226f68a
VT		 478 * By default, submodes :
479 * vif[0] - AP/STA/IBSS
480 * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
481 * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
7b85832d 482 */
3226f68a
VT		 483
484 for (i = 0; i < ar->max_norm_iface; i++)
485 fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
486 (i * HI_OPTION_FW_SUBMODE_BITS);
487
71f96ee6 488 for (i = ar->max_norm_iface; i < ar->vif_max; i++)
3226f68a
VT		 489 fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
490 (i * HI_OPTION_FW_SUBMODE_BITS);
7b85832d 491
b64de356 492 if (ar->p2p && ar->vif_max == 1)
7b85832d 493 fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
7b85832d 494
24fc32b3
KV		 495 if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
496 HTC_PROTOCOL_VERSION) != 0) {
bdcd8170
KV		 497 ath6kl_err("bmi_write_memory for htc version failed\n");
498 return -EIO;
499 }
500
501 /* set the firmware mode to STA/IBSS/AP */
502 param = 0;
503
80fb2686 504 if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
bdcd8170
KV		 505 ath6kl_err("bmi_read_memory for setting fwmode failed\n");
506 return -EIO;
507 }
508
71f96ee6 509 param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
7b85832d
VT		 510 param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
511 param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
512
bdcd8170
KV		 513 param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
514 param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
515
24fc32b3 516 if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
bdcd8170
KV		 517 ath6kl_err("bmi_write_memory for setting fwmode failed\n");
518 return -EIO;
519 }
520
521 ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
522
523 /*
524 * Hardcode the address use for the extended board data
525 * Ideally this should be pre-allocate by the OS at boot time
526 * But since it is a new feature and board data is loaded
527 * at init time, we have to workaround this from host.
528 * It is difficult to patch the firmware boot code,
529 * but possible in theory.
530 */
531
991b27ea
KV		 532 param = ar->hw.board_ext_data_addr;
533 ram_reserved_size = ar->hw.reserved_ram_size;
bdcd8170 534
24fc32b3 535 if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
991b27ea
KV		 536 ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
537 return -EIO;
538 }
539
24fc32b3
KV		 540 if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
541 ram_reserved_size) != 0) {
991b27ea
KV		 542 ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
543 return -EIO;
bdcd8170
KV		 544 }
545
546 /* set the block size for the target */
547 if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
548 /* use default number of control buffers */
549 return -EIO;
550
39586bf2 551 /* Configure GPIO AR600x UART */
24fc32b3
KV		 552 status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
553 ar->hw.uarttx_pin);
39586bf2
RH		 554 if (status)
555 return status;
556
557 /* Configure target refclk_hz */
24fc32b3 558 status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
39586bf2
RH		 559 if (status)
560 return status;
561
bdcd8170
KV		 562 return 0;
563}
564
bdcd8170 565/* firmware upload */
bdcd8170
KV		 566static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
567 u8 **fw, size_t *fw_len)
568{
569 const struct firmware *fw_entry;
570 int ret;
571
572 ret = request_firmware(&fw_entry, filename, ar->dev);
573 if (ret)
574 return ret;
575
576 *fw_len = fw_entry->size;
577 *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
578
579 if (*fw == NULL)
580 ret = -ENOMEM;
581
582 release_firmware(fw_entry);
583
584 return ret;
585}
586
92ecbff4 587#ifdef CONFIG_OF
92ecbff4
SL		 588/*
589 * Check the device tree for a board-id and use it to construct
590 * the pathname to the firmware file. Used (for now) to find a
591 * fallback to the "bdata.bin" file--typically a symlink to the
592 * appropriate board-specific file.
593 */
594static bool check_device_tree(struct ath6kl *ar)
595{
596 static const char *board_id_prop = "atheros,board-id";
597 struct device_node *node;
598 char board_filename[64];
599 const char *board_id;
600 int ret;
601
602 for_each_compatible_node(node, NULL, "atheros,ath6kl") {
603 board_id = of_get_property(node, board_id_prop, NULL);
604 if (board_id == NULL) {
605 ath6kl_warn("No \"%s\" property on %s node.\n",
606 board_id_prop, node->name);
607 continue;
608 }
609 snprintf(board_filename, sizeof(board_filename),
c0038972 610 "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
92ecbff4
SL		 611
612 ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
613 &ar->fw_board_len);
614 if (ret) {
615 ath6kl_err("Failed to get DT board file %s: %d\n",
616 board_filename, ret);
617 continue;
618 }
619 return true;
620 }
621 return false;
622}
623#else
624static bool check_device_tree(struct ath6kl *ar)
625{
626 return false;
627}
628#endif /* CONFIG_OF */
629
bdcd8170
KV		 630static int ath6kl_fetch_board_file(struct ath6kl *ar)
631{
632 const char *filename;
633 int ret;
634
772c31ee
KV		 635 if (ar->fw_board != NULL)
636 return 0;
637
d1a9421d
KV		 638 if (WARN_ON(ar->hw.fw_board == NULL))
639 return -EINVAL;
640
641 filename = ar->hw.fw_board;
bdcd8170
KV		 642
643 ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
644 &ar->fw_board_len);
645 if (ret == 0) {
646 /* managed to get proper board file */
647 return 0;
648 }
649
92ecbff4
SL		 650 if (check_device_tree(ar)) {
651 /* got board file from device tree */
652 return 0;
653 }
654
bdcd8170
KV		 655 /* there was no proper board file, try to use default instead */
656 ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
657 filename, ret);
658
d1a9421d 659 filename = ar->hw.fw_default_board;
bdcd8170
KV		 660
661 ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
662 &ar->fw_board_len);
663 if (ret) {
664 ath6kl_err("Failed to get default board file %s: %d\n",
665 filename, ret);
666 return ret;
667 }
668
669 ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
670 ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
671
672 return 0;
673}
674
772c31ee
KV		 675static int ath6kl_fetch_otp_file(struct ath6kl *ar)
676{
c0038972 677 char filename[100];
772c31ee
KV		 678 int ret;
679
680 if (ar->fw_otp != NULL)
681 return 0;
682
c0038972 683 if (ar->hw.fw.otp == NULL) {
d1a9421d
KV		 684 ath6kl_dbg(ATH6KL_DBG_BOOT,
685 "no OTP file configured for this hw\n");
772c31ee 686 return 0;
772c31ee
KV		 687 }
688
c0038972
KV		 689 snprintf(filename, sizeof(filename), "%s/%s",
690 ar->hw.fw.dir, ar->hw.fw.otp);
d1a9421d 691
772c31ee
KV		 692 ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
693 &ar->fw_otp_len);
694 if (ret) {
695 ath6kl_err("Failed to get OTP file %s: %d\n",
696 filename, ret);
697 return ret;
698 }
699
700 return 0;
701}
702
5f1127ff 703static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
772c31ee 704{
c0038972 705 char filename[100];
772c31ee
KV		 706 int ret;
707
5f1127ff 708 if (ar->testmode == 0)
772c31ee
KV		 709 return 0;
710
5f1127ff 711 ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
772c31ee 712
5f1127ff
KV		 713 if (ar->testmode == 2) {
714 if (ar->hw.fw.utf == NULL) {
715 ath6kl_warn("testmode 2 not supported\n");
716 return -EOPNOTSUPP;
717 }
d1a9421d 718
5f1127ff
KV		 719 snprintf(filename, sizeof(filename), "%s/%s",
720 ar->hw.fw.dir, ar->hw.fw.utf);
721 } else {
722 if (ar->hw.fw.tcmd == NULL) {
723 ath6kl_warn("testmode 1 not supported\n");
724 return -EOPNOTSUPP;
cd23c1c9 725 }
772c31ee 726
5f1127ff
KV		 727 snprintf(filename, sizeof(filename), "%s/%s",
728 ar->hw.fw.dir, ar->hw.fw.tcmd);
772c31ee
KV		 729 }
730
5f1127ff
KV		 731 set_bit(TESTMODE, &ar->flag);
732
733 ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
734 if (ret) {
735 ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
736 ar->testmode, filename, ret);
737 return ret;
738 }
739
740 return 0;
741}
742
743static int ath6kl_fetch_fw_file(struct ath6kl *ar)
744{
745 char filename[100];
746 int ret;
747
748 if (ar->fw != NULL)
749 return 0;
750
c0038972
KV		 751 /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
752 if (WARN_ON(ar->hw.fw.fw == NULL))
d1a9421d
KV		 753 return -EINVAL;
754
c0038972
KV		 755 snprintf(filename, sizeof(filename), "%s/%s",
756 ar->hw.fw.dir, ar->hw.fw.fw);
772c31ee 757
772c31ee
KV		 758 ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
759 if (ret) {
760 ath6kl_err("Failed to get firmware file %s: %d\n",
761 filename, ret);
762 return ret;
763 }
764
765 return 0;
766}
767
768static int ath6kl_fetch_patch_file(struct ath6kl *ar)
769{
c0038972 770 char filename[100];
772c31ee
KV		 771 int ret;
772
d1a9421d 773 if (ar->fw_patch != NULL)
772c31ee 774 return 0;
772c31ee 775
c0038972 776 if (ar->hw.fw.patch == NULL)
d1a9421d
KV		 777 return 0;
778
c0038972
KV		 779 snprintf(filename, sizeof(filename), "%s/%s",
780 ar->hw.fw.dir, ar->hw.fw.patch);
d1a9421d
KV		 781
782 ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
783 &ar->fw_patch_len);
784 if (ret) {
785 ath6kl_err("Failed to get patch file %s: %d\n",
786 filename, ret);
787 return ret;
772c31ee
KV		 788 }
789
790 return 0;
791}
792
cd23c1c9
AY		 793static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
794{
795 char filename[100];
796 int ret;
797
5f1127ff 798 if (ar->testmode != 2)
cd23c1c9
AY		 799 return 0;
800
801 if (ar->fw_testscript != NULL)
802 return 0;
803
804 if (ar->hw.fw.testscript == NULL)
805 return 0;
806
807 snprintf(filename, sizeof(filename), "%s/%s",
96f1fadc 808 ar->hw.fw.dir, ar->hw.fw.testscript);
cd23c1c9
AY		 809
810 ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
811 &ar->fw_testscript_len);
812 if (ret) {
813 ath6kl_err("Failed to get testscript file %s: %d\n",
96f1fadc 814 filename, ret);
cd23c1c9
AY		 815 return ret;
816 }
817
818 return 0;
819}
820
50d41234 821static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
772c31ee
KV		 822{
823 int ret;
824
772c31ee
KV		 825 ret = ath6kl_fetch_otp_file(ar);
826 if (ret)
827 return ret;
828
829 ret = ath6kl_fetch_fw_file(ar);
830 if (ret)
831 return ret;
832
833 ret = ath6kl_fetch_patch_file(ar);
834 if (ret)
835 return ret;
836
cd23c1c9
AY		 837 ret = ath6kl_fetch_testscript_file(ar);
838 if (ret)
839 return ret;
840
772c31ee
KV		 841 return 0;
842}
bdcd8170 843
65a8b4cc 844static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
50d41234
KV		 845{
846 size_t magic_len, len, ie_len;
847 const struct firmware *fw;
848 struct ath6kl_fw_ie *hdr;
c0038972 849 char filename[100];
50d41234 850 const u8 *data;
97e0496d 851 int ret, ie_id, i, index, bit;
8a137480 852 __le32 *val;
50d41234 853
65a8b4cc 854 snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
50d41234
KV		 855
856 ret = request_firmware(&fw, filename, ar->dev);
857 if (ret)
858 return ret;
859
860 data = fw->data;
861 len = fw->size;
862
863 /* magic also includes the null byte, check that as well */
864 magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
865
866 if (len < magic_len) {
867 ret = -EINVAL;
868 goto out;
869 }
870
871 if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
872 ret = -EINVAL;
873 goto out;
874 }
875
876 len -= magic_len;
877 data += magic_len;
878
879 /* loop elements */
880 while (len > sizeof(struct ath6kl_fw_ie)) {
881 /* hdr is unaligned! */
882 hdr = (struct ath6kl_fw_ie *) data;
883
884 ie_id = le32_to_cpup(&hdr->id);
885 ie_len = le32_to_cpup(&hdr->len);
886
887 len -= sizeof(*hdr);
888 data += sizeof(*hdr);
889
890 if (len < ie_len) {
891 ret = -EINVAL;
892 goto out;
893 }
894
895 switch (ie_id) {
896 case ATH6KL_FW_IE_OTP_IMAGE:
ef548626 897 ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
96f1fadc 898 ie_len);
6bc36431 899
50d41234
KV		 900 ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
901
902 if (ar->fw_otp == NULL) {
903 ret = -ENOMEM;
904 goto out;
905 }
906
907 ar->fw_otp_len = ie_len;
908 break;
909 case ATH6KL_FW_IE_FW_IMAGE:
ef548626 910 ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
96f1fadc 911 ie_len);
6bc36431 912
5f1127ff
KV		 913 /* in testmode we already might have a fw file */
914 if (ar->fw != NULL)
915 break;
916
50d41234
KV		 917 ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
918
919 if (ar->fw == NULL) {
920 ret = -ENOMEM;
921 goto out;
922 }
923
924 ar->fw_len = ie_len;
925 break;
926 case ATH6KL_FW_IE_PATCH_IMAGE:
ef548626 927 ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
96f1fadc 928 ie_len);
6bc36431 929
50d41234
KV		 930 ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
931
932 if (ar->fw_patch == NULL) {
933 ret = -ENOMEM;
934 goto out;
935 }
936
937 ar->fw_patch_len = ie_len;
938 break;
8a137480
KV		 939 case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
940 val = (__le32 *) data;
941 ar->hw.reserved_ram_size = le32_to_cpup(val);
6bc36431
KV		 942
943 ath6kl_dbg(ATH6KL_DBG_BOOT,
944 "found reserved ram size ie 0x%d\n",
945 ar->hw.reserved_ram_size);
8a137480 946 break;
97e0496d 947 case ATH6KL_FW_IE_CAPABILITIES:
277d90f4
KV		 948 if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
949 break;
950
6bc36431 951 ath6kl_dbg(ATH6KL_DBG_BOOT,
ef548626 952 "found firmware capabilities ie (%zd B)\n",
6bc36431
KV		 953 ie_len);
954
97e0496d 955 for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
277d90f4 956 index = i / 8;
97e0496d
KV		 957 bit = i % 8;
958
959 if (data[index] & (1 << bit))
960 __set_bit(i, ar->fw_capabilities);
961 }
6bc36431
KV		 962
963 ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
964 ar->fw_capabilities,
965 sizeof(ar->fw_capabilities));
97e0496d 966 break;
1b4304da
KV		 967 case ATH6KL_FW_IE_PATCH_ADDR:
968 if (ie_len != sizeof(*val))
969 break;
970
971 val = (__le32 *) data;
972 ar->hw.dataset_patch_addr = le32_to_cpup(val);
6bc36431
KV		 973
974 ath6kl_dbg(ATH6KL_DBG_BOOT,
03ef0250 975 "found patch address ie 0x%x\n",
6bc36431 976 ar->hw.dataset_patch_addr);
1b4304da 977 break;
03ef0250
KV		 978 case ATH6KL_FW_IE_BOARD_ADDR:
979 if (ie_len != sizeof(*val))
980 break;
981
982 val = (__le32 *) data;
983 ar->hw.board_addr = le32_to_cpup(val);
984
985 ath6kl_dbg(ATH6KL_DBG_BOOT,
986 "found board address ie 0x%x\n",
987 ar->hw.board_addr);
988 break;
368b1b0f
KV		 989 case ATH6KL_FW_IE_VIF_MAX:
990 if (ie_len != sizeof(*val))
991 break;
992
993 val = (__le32 *) data;
994 ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
995 ATH6KL_VIF_MAX);
996
f143379d
VT		 997 if (ar->vif_max > 1 && !ar->p2p)
998 ar->max_norm_iface = 2;
999
368b1b0f
KV		 1000 ath6kl_dbg(ATH6KL_DBG_BOOT,
1001 "found vif max ie %d\n", ar->vif_max);
1002 break;
50d41234 1003 default:
6bc36431 1004 ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
50d41234
KV		 1005 le32_to_cpup(&hdr->id));
1006 break;
1007 }
1008
1009 len -= ie_len;
1010 data += ie_len;
1011 };
1012
1013 ret = 0;
1014out:
1015 release_firmware(fw);
1016
1017 return ret;
1018}
1019
45eaa78f 1020int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
50d41234
KV		 1021{
1022 int ret;
1023
1024 ret = ath6kl_fetch_board_file(ar);
1025 if (ret)
1026 return ret;
1027
5f1127ff
KV		 1028 ret = ath6kl_fetch_testmode_file(ar);
1029 if (ret)
1030 return ret;
1031
65a8b4cc 1032 ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
6bc36431 1033 if (ret == 0) {
65a8b4cc
KV		 1034 ar->fw_api = 3;
1035 goto out;
1036 }
1037
1038 ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
1039 if (ret == 0) {
1040 ar->fw_api = 2;
1041 goto out;
6bc36431 1042 }
50d41234
KV		 1043
1044 ret = ath6kl_fetch_fw_api1(ar);
1045 if (ret)
1046 return ret;
1047
65a8b4cc
KV		 1048 ar->fw_api = 1;
1049
1050out:
1051 ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
6bc36431 1052
50d41234
KV		 1053 return 0;
1054}
1055
bdcd8170
KV		 1056static int ath6kl_upload_board_file(struct ath6kl *ar)
1057{
1058 u32 board_address, board_ext_address, param;
31024d99 1059 u32 board_data_size, board_ext_data_size;
bdcd8170
KV		 1060 int ret;
1061
772c31ee
KV		 1062 if (WARN_ON(ar->fw_board == NULL))
1063 return -ENOENT;
bdcd8170 1064
31024d99
KF		 1065 /*
1066 * Determine where in Target RAM to write Board Data.
1067 * For AR6004, host determine Target RAM address for
1068 * writing board data.
1069 */
0d4d72bf 1070 if (ar->hw.board_addr != 0) {
24fc32b3
KV		 1071 ath6kl_bmi_write_hi32(ar, hi_board_data,
1072 ar->hw.board_addr);
31024d99 1073 } else {
80fb2686 1074 ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
31024d99
KF		 1075 }
1076
bdcd8170 1077 /* determine where in target ram to write extended board data */
80fb2686 1078 ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
bdcd8170 1079
50e2740b
KV		 1080 if (ar->target_type == TARGET_TYPE_AR6003 &&
1081 board_ext_address == 0) {
bdcd8170
KV		 1082 ath6kl_err("Failed to get board file target address.\n");
1083 return -EINVAL;
1084 }
1085
31024d99
KF		 1086 switch (ar->target_type) {
1087 case TARGET_TYPE_AR6003:
1088 board_data_size = AR6003_BOARD_DATA_SZ;
1089 board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
fb1ac2ef
PK		 1090 if (ar->fw_board_len > (board_data_size + board_ext_data_size))
1091 board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
31024d99
KF		 1092 break;
1093 case TARGET_TYPE_AR6004:
1094 board_data_size = AR6004_BOARD_DATA_SZ;
1095 board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
1096 break;
1097 default:
1098 WARN_ON(1);
1099 return -EINVAL;
1100 break;
1101 }
1102
50e2740b
KV		 1103 if (board_ext_address &&
1104 ar->fw_board_len == (board_data_size + board_ext_data_size)) {
31024d99 1105
bdcd8170 1106 /* write extended board data */
6bc36431
KV		 1107 ath6kl_dbg(ATH6KL_DBG_BOOT,
1108 "writing extended board data to 0x%x (%d B)\n",
1109 board_ext_address, board_ext_data_size);
1110
bdcd8170 1111 ret = ath6kl_bmi_write(ar, board_ext_address,
31024d99
KF		 1112 ar->fw_board + board_data_size,
1113 board_ext_data_size);
bdcd8170
KV		 1114 if (ret) {
1115 ath6kl_err("Failed to write extended board data: %d\n",
1116 ret);
1117 return ret;
1118 }
1119
1120 /* record that extended board data is initialized */
31024d99
KF		 1121 param = (board_ext_data_size << 16) | 1;
1122
24fc32b3 1123 ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
bdcd8170
KV		 1124 }
1125
31024d99 1126 if (ar->fw_board_len < board_data_size) {
bdcd8170
KV		 1127 ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
1128 ret = -EINVAL;
1129 return ret;
1130 }
1131
6bc36431
KV		 1132 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
1133 board_address, board_data_size);
1134
bdcd8170 1135 ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
31024d99 1136 board_data_size);
bdcd8170
KV		 1137
1138 if (ret) {
1139 ath6kl_err("Board file bmi write failed: %d\n", ret);
1140 return ret;
1141 }
1142
1143 /* record the fact that Board Data IS initialized */
24fc32b3 1144 ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
bdcd8170
KV		 1145
1146 return ret;
1147}
1148
1149static int ath6kl_upload_otp(struct ath6kl *ar)
1150{
bdcd8170 1151 u32 address, param;
bef26a7f 1152 bool from_hw = false;
bdcd8170
KV		 1153 int ret;
1154
50e2740b
KV		 1155 if (ar->fw_otp == NULL)
1156 return 0;
bdcd8170 1157
a01ac414 1158 address = ar->hw.app_load_addr;
bdcd8170 1159
ef548626 1160 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
6bc36431
KV		 1161 ar->fw_otp_len);
1162
bdcd8170
KV		 1163 ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
1164 ar->fw_otp_len);
1165 if (ret) {
1166 ath6kl_err("Failed to upload OTP file: %d\n", ret);
1167 return ret;
1168 }
1169
639d0b89 1170 /* read firmware start address */
80fb2686 1171 ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
639d0b89
KV		 1172
1173 if (ret) {
1174 ath6kl_err("Failed to read hi_app_start: %d\n", ret);
1175 return ret;
1176 }
1177
bef26a7f
KV		 1178 if (ar->hw.app_start_override_addr == 0) {
1179 ar->hw.app_start_override_addr = address;
1180 from_hw = true;
1181 }
639d0b89 1182
bef26a7f
KV		 1183 ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
1184 from_hw ? " (from hw)" : "",
6bc36431
KV		 1185 ar->hw.app_start_override_addr);
1186
bdcd8170 1187 /* execute the OTP code */
bef26a7f
KV		 1188 ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
1189 ar->hw.app_start_override_addr);
bdcd8170 1190 param = 0;
bef26a7f 1191 ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
bdcd8170
KV		 1192
1193 return ret;
1194}
1195
1196static int ath6kl_upload_firmware(struct ath6kl *ar)
1197{
bdcd8170
KV		 1198 u32 address;
1199 int ret;
1200
772c31ee 1201 if (WARN_ON(ar->fw == NULL))
50e2740b 1202 return 0;
bdcd8170 1203
a01ac414 1204 address = ar->hw.app_load_addr;
bdcd8170 1205
ef548626 1206 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
6bc36431
KV		 1207 address, ar->fw_len);
1208
bdcd8170
KV		 1209 ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
1210
1211 if (ret) {
1212 ath6kl_err("Failed to write firmware: %d\n", ret);
1213 return ret;
1214 }
1215
31024d99
KF		 1216 /*
1217 * Set starting address for firmware
1218 * Don't need to setup app_start override addr on AR6004
1219 */
1220 if (ar->target_type != TARGET_TYPE_AR6004) {
a01ac414 1221 address = ar->hw.app_start_override_addr;
31024d99
KF		 1222 ath6kl_bmi_set_app_start(ar, address);
1223 }
bdcd8170
KV		 1224 return ret;
1225}
1226
1227static int ath6kl_upload_patch(struct ath6kl *ar)
1228{
24fc32b3 1229 u32 address;
bdcd8170
KV		 1230 int ret;
1231
50e2740b
KV		 1232 if (ar->fw_patch == NULL)
1233 return 0;
bdcd8170 1234
a01ac414 1235 address = ar->hw.dataset_patch_addr;
bdcd8170 1236
ef548626 1237 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
6bc36431
KV		 1238 address, ar->fw_patch_len);
1239
bdcd8170
KV		 1240 ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
1241 if (ret) {
1242 ath6kl_err("Failed to write patch file: %d\n", ret);
1243 return ret;
1244 }
1245
24fc32b3 1246 ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
bdcd8170
KV		 1247
1248 return 0;
1249}
1250
cd23c1c9
AY		 1251static int ath6kl_upload_testscript(struct ath6kl *ar)
1252{
24fc32b3 1253 u32 address;
cd23c1c9
AY		 1254 int ret;
1255
5f1127ff 1256 if (ar->testmode != 2)
cd23c1c9
AY		 1257 return 0;
1258
1259 if (ar->fw_testscript == NULL)
1260 return 0;
1261
1262 address = ar->hw.testscript_addr;
1263
1264 ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
96f1fadc 1265 address, ar->fw_testscript_len);
cd23c1c9
AY		 1266
1267 ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
1268 ar->fw_testscript_len);
1269 if (ret) {
1270 ath6kl_err("Failed to write testscript file: %d\n", ret);
1271 return ret;
1272 }
1273
24fc32b3
KV		 1274 ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
1275 ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
1276 ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
cd23c1c9
AY		 1277
1278 return 0;
1279}
1280
bdcd8170
KV		 1281static int ath6kl_init_upload(struct ath6kl *ar)
1282{
1283 u32 param, options, sleep, address;
1284 int status = 0;
1285
31024d99 1286 if (ar->target_type != TARGET_TYPE_AR6003 &&
96f1fadc 1287 ar->target_type != TARGET_TYPE_AR6004)
bdcd8170
KV		 1288 return -EINVAL;
1289
1290 /* temporarily disable system sleep */
1291 address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1292 status = ath6kl_bmi_reg_read(ar, address, &param);
1293 if (status)
1294 return status;
1295
1296 options = param;
1297
1298 param |= ATH6KL_OPTION_SLEEP_DISABLE;
1299 status = ath6kl_bmi_reg_write(ar, address, param);
1300 if (status)
1301 return status;
1302
1303 address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1304 status = ath6kl_bmi_reg_read(ar, address, &param);
1305 if (status)
1306 return status;
1307
1308 sleep = param;
1309
1310 param |= SM(SYSTEM_SLEEP_DISABLE, 1);
1311 status = ath6kl_bmi_reg_write(ar, address, param);
1312 if (status)
1313 return status;
1314
1315 ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
1316 options, sleep);
1317
1318 /* program analog PLL register */
31024d99
KF		 1319 /* no need to control 40/44MHz clock on AR6004 */
1320 if (ar->target_type != TARGET_TYPE_AR6004) {
1321 status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
1322 0xF9104001);
bdcd8170 1323
31024d99
KF		 1324 if (status)
1325 return status;
bdcd8170 1326
31024d99
KF		 1327 /* Run at 80/88MHz by default */
1328 param = SM(CPU_CLOCK_STANDARD, 1);
1329
1330 address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
1331 status = ath6kl_bmi_reg_write(ar, address, param);
1332 if (status)
1333 return status;
1334 }
bdcd8170
KV		 1335
1336 param = 0;
1337 address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
1338 param = SM(LPO_CAL_ENABLE, 1);
1339 status = ath6kl_bmi_reg_write(ar, address, param);
1340 if (status)
1341 return status;
1342
1343 /* WAR to avoid SDIO CRC err */
4480bb59
RM		 1344 if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
1345 ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
bdcd8170
KV		 1346 ath6kl_err("temporary war to avoid sdio crc error\n");
1347
1348 param = 0x20;
1349
1350 address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
1351 status = ath6kl_bmi_reg_write(ar, address, param);
1352 if (status)
1353 return status;
1354
1355 address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
1356 status = ath6kl_bmi_reg_write(ar, address, param);
1357 if (status)
1358 return status;
1359
1360 address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
1361 status = ath6kl_bmi_reg_write(ar, address, param);
1362 if (status)
1363 return status;
1364
1365 address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
1366 status = ath6kl_bmi_reg_write(ar, address, param);
1367 if (status)
1368 return status;
1369 }
1370
1371 /* write EEPROM data to Target RAM */
1372 status = ath6kl_upload_board_file(ar);
1373 if (status)
1374 return status;
1375
1376 /* transfer One time Programmable data */
1377 status = ath6kl_upload_otp(ar);
1378 if (status)
1379 return status;
1380
1381 /* Download Target firmware */
1382 status = ath6kl_upload_firmware(ar);
1383 if (status)
1384 return status;
1385
1386 status = ath6kl_upload_patch(ar);
1387 if (status)
1388 return status;
1389
cd23c1c9
AY		 1390 /* Download the test script */
1391 status = ath6kl_upload_testscript(ar);
1392 if (status)
1393 return status;
1394
bdcd8170
KV		 1395 /* Restore system sleep */
1396 address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
1397 status = ath6kl_bmi_reg_write(ar, address, sleep);
1398 if (status)
1399 return status;
1400
1401 address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
1402 param = options | 0x20;
1403 status = ath6kl_bmi_reg_write(ar, address, param);
1404 if (status)
1405 return status;
1406
bdcd8170
KV		 1407 return status;
1408}
1409
45eaa78f 1410int ath6kl_init_hw_params(struct ath6kl *ar)
a01ac414 1411{
1b46dc04 1412 const struct ath6kl_hw *uninitialized_var(hw);
856f4b31 1413 int i;
bef26a7f 1414
856f4b31
KV		 1415 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
1416 hw = &hw_list[i];
bef26a7f 1417
856f4b31
KV		 1418 if (hw->id == ar->version.target_ver)
1419 break;
1420 }
1421
1422 if (i == ARRAY_SIZE(hw_list)) {
a01ac414
KV		 1423 ath6kl_err("Unsupported hardware version: 0x%x\n",
1424 ar->version.target_ver);
1425 return -EINVAL;
1426 }
1427
856f4b31
KV		 1428 ar->hw = *hw;
1429
6bc36431
KV		 1430 ath6kl_dbg(ATH6KL_DBG_BOOT,
1431 "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
1432 ar->version.target_ver, ar->target_type,
1433 ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
1434 ath6kl_dbg(ATH6KL_DBG_BOOT,
1435 "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
1436 ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
1437 ar->hw.reserved_ram_size);
39586bf2
RH		 1438 ath6kl_dbg(ATH6KL_DBG_BOOT,
1439 "refclk_hz %d uarttx_pin %d",
1440 ar->hw.refclk_hz, ar->hw.uarttx_pin);
6bc36431 1441
a01ac414
KV		 1442 return 0;
1443}
1444
293badf4
KV		 1445static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
1446{
1447 switch (type) {
1448 case ATH6KL_HIF_TYPE_SDIO:
1449 return "sdio";
1450 case ATH6KL_HIF_TYPE_USB:
1451 return "usb";
1452 }
1453
1454 return NULL;
1455}
1456
5fe4dffb 1457int ath6kl_init_hw_start(struct ath6kl *ar)
20459ee2
KV		 1458{
1459 long timeleft;
1460 int ret, i;
1461
5fe4dffb
KV		 1462 ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
1463
20459ee2
KV		 1464 ret = ath6kl_hif_power_on(ar);
1465 if (ret)
1466 return ret;
1467
1468 ret = ath6kl_configure_target(ar);
1469 if (ret)
1470 goto err_power_off;
1471
1472 ret = ath6kl_init_upload(ar);
1473 if (ret)
1474 goto err_power_off;
1475
1476 /* Do we need to finish the BMI phase */
1477 /* FIXME: return error from ath6kl_bmi_done() */
1478 if (ath6kl_bmi_done(ar)) {
1479 ret = -EIO;
1480 goto err_power_off;
1481 }
1482
1483 /*
1484 * The reason we have to wait for the target here is that the
1485 * driver layer has to init BMI in order to set the host block
1486 * size.
1487 */
1488 if (ath6kl_htc_wait_target(ar->htc_target)) {
1489 ret = -EIO;
1490 goto err_power_off;
1491 }
1492
1493 if (ath6kl_init_service_ep(ar)) {
1494 ret = -EIO;
1495 goto err_cleanup_scatter;
1496 }
1497
1498 /* setup credit distribution */
1499 ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
1500
1501 /* start HTC */
1502 ret = ath6kl_htc_start(ar->htc_target);
1503 if (ret) {
1504 /* FIXME: call this */
1505 ath6kl_cookie_cleanup(ar);
1506 goto err_cleanup_scatter;
1507 }
1508
1509 /* Wait for Wmi event to be ready */
1510 timeleft = wait_event_interruptible_timeout(ar->event_wq,
1511 test_bit(WMI_READY,
1512 &ar->flag),
1513 WMI_TIMEOUT);
1514
1515 ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
1516
293badf4
KV		 1517
1518 if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
65a8b4cc 1519 ath6kl_info("%s %s fw %s api %d%s\n",
293badf4
KV		 1520 ar->hw.name,
1521 ath6kl_init_get_hif_name(ar->hif_type),
1522 ar->wiphy->fw_version,
65a8b4cc 1523 ar->fw_api,
293badf4
KV		 1524 test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
1525 }
1526
20459ee2
KV		 1527 if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
1528 ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
1529 ATH6KL_ABI_VERSION, ar->version.abi_ver);
1530 ret = -EIO;
1531 goto err_htc_stop;
1532 }
1533
1534 if (!timeleft || signal_pending(current)) {
1535 ath6kl_err("wmi is not ready or wait was interrupted\n");
1536 ret = -EIO;
1537 goto err_htc_stop;
1538 }
1539
1540 ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
1541
1542 /* communicate the wmi protocol verision to the target */
1543 /* FIXME: return error */
1544 if ((ath6kl_set_host_app_area(ar)) != 0)
1545 ath6kl_err("unable to set the host app area\n");
1546
71f96ee6 1547 for (i = 0; i < ar->vif_max; i++) {
20459ee2
KV		 1548 ret = ath6kl_target_config_wlan_params(ar, i);
1549 if (ret)
1550 goto err_htc_stop;
1551 }
1552
76a9fbe2
KV		 1553 ar->state = ATH6KL_STATE_ON;
1554
20459ee2
KV		 1555 return 0;
1556
1557err_htc_stop:
1558 ath6kl_htc_stop(ar->htc_target);
1559err_cleanup_scatter:
1560 ath6kl_hif_cleanup_scatter(ar);
1561err_power_off:
1562 ath6kl_hif_power_off(ar);
1563
1564 return ret;
1565}
1566
5fe4dffb
KV		 1567int ath6kl_init_hw_stop(struct ath6kl *ar)
1568{
1569 int ret;
1570
1571 ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
1572
1573 ath6kl_htc_stop(ar->htc_target);
1574
1575 ath6kl_hif_stop(ar);
1576
1577 ath6kl_bmi_reset(ar);
1578
1579 ret = ath6kl_hif_power_off(ar);
1580 if (ret)
1581 ath6kl_warn("failed to power off hif: %d\n", ret);
1582
76a9fbe2
KV		 1583 ar->state = ATH6KL_STATE_OFF;
1584
5fe4dffb
KV		 1585 return 0;
1586}
1587
c25889e8 1588/* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
55055976 1589void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
6db8fa53
VT		 1590{
1591 static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1592 bool discon_issued;
1593
1594 netif_stop_queue(vif->ndev);
1595
1596 clear_bit(WLAN_ENABLED, &vif->flags);
1597
1598 if (wmi_ready) {
1599 discon_issued = test_bit(CONNECTED, &vif->flags) ||
1600 test_bit(CONNECT_PEND, &vif->flags);
1601 ath6kl_disconnect(vif);
1602 del_timer(&vif->disconnect_timer);
1603
1604 if (discon_issued)
1605 ath6kl_disconnect_event(vif, DISCONNECT_CMD,
1606 (vif->nw_type & AP_NETWORK) ?
1607 bcast_mac : vif->bssid,
1608 0, NULL, 0);
1609 }
1610
1611 if (vif->scan_req) {
1612 cfg80211_scan_done(vif->scan_req, true);
1613 vif->scan_req = NULL;
1614 }
6db8fa53
VT		 1615}
1616
bdcd8170
KV		 1617void ath6kl_stop_txrx(struct ath6kl *ar)
1618{
990bd915 1619 struct ath6kl_vif *vif, *tmp_vif;
1d2a4456 1620 int i;
bdcd8170
KV		 1621
1622 set_bit(DESTROY_IN_PROGRESS, &ar->flag);
1623
1624 if (down_interruptible(&ar->sem)) {
1625 ath6kl_err("down_interruptible failed\n");
1626 return;
1627 }
1628
1d2a4456
VT		 1629 for (i = 0; i < AP_MAX_NUM_STA; i++)
1630 aggr_reset_state(ar->sta_list[i].aggr_conn);
1631
11f6e40d 1632 spin_lock_bh(&ar->list_lock);
990bd915
VT		 1633 list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
1634 list_del(&vif->list);
11f6e40d 1635 spin_unlock_bh(&ar->list_lock);
990bd915 1636 ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
27929723 1637 rtnl_lock();
c25889e8 1638 ath6kl_cfg80211_vif_cleanup(vif);
27929723 1639 rtnl_unlock();
11f6e40d 1640 spin_lock_bh(&ar->list_lock);
990bd915 1641 }
11f6e40d 1642 spin_unlock_bh(&ar->list_lock);
bdcd8170 1643
6db8fa53 1644 clear_bit(WMI_READY, &ar->flag);
bdcd8170 1645
6db8fa53
VT		 1646 /*
1647 * After wmi_shudown all WMI events will be dropped. We
1648 * need to cleanup the buffers allocated in AP mode and
1649 * give disconnect notification to stack, which usually
1650 * happens in the disconnect_event. Simulate the disconnect
1651 * event by calling the function directly. Sometimes
1652 * disconnect_event will be received when the debug logs
1653 * are collected.
1654 */
1655 ath6kl_wmi_shutdown(ar->wmi);
bdcd8170 1656
6db8fa53
VT		 1657 clear_bit(WMI_ENABLED, &ar->flag);
1658 if (ar->htc_target) {
1659 ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
1660 ath6kl_htc_stop(ar->htc_target);
bdcd8170
KV		 1661 }
1662
6db8fa53
VT		 1663 /*
1664 * Try to reset the device if we can. The driver may have been
1665 * configure NOT to reset the target during a debug session.
1666 */
1667 ath6kl_dbg(ATH6KL_DBG_TRC,
96f1fadc 1668 "attempting to reset target on instance destroy\n");
6db8fa53 1669 ath6kl_reset_device(ar, ar->target_type, true, true);
19703573 1670
6db8fa53 1671 clear_bit(WLAN_ENABLED, &ar->flag);
e8ad9a06
VT		 1672
1673 up(&ar->sem);
bdcd8170 1674}
d6a434d6 1675EXPORT_SYMBOL(ath6kl_stop_txrx);
kernel source for telekom puls (alcatel/mediatek)