[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath5k / attach.c

/*
 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

/*************************************\
* Attach/Detach Functions and helpers *
\*************************************/

#include <linux/pci.h>
#include "ath5k.h"
#include "reg.h"
#include "debug.h"
#include "base.h"

/**
 * ath5k_hw_post - Power On Self Test helper function
 *
 * @ah: The &struct ath5k_hw
 */
static int ath5k_hw_post(struct ath5k_hw *ah)
{

	static const u32 static_pattern[4] = {
		0x55555555,	0xaaaaaaaa,
		0x66666666,	0x99999999
	};
	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	int i, c;
	u16 cur_reg;
	u32 var_pattern;
	u32 init_val;
	u32 cur_val;

	for (c = 0; c < 2; c++) {

		cur_reg = regs[c];

		/* Save previous value */
		init_val = ath5k_hw_reg_read(ah, cur_reg);

		for (i = 0; i < 256; i++) {
			var_pattern = i << 16 | i;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x0039080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		for (i = 0; i < 4; i++) {
			var_pattern = static_pattern[i];
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x003b080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		/* Restore previous value */
		ath5k_hw_reg_write(ah, init_val, cur_reg);

	}

	return 0;

}

/**
 * ath5k_hw_attach - Check if hw is supported and init the needed structs
 *
 * @sc: The &struct ath5k_softc we got from the driver's attach function
 * @mac_version: The mac version id (check out ath5k.h) based on pci id
 *
 * Check if the device is supported, perform a POST and initialize the needed
 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
 * -ENODEV if the device is not supported or prints an error msg if something
 * else went wrong.
 */
struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
{
	struct ath5k_hw *ah;
	struct pci_dev *pdev = sc->pdev;
	int ret;
	u32 srev;

	/*If we passed the test malloc a ath5k_hw struct*/
	ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
	if (ah == NULL) {
		ret = -ENOMEM;
		ATH5K_ERR(sc, "out of memory\n");
		goto err;
	}

	ah->ah_sc = sc;
	ah->ah_iobase = sc->iobase;

	/*
	 * HW information
	 */
	ah->ah_op_mode = NL80211_IFTYPE_STATION;
	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
	ah->ah_turbo = false;
	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	ah->ah_imr = 0;
	ah->ah_atim_window = 0;
	ah->ah_aifs = AR5K_TUNE_AIFS;
	ah->ah_cw_min = AR5K_TUNE_CWMIN;
	ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
	ah->ah_software_retry = false;

	/*
	 * Set the mac version based on the pci id
	 */
	ah->ah_version = mac_version;

	/*Fill the ath5k_hw struct with the needed functions*/
	ret = ath5k_hw_init_desc_functions(ah);
	if (ret)
		goto err_free;

	/* Bring device out of sleep and reset it's units */
	ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
	if (ret)
		goto err_free;

	/* Get MAC, PHY and RADIO revisions */
	srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	ah->ah_mac_srev = srev;
	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
	ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
			0xffffffff;
	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
			CHANNEL_5GHZ);
	ah->ah_phy = AR5K_PHY(0);

	/* Try to identify radio chip based on it's srev */
	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	case AR5K_SREV_RAD_5111:
		ah->ah_radio = AR5K_RF5111;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_5112:
	case AR5K_SREV_RAD_2112:
		ah->ah_radio = AR5K_RF5112;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_2413:
		ah->ah_radio = AR5K_RF2413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5413:
		ah->ah_radio = AR5K_RF5413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2316:
		ah->ah_radio = AR5K_RF2316;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2317:
		ah->ah_radio = AR5K_RF2317;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5424:
		if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
		ah->ah_mac_version == AR5K_SREV_AR2417){
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
		} else {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
		}
		break;
	default:
		/* Identify radio based on mac/phy srev */
		if (ah->ah_version == AR5K_AR5210) {
			ah->ah_radio = AR5K_RF5110;
			ah->ah_single_chip = false;
		} else if (ah->ah_version == AR5K_AR5211) {
			ah->ah_radio = AR5K_RF5111;
			ah->ah_single_chip = false;
			ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
								CHANNEL_2GHZ);
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
		ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
		} else if (srev == AR5K_SREV_AR5213A &&
		ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
			ah->ah_radio = AR5K_RF5112;
			ah->ah_single_chip = false;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
			ah->ah_radio = AR5K_RF2316;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
			ah->ah_radio = AR5K_RF2413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
		} else {
			ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
			ret = -ENODEV;
			goto err_free;
		}
	}


	/* Return on unsuported chips (unsupported eeprom etc) */
	if ((srev >= AR5K_SREV_AR5416) &&
	(srev < AR5K_SREV_AR2425)) {
		ATH5K_ERR(sc, "Device not yet supported.\n");
		ret = -ENODEV;
		goto err_free;
	}

	/*
	 * POST
	 */
	ret = ath5k_hw_post(ah);
	if (ret)
		goto err_free;

	/* Enable pci core retry fix on Hainan (5213A) and later chips */
	if (srev >= AR5K_SREV_AR5213A)
		ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);

	/*
	 * Get card capabilities, calibration values etc
	 * TODO: EEPROM work
	 */
	ret = ath5k_eeprom_init(ah);
	if (ret) {
		ATH5K_ERR(sc, "unable to init EEPROM\n");
		goto err_free;
	}

	/*
	 * Write PCI-E power save settings
	 */
	if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
		struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;

		ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);

		/* Shut off RX when elecidle is asserted */
		ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);

		/* If serdes programing is enabled, increase PCI-E
		 * tx power for systems with long trace from host
		 * to minicard connector. */
		if (ee->ee_serdes)
			ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
		else
			ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);

		/* Shut off PLL and CLKREQ active in L1 */
		ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);

		/* Preserve other settings */
		ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);

		/* Reset SERDES to load new settings */
		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
		mdelay(1);
	}

	/* Get misc capabilities */
	ret = ath5k_hw_set_capabilities(ah);
	if (ret) {
		ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
			sc->pdev->device);
		goto err_free;
	}

	if (srev >= AR5K_SREV_AR2414) {
		ah->ah_combined_mic = true;
		AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
			AR5K_MISC_MODE_COMBINED_MIC);
	}

	/* MAC address is cleared until add_interface */
	ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});

	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
	memset(ah->ah_bssid, 0xff, ETH_ALEN);
	ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
	ath5k_hw_set_opmode(ah);

	ath5k_hw_rfgain_opt_init(ah);

	/* turn on HW LEDs */
	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);

	return ah;
err_free:
	kfree(ah);
err:
	return ERR_PTR(ret);
}

/**
 * ath5k_hw_detach - Free the ath5k_hw struct
 *
 * @ah: The &struct ath5k_hw
 */
void ath5k_hw_detach(struct ath5k_hw *ah)
{
	ATH5K_TRACE(ah->ah_sc);

	__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);

	if (ah->ah_rf_banks != NULL)
		kfree(ah->ah_rf_banks);

	ath5k_eeprom_detach(ah);

	/* assume interrupts are down */
	kfree(ah);
}
Commit	Line	Data
c6e387a2 NK	1	/*
	2	* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
	3	* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
	4	*
	5	* Permission to use, copy, modify, and distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*
	17	*/
	18
	19	/*************************************\
	20	* Attach/Detach Functions and helpers *
	21	\*************************************/
	22
	23	#include <linux/pci.h>
	24	#include "ath5k.h"
	25	#include "reg.h"
	26	#include "debug.h"
	27	#include "base.h"
	28
	29	/**
	30	* ath5k_hw_post - Power On Self Test helper function
	31	*
	32	* @ah: The &struct ath5k_hw
	33	*/
	34	static int ath5k_hw_post(struct ath5k_hw *ah)
	35	{
	36
2c91108c	37	static const u32 static_pattern[4] = {
c6e387a2 NK	38	0x55555555, 0xaaaaaaaa,
	39	0x66666666, 0x99999999
	40	};
2c91108c JS	41	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	42	int i, c;
	43	u16 cur_reg;
	44	u32 var_pattern;
c6e387a2 NK	45	u32 init_val;
	46	u32 cur_val;
	47
	48	for (c = 0; c < 2; c++) {
	49
	50	cur_reg = regs[c];
	51
	52	/* Save previous value */
	53	init_val = ath5k_hw_reg_read(ah, cur_reg);
	54
	55	for (i = 0; i < 256; i++) {
	56	var_pattern = i << 16 \| i;
	57	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	58	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	59
	60	if (cur_val != var_pattern) {
	61	ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
	62	return -EAGAIN;
	63	}
	64
	65	/* Found on ndiswrapper dumps */
	66	var_pattern = 0x0039080f;
	67	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	68	}
	69
	70	for (i = 0; i < 4; i++) {
	71	var_pattern = static_pattern[i];
	72	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	73	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	74
	75	if (cur_val != var_pattern) {
	76	ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
	77	return -EAGAIN;
	78	}
	79
	80	/* Found on ndiswrapper dumps */
	81	var_pattern = 0x003b080f;
	82	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	83	}
	84
	85	/* Restore previous value */
	86	ath5k_hw_reg_write(ah, init_val, cur_reg);
	87
	88	}
	89
	90	return 0;
	91
	92	}
	93
	94	/**
	95	* ath5k_hw_attach - Check if hw is supported and init the needed structs
	96	*
	97	* @sc: The &struct ath5k_softc we got from the driver's attach function
	98	* @mac_version: The mac version id (check out ath5k.h) based on pci id
	99	*
	100	* Check if the device is supported, perform a POST and initialize the needed
	101	* structs. Returns -ENOMEM if we don't have memory for the needed structs,
	102	* -ENODEV if the device is not supported or prints an error msg if something
	103	* else went wrong.
	104	*/
	105	struct ath5k_hw ath5k_hw_attach(struct ath5k_softc sc, u8 mac_version)
	106	{
	107	struct ath5k_hw *ah;
	108	struct pci_dev *pdev = sc->pdev;
c6e387a2 NK	109	int ret;
	110	u32 srev;
	111
	112	/If we passed the test malloc a ath5k_hw struct/
	113	ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
	114	if (ah == NULL) {
	115	ret = -ENOMEM;
	116	ATH5K_ERR(sc, "out of memory\n");
	117	goto err;
	118	}
	119
	120	ah->ah_sc = sc;
	121	ah->ah_iobase = sc->iobase;
	122
	123	/*
	124	* HW information
	125	*/
05c914fe	126	ah->ah_op_mode = NL80211_IFTYPE_STATION;
c6e387a2 NK	127	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
	128	ah->ah_turbo = false;
	129	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	130	ah->ah_imr = 0;
	131	ah->ah_atim_window = 0;
	132	ah->ah_aifs = AR5K_TUNE_AIFS;
	133	ah->ah_cw_min = AR5K_TUNE_CWMIN;
	134	ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
	135	ah->ah_software_retry = false;
c6e387a2 NK	136
c6e387a2 NK	137	/*
ee81c554	138	* Set the mac version based on the pci id
c6e387a2 NK	139	*/
	140	ah->ah_version = mac_version;
	141
	142	/Fill the ath5k_hw struct with the needed functions/
	143	ret = ath5k_hw_init_desc_functions(ah);
	144	if (ret)
	145	goto err_free;
	146
	147	/* Bring device out of sleep and reset it's units */
	148	ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
	149	if (ret)
	150	goto err_free;
	151
	152	/* Get MAC, PHY and RADIO revisions */
	153	srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	154	ah->ah_mac_srev = srev;
	155	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
	156	ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
	157	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
	158	0xffffffff;
	159	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
	160	CHANNEL_5GHZ);
ee81c554	161	ah->ah_phy = AR5K_PHY(0);
c6e387a2	162
ee81c554 NK	163	/* Try to identify radio chip based on it's srev */
	164	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	165	case AR5K_SREV_RAD_5111:
c6e387a2	166	ah->ah_radio = AR5K_RF5111;
ee81c554 NK	167	ah->ah_single_chip = false;
	168	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	169	CHANNEL_2GHZ);
ee81c554 NK	170	break;
	171	case AR5K_SREV_RAD_5112:
	172	case AR5K_SREV_RAD_2112:
c6e387a2	173	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	174	ah->ah_single_chip = false;
	175	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	176	CHANNEL_2GHZ);
ee81c554 NK	177	break;
ee81c554 NK	178	case AR5K_SREV_RAD_2413:
c6e387a2	179	ah->ah_radio = AR5K_RF2413;
ee81c554	180	ah->ah_single_chip = true;
ee81c554 NK	181	break;
ee81c554 NK	182	case AR5K_SREV_RAD_5413:
c6e387a2	183	ah->ah_radio = AR5K_RF5413;
ee81c554	184	ah->ah_single_chip = true;
ee81c554 NK	185	break;
	186	case AR5K_SREV_RAD_2316:
	187	ah->ah_radio = AR5K_RF2316;
	188	ah->ah_single_chip = true;
ee81c554 NK	189	break;
	190	case AR5K_SREV_RAD_2317:
	191	ah->ah_radio = AR5K_RF2317;
	192	ah->ah_single_chip = true;
ee81c554 NK	193	break;
	194	case AR5K_SREV_RAD_5424:
	195	if (ah->ah_mac_version == AR5K_SREV_AR2425 \|\|
	196	ah->ah_mac_version == AR5K_SREV_AR2417){
	197	ah->ah_radio = AR5K_RF2425;
	198	ah->ah_single_chip = true;
ee81c554	199	} else {
c6e387a2	200	ah->ah_radio = AR5K_RF5413;
ee81c554	201	ah->ah_single_chip = true;
ee81c554 NK	202	}
	203	break;
	204	default:
	205	/* Identify radio based on mac/phy srev */
	206	if (ah->ah_version == AR5K_AR5210) {
	207	ah->ah_radio = AR5K_RF5110;
	208	ah->ah_single_chip = false;
	209	} else if (ah->ah_version == AR5K_AR5211) {
	210	ah->ah_radio = AR5K_RF5111;
	211	ah->ah_single_chip = false;
	212	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	213	CHANNEL_2GHZ);
	214	} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) \|\|
	215	ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) \|\|
	216	ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
	217	ah->ah_radio = AR5K_RF2425;
	218	ah->ah_single_chip = true;
	219	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ee81c554	220	} else if (srev == AR5K_SREV_AR5213A &&
e8f055f0	221	ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ee81c554 NK	222	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	223	ah->ah_single_chip = false;
e8f055f0	224	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
ee81c554 NK	225	} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
	226	ah->ah_radio = AR5K_RF2316;
	227	ah->ah_single_chip = true;
	228	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ee81c554 NK	229	} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) \|\|
	230	ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
	231	ah->ah_radio = AR5K_RF5413;
	232	ah->ah_single_chip = true;
	233	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ee81c554 NK	234	} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) \|\|
	235	ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
	236	ah->ah_radio = AR5K_RF2413;
	237	ah->ah_single_chip = true;
	238	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ee81c554 NK	239	} else {
	240	ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
	241	ret = -ENODEV;
	242	goto err_free;
c6e387a2 NK	243	}
c6e387a2 NK	244	}
ee81c554 NK	245
	246
	247	/* Return on unsuported chips (unsupported eeprom etc) */
	248	if ((srev >= AR5K_SREV_AR5416) &&
	249	(srev < AR5K_SREV_AR2425)) {
	250	ATH5K_ERR(sc, "Device not yet supported.\n");
	251	ret = -ENODEV;
	252	goto err_free;
	253	}
c6e387a2	254
c6e387a2 NK	255	/*
	256	* POST
	257	*/
	258	ret = ath5k_hw_post(ah);
	259	if (ret)
	260	goto err_free;
	261
ee81c554 NK	262	/* Enable pci core retry fix on Hainan (5213A) and later chips */
ee81c554 NK	263	if (srev >= AR5K_SREV_AR5213A)
1bef016a	264	ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
c6e387a2 NK	265
c6e387a2 NK	266	/*
ee81c554 NK	267	* Get card capabilities, calibration values etc
ee81c554 NK	268	* TODO: EEPROM work
c6e387a2 NK	269	*/
	270	ret = ath5k_eeprom_init(ah);
	271	if (ret) {
	272	ATH5K_ERR(sc, "unable to init EEPROM\n");
	273	goto err_free;
	274	}
	275
c38e7a93 NK	276	/*
	277	* Write PCI-E power save settings
	278	*/
	279	if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
	280	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
	281
	282	ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
	283	ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
	284
	285	/* Shut off RX when elecidle is asserted */
	286	ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
	287	ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
	288
	289	/* If serdes programing is enabled, increase PCI-E
	290	* tx power for systems with long trace from host
	291	* to minicard connector. */
	292	if (ee->ee_serdes)
	293	ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
	294	else
	295	ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
	296
	297	/* Shut off PLL and CLKREQ active in L1 */
	298	ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
	299
	300	/* Preserve other settings */
	301	ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
	302	ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
	303	ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
	304
	305	/* Reset SERDES to load new settings */
	306	ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
	307	mdelay(1);
	308	}
	309
c6e387a2 NK	310	/* Get misc capabilities */
	311	ret = ath5k_hw_set_capabilities(ah);
	312	if (ret) {
	313	ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
	314	sc->pdev->device);
	315	goto err_free;
	316	}
	317
f650470a BC	318	if (srev >= AR5K_SREV_AR2414) {
	319	ah->ah_combined_mic = true;
	320	AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
	321	AR5K_MISC_MODE_COMBINED_MIC);
	322	}
	323
0e149cf5	324	/* MAC address is cleared until add_interface */
2c91108c	325	ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
0e149cf5	326
c6e387a2 NK	327	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
	328	memset(ah->ah_bssid, 0xff, ETH_ALEN);
	329	ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
	330	ath5k_hw_set_opmode(ah);
	331
6f3b414a	332	ath5k_hw_rfgain_opt_init(ah);
c6e387a2	333
f0f3d388 BC	334	/* turn on HW LEDs */
	335	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
	336
c6e387a2 NK	337	return ah;
	338	err_free:
	339	kfree(ah);
	340	err:
	341	return ERR_PTR(ret);
	342	}
	343
	344	/**
	345	* ath5k_hw_detach - Free the ath5k_hw struct
	346	*
	347	* @ah: The &struct ath5k_hw
	348	*/
	349	void ath5k_hw_detach(struct ath5k_hw *ah)
	350	{
	351	ATH5K_TRACE(ah->ah_sc);
	352
	353	__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
	354
	355	if (ah->ah_rf_banks != NULL)
	356	kfree(ah->ah_rf_banks);
	357
8f655dde NK	358	ath5k_eeprom_detach(ah);
8f655dde NK	359
c6e387a2 NK	360	/* assume interrupts are down */
	361	kfree(ah);
	362	}