Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux | |
3 | * | |
4 | * This software may be used and distributed according to the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * The author may be reached as romieu@cogenit.fr. | |
8 | * Specific bug reports/asian food will be welcome. | |
9 | * | |
10 | * Special thanks to the nice people at CS-Telecom for the hardware and the | |
11 | * access to the test/measure tools. | |
12 | * | |
13 | * | |
14 | * Theory of Operation | |
15 | * | |
16 | * I. Board Compatibility | |
17 | * | |
18 | * This device driver is designed for the Siemens PEB20534 4 ports serial | |
19 | * controller as found on Etinc PCISYNC cards. The documentation for the | |
20 | * chipset is available at http://www.infineon.com: | |
21 | * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with | |
22 | * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1"; | |
23 | * - Application Hint "Management of DSCC4 on-chip FIFO resources". | |
24 | * - Errata sheet DS5 (courtesy of Michael Skerritt). | |
25 | * Jens David has built an adapter based on the same chipset. Take a look | |
26 | * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific | |
27 | * driver. | |
28 | * Sample code (2 revisions) is available at Infineon. | |
29 | * | |
30 | * II. Board-specific settings | |
31 | * | |
32 | * Pcisync can transmit some clock signal to the outside world on the | |
33 | * *first two* ports provided you put a quartz and a line driver on it and | |
34 | * remove the jumpers. The operation is described on Etinc web site. If you | |
35 | * go DCE on these ports, don't forget to use an adequate cable. | |
36 | * | |
37 | * Sharing of the PCI interrupt line for this board is possible. | |
38 | * | |
39 | * III. Driver operation | |
40 | * | |
41 | * The rx/tx operations are based on a linked list of descriptors. The driver | |
42 | * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more | |
43 | * I tried to fix it, the more it started to look like (convoluted) software | |
44 | * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider | |
45 | * this a rfc2119 MUST. | |
46 | * | |
47 | * Tx direction | |
48 | * When the tx ring is full, the xmit routine issues a call to netdev_stop. | |
49 | * The device is supposed to be enabled again during an ALLS irq (we could | |
50 | * use HI but as it's easy to lose events, it's fscked). | |
51 | * | |
52 | * Rx direction | |
53 | * The received frames aren't supposed to span over multiple receiving areas. | |
54 | * I may implement it some day but it isn't the highest ranked item. | |
55 | * | |
56 | * IV. Notes | |
57 | * The current error (XDU, RFO) recovery code is untested. | |
58 | * So far, RDO takes his RX channel down and the right sequence to enable it | |
25985edc | 59 | * again is still a mystery. If RDO happens, plan a reboot. More details |
1da177e4 LT |
60 | * in the code (NB: as this happens, TX still works). |
61 | * Don't mess the cables during operation, especially on DTE ports. I don't | |
62 | * suggest it for DCE either but at least one can get some messages instead | |
63 | * of a complete instant freeze. | |
64 | * Tests are done on Rev. 20 of the silicium. The RDO handling changes with | |
65 | * the documentation/chipset releases. | |
66 | * | |
67 | * TODO: | |
68 | * - test X25. | |
69 | * - use polling at high irq/s, | |
70 | * - performance analysis, | |
71 | * - endianness. | |
72 | * | |
73 | * 2001/12/10 Daniela Squassoni <daniela@cyclades.com> | |
74 | * - Contribution to support the new generic HDLC layer. | |
75 | * | |
76 | * 2002/01 Ueimor | |
77 | * - old style interface removal | |
78 | * - dscc4_release_ring fix (related to DMA mapping) | |
79 | * - hard_start_xmit fix (hint: TxSizeMax) | |
80 | * - misc crapectomy. | |
81 | */ | |
82 | ||
09a1732b JP |
83 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
84 | ||
1da177e4 | 85 | #include <linux/module.h> |
d43c36dc | 86 | #include <linux/sched.h> |
1da177e4 LT |
87 | #include <linux/types.h> |
88 | #include <linux/errno.h> | |
89 | #include <linux/list.h> | |
90 | #include <linux/ioport.h> | |
91 | #include <linux/pci.h> | |
92 | #include <linux/kernel.h> | |
93 | #include <linux/mm.h> | |
5a0e3ad6 | 94 | #include <linux/slab.h> |
1da177e4 | 95 | |
1da177e4 LT |
96 | #include <asm/cache.h> |
97 | #include <asm/byteorder.h> | |
98 | #include <asm/uaccess.h> | |
99 | #include <asm/io.h> | |
100 | #include <asm/irq.h> | |
101 | ||
102 | #include <linux/init.h> | |
a6b7a407 | 103 | #include <linux/interrupt.h> |
1da177e4 LT |
104 | #include <linux/string.h> |
105 | ||
106 | #include <linux/if_arp.h> | |
107 | #include <linux/netdevice.h> | |
108 | #include <linux/skbuff.h> | |
109 | #include <linux/delay.h> | |
1da177e4 | 110 | #include <linux/hdlc.h> |
14cc3e2b | 111 | #include <linux/mutex.h> |
1da177e4 LT |
112 | |
113 | /* Version */ | |
114 | static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n"; | |
115 | static int debug; | |
116 | static int quartz; | |
117 | ||
118 | #ifdef CONFIG_DSCC4_PCI_RST | |
14cc3e2b | 119 | static DEFINE_MUTEX(dscc4_mutex); |
1da177e4 LT |
120 | static u32 dscc4_pci_config_store[16]; |
121 | #endif | |
122 | ||
123 | #define DRV_NAME "dscc4" | |
124 | ||
125 | #undef DSCC4_POLLING | |
126 | ||
127 | /* Module parameters */ | |
128 | ||
129 | MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>"); | |
b595076a | 130 | MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller"); |
1da177e4 LT |
131 | MODULE_LICENSE("GPL"); |
132 | module_param(debug, int, 0); | |
133 | MODULE_PARM_DESC(debug,"Enable/disable extra messages"); | |
134 | module_param(quartz, int, 0); | |
135 | MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)"); | |
136 | ||
137 | /* Structures */ | |
138 | ||
139 | struct thingie { | |
140 | int define; | |
141 | u32 bits; | |
142 | }; | |
143 | ||
144 | struct TxFD { | |
409cd63e AV |
145 | __le32 state; |
146 | __le32 next; | |
147 | __le32 data; | |
148 | __le32 complete; | |
1da177e4 | 149 | u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */ |
409cd63e AV |
150 | /* FWIW, datasheet calls that "dummy" and says that card |
151 | * never looks at it; neither does the driver */ | |
1da177e4 LT |
152 | }; |
153 | ||
154 | struct RxFD { | |
409cd63e AV |
155 | __le32 state1; |
156 | __le32 next; | |
157 | __le32 data; | |
158 | __le32 state2; | |
159 | __le32 end; | |
1da177e4 LT |
160 | }; |
161 | ||
162 | #define DUMMY_SKB_SIZE 64 | |
163 | #define TX_LOW 8 | |
164 | #define TX_RING_SIZE 32 | |
165 | #define RX_RING_SIZE 32 | |
166 | #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD) | |
167 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD) | |
168 | #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */ | |
169 | #define TX_TIMEOUT (HZ/10) | |
170 | #define DSCC4_HZ_MAX 33000000 | |
171 | #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */ | |
172 | #define dev_per_card 4 | |
173 | #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */ | |
174 | ||
175 | #define SOURCE_ID(flags) (((flags) >> 28) & 0x03) | |
176 | #define TO_SIZE(state) (((state) >> 16) & 0x1fff) | |
177 | ||
178 | /* | |
179 | * Given the operating range of Linux HDLC, the 2 defines below could be | |
180 | * made simpler. However they are a fine reminder for the limitations of | |
181 | * the driver: it's better to stay < TxSizeMax and < RxSizeMax. | |
182 | */ | |
183 | #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16) | |
184 | #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16) | |
185 | #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */ | |
186 | #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET) | |
187 | ||
188 | struct dscc4_pci_priv { | |
409cd63e | 189 | __le32 *iqcfg; |
1da177e4 LT |
190 | int cfg_cur; |
191 | spinlock_t lock; | |
192 | struct pci_dev *pdev; | |
193 | ||
194 | struct dscc4_dev_priv *root; | |
195 | dma_addr_t iqcfg_dma; | |
196 | u32 xtal_hz; | |
197 | }; | |
198 | ||
199 | struct dscc4_dev_priv { | |
200 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
201 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
202 | ||
203 | struct RxFD *rx_fd; | |
204 | struct TxFD *tx_fd; | |
409cd63e AV |
205 | __le32 *iqrx; |
206 | __le32 *iqtx; | |
1da177e4 LT |
207 | |
208 | /* FIXME: check all the volatile are required */ | |
209 | volatile u32 tx_current; | |
210 | u32 rx_current; | |
211 | u32 iqtx_current; | |
212 | u32 iqrx_current; | |
213 | ||
214 | volatile u32 tx_dirty; | |
215 | volatile u32 ltda; | |
216 | u32 rx_dirty; | |
217 | u32 lrda; | |
218 | ||
219 | dma_addr_t tx_fd_dma; | |
220 | dma_addr_t rx_fd_dma; | |
221 | dma_addr_t iqtx_dma; | |
222 | dma_addr_t iqrx_dma; | |
223 | ||
224 | u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */ | |
225 | ||
226 | struct timer_list timer; | |
227 | ||
228 | struct dscc4_pci_priv *pci_priv; | |
229 | spinlock_t lock; | |
230 | ||
231 | int dev_id; | |
232 | volatile u32 flags; | |
233 | u32 timer_help; | |
234 | ||
235 | unsigned short encoding; | |
236 | unsigned short parity; | |
237 | struct net_device *dev; | |
238 | sync_serial_settings settings; | |
239 | void __iomem *base_addr; | |
240 | u32 __pad __attribute__ ((aligned (4))); | |
241 | }; | |
242 | ||
243 | /* GLOBAL registers definitions */ | |
244 | #define GCMDR 0x00 | |
245 | #define GSTAR 0x04 | |
246 | #define GMODE 0x08 | |
247 | #define IQLENR0 0x0C | |
248 | #define IQLENR1 0x10 | |
249 | #define IQRX0 0x14 | |
250 | #define IQTX0 0x24 | |
251 | #define IQCFG 0x3c | |
252 | #define FIFOCR1 0x44 | |
253 | #define FIFOCR2 0x48 | |
254 | #define FIFOCR3 0x4c | |
255 | #define FIFOCR4 0x34 | |
256 | #define CH0CFG 0x50 | |
257 | #define CH0BRDA 0x54 | |
258 | #define CH0BTDA 0x58 | |
259 | #define CH0FRDA 0x98 | |
260 | #define CH0FTDA 0xb0 | |
261 | #define CH0LRDA 0xc8 | |
262 | #define CH0LTDA 0xe0 | |
263 | ||
264 | /* SCC registers definitions */ | |
265 | #define SCC_START 0x0100 | |
266 | #define SCC_OFFSET 0x80 | |
267 | #define CMDR 0x00 | |
268 | #define STAR 0x04 | |
269 | #define CCR0 0x08 | |
270 | #define CCR1 0x0c | |
271 | #define CCR2 0x10 | |
272 | #define BRR 0x2C | |
273 | #define RLCR 0x40 | |
274 | #define IMR 0x54 | |
275 | #define ISR 0x58 | |
276 | ||
277 | #define GPDIR 0x0400 | |
278 | #define GPDATA 0x0404 | |
279 | #define GPIM 0x0408 | |
280 | ||
281 | /* Bit masks */ | |
282 | #define EncodingMask 0x00700000 | |
283 | #define CrcMask 0x00000003 | |
284 | ||
285 | #define IntRxScc0 0x10000000 | |
286 | #define IntTxScc0 0x01000000 | |
287 | ||
288 | #define TxPollCmd 0x00000400 | |
289 | #define RxActivate 0x08000000 | |
290 | #define MTFi 0x04000000 | |
291 | #define Rdr 0x00400000 | |
292 | #define Rdt 0x00200000 | |
293 | #define Idr 0x00100000 | |
294 | #define Idt 0x00080000 | |
295 | #define TxSccRes 0x01000000 | |
296 | #define RxSccRes 0x00010000 | |
297 | #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */ | |
298 | #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */ | |
299 | ||
300 | #define Ccr0ClockMask 0x0000003f | |
301 | #define Ccr1LoopMask 0x00000200 | |
302 | #define IsrMask 0x000fffff | |
303 | #define BrrExpMask 0x00000f00 | |
304 | #define BrrMultMask 0x0000003f | |
305 | #define EncodingMask 0x00700000 | |
409cd63e | 306 | #define Hold cpu_to_le32(0x40000000) |
1da177e4 LT |
307 | #define SccBusy 0x10000000 |
308 | #define PowerUp 0x80000000 | |
309 | #define Vis 0x00001000 | |
310 | #define FrameOk (FrameVfr | FrameCrc) | |
311 | #define FrameVfr 0x80 | |
312 | #define FrameRdo 0x40 | |
313 | #define FrameCrc 0x20 | |
314 | #define FrameRab 0x10 | |
409cd63e AV |
315 | #define FrameAborted cpu_to_le32(0x00000200) |
316 | #define FrameEnd cpu_to_le32(0x80000000) | |
317 | #define DataComplete cpu_to_le32(0x40000000) | |
1da177e4 LT |
318 | #define LengthCheck 0x00008000 |
319 | #define SccEvt 0x02000000 | |
320 | #define NoAck 0x00000200 | |
321 | #define Action 0x00000001 | |
409cd63e | 322 | #define HiDesc cpu_to_le32(0x20000000) |
1da177e4 LT |
323 | |
324 | /* SCC events */ | |
325 | #define RxEvt 0xf0000000 | |
326 | #define TxEvt 0x0f000000 | |
327 | #define Alls 0x00040000 | |
328 | #define Xdu 0x00010000 | |
329 | #define Cts 0x00004000 | |
330 | #define Xmr 0x00002000 | |
331 | #define Xpr 0x00001000 | |
332 | #define Rdo 0x00000080 | |
333 | #define Rfs 0x00000040 | |
334 | #define Cd 0x00000004 | |
335 | #define Rfo 0x00000002 | |
336 | #define Flex 0x00000001 | |
337 | ||
338 | /* DMA core events */ | |
339 | #define Cfg 0x00200000 | |
340 | #define Hi 0x00040000 | |
341 | #define Fi 0x00020000 | |
342 | #define Err 0x00010000 | |
343 | #define Arf 0x00000002 | |
344 | #define ArAck 0x00000001 | |
345 | ||
346 | /* State flags */ | |
347 | #define Ready 0x00000000 | |
348 | #define NeedIDR 0x00000001 | |
349 | #define NeedIDT 0x00000002 | |
350 | #define RdoSet 0x00000004 | |
351 | #define FakeReset 0x00000008 | |
352 | ||
353 | /* Don't mask RDO. Ever. */ | |
354 | #ifdef DSCC4_POLLING | |
355 | #define EventsMask 0xfffeef7f | |
356 | #else | |
357 | #define EventsMask 0xfffa8f7a | |
358 | #endif | |
359 | ||
360 | /* Functions prototypes */ | |
361 | static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); | |
362 | static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); | |
363 | static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr); | |
364 | static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent); | |
365 | static int dscc4_open(struct net_device *); | |
d71a6749 SH |
366 | static netdev_tx_t dscc4_start_xmit(struct sk_buff *, |
367 | struct net_device *); | |
1da177e4 LT |
368 | static int dscc4_close(struct net_device *); |
369 | static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
370 | static int dscc4_init_ring(struct net_device *); | |
371 | static void dscc4_release_ring(struct dscc4_dev_priv *); | |
372 | static void dscc4_timer(unsigned long); | |
373 | static void dscc4_tx_timeout(struct net_device *); | |
7d12e780 | 374 | static irqreturn_t dscc4_irq(int irq, void *dev_id); |
1da177e4 LT |
375 | static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short); |
376 | static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *); | |
377 | #ifdef DSCC4_POLLING | |
378 | static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *); | |
379 | #endif | |
380 | ||
381 | static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev) | |
382 | { | |
383 | return dev_to_hdlc(dev)->priv; | |
384 | } | |
385 | ||
386 | static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p) | |
387 | { | |
388 | return p->dev; | |
389 | } | |
390 | ||
391 | static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv, | |
392 | struct net_device *dev, int offset) | |
393 | { | |
394 | u32 state; | |
395 | ||
396 | /* Cf scc_writel for concern regarding thread-safety */ | |
397 | state = dpriv->scc_regs[offset >> 2]; | |
398 | state &= ~mask; | |
399 | state |= value; | |
400 | dpriv->scc_regs[offset >> 2] = state; | |
401 | writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset); | |
402 | } | |
403 | ||
404 | static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv, | |
405 | struct net_device *dev, int offset) | |
406 | { | |
407 | /* | |
408 | * Thread-UNsafe. | |
409 | * As of 2002/02/16, there are no thread racing for access. | |
410 | */ | |
411 | dpriv->scc_regs[offset >> 2] = bits; | |
412 | writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset); | |
413 | } | |
414 | ||
415 | static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset) | |
416 | { | |
417 | return dpriv->scc_regs[offset >> 2]; | |
418 | } | |
419 | ||
420 | static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
421 | { | |
422 | /* Cf errata DS5 p.4 */ | |
423 | readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); | |
424 | return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); | |
425 | } | |
426 | ||
427 | static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv, | |
428 | struct net_device *dev) | |
429 | { | |
430 | dpriv->ltda = dpriv->tx_fd_dma + | |
431 | ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD); | |
432 | writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); | |
433 | /* Flush posted writes *NOW* */ | |
434 | readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); | |
435 | } | |
436 | ||
437 | static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv, | |
438 | struct net_device *dev) | |
439 | { | |
440 | dpriv->lrda = dpriv->rx_fd_dma + | |
441 | ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD); | |
442 | writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
443 | } | |
444 | ||
445 | static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv) | |
446 | { | |
447 | return dpriv->tx_current == dpriv->tx_dirty; | |
448 | } | |
449 | ||
450 | static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv, | |
451 | struct net_device *dev) | |
452 | { | |
453 | return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda; | |
454 | } | |
455 | ||
7665a089 AB |
456 | static int state_check(u32 state, struct dscc4_dev_priv *dpriv, |
457 | struct net_device *dev, const char *msg) | |
1da177e4 LT |
458 | { |
459 | int ret = 0; | |
460 | ||
461 | if (debug > 1) { | |
462 | if (SOURCE_ID(state) != dpriv->dev_id) { | |
463 | printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n", | |
464 | dev->name, msg, SOURCE_ID(state), state ); | |
465 | ret = -1; | |
466 | } | |
467 | if (state & 0x0df80c00) { | |
468 | printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n", | |
469 | dev->name, msg, state); | |
470 | ret = -1; | |
471 | } | |
472 | } | |
473 | return ret; | |
474 | } | |
475 | ||
7665a089 AB |
476 | static void dscc4_tx_print(struct net_device *dev, |
477 | struct dscc4_dev_priv *dpriv, | |
478 | char *msg) | |
1da177e4 LT |
479 | { |
480 | printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n", | |
481 | dev->name, dpriv->tx_current, dpriv->tx_dirty, msg); | |
482 | } | |
483 | ||
484 | static void dscc4_release_ring(struct dscc4_dev_priv *dpriv) | |
485 | { | |
486 | struct pci_dev *pdev = dpriv->pci_priv->pdev; | |
487 | struct TxFD *tx_fd = dpriv->tx_fd; | |
488 | struct RxFD *rx_fd = dpriv->rx_fd; | |
489 | struct sk_buff **skbuff; | |
490 | int i; | |
491 | ||
492 | pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma); | |
493 | pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma); | |
494 | ||
495 | skbuff = dpriv->tx_skbuff; | |
496 | for (i = 0; i < TX_RING_SIZE; i++) { | |
497 | if (*skbuff) { | |
409cd63e AV |
498 | pci_unmap_single(pdev, le32_to_cpu(tx_fd->data), |
499 | (*skbuff)->len, PCI_DMA_TODEVICE); | |
1da177e4 LT |
500 | dev_kfree_skb(*skbuff); |
501 | } | |
502 | skbuff++; | |
503 | tx_fd++; | |
504 | } | |
505 | ||
506 | skbuff = dpriv->rx_skbuff; | |
507 | for (i = 0; i < RX_RING_SIZE; i++) { | |
508 | if (*skbuff) { | |
409cd63e | 509 | pci_unmap_single(pdev, le32_to_cpu(rx_fd->data), |
1da177e4 LT |
510 | RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); |
511 | dev_kfree_skb(*skbuff); | |
512 | } | |
513 | skbuff++; | |
514 | rx_fd++; | |
515 | } | |
516 | } | |
517 | ||
7665a089 AB |
518 | static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, |
519 | struct net_device *dev) | |
1da177e4 LT |
520 | { |
521 | unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE; | |
522 | struct RxFD *rx_fd = dpriv->rx_fd + dirty; | |
523 | const int len = RX_MAX(HDLC_MAX_MRU); | |
524 | struct sk_buff *skb; | |
525 | int ret = 0; | |
526 | ||
527 | skb = dev_alloc_skb(len); | |
528 | dpriv->rx_skbuff[dirty] = skb; | |
529 | if (skb) { | |
530 | skb->protocol = hdlc_type_trans(skb, dev); | |
409cd63e AV |
531 | rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev, |
532 | skb->data, len, PCI_DMA_FROMDEVICE)); | |
1da177e4 | 533 | } else { |
409cd63e | 534 | rx_fd->data = 0; |
1da177e4 LT |
535 | ret = -1; |
536 | } | |
537 | return ret; | |
538 | } | |
539 | ||
540 | /* | |
541 | * IRQ/thread/whatever safe | |
542 | */ | |
543 | static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv, | |
544 | struct net_device *dev, char *msg) | |
545 | { | |
546 | s8 i = 0; | |
547 | ||
548 | do { | |
549 | if (!(scc_readl_star(dpriv, dev) & SccBusy)) { | |
550 | printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name, | |
551 | msg, i); | |
552 | goto done; | |
553 | } | |
3173c890 | 554 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
555 | rmb(); |
556 | } while (++i > 0); | |
09a1732b | 557 | netdev_err(dev, "%s timeout\n", msg); |
1da177e4 LT |
558 | done: |
559 | return (i >= 0) ? i : -EAGAIN; | |
560 | } | |
561 | ||
562 | static int dscc4_do_action(struct net_device *dev, char *msg) | |
563 | { | |
564 | void __iomem *ioaddr = dscc4_priv(dev)->base_addr; | |
565 | s16 i = 0; | |
566 | ||
567 | writel(Action, ioaddr + GCMDR); | |
568 | ioaddr += GSTAR; | |
569 | do { | |
570 | u32 state = readl(ioaddr); | |
571 | ||
572 | if (state & ArAck) { | |
09a1732b | 573 | netdev_dbg(dev, "%s ack\n", msg); |
1da177e4 LT |
574 | writel(ArAck, ioaddr); |
575 | goto done; | |
576 | } else if (state & Arf) { | |
09a1732b | 577 | netdev_err(dev, "%s failed\n", msg); |
1da177e4 LT |
578 | writel(Arf, ioaddr); |
579 | i = -1; | |
580 | goto done; | |
581 | } | |
582 | rmb(); | |
583 | } while (++i > 0); | |
09a1732b | 584 | netdev_err(dev, "%s timeout\n", msg); |
1da177e4 LT |
585 | done: |
586 | return i; | |
587 | } | |
588 | ||
589 | static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv) | |
590 | { | |
591 | int cur = dpriv->iqtx_current%IRQ_RING_SIZE; | |
592 | s8 i = 0; | |
593 | ||
594 | do { | |
595 | if (!(dpriv->flags & (NeedIDR | NeedIDT)) || | |
409cd63e | 596 | (dpriv->iqtx[cur] & cpu_to_le32(Xpr))) |
1da177e4 LT |
597 | break; |
598 | smp_rmb(); | |
3173c890 | 599 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
600 | } while (++i > 0); |
601 | ||
602 | return (i >= 0 ) ? i : -EAGAIN; | |
603 | } | |
604 | ||
605 | #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */ | |
606 | static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
607 | { | |
608 | unsigned long flags; | |
609 | ||
610 | spin_lock_irqsave(&dpriv->pci_priv->lock, flags); | |
611 | /* Cf errata DS5 p.6 */ | |
612 | writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
613 | scc_patchl(PowerUp, 0, dpriv, dev, CCR0); | |
614 | readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
615 | writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); | |
616 | writel(Action, dpriv->base_addr + GCMDR); | |
617 | spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags); | |
618 | } | |
619 | ||
620 | #endif | |
621 | ||
622 | #if 0 | |
623 | static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
624 | { | |
625 | u16 i = 0; | |
626 | ||
627 | /* Cf errata DS5 p.7 */ | |
628 | scc_patchl(PowerUp, 0, dpriv, dev, CCR0); | |
629 | scc_writel(0x00050000, dpriv, dev, CCR2); | |
630 | /* | |
631 | * Must be longer than the time required to fill the fifo. | |
632 | */ | |
633 | while (!dscc4_tx_quiescent(dpriv, dev) && ++i) { | |
634 | udelay(1); | |
635 | wmb(); | |
636 | } | |
637 | ||
638 | writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); | |
639 | if (dscc4_do_action(dev, "Rdt") < 0) | |
09a1732b | 640 | netdev_err(dev, "Tx reset failed\n"); |
1da177e4 LT |
641 | } |
642 | #endif | |
643 | ||
644 | /* TODO: (ab)use this function to refill a completely depleted RX ring. */ | |
645 | static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, | |
646 | struct net_device *dev) | |
647 | { | |
648 | struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE; | |
1da177e4 LT |
649 | struct pci_dev *pdev = dpriv->pci_priv->pdev; |
650 | struct sk_buff *skb; | |
651 | int pkt_len; | |
652 | ||
653 | skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE]; | |
654 | if (!skb) { | |
b39d66a8 | 655 | printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__); |
1da177e4 LT |
656 | goto refill; |
657 | } | |
409cd63e AV |
658 | pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2)); |
659 | pci_unmap_single(pdev, le32_to_cpu(rx_fd->data), | |
660 | RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); | |
1da177e4 | 661 | if ((skb->data[--pkt_len] & FrameOk) == FrameOk) { |
198191c4 KH |
662 | dev->stats.rx_packets++; |
663 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 LT |
664 | skb_put(skb, pkt_len); |
665 | if (netif_running(dev)) | |
666 | skb->protocol = hdlc_type_trans(skb, dev); | |
1da177e4 LT |
667 | netif_rx(skb); |
668 | } else { | |
669 | if (skb->data[pkt_len] & FrameRdo) | |
198191c4 | 670 | dev->stats.rx_fifo_errors++; |
5de3fcab | 671 | else if (!(skb->data[pkt_len] & FrameCrc)) |
198191c4 | 672 | dev->stats.rx_crc_errors++; |
5de3fcab | 673 | else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) != |
fab4e763 | 674 | (FrameVfr | FrameRab)) |
198191c4 | 675 | dev->stats.rx_length_errors++; |
5de3fcab | 676 | dev->stats.rx_errors++; |
1da177e4 LT |
677 | dev_kfree_skb_irq(skb); |
678 | } | |
679 | refill: | |
680 | while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) { | |
681 | if (try_get_rx_skb(dpriv, dev) < 0) | |
682 | break; | |
683 | dpriv->rx_dirty++; | |
684 | } | |
685 | dscc4_rx_update(dpriv, dev); | |
686 | rx_fd->state2 = 0x00000000; | |
409cd63e | 687 | rx_fd->end = cpu_to_le32(0xbabeface); |
1da177e4 LT |
688 | } |
689 | ||
690 | static void dscc4_free1(struct pci_dev *pdev) | |
691 | { | |
692 | struct dscc4_pci_priv *ppriv; | |
693 | struct dscc4_dev_priv *root; | |
694 | int i; | |
695 | ||
696 | ppriv = pci_get_drvdata(pdev); | |
697 | root = ppriv->root; | |
698 | ||
699 | for (i = 0; i < dev_per_card; i++) | |
700 | unregister_hdlc_device(dscc4_to_dev(root + i)); | |
701 | ||
702 | pci_set_drvdata(pdev, NULL); | |
703 | ||
704 | for (i = 0; i < dev_per_card; i++) | |
705 | free_netdev(root[i].dev); | |
706 | kfree(root); | |
707 | kfree(ppriv); | |
708 | } | |
709 | ||
1dd06ae8 | 710 | static int dscc4_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
711 | { |
712 | struct dscc4_pci_priv *priv; | |
713 | struct dscc4_dev_priv *dpriv; | |
714 | void __iomem *ioaddr; | |
715 | int i, rc; | |
716 | ||
717 | printk(KERN_DEBUG "%s", version); | |
718 | ||
719 | rc = pci_enable_device(pdev); | |
720 | if (rc < 0) | |
721 | goto out; | |
722 | ||
723 | rc = pci_request_region(pdev, 0, "registers"); | |
724 | if (rc < 0) { | |
09a1732b | 725 | pr_err("can't reserve MMIO region (regs)\n"); |
1da177e4 LT |
726 | goto err_disable_0; |
727 | } | |
728 | rc = pci_request_region(pdev, 1, "LBI interface"); | |
729 | if (rc < 0) { | |
09a1732b | 730 | pr_err("can't reserve MMIO region (lbi)\n"); |
1da177e4 LT |
731 | goto err_free_mmio_region_1; |
732 | } | |
733 | ||
275f165f | 734 | ioaddr = pci_ioremap_bar(pdev, 0); |
1da177e4 | 735 | if (!ioaddr) { |
09a1732b JP |
736 | pr_err("cannot remap MMIO region %llx @ %llx\n", |
737 | (unsigned long long)pci_resource_len(pdev, 0), | |
738 | (unsigned long long)pci_resource_start(pdev, 0)); | |
1da177e4 LT |
739 | rc = -EIO; |
740 | goto err_free_mmio_regions_2; | |
741 | } | |
7c7459d1 GKH |
742 | printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n", |
743 | (unsigned long long)pci_resource_start(pdev, 0), | |
744 | (unsigned long long)pci_resource_start(pdev, 1), pdev->irq); | |
1da177e4 LT |
745 | |
746 | /* Cf errata DS5 p.2 */ | |
747 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8); | |
748 | pci_set_master(pdev); | |
749 | ||
750 | rc = dscc4_found1(pdev, ioaddr); | |
751 | if (rc < 0) | |
752 | goto err_iounmap_3; | |
753 | ||
754 | priv = pci_get_drvdata(pdev); | |
755 | ||
1fb9df5d | 756 | rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root); |
1da177e4 | 757 | if (rc < 0) { |
09a1732b | 758 | pr_warn("IRQ %d busy\n", pdev->irq); |
1da177e4 LT |
759 | goto err_release_4; |
760 | } | |
761 | ||
762 | /* power up/little endian/dma core controlled via lrda/ltda */ | |
763 | writel(0x00000001, ioaddr + GMODE); | |
764 | /* Shared interrupt queue */ | |
765 | { | |
766 | u32 bits; | |
767 | ||
768 | bits = (IRQ_RING_SIZE >> 5) - 1; | |
769 | bits |= bits << 4; | |
770 | bits |= bits << 8; | |
771 | bits |= bits << 16; | |
772 | writel(bits, ioaddr + IQLENR0); | |
773 | } | |
774 | /* Global interrupt queue */ | |
775 | writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1); | |
623d896b JL |
776 | |
777 | rc = -ENOMEM; | |
778 | ||
409cd63e AV |
779 | priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev, |
780 | IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma); | |
1da177e4 LT |
781 | if (!priv->iqcfg) |
782 | goto err_free_irq_5; | |
783 | writel(priv->iqcfg_dma, ioaddr + IQCFG); | |
784 | ||
1da177e4 LT |
785 | /* |
786 | * SCC 0-3 private rx/tx irq structures | |
787 | * IQRX/TXi needs to be set soon. Learned it the hard way... | |
788 | */ | |
789 | for (i = 0; i < dev_per_card; i++) { | |
790 | dpriv = priv->root + i; | |
409cd63e | 791 | dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev, |
1da177e4 LT |
792 | IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma); |
793 | if (!dpriv->iqtx) | |
794 | goto err_free_iqtx_6; | |
795 | writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4); | |
796 | } | |
797 | for (i = 0; i < dev_per_card; i++) { | |
798 | dpriv = priv->root + i; | |
409cd63e | 799 | dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev, |
1da177e4 LT |
800 | IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma); |
801 | if (!dpriv->iqrx) | |
802 | goto err_free_iqrx_7; | |
803 | writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4); | |
804 | } | |
805 | ||
806 | /* Cf application hint. Beware of hard-lock condition on threshold. */ | |
807 | writel(0x42104000, ioaddr + FIFOCR1); | |
808 | //writel(0x9ce69800, ioaddr + FIFOCR2); | |
809 | writel(0xdef6d800, ioaddr + FIFOCR2); | |
810 | //writel(0x11111111, ioaddr + FIFOCR4); | |
811 | writel(0x18181818, ioaddr + FIFOCR4); | |
812 | // FIXME: should depend on the chipset revision | |
813 | writel(0x0000000e, ioaddr + FIFOCR3); | |
814 | ||
815 | writel(0xff200001, ioaddr + GCMDR); | |
816 | ||
817 | rc = 0; | |
818 | out: | |
819 | return rc; | |
820 | ||
821 | err_free_iqrx_7: | |
822 | while (--i >= 0) { | |
823 | dpriv = priv->root + i; | |
824 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
825 | dpriv->iqrx, dpriv->iqrx_dma); | |
826 | } | |
827 | i = dev_per_card; | |
828 | err_free_iqtx_6: | |
829 | while (--i >= 0) { | |
830 | dpriv = priv->root + i; | |
831 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
832 | dpriv->iqtx, dpriv->iqtx_dma); | |
833 | } | |
834 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg, | |
835 | priv->iqcfg_dma); | |
836 | err_free_irq_5: | |
837 | free_irq(pdev->irq, priv->root); | |
838 | err_release_4: | |
839 | dscc4_free1(pdev); | |
840 | err_iounmap_3: | |
841 | iounmap (ioaddr); | |
842 | err_free_mmio_regions_2: | |
843 | pci_release_region(pdev, 1); | |
844 | err_free_mmio_region_1: | |
845 | pci_release_region(pdev, 0); | |
846 | err_disable_0: | |
847 | pci_disable_device(pdev); | |
848 | goto out; | |
849 | }; | |
850 | ||
851 | /* | |
852 | * Let's hope the default values are decent enough to protect my | |
853 | * feet from the user's gun - Ueimor | |
854 | */ | |
855 | static void dscc4_init_registers(struct dscc4_dev_priv *dpriv, | |
856 | struct net_device *dev) | |
857 | { | |
858 | /* No interrupts, SCC core disabled. Let's relax */ | |
859 | scc_writel(0x00000000, dpriv, dev, CCR0); | |
860 | ||
861 | scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR); | |
862 | ||
863 | /* | |
864 | * No address recognition/crc-CCITT/cts enabled | |
865 | * Shared flags transmission disabled - cf errata DS5 p.11 | |
866 | * Carrier detect disabled - cf errata p.14 | |
867 | * FIXME: carrier detection/polarity may be handled more gracefully. | |
868 | */ | |
869 | scc_writel(0x02408000, dpriv, dev, CCR1); | |
870 | ||
871 | /* crc not forwarded - Cf errata DS5 p.11 */ | |
872 | scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); | |
873 | // crc forwarded | |
874 | //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2); | |
875 | } | |
876 | ||
877 | static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz) | |
878 | { | |
879 | int ret = 0; | |
880 | ||
881 | if ((hz < 0) || (hz > DSCC4_HZ_MAX)) | |
882 | ret = -EOPNOTSUPP; | |
883 | else | |
884 | dpriv->pci_priv->xtal_hz = hz; | |
885 | ||
886 | return ret; | |
887 | } | |
888 | ||
991990a1 KH |
889 | static const struct net_device_ops dscc4_ops = { |
890 | .ndo_open = dscc4_open, | |
891 | .ndo_stop = dscc4_close, | |
892 | .ndo_change_mtu = hdlc_change_mtu, | |
893 | .ndo_start_xmit = hdlc_start_xmit, | |
894 | .ndo_do_ioctl = dscc4_ioctl, | |
895 | .ndo_tx_timeout = dscc4_tx_timeout, | |
896 | }; | |
897 | ||
1da177e4 LT |
898 | static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr) |
899 | { | |
900 | struct dscc4_pci_priv *ppriv; | |
901 | struct dscc4_dev_priv *root; | |
902 | int i, ret = -ENOMEM; | |
903 | ||
dd00cc48 | 904 | root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL); |
e404decb | 905 | if (!root) |
1da177e4 | 906 | goto err_out; |
1da177e4 LT |
907 | |
908 | for (i = 0; i < dev_per_card; i++) { | |
909 | root[i].dev = alloc_hdlcdev(root + i); | |
910 | if (!root[i].dev) | |
911 | goto err_free_dev; | |
912 | } | |
913 | ||
dd00cc48 | 914 | ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL); |
e404decb | 915 | if (!ppriv) |
1da177e4 | 916 | goto err_free_dev; |
1da177e4 LT |
917 | |
918 | ppriv->root = root; | |
919 | spin_lock_init(&ppriv->lock); | |
920 | ||
921 | for (i = 0; i < dev_per_card; i++) { | |
922 | struct dscc4_dev_priv *dpriv = root + i; | |
923 | struct net_device *d = dscc4_to_dev(dpriv); | |
924 | hdlc_device *hdlc = dev_to_hdlc(d); | |
925 | ||
926 | d->base_addr = (unsigned long)ioaddr; | |
1da177e4 | 927 | d->irq = pdev->irq; |
991990a1 | 928 | d->netdev_ops = &dscc4_ops; |
1da177e4 | 929 | d->watchdog_timeo = TX_TIMEOUT; |
1da177e4 LT |
930 | SET_NETDEV_DEV(d, &pdev->dev); |
931 | ||
932 | dpriv->dev_id = i; | |
933 | dpriv->pci_priv = ppriv; | |
934 | dpriv->base_addr = ioaddr; | |
935 | spin_lock_init(&dpriv->lock); | |
936 | ||
937 | hdlc->xmit = dscc4_start_xmit; | |
938 | hdlc->attach = dscc4_hdlc_attach; | |
939 | ||
940 | dscc4_init_registers(dpriv, d); | |
941 | dpriv->parity = PARITY_CRC16_PR0_CCITT; | |
942 | dpriv->encoding = ENCODING_NRZ; | |
943 | ||
944 | ret = dscc4_init_ring(d); | |
945 | if (ret < 0) | |
946 | goto err_unregister; | |
947 | ||
948 | ret = register_hdlc_device(d); | |
949 | if (ret < 0) { | |
09a1732b | 950 | pr_err("unable to register\n"); |
1da177e4 LT |
951 | dscc4_release_ring(dpriv); |
952 | goto err_unregister; | |
953 | } | |
954 | } | |
955 | ||
956 | ret = dscc4_set_quartz(root, quartz); | |
957 | if (ret < 0) | |
958 | goto err_unregister; | |
959 | ||
960 | pci_set_drvdata(pdev, ppriv); | |
961 | return ret; | |
962 | ||
963 | err_unregister: | |
964 | while (i-- > 0) { | |
965 | dscc4_release_ring(root + i); | |
966 | unregister_hdlc_device(dscc4_to_dev(root + i)); | |
967 | } | |
968 | kfree(ppriv); | |
969 | i = dev_per_card; | |
970 | err_free_dev: | |
971 | while (i-- > 0) | |
972 | free_netdev(root[i].dev); | |
973 | kfree(root); | |
974 | err_out: | |
975 | return ret; | |
976 | }; | |
977 | ||
978 | /* FIXME: get rid of the unneeded code */ | |
979 | static void dscc4_timer(unsigned long data) | |
980 | { | |
981 | struct net_device *dev = (struct net_device *)data; | |
982 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
983 | // struct dscc4_pci_priv *ppriv; | |
984 | ||
985 | goto done; | |
986 | done: | |
987 | dpriv->timer.expires = jiffies + TX_TIMEOUT; | |
988 | add_timer(&dpriv->timer); | |
989 | } | |
990 | ||
991 | static void dscc4_tx_timeout(struct net_device *dev) | |
992 | { | |
993 | /* FIXME: something is missing there */ | |
994 | } | |
995 | ||
996 | static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv) | |
997 | { | |
998 | sync_serial_settings *settings = &dpriv->settings; | |
999 | ||
1000 | if (settings->loopback && (settings->clock_type != CLOCK_INT)) { | |
1001 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1002 | ||
09a1732b | 1003 | netdev_info(dev, "loopback requires clock\n"); |
1da177e4 LT |
1004 | return -1; |
1005 | } | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | #ifdef CONFIG_DSCC4_PCI_RST | |
1010 | /* | |
1011 | * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together | |
1012 | * so as to provide a safe way to reset the asic while not the whole machine | |
1013 | * rebooting. | |
1014 | * | |
1015 | * This code doesn't need to be efficient. Keep It Simple | |
1016 | */ | |
1017 | static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr) | |
1018 | { | |
1019 | int i; | |
1020 | ||
14cc3e2b | 1021 | mutex_lock(&dscc4_mutex); |
1da177e4 LT |
1022 | for (i = 0; i < 16; i++) |
1023 | pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i); | |
1024 | ||
1025 | /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */ | |
1026 | writel(0x001c0000, ioaddr + GMODE); | |
1027 | /* Configure GPIO port as output */ | |
1028 | writel(0x0000ffff, ioaddr + GPDIR); | |
1029 | /* Disable interruption */ | |
1030 | writel(0x0000ffff, ioaddr + GPIM); | |
1031 | ||
1032 | writel(0x0000ffff, ioaddr + GPDATA); | |
1033 | writel(0x00000000, ioaddr + GPDATA); | |
1034 | ||
1035 | /* Flush posted writes */ | |
1036 | readl(ioaddr + GSTAR); | |
1037 | ||
3173c890 | 1038 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
1039 | |
1040 | for (i = 0; i < 16; i++) | |
1041 | pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]); | |
14cc3e2b | 1042 | mutex_unlock(&dscc4_mutex); |
1da177e4 LT |
1043 | } |
1044 | #else | |
1045 | #define dscc4_pci_reset(pdev,ioaddr) do {} while (0) | |
1046 | #endif /* CONFIG_DSCC4_PCI_RST */ | |
1047 | ||
1048 | static int dscc4_open(struct net_device *dev) | |
1049 | { | |
1050 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1051 | struct dscc4_pci_priv *ppriv; | |
1052 | int ret = -EAGAIN; | |
1053 | ||
991990a1 | 1054 | if ((dscc4_loopback_check(dpriv) < 0)) |
1da177e4 LT |
1055 | goto err; |
1056 | ||
1057 | if ((ret = hdlc_open(dev))) | |
1058 | goto err; | |
1059 | ||
1060 | ppriv = dpriv->pci_priv; | |
1061 | ||
1062 | /* | |
1063 | * Due to various bugs, there is no way to reliably reset a | |
25985edc | 1064 | * specific port (manufacturer's dependent special PCI #RST wiring |
1da177e4 LT |
1065 | * apart: it affects all ports). Thus the device goes in the best |
1066 | * silent mode possible at dscc4_close() time and simply claims to | |
1067 | * be up if it's opened again. It still isn't possible to change | |
1068 | * the HDLC configuration without rebooting but at least the ports | |
1069 | * can be up/down ifconfig'ed without killing the host. | |
1070 | */ | |
1071 | if (dpriv->flags & FakeReset) { | |
1072 | dpriv->flags &= ~FakeReset; | |
1073 | scc_patchl(0, PowerUp, dpriv, dev, CCR0); | |
1074 | scc_patchl(0, 0x00050000, dpriv, dev, CCR2); | |
1075 | scc_writel(EventsMask, dpriv, dev, IMR); | |
09a1732b | 1076 | netdev_info(dev, "up again\n"); |
1da177e4 LT |
1077 | goto done; |
1078 | } | |
1079 | ||
1080 | /* IDT+IDR during XPR */ | |
1081 | dpriv->flags = NeedIDR | NeedIDT; | |
1082 | ||
1083 | scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0); | |
1084 | ||
1085 | /* | |
1086 | * The following is a bit paranoid... | |
1087 | * | |
1088 | * NB: the datasheet "...CEC will stay active if the SCC is in | |
1089 | * power-down mode or..." and CCR2.RAC = 1 are two different | |
1090 | * situations. | |
1091 | */ | |
1092 | if (scc_readl_star(dpriv, dev) & SccBusy) { | |
09a1732b | 1093 | netdev_err(dev, "busy - try later\n"); |
1da177e4 LT |
1094 | ret = -EAGAIN; |
1095 | goto err_out; | |
1096 | } else | |
09a1732b | 1097 | netdev_info(dev, "available - good\n"); |
1da177e4 LT |
1098 | |
1099 | scc_writel(EventsMask, dpriv, dev, IMR); | |
1100 | ||
1101 | /* Posted write is flushed in the wait_ack loop */ | |
1102 | scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR); | |
1103 | ||
1104 | if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0) | |
1105 | goto err_disable_scc_events; | |
1106 | ||
1107 | /* | |
1108 | * I would expect XPR near CE completion (before ? after ?). | |
1109 | * At worst, this code won't see a late XPR and people | |
1110 | * will have to re-issue an ifconfig (this is harmless). | |
1111 | * WARNING, a really missing XPR usually means a hardware | |
1112 | * reset is needed. Suggestions anyone ? | |
1113 | */ | |
1114 | if ((ret = dscc4_xpr_ack(dpriv)) < 0) { | |
09a1732b | 1115 | pr_err("XPR timeout\n"); |
1da177e4 LT |
1116 | goto err_disable_scc_events; |
1117 | } | |
1118 | ||
1119 | if (debug > 2) | |
1120 | dscc4_tx_print(dev, dpriv, "Open"); | |
1121 | ||
1122 | done: | |
1123 | netif_start_queue(dev); | |
1124 | ||
1125 | init_timer(&dpriv->timer); | |
1126 | dpriv->timer.expires = jiffies + 10*HZ; | |
1127 | dpriv->timer.data = (unsigned long)dev; | |
d8bda9f1 | 1128 | dpriv->timer.function = dscc4_timer; |
1da177e4 LT |
1129 | add_timer(&dpriv->timer); |
1130 | netif_carrier_on(dev); | |
1131 | ||
1132 | return 0; | |
1133 | ||
1134 | err_disable_scc_events: | |
1135 | scc_writel(0xffffffff, dpriv, dev, IMR); | |
1136 | scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0); | |
1137 | err_out: | |
1138 | hdlc_close(dev); | |
1139 | err: | |
1140 | return ret; | |
1141 | } | |
1142 | ||
1143 | #ifdef DSCC4_POLLING | |
1144 | static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
1145 | { | |
1146 | /* FIXME: it's gonna be easy (TM), for sure */ | |
1147 | } | |
1148 | #endif /* DSCC4_POLLING */ | |
1149 | ||
d71a6749 SH |
1150 | static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb, |
1151 | struct net_device *dev) | |
1da177e4 LT |
1152 | { |
1153 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1154 | struct dscc4_pci_priv *ppriv = dpriv->pci_priv; | |
1155 | struct TxFD *tx_fd; | |
1156 | int next; | |
1157 | ||
1158 | next = dpriv->tx_current%TX_RING_SIZE; | |
1159 | dpriv->tx_skbuff[next] = skb; | |
1160 | tx_fd = dpriv->tx_fd + next; | |
1161 | tx_fd->state = FrameEnd | TO_STATE_TX(skb->len); | |
409cd63e AV |
1162 | tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len, |
1163 | PCI_DMA_TODEVICE)); | |
1da177e4 LT |
1164 | tx_fd->complete = 0x00000000; |
1165 | tx_fd->jiffies = jiffies; | |
1166 | mb(); | |
1167 | ||
1168 | #ifdef DSCC4_POLLING | |
1169 | spin_lock(&dpriv->lock); | |
1170 | while (dscc4_tx_poll(dpriv, dev)); | |
1171 | spin_unlock(&dpriv->lock); | |
1172 | #endif | |
1173 | ||
1da177e4 LT |
1174 | if (debug > 2) |
1175 | dscc4_tx_print(dev, dpriv, "Xmit"); | |
1176 | /* To be cleaned(unsigned int)/optimized. Later, ok ? */ | |
1177 | if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)) | |
1178 | netif_stop_queue(dev); | |
1179 | ||
1180 | if (dscc4_tx_quiescent(dpriv, dev)) | |
1181 | dscc4_do_tx(dpriv, dev); | |
1182 | ||
ec634fe3 | 1183 | return NETDEV_TX_OK; |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | static int dscc4_close(struct net_device *dev) | |
1187 | { | |
1188 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1189 | ||
1190 | del_timer_sync(&dpriv->timer); | |
1191 | netif_stop_queue(dev); | |
1192 | ||
1193 | scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0); | |
1194 | scc_patchl(0x00050000, 0, dpriv, dev, CCR2); | |
1195 | scc_writel(0xffffffff, dpriv, dev, IMR); | |
1196 | ||
1197 | dpriv->flags |= FakeReset; | |
1198 | ||
1199 | hdlc_close(dev); | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static inline int dscc4_check_clock_ability(int port) | |
1205 | { | |
1206 | int ret = 0; | |
1207 | ||
1208 | #ifdef CONFIG_DSCC4_PCISYNC | |
1209 | if (port >= 2) | |
1210 | ret = -1; | |
1211 | #endif | |
1212 | return ret; | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * DS1 p.137: "There are a total of 13 different clocking modes..." | |
1217 | * ^^ | |
1218 | * Design choices: | |
1219 | * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a). | |
1220 | * Clock mode 3b _should_ work but the testing seems to make this point | |
1221 | * dubious (DIY testing requires setting CCR0 at 0x00000033). | |
1222 | * This is supposed to provide least surprise "DTE like" behavior. | |
1223 | * - if line rate is specified, clocks are assumed to be locally generated. | |
1224 | * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing | |
1225 | * between these it automagically done according on the required frequency | |
1226 | * scaling. Of course some rounding may take place. | |
1227 | * - no high speed mode (40Mb/s). May be trivial to do but I don't have an | |
1228 | * appropriate external clocking device for testing. | |
25985edc | 1229 | * - no time-slot/clock mode 5: shameless laziness. |
1da177e4 | 1230 | * |
25985edc | 1231 | * The clock signals wiring can be (is ?) manufacturer dependent. Good luck. |
1da177e4 LT |
1232 | * |
1233 | * BIG FAT WARNING: if the device isn't provided enough clocking signal, it | |
1234 | * won't pass the init sequence. For example, straight back-to-back DTE without | |
1235 | * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is | |
1236 | * called. | |
1237 | * | |
1238 | * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153 | |
1239 | * DS0 for example) | |
1240 | * | |
1241 | * Clock mode related bits of CCR0: | |
1242 | * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only) | |
1243 | * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b | |
1244 | * | | +-------- High Speed: say 0 | |
1245 | * | | | +-+-+-- Clock Mode: 0..7 | |
1246 | * | | | | | | | |
1247 | * -+-+-+-+-+-+-+-+ | |
1248 | * x|x|5|4|3|2|1|0| lower bits | |
1249 | * | |
1250 | * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b) | |
1251 | * +-+-+-+------------------ M (0..15) | |
1252 | * | | | | +-+-+-+-+-+-- N (0..63) | |
1253 | * 0 0 0 0 | | | | 0 0 | | | | | | | |
1254 | * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
1255 | * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits | |
1256 | * | |
1257 | */ | |
1258 | static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state) | |
1259 | { | |
1260 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1261 | int ret = -1; | |
1262 | u32 brr; | |
1263 | ||
1264 | *state &= ~Ccr0ClockMask; | |
1265 | if (*bps) { /* Clock generated - required for DCE */ | |
1266 | u32 n = 0, m = 0, divider; | |
1267 | int xtal; | |
1268 | ||
1269 | xtal = dpriv->pci_priv->xtal_hz; | |
1270 | if (!xtal) | |
1271 | goto done; | |
1272 | if (dscc4_check_clock_ability(dpriv->dev_id) < 0) | |
1273 | goto done; | |
1274 | divider = xtal / *bps; | |
1275 | if (divider > BRR_DIVIDER_MAX) { | |
1276 | divider >>= 4; | |
1277 | *state |= 0x00000036; /* Clock mode 6b (BRG/16) */ | |
1278 | } else | |
1279 | *state |= 0x00000037; /* Clock mode 7b (BRG) */ | |
1280 | if (divider >> 22) { | |
1281 | n = 63; | |
1282 | m = 15; | |
1283 | } else if (divider) { | |
1284 | /* Extraction of the 6 highest weighted bits */ | |
1285 | m = 0; | |
1286 | while (0xffffffc0 & divider) { | |
1287 | m++; | |
1288 | divider >>= 1; | |
1289 | } | |
1290 | n = divider; | |
1291 | } | |
1292 | brr = (m << 8) | n; | |
1293 | divider = n << m; | |
1294 | if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */ | |
1295 | divider <<= 4; | |
1296 | *bps = xtal / divider; | |
1297 | } else { | |
1298 | /* | |
1299 | * External clock - DTE | |
1300 | * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00). | |
1301 | * Nothing more to be done | |
1302 | */ | |
1303 | brr = 0; | |
1304 | } | |
1305 | scc_writel(brr, dpriv, dev, BRR); | |
1306 | ret = 0; | |
1307 | done: | |
1308 | return ret; | |
1309 | } | |
1310 | ||
1311 | static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1312 | { | |
1313 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1314 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1315 | const size_t size = sizeof(dpriv->settings); | |
1316 | int ret = 0; | |
1317 | ||
1318 | if (dev->flags & IFF_UP) | |
1319 | return -EBUSY; | |
1320 | ||
1321 | if (cmd != SIOCWANDEV) | |
1322 | return -EOPNOTSUPP; | |
1323 | ||
1324 | switch(ifr->ifr_settings.type) { | |
1325 | case IF_GET_IFACE: | |
1326 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1327 | if (ifr->ifr_settings.size < size) { | |
1328 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1329 | return -ENOBUFS; | |
1330 | } | |
1331 | if (copy_to_user(line, &dpriv->settings, size)) | |
1332 | return -EFAULT; | |
1333 | break; | |
1334 | ||
1335 | case IF_IFACE_SYNC_SERIAL: | |
1336 | if (!capable(CAP_NET_ADMIN)) | |
1337 | return -EPERM; | |
1338 | ||
1339 | if (dpriv->flags & FakeReset) { | |
09a1732b | 1340 | netdev_info(dev, "please reset the device before this command\n"); |
1da177e4 LT |
1341 | return -EPERM; |
1342 | } | |
1343 | if (copy_from_user(&dpriv->settings, line, size)) | |
1344 | return -EFAULT; | |
1345 | ret = dscc4_set_iface(dpriv, dev); | |
1346 | break; | |
1347 | ||
1348 | default: | |
1349 | ret = hdlc_ioctl(dev, ifr, cmd); | |
1350 | break; | |
1351 | } | |
1352 | ||
1353 | return ret; | |
1354 | } | |
1355 | ||
215faf9c | 1356 | static int dscc4_match(const struct thingie *p, int value) |
1da177e4 LT |
1357 | { |
1358 | int i; | |
1359 | ||
1360 | for (i = 0; p[i].define != -1; i++) { | |
1361 | if (value == p[i].define) | |
1362 | break; | |
1363 | } | |
1364 | if (p[i].define == -1) | |
1365 | return -1; | |
1366 | else | |
1367 | return i; | |
1368 | } | |
1369 | ||
1370 | static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv, | |
1371 | struct net_device *dev) | |
1372 | { | |
1373 | sync_serial_settings *settings = &dpriv->settings; | |
1374 | int ret = -EOPNOTSUPP; | |
1375 | u32 bps, state; | |
1376 | ||
1377 | bps = settings->clock_rate; | |
1378 | state = scc_readl(dpriv, CCR0); | |
1379 | if (dscc4_set_clock(dev, &bps, &state) < 0) | |
1380 | goto done; | |
1381 | if (bps) { /* DCE */ | |
1382 | printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name); | |
1383 | if (settings->clock_rate != bps) { | |
1384 | printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n", | |
1385 | dev->name, settings->clock_rate, bps); | |
1386 | settings->clock_rate = bps; | |
1387 | } | |
1388 | } else { /* DTE */ | |
1389 | state |= PowerUp | Vis; | |
1390 | printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name); | |
1391 | } | |
1392 | scc_writel(state, dpriv, dev, CCR0); | |
1393 | ret = 0; | |
1394 | done: | |
1395 | return ret; | |
1396 | } | |
1397 | ||
1398 | static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv, | |
1399 | struct net_device *dev) | |
1400 | { | |
215faf9c | 1401 | static const struct thingie encoding[] = { |
1da177e4 LT |
1402 | { ENCODING_NRZ, 0x00000000 }, |
1403 | { ENCODING_NRZI, 0x00200000 }, | |
1404 | { ENCODING_FM_MARK, 0x00400000 }, | |
1405 | { ENCODING_FM_SPACE, 0x00500000 }, | |
1406 | { ENCODING_MANCHESTER, 0x00600000 }, | |
1407 | { -1, 0} | |
1408 | }; | |
1409 | int i, ret = 0; | |
1410 | ||
1411 | i = dscc4_match(encoding, dpriv->encoding); | |
1412 | if (i >= 0) | |
1413 | scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0); | |
1414 | else | |
1415 | ret = -EOPNOTSUPP; | |
1416 | return ret; | |
1417 | } | |
1418 | ||
1419 | static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv, | |
1420 | struct net_device *dev) | |
1421 | { | |
1422 | sync_serial_settings *settings = &dpriv->settings; | |
1423 | u32 state; | |
1424 | ||
1425 | state = scc_readl(dpriv, CCR1); | |
1426 | if (settings->loopback) { | |
1427 | printk(KERN_DEBUG "%s: loopback\n", dev->name); | |
1428 | state |= 0x00000100; | |
1429 | } else { | |
1430 | printk(KERN_DEBUG "%s: normal\n", dev->name); | |
1431 | state &= ~0x00000100; | |
1432 | } | |
1433 | scc_writel(state, dpriv, dev, CCR1); | |
1434 | return 0; | |
1435 | } | |
1436 | ||
1437 | static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv, | |
1438 | struct net_device *dev) | |
1439 | { | |
215faf9c | 1440 | static const struct thingie crc[] = { |
1da177e4 LT |
1441 | { PARITY_CRC16_PR0_CCITT, 0x00000010 }, |
1442 | { PARITY_CRC16_PR1_CCITT, 0x00000000 }, | |
1443 | { PARITY_CRC32_PR0_CCITT, 0x00000011 }, | |
1444 | { PARITY_CRC32_PR1_CCITT, 0x00000001 } | |
1445 | }; | |
1446 | int i, ret = 0; | |
1447 | ||
1448 | i = dscc4_match(crc, dpriv->parity); | |
1449 | if (i >= 0) | |
1450 | scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1); | |
1451 | else | |
1452 | ret = -EOPNOTSUPP; | |
1453 | return ret; | |
1454 | } | |
1455 | ||
1456 | static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
1457 | { | |
1458 | struct { | |
1459 | int (*action)(struct dscc4_dev_priv *, struct net_device *); | |
1460 | } *p, do_setting[] = { | |
1461 | { dscc4_encoding_setting }, | |
1462 | { dscc4_clock_setting }, | |
1463 | { dscc4_loopback_setting }, | |
1464 | { dscc4_crc_setting }, | |
1465 | { NULL } | |
1466 | }; | |
1467 | int ret = 0; | |
1468 | ||
1469 | for (p = do_setting; p->action; p++) { | |
1470 | if ((ret = p->action(dpriv, dev)) < 0) | |
1471 | break; | |
1472 | } | |
1473 | return ret; | |
1474 | } | |
1475 | ||
7d12e780 | 1476 | static irqreturn_t dscc4_irq(int irq, void *token) |
1da177e4 LT |
1477 | { |
1478 | struct dscc4_dev_priv *root = token; | |
1479 | struct dscc4_pci_priv *priv; | |
1480 | struct net_device *dev; | |
1481 | void __iomem *ioaddr; | |
1482 | u32 state; | |
1483 | unsigned long flags; | |
1484 | int i, handled = 1; | |
1485 | ||
1486 | priv = root->pci_priv; | |
1487 | dev = dscc4_to_dev(root); | |
1488 | ||
1489 | spin_lock_irqsave(&priv->lock, flags); | |
1490 | ||
1491 | ioaddr = root->base_addr; | |
1492 | ||
1493 | state = readl(ioaddr + GSTAR); | |
1494 | if (!state) { | |
1495 | handled = 0; | |
1496 | goto out; | |
1497 | } | |
1498 | if (debug > 3) | |
1499 | printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state); | |
1500 | writel(state, ioaddr + GSTAR); | |
1501 | ||
1502 | if (state & Arf) { | |
09a1732b | 1503 | netdev_err(dev, "failure (Arf). Harass the maintainer\n"); |
1da177e4 LT |
1504 | goto out; |
1505 | } | |
1506 | state &= ~ArAck; | |
1507 | if (state & Cfg) { | |
1508 | if (debug > 0) | |
1509 | printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME); | |
409cd63e | 1510 | if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf)) |
09a1732b | 1511 | netdev_err(dev, "CFG failed\n"); |
1da177e4 LT |
1512 | if (!(state &= ~Cfg)) |
1513 | goto out; | |
1514 | } | |
1515 | if (state & RxEvt) { | |
1516 | i = dev_per_card - 1; | |
1517 | do { | |
1518 | dscc4_rx_irq(priv, root + i); | |
1519 | } while (--i >= 0); | |
1520 | state &= ~RxEvt; | |
1521 | } | |
1522 | if (state & TxEvt) { | |
1523 | i = dev_per_card - 1; | |
1524 | do { | |
1525 | dscc4_tx_irq(priv, root + i); | |
1526 | } while (--i >= 0); | |
1527 | state &= ~TxEvt; | |
1528 | } | |
1529 | out: | |
1530 | spin_unlock_irqrestore(&priv->lock, flags); | |
1531 | return IRQ_RETVAL(handled); | |
1532 | } | |
1533 | ||
1534 | static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv, | |
1535 | struct dscc4_dev_priv *dpriv) | |
1536 | { | |
1537 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1538 | u32 state; | |
1539 | int cur, loop = 0; | |
1540 | ||
1541 | try: | |
1542 | cur = dpriv->iqtx_current%IRQ_RING_SIZE; | |
409cd63e | 1543 | state = le32_to_cpu(dpriv->iqtx[cur]); |
1da177e4 LT |
1544 | if (!state) { |
1545 | if (debug > 4) | |
1546 | printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name, | |
1547 | state); | |
1548 | if ((debug > 1) && (loop > 1)) | |
1549 | printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop); | |
1550 | if (loop && netif_queue_stopped(dev)) | |
1551 | if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE) | |
1552 | netif_wake_queue(dev); | |
1553 | ||
1554 | if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) && | |
1555 | !dscc4_tx_done(dpriv)) | |
1556 | dscc4_do_tx(dpriv, dev); | |
1557 | return; | |
1558 | } | |
1559 | loop++; | |
1560 | dpriv->iqtx[cur] = 0; | |
1561 | dpriv->iqtx_current++; | |
1562 | ||
1563 | if (state_check(state, dpriv, dev, "Tx") < 0) | |
1564 | return; | |
1565 | ||
1566 | if (state & SccEvt) { | |
1567 | if (state & Alls) { | |
1da177e4 LT |
1568 | struct sk_buff *skb; |
1569 | struct TxFD *tx_fd; | |
1570 | ||
1571 | if (debug > 2) | |
1572 | dscc4_tx_print(dev, dpriv, "Alls"); | |
1573 | /* | |
1574 | * DataComplete can't be trusted for Tx completion. | |
1575 | * Cf errata DS5 p.8 | |
1576 | */ | |
1577 | cur = dpriv->tx_dirty%TX_RING_SIZE; | |
1578 | tx_fd = dpriv->tx_fd + cur; | |
1579 | skb = dpriv->tx_skbuff[cur]; | |
1580 | if (skb) { | |
409cd63e | 1581 | pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data), |
1da177e4 LT |
1582 | skb->len, PCI_DMA_TODEVICE); |
1583 | if (tx_fd->state & FrameEnd) { | |
198191c4 KH |
1584 | dev->stats.tx_packets++; |
1585 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
1586 | } |
1587 | dev_kfree_skb_irq(skb); | |
1588 | dpriv->tx_skbuff[cur] = NULL; | |
1589 | ++dpriv->tx_dirty; | |
1590 | } else { | |
1591 | if (debug > 1) | |
09a1732b JP |
1592 | netdev_err(dev, "Tx: NULL skb %d\n", |
1593 | cur); | |
1da177e4 LT |
1594 | } |
1595 | /* | |
1596 | * If the driver ends sending crap on the wire, it | |
1597 | * will be way easier to diagnose than the (not so) | |
1598 | * random freeze induced by null sized tx frames. | |
1599 | */ | |
1600 | tx_fd->data = tx_fd->next; | |
1601 | tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE); | |
1602 | tx_fd->complete = 0x00000000; | |
1603 | tx_fd->jiffies = 0; | |
1604 | ||
1605 | if (!(state &= ~Alls)) | |
1606 | goto try; | |
1607 | } | |
1608 | /* | |
1609 | * Transmit Data Underrun | |
1610 | */ | |
1611 | if (state & Xdu) { | |
09a1732b | 1612 | netdev_err(dev, "Tx Data Underrun. Ask maintainer\n"); |
1da177e4 LT |
1613 | dpriv->flags = NeedIDT; |
1614 | /* Tx reset */ | |
1615 | writel(MTFi | Rdt, | |
1616 | dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG); | |
1617 | writel(Action, dpriv->base_addr + GCMDR); | |
1618 | return; | |
1619 | } | |
1620 | if (state & Cts) { | |
09a1732b | 1621 | netdev_info(dev, "CTS transition\n"); |
1da177e4 LT |
1622 | if (!(state &= ~Cts)) /* DEBUG */ |
1623 | goto try; | |
1624 | } | |
1625 | if (state & Xmr) { | |
1626 | /* Frame needs to be sent again - FIXME */ | |
09a1732b | 1627 | netdev_err(dev, "Tx ReTx. Ask maintainer\n"); |
1da177e4 LT |
1628 | if (!(state &= ~Xmr)) /* DEBUG */ |
1629 | goto try; | |
1630 | } | |
1631 | if (state & Xpr) { | |
1632 | void __iomem *scc_addr; | |
1633 | unsigned long ring; | |
1634 | int i; | |
1635 | ||
1636 | /* | |
1637 | * - the busy condition happens (sometimes); | |
1638 | * - it doesn't seem to make the handler unreliable. | |
1639 | */ | |
1640 | for (i = 1; i; i <<= 1) { | |
1641 | if (!(scc_readl_star(dpriv, dev) & SccBusy)) | |
1642 | break; | |
1643 | } | |
1644 | if (!i) | |
09a1732b | 1645 | netdev_info(dev, "busy in irq\n"); |
1da177e4 LT |
1646 | |
1647 | scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; | |
1648 | /* Keep this order: IDT before IDR */ | |
1649 | if (dpriv->flags & NeedIDT) { | |
1650 | if (debug > 2) | |
1651 | dscc4_tx_print(dev, dpriv, "Xpr"); | |
1652 | ring = dpriv->tx_fd_dma + | |
1653 | (dpriv->tx_dirty%TX_RING_SIZE)* | |
1654 | sizeof(struct TxFD); | |
1655 | writel(ring, scc_addr + CH0BTDA); | |
1656 | dscc4_do_tx(dpriv, dev); | |
1657 | writel(MTFi | Idt, scc_addr + CH0CFG); | |
1658 | if (dscc4_do_action(dev, "IDT") < 0) | |
1659 | goto err_xpr; | |
1660 | dpriv->flags &= ~NeedIDT; | |
1661 | } | |
1662 | if (dpriv->flags & NeedIDR) { | |
1663 | ring = dpriv->rx_fd_dma + | |
1664 | (dpriv->rx_current%RX_RING_SIZE)* | |
1665 | sizeof(struct RxFD); | |
1666 | writel(ring, scc_addr + CH0BRDA); | |
1667 | dscc4_rx_update(dpriv, dev); | |
1668 | writel(MTFi | Idr, scc_addr + CH0CFG); | |
1669 | if (dscc4_do_action(dev, "IDR") < 0) | |
1670 | goto err_xpr; | |
1671 | dpriv->flags &= ~NeedIDR; | |
1672 | smp_wmb(); | |
1673 | /* Activate receiver and misc */ | |
1674 | scc_writel(0x08050008, dpriv, dev, CCR2); | |
1675 | } | |
1676 | err_xpr: | |
1677 | if (!(state &= ~Xpr)) | |
1678 | goto try; | |
1679 | } | |
1680 | if (state & Cd) { | |
1681 | if (debug > 0) | |
09a1732b | 1682 | netdev_info(dev, "CD transition\n"); |
1da177e4 LT |
1683 | if (!(state &= ~Cd)) /* DEBUG */ |
1684 | goto try; | |
1685 | } | |
1686 | } else { /* ! SccEvt */ | |
1687 | if (state & Hi) { | |
1688 | #ifdef DSCC4_POLLING | |
1689 | while (!dscc4_tx_poll(dpriv, dev)); | |
1690 | #endif | |
09a1732b | 1691 | netdev_info(dev, "Tx Hi\n"); |
1da177e4 LT |
1692 | state &= ~Hi; |
1693 | } | |
1694 | if (state & Err) { | |
09a1732b | 1695 | netdev_info(dev, "Tx ERR\n"); |
198191c4 | 1696 | dev->stats.tx_errors++; |
1da177e4 LT |
1697 | state &= ~Err; |
1698 | } | |
1699 | } | |
1700 | goto try; | |
1701 | } | |
1702 | ||
1703 | static void dscc4_rx_irq(struct dscc4_pci_priv *priv, | |
1704 | struct dscc4_dev_priv *dpriv) | |
1705 | { | |
1706 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1707 | u32 state; | |
1708 | int cur; | |
1709 | ||
1710 | try: | |
1711 | cur = dpriv->iqrx_current%IRQ_RING_SIZE; | |
409cd63e | 1712 | state = le32_to_cpu(dpriv->iqrx[cur]); |
1da177e4 LT |
1713 | if (!state) |
1714 | return; | |
1715 | dpriv->iqrx[cur] = 0; | |
1716 | dpriv->iqrx_current++; | |
1717 | ||
1718 | if (state_check(state, dpriv, dev, "Rx") < 0) | |
1719 | return; | |
1720 | ||
1721 | if (!(state & SccEvt)){ | |
1722 | struct RxFD *rx_fd; | |
1723 | ||
1724 | if (debug > 4) | |
1725 | printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name, | |
1726 | state); | |
1727 | state &= 0x00ffffff; | |
1728 | if (state & Err) { /* Hold or reset */ | |
1729 | printk(KERN_DEBUG "%s: Rx ERR\n", dev->name); | |
1730 | cur = dpriv->rx_current%RX_RING_SIZE; | |
1731 | rx_fd = dpriv->rx_fd + cur; | |
1732 | /* | |
1733 | * Presume we're not facing a DMAC receiver reset. | |
1734 | * As We use the rx size-filtering feature of the | |
1735 | * DSCC4, the beginning of a new frame is waiting in | |
1736 | * the rx fifo. I bet a Receive Data Overflow will | |
1737 | * happen most of time but let's try and avoid it. | |
1738 | * Btw (as for RDO) if one experiences ERR whereas | |
1739 | * the system looks rather idle, there may be a | |
1740 | * problem with latency. In this case, increasing | |
1741 | * RX_RING_SIZE may help. | |
1742 | */ | |
1743 | //while (dpriv->rx_needs_refill) { | |
1744 | while (!(rx_fd->state1 & Hold)) { | |
1745 | rx_fd++; | |
1746 | cur++; | |
1747 | if (!(cur = cur%RX_RING_SIZE)) | |
1748 | rx_fd = dpriv->rx_fd; | |
1749 | } | |
1750 | //dpriv->rx_needs_refill--; | |
1751 | try_get_rx_skb(dpriv, dev); | |
1752 | if (!rx_fd->data) | |
1753 | goto try; | |
1754 | rx_fd->state1 &= ~Hold; | |
1755 | rx_fd->state2 = 0x00000000; | |
409cd63e | 1756 | rx_fd->end = cpu_to_le32(0xbabeface); |
1da177e4 LT |
1757 | //} |
1758 | goto try; | |
1759 | } | |
1760 | if (state & Fi) { | |
1761 | dscc4_rx_skb(dpriv, dev); | |
1762 | goto try; | |
1763 | } | |
1764 | if (state & Hi ) { /* HI bit */ | |
09a1732b | 1765 | netdev_info(dev, "Rx Hi\n"); |
1da177e4 LT |
1766 | state &= ~Hi; |
1767 | goto try; | |
1768 | } | |
1769 | } else { /* SccEvt */ | |
1770 | if (debug > 1) { | |
1771 | //FIXME: verifier la presence de tous les evenements | |
1772 | static struct { | |
1773 | u32 mask; | |
1774 | const char *irq_name; | |
1775 | } evts[] = { | |
1776 | { 0x00008000, "TIN"}, | |
1777 | { 0x00000020, "RSC"}, | |
1778 | { 0x00000010, "PCE"}, | |
1779 | { 0x00000008, "PLLA"}, | |
1780 | { 0, NULL} | |
1781 | }, *evt; | |
1782 | ||
1783 | for (evt = evts; evt->irq_name; evt++) { | |
1784 | if (state & evt->mask) { | |
1785 | printk(KERN_DEBUG "%s: %s\n", | |
1786 | dev->name, evt->irq_name); | |
1787 | if (!(state &= ~evt->mask)) | |
1788 | goto try; | |
1789 | } | |
1790 | } | |
1791 | } else { | |
1792 | if (!(state &= ~0x0000c03c)) | |
1793 | goto try; | |
1794 | } | |
1795 | if (state & Cts) { | |
09a1732b | 1796 | netdev_info(dev, "CTS transition\n"); |
1da177e4 LT |
1797 | if (!(state &= ~Cts)) /* DEBUG */ |
1798 | goto try; | |
1799 | } | |
1800 | /* | |
1801 | * Receive Data Overflow (FIXME: fscked) | |
1802 | */ | |
1803 | if (state & Rdo) { | |
1804 | struct RxFD *rx_fd; | |
1805 | void __iomem *scc_addr; | |
1806 | int cur; | |
1807 | ||
1808 | //if (debug) | |
1809 | // dscc4_rx_dump(dpriv); | |
1810 | scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; | |
1811 | ||
1812 | scc_patchl(RxActivate, 0, dpriv, dev, CCR2); | |
1813 | /* | |
1814 | * This has no effect. Why ? | |
1815 | * ORed with TxSccRes, one sees the CFG ack (for | |
1816 | * the TX part only). | |
1817 | */ | |
1818 | scc_writel(RxSccRes, dpriv, dev, CMDR); | |
1819 | dpriv->flags |= RdoSet; | |
1820 | ||
1821 | /* | |
1822 | * Let's try and save something in the received data. | |
1823 | * rx_current must be incremented at least once to | |
1824 | * avoid HOLD in the BRDA-to-be-pointed desc. | |
1825 | */ | |
1826 | do { | |
1827 | cur = dpriv->rx_current++%RX_RING_SIZE; | |
1828 | rx_fd = dpriv->rx_fd + cur; | |
1829 | if (!(rx_fd->state2 & DataComplete)) | |
1830 | break; | |
1831 | if (rx_fd->state2 & FrameAborted) { | |
198191c4 | 1832 | dev->stats.rx_over_errors++; |
1da177e4 LT |
1833 | rx_fd->state1 |= Hold; |
1834 | rx_fd->state2 = 0x00000000; | |
409cd63e | 1835 | rx_fd->end = cpu_to_le32(0xbabeface); |
1da177e4 LT |
1836 | } else |
1837 | dscc4_rx_skb(dpriv, dev); | |
1838 | } while (1); | |
1839 | ||
1840 | if (debug > 0) { | |
1841 | if (dpriv->flags & RdoSet) | |
1842 | printk(KERN_DEBUG | |
1843 | "%s: no RDO in Rx data\n", DRV_NAME); | |
1844 | } | |
1845 | #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY | |
1846 | /* | |
1847 | * FIXME: must the reset be this violent ? | |
1848 | */ | |
1849 | #warning "FIXME: CH0BRDA" | |
1850 | writel(dpriv->rx_fd_dma + | |
1851 | (dpriv->rx_current%RX_RING_SIZE)* | |
1852 | sizeof(struct RxFD), scc_addr + CH0BRDA); | |
1853 | writel(MTFi|Rdr|Idr, scc_addr + CH0CFG); | |
1854 | if (dscc4_do_action(dev, "RDR") < 0) { | |
09a1732b | 1855 | netdev_err(dev, "RDO recovery failed(RDR)\n"); |
1da177e4 LT |
1856 | goto rdo_end; |
1857 | } | |
1858 | writel(MTFi|Idr, scc_addr + CH0CFG); | |
1859 | if (dscc4_do_action(dev, "IDR") < 0) { | |
09a1732b | 1860 | netdev_err(dev, "RDO recovery failed(IDR)\n"); |
1da177e4 LT |
1861 | goto rdo_end; |
1862 | } | |
1863 | rdo_end: | |
1864 | #endif | |
1865 | scc_patchl(0, RxActivate, dpriv, dev, CCR2); | |
1866 | goto try; | |
1867 | } | |
1868 | if (state & Cd) { | |
09a1732b | 1869 | netdev_info(dev, "CD transition\n"); |
1da177e4 LT |
1870 | if (!(state &= ~Cd)) /* DEBUG */ |
1871 | goto try; | |
1872 | } | |
1873 | if (state & Flex) { | |
1874 | printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME); | |
1875 | if (!(state &= ~Flex)) | |
1876 | goto try; | |
1877 | } | |
1878 | } | |
1879 | } | |
1880 | ||
1881 | /* | |
1882 | * I had expected the following to work for the first descriptor | |
1883 | * (tx_fd->state = 0xc0000000) | |
1884 | * - Hold=1 (don't try and branch to the next descripto); | |
1885 | * - No=0 (I want an empty data section, i.e. size=0); | |
1886 | * - Fe=1 (required by No=0 or we got an Err irq and must reset). | |
1887 | * It failed and locked solid. Thus the introduction of a dummy skb. | |
1888 | * Problem is acknowledged in errata sheet DS5. Joy :o/ | |
1889 | */ | |
7665a089 | 1890 | static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv) |
1da177e4 LT |
1891 | { |
1892 | struct sk_buff *skb; | |
1893 | ||
1894 | skb = dev_alloc_skb(DUMMY_SKB_SIZE); | |
1895 | if (skb) { | |
1896 | int last = dpriv->tx_dirty%TX_RING_SIZE; | |
1897 | struct TxFD *tx_fd = dpriv->tx_fd + last; | |
1898 | ||
1899 | skb->len = DUMMY_SKB_SIZE; | |
27d7ff46 ACM |
1900 | skb_copy_to_linear_data(skb, version, |
1901 | strlen(version) % DUMMY_SKB_SIZE); | |
1da177e4 | 1902 | tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE); |
409cd63e AV |
1903 | tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev, |
1904 | skb->data, DUMMY_SKB_SIZE, | |
1905 | PCI_DMA_TODEVICE)); | |
1da177e4 LT |
1906 | dpriv->tx_skbuff[last] = skb; |
1907 | } | |
1908 | return skb; | |
1909 | } | |
1910 | ||
1911 | static int dscc4_init_ring(struct net_device *dev) | |
1912 | { | |
1913 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1914 | struct pci_dev *pdev = dpriv->pci_priv->pdev; | |
1915 | struct TxFD *tx_fd; | |
1916 | struct RxFD *rx_fd; | |
1917 | void *ring; | |
1918 | int i; | |
1919 | ||
1920 | ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma); | |
1921 | if (!ring) | |
1922 | goto err_out; | |
1923 | dpriv->rx_fd = rx_fd = (struct RxFD *) ring; | |
1924 | ||
1925 | ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma); | |
1926 | if (!ring) | |
1927 | goto err_free_dma_rx; | |
1928 | dpriv->tx_fd = tx_fd = (struct TxFD *) ring; | |
1929 | ||
1930 | memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE); | |
1931 | dpriv->tx_dirty = 0xffffffff; | |
1932 | i = dpriv->tx_current = 0; | |
1933 | do { | |
1934 | tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE); | |
1935 | tx_fd->complete = 0x00000000; | |
1936 | /* FIXME: NULL should be ok - to be tried */ | |
409cd63e AV |
1937 | tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma); |
1938 | (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma + | |
1da177e4 LT |
1939 | (++i%TX_RING_SIZE)*sizeof(*tx_fd)); |
1940 | } while (i < TX_RING_SIZE); | |
1941 | ||
3e710bfa | 1942 | if (!dscc4_init_dummy_skb(dpriv)) |
1da177e4 LT |
1943 | goto err_free_dma_tx; |
1944 | ||
1945 | memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE); | |
1946 | i = dpriv->rx_dirty = dpriv->rx_current = 0; | |
1947 | do { | |
1948 | /* size set by the host. Multiple of 4 bytes please */ | |
1949 | rx_fd->state1 = HiDesc; | |
1950 | rx_fd->state2 = 0x00000000; | |
409cd63e | 1951 | rx_fd->end = cpu_to_le32(0xbabeface); |
1da177e4 LT |
1952 | rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU); |
1953 | // FIXME: return value verifiee mais traitement suspect | |
1954 | if (try_get_rx_skb(dpriv, dev) >= 0) | |
1955 | dpriv->rx_dirty++; | |
409cd63e | 1956 | (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma + |
1da177e4 LT |
1957 | (++i%RX_RING_SIZE)*sizeof(*rx_fd)); |
1958 | } while (i < RX_RING_SIZE); | |
1959 | ||
1960 | return 0; | |
1961 | ||
1962 | err_free_dma_tx: | |
1963 | pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma); | |
1964 | err_free_dma_rx: | |
1965 | pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma); | |
1966 | err_out: | |
1967 | return -ENOMEM; | |
1968 | } | |
1969 | ||
6ad888c6 | 1970 | static void dscc4_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1971 | { |
1972 | struct dscc4_pci_priv *ppriv; | |
1973 | struct dscc4_dev_priv *root; | |
1974 | void __iomem *ioaddr; | |
1975 | int i; | |
1976 | ||
1977 | ppriv = pci_get_drvdata(pdev); | |
1978 | root = ppriv->root; | |
1979 | ||
1980 | ioaddr = root->base_addr; | |
1981 | ||
1982 | dscc4_pci_reset(pdev, ioaddr); | |
1983 | ||
1984 | free_irq(pdev->irq, root); | |
1985 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg, | |
1986 | ppriv->iqcfg_dma); | |
1987 | for (i = 0; i < dev_per_card; i++) { | |
1988 | struct dscc4_dev_priv *dpriv = root + i; | |
1989 | ||
1990 | dscc4_release_ring(dpriv); | |
1991 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
1992 | dpriv->iqrx, dpriv->iqrx_dma); | |
1993 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
1994 | dpriv->iqtx, dpriv->iqtx_dma); | |
1995 | } | |
1996 | ||
1997 | dscc4_free1(pdev); | |
1998 | ||
1999 | iounmap(ioaddr); | |
2000 | ||
2001 | pci_release_region(pdev, 1); | |
2002 | pci_release_region(pdev, 0); | |
2003 | ||
2004 | pci_disable_device(pdev); | |
2005 | } | |
2006 | ||
2007 | static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding, | |
2008 | unsigned short parity) | |
2009 | { | |
2010 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
2011 | ||
2012 | if (encoding != ENCODING_NRZ && | |
2013 | encoding != ENCODING_NRZI && | |
2014 | encoding != ENCODING_FM_MARK && | |
2015 | encoding != ENCODING_FM_SPACE && | |
2016 | encoding != ENCODING_MANCHESTER) | |
2017 | return -EINVAL; | |
2018 | ||
2019 | if (parity != PARITY_NONE && | |
2020 | parity != PARITY_CRC16_PR0_CCITT && | |
2021 | parity != PARITY_CRC16_PR1_CCITT && | |
2022 | parity != PARITY_CRC32_PR0_CCITT && | |
2023 | parity != PARITY_CRC32_PR1_CCITT) | |
2024 | return -EINVAL; | |
2025 | ||
2026 | dpriv->encoding = encoding; | |
2027 | dpriv->parity = parity; | |
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | #ifndef MODULE | |
2032 | static int __init dscc4_setup(char *str) | |
2033 | { | |
2034 | int *args[] = { &debug, &quartz, NULL }, **p = args; | |
2035 | ||
2036 | while (*p && (get_option(&str, *p) == 2)) | |
2037 | p++; | |
2038 | return 1; | |
2039 | } | |
2040 | ||
2041 | __setup("dscc4.setup=", dscc4_setup); | |
2042 | #endif | |
2043 | ||
a3aa1884 | 2044 | static DEFINE_PCI_DEVICE_TABLE(dscc4_pci_tbl) = { |
1da177e4 LT |
2045 | { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4, |
2046 | PCI_ANY_ID, PCI_ANY_ID, }, | |
2047 | { 0,} | |
2048 | }; | |
2049 | MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl); | |
2050 | ||
2051 | static struct pci_driver dscc4_driver = { | |
2052 | .name = DRV_NAME, | |
2053 | .id_table = dscc4_pci_tbl, | |
2054 | .probe = dscc4_init_one, | |
6ad888c6 | 2055 | .remove = dscc4_remove_one, |
1da177e4 LT |
2056 | }; |
2057 | ||
eff98db0 | 2058 | module_pci_driver(dscc4_driver); |