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1 | /****************************************************************************** |
2 | * This software may be used and distributed according to the terms of | |
3 | * the GNU General Public License (GPL), incorporated herein by reference. | |
4 | * Drivers based on or derived from this code fall under the GPL and must | |
5 | * retain the authorship, copyright and license notice. This file is not | |
6 | * a complete program and may only be used when the entire operating | |
7 | * system is licensed under the GPL. | |
8 | * See the file COPYING in this distribution for more information. | |
9 | * | |
10 | * vxge-reg.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O Virtualized | |
11 | * Server Adapter. | |
12 | * Copyright(c) 2002-2009 Neterion Inc. | |
13 | ******************************************************************************/ | |
14 | #ifndef VXGE_REG_H | |
15 | #define VXGE_REG_H | |
16 | ||
17 | /* | |
18 | * vxge_mBIT(loc) - set bit at offset | |
19 | */ | |
20 | #define vxge_mBIT(loc) (0x8000000000000000ULL >> (loc)) | |
21 | ||
22 | /* | |
23 | * vxge_vBIT(val, loc, sz) - set bits at offset | |
24 | */ | |
25 | #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) | |
26 | #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) | |
27 | ||
28 | /* | |
29 | * vxge_bVALn(bits, loc, n) - Get the value of n bits at location | |
30 | */ | |
31 | #define vxge_bVALn(bits, loc, n) \ | |
32 | ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1)) | |
33 | ||
34 | #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ | |
35 | vxge_bVALn(bits, 0, 16) | |
36 | #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ | |
37 | vxge_bVALn(bits, 48, 8) | |
38 | #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ | |
39 | vxge_bVALn(bits, 56, 8) | |
40 | ||
41 | #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ | |
42 | vxge_bVALn(bits, 3, 5) | |
43 | #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \ | |
44 | vxge_bVALn(bits, 5, 3) | |
45 | #define VXGE_HW_PF_SW_RESET_COMMAND 0xA5 | |
46 | ||
47 | #define VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES 17 | |
48 | #define VXGE_HW_TITAN_SRPCIM_REG_SPACES 17 | |
49 | #define VXGE_HW_TITAN_VPMGMT_REG_SPACES 17 | |
50 | #define VXGE_HW_TITAN_VPATH_REG_SPACES 17 | |
51 | ||
52 | #define VXGE_HW_ASIC_MODE_RESERVED 0 | |
53 | #define VXGE_HW_ASIC_MODE_NO_IOV 1 | |
54 | #define VXGE_HW_ASIC_MODE_SR_IOV 2 | |
55 | #define VXGE_HW_ASIC_MODE_MR_IOV 3 | |
56 | ||
57 | #define VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN vxge_mBIT(3) | |
58 | #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE vxge_mBIT(19) | |
59 | #define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH vxge_mBIT(23) | |
60 | #define VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS vxge_mBIT(31) | |
61 | ||
62 | #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1) | |
63 | ||
64 | #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \ | |
65 | vxge_bVALn(bits, 0, 32) | |
66 | ||
67 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \ | |
68 | vxge_bVALn(bits, 50, 14) | |
69 | ||
70 | #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \ | |
71 | vxge_bVALn(bits, 0, 17) | |
72 | ||
73 | #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \ | |
74 | vxge_bVALn(bits, 3, 5) | |
75 | ||
76 | #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \ | |
77 | vxge_bVALn(bits, 17, 15) | |
78 | ||
79 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE 0 | |
80 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY 1 | |
81 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE 2 | |
82 | ||
83 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY 0 | |
84 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE 1 | |
85 | ||
86 | #define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val) \ | |
87 | (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7)) | |
88 | #define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val) \ | |
89 | vxge_bVALn(val, 61, 3) | |
90 | #define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val) \ | |
91 | (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7)) | |
92 | #define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val) \ | |
93 | vxge_bVALn(val, 61, 3) | |
94 | ||
95 | #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits | |
96 | #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits | |
97 | ||
98 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \ | |
99 | vxge_bVALn(bits, 1, 15) | |
100 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \ | |
101 | vxge_bVALn(bits, 17, 15) | |
102 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \ | |
103 | vxge_bVALn(bits, 33, 15) | |
104 | ||
105 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vxge_vBIT(val, 42, 5) | |
106 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vxge_vBIT(val, 47, 2) | |
107 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) \ | |
108 | vxge_vBIT(val, 49, 15) | |
109 | ||
110 | #define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER 0 | |
111 | #define VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER 1 | |
112 | #define VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER 2 | |
113 | ||
114 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE_A 0 | |
115 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE_B 2 | |
116 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE_C 1 | |
117 | ||
118 | #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ 0 | |
119 | #define VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE 1 | |
120 | ||
121 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA 0 | |
122 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID 1 | |
123 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 | |
124 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN 3 | |
125 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN 4 | |
126 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 | |
127 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 | |
128 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 | |
129 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 | |
130 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 | |
131 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 | |
132 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS 11 | |
133 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 | |
134 | #define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION 13 | |
135 | ||
136 | #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ | |
137 | vxge_bVALn(bits, 0, 48) | |
138 | #define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) | |
139 | ||
140 | #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ | |
141 | vxge_bVALn(bits, 0, 48) | |
142 | #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vxge_vBIT(val, 0, 48) | |
143 | #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE \ | |
144 | vxge_mBIT(54) | |
145 | #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \ | |
146 | vxge_bVALn(bits, 55, 5) | |
147 | #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) \ | |
148 | vxge_vBIT(val, 55, 5) | |
149 | #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \ | |
150 | vxge_bVALn(bits, 62, 2) | |
151 | #define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vxge_vBIT(val, 62, 2) | |
152 | ||
153 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY 0 | |
154 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY 1 | |
155 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY 2 | |
156 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY 3 | |
157 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY 0 | |
158 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY 1 | |
159 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY 3 | |
160 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL 4 | |
161 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR 172 | |
162 | ||
163 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA 0 | |
164 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID 1 | |
165 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE 2 | |
166 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN 3 | |
167 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG 5 | |
168 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT 6 | |
169 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG 7 | |
170 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK 8 | |
171 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY 9 | |
172 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS 10 | |
173 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS 11 | |
174 | #define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12 | |
175 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO 13 | |
176 | ||
177 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ | |
178 | vxge_bVALn(bits, 0, 48) | |
179 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vxge_vBIT(val, 0, 48) | |
180 | ||
181 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12) | |
182 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vxge_vBIT(val, 0, 12) | |
183 | ||
184 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11) | |
185 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val) vxge_vBIT(val, 0, 16) | |
186 | ||
187 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \ | |
188 | vxge_bVALn(bits, 3, 1) | |
189 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL vxge_mBIT(3) | |
190 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \ | |
191 | vxge_bVALn(bits, 7, 1) | |
192 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL vxge_mBIT(7) | |
193 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \ | |
194 | vxge_bVALn(bits, 8, 16) | |
195 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val) vxge_vBIT(val, 8, 16) | |
196 | ||
197 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \ | |
198 | vxge_bVALn(bits, 3, 1) | |
199 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN vxge_mBIT(3) | |
200 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \ | |
201 | vxge_bVALn(bits, 4, 4) | |
202 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) \ | |
203 | vxge_vBIT(val, 4, 4) | |
204 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \ | |
205 | vxge_bVALn(bits, 10, 2) | |
206 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) \ | |
207 | vxge_vBIT(val, 10, 2) | |
208 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS 0 | |
209 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS 1 | |
210 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C 2 | |
211 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \ | |
212 | vxge_bVALn(bits, 15, 1) | |
213 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN vxge_mBIT(15) | |
214 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \ | |
215 | vxge_bVALn(bits, 19, 1) | |
216 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN vxge_mBIT(19) | |
217 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \ | |
218 | vxge_bVALn(bits, 23, 1) | |
219 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN vxge_mBIT(23) | |
220 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \ | |
221 | vxge_bVALn(bits, 27, 1) | |
222 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN vxge_mBIT(27) | |
223 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \ | |
224 | vxge_bVALn(bits, 31, 1) | |
225 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN vxge_mBIT(31) | |
226 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \ | |
227 | vxge_bVALn(bits, 35, 1) | |
228 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN vxge_mBIT(35) | |
229 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \ | |
230 | vxge_bVALn(bits, 39, 1) | |
231 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE vxge_mBIT(39) | |
232 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \ | |
233 | vxge_bVALn(bits, 43, 1) | |
234 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN vxge_mBIT(43) | |
235 | ||
236 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \ | |
237 | vxge_bVALn(bits, 3, 1) | |
238 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN vxge_mBIT(3) | |
239 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \ | |
240 | vxge_bVALn(bits, 9, 7) | |
241 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val) \ | |
242 | vxge_vBIT(val, 9, 7) | |
243 | ||
244 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \ | |
245 | vxge_bVALn(bits, 0, 8) | |
246 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val) \ | |
247 | vxge_vBIT(val, 0, 8) | |
248 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \ | |
249 | vxge_bVALn(bits, 8, 1) | |
250 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) | |
251 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \ | |
252 | vxge_bVALn(bits, 9, 7) | |
253 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val) \ | |
254 | vxge_vBIT(val, 9, 7) | |
255 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \ | |
256 | vxge_bVALn(bits, 16, 8) | |
257 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val) \ | |
258 | vxge_vBIT(val, 16, 8) | |
259 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \ | |
260 | vxge_bVALn(bits, 24, 1) | |
261 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) | |
262 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \ | |
263 | vxge_bVALn(bits, 25, 7) | |
264 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val) \ | |
265 | vxge_vBIT(val, 25, 7) | |
266 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \ | |
267 | vxge_bVALn(bits, 0, 8) | |
268 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val) \ | |
269 | vxge_vBIT(val, 0, 8) | |
270 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \ | |
271 | vxge_bVALn(bits, 8, 1) | |
272 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN vxge_mBIT(8) | |
273 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \ | |
274 | vxge_bVALn(bits, 9, 7) | |
275 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val) \ | |
276 | vxge_vBIT(val, 9, 7) | |
277 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \ | |
278 | vxge_bVALn(bits, 16, 8) | |
279 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val) \ | |
280 | vxge_vBIT(val, 16, 8) | |
281 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \ | |
282 | vxge_bVALn(bits, 24, 1) | |
283 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN vxge_mBIT(24) | |
284 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \ | |
285 | vxge_bVALn(bits, 25, 7) | |
286 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val) \ | |
287 | vxge_vBIT(val, 25, 7) | |
288 | ||
289 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \ | |
290 | vxge_bVALn(bits, 0, 32) | |
291 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val) \ | |
292 | vxge_vBIT(val, 0, 32) | |
293 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \ | |
294 | vxge_bVALn(bits, 32, 32) | |
295 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val) \ | |
296 | vxge_vBIT(val, 32, 32) | |
297 | ||
298 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \ | |
299 | vxge_bVALn(bits, 0, 16) | |
300 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val) \ | |
301 | vxge_vBIT(val, 0, 16) | |
302 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \ | |
303 | vxge_bVALn(bits, 16, 16) | |
304 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val) \ | |
305 | vxge_vBIT(val, 16, 16) | |
306 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \ | |
307 | vxge_bVALn(bits, 32, 4) | |
308 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val) \ | |
309 | vxge_vBIT(val, 32, 4) | |
310 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \ | |
311 | vxge_bVALn(bits, 36, 4) | |
312 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val) \ | |
313 | vxge_vBIT(val, 36, 4) | |
314 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \ | |
315 | vxge_bVALn(bits, 40, 2) | |
316 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val) \ | |
317 | vxge_vBIT(val, 40, 2) | |
318 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \ | |
319 | vxge_bVALn(bits, 42, 2) | |
320 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val) \ | |
321 | vxge_vBIT(val, 42, 2) | |
322 | ||
323 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \ | |
324 | vxge_bVALn(bits, 0, 64) | |
325 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY vxge_vBIT(val, 0, 64) | |
326 | ||
327 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \ | |
328 | vxge_bVALn(bits, 3, 1) | |
329 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN vxge_mBIT(3) | |
330 | ||
331 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \ | |
332 | vxge_bVALn(bits, 3, 1) | |
333 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN vxge_mBIT(3) | |
334 | ||
335 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ | |
336 | vxge_bVALn(bits, 0, 48) | |
337 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val) \ | |
338 | vxge_vBIT(val, 0, 48) | |
339 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val) \ | |
340 | vxge_vBIT(val, 62, 2) | |
341 | ||
342 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \ | |
343 | vxge_bVALn(bits, 0, 8) | |
344 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val) \ | |
345 | vxge_vBIT(val, 0, 8) | |
346 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \ | |
347 | vxge_bVALn(bits, 8, 1) | |
348 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN vxge_mBIT(8) | |
349 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \ | |
350 | vxge_bVALn(bits, 9, 7) | |
351 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val) \ | |
352 | vxge_vBIT(val, 9, 7) | |
353 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \ | |
354 | vxge_bVALn(bits, 16, 8) | |
355 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val) \ | |
356 | vxge_vBIT(val, 16, 8) | |
357 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \ | |
358 | vxge_bVALn(bits, 24, 1) | |
359 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN vxge_mBIT(24) | |
360 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \ | |
361 | vxge_bVALn(bits, 25, 7) | |
362 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val) \ | |
363 | vxge_vBIT(val, 25, 7) | |
364 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \ | |
365 | vxge_bVALn(bits, 32, 8) | |
366 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val) \ | |
367 | vxge_vBIT(val, 32, 8) | |
368 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \ | |
369 | vxge_bVALn(bits, 40, 1) | |
370 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN vxge_mBIT(40) | |
371 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \ | |
372 | vxge_bVALn(bits, 41, 7) | |
373 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val) \ | |
374 | vxge_vBIT(val, 41, 7) | |
375 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \ | |
376 | vxge_bVALn(bits, 48, 8) | |
377 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val) \ | |
378 | vxge_vBIT(val, 48, 8) | |
379 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \ | |
380 | vxge_bVALn(bits, 56, 1) | |
381 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN vxge_mBIT(56) | |
382 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \ | |
383 | vxge_bVALn(bits, 57, 7) | |
384 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val) \ | |
385 | vxge_vBIT(val, 57, 7) | |
386 | ||
387 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER 0 | |
388 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER 1 | |
389 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION 2 | |
390 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE 3 | |
391 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0 4 | |
392 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1 5 | |
393 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2 6 | |
394 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3 7 | |
395 | ||
396 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON 1 | |
397 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF 0 | |
398 | ||
399 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \ | |
400 | vxge_bVALn(bits, 0, 8) | |
401 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val) vxge_vBIT(val, 0, 8) | |
402 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \ | |
403 | vxge_bVALn(bits, 8, 8) | |
404 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val) vxge_vBIT(val, 8, 8) | |
405 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \ | |
406 | vxge_bVALn(bits, 16, 16) | |
407 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val) \ | |
408 | vxge_vBIT(val, 16, 16) | |
409 | ||
410 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \ | |
411 | vxge_bVALn(bits, 32, 8) | |
412 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR vxge_vBIT(val, 32, 8) | |
413 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \ | |
414 | vxge_bVALn(bits, 40, 8) | |
415 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR vxge_vBIT(val, 40, 8) | |
416 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \ | |
417 | vxge_bVALn(bits, 48, 16) | |
418 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD vxge_vBIT(val, 48, 16) | |
419 | ||
420 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \ | |
421 | vxge_bVALn(bits, 0, 8) | |
422 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val) vxge_vBIT(val, 0, 8) | |
423 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \ | |
424 | vxge_bVALn(bits, 8, 8) | |
425 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val) vxge_vBIT(val, 8, 8) | |
426 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \ | |
427 | vxge_bVALn(bits, 16, 16) | |
428 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val) \ | |
429 | vxge_vBIT(val, 16, 16) | |
430 | ||
431 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \ | |
432 | vxge_bVALn(bits, 32, 8) | |
433 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR vxge_vBIT(val, 32, 8) | |
434 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \ | |
435 | vxge_bVALn(bits, 40, 8) | |
436 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR vxge_vBIT(val, 40, 8) | |
437 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ | |
438 | vxge_bVALn(bits, 48, 16) | |
439 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16) | |
440 | ||
441 | #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ | |
442 | vxge_bVALn(bits, 0, 18) | |
443 | ||
444 | #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \ | |
445 | vxge_bVALn(bits, 48, 16) | |
446 | #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \ | |
447 | vxge_bVALn(bits, 32, 32) | |
448 | #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16) | |
449 | #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \ | |
450 | vxge_bVALn(bits, 0, 32) | |
451 | #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \ | |
452 | vxge_bVALn(bits, 0, 32) | |
453 | #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \ | |
454 | vxge_bVALn(bits, 0, 32) | |
455 | #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits) | |
456 | #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits) | |
457 | #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \ | |
458 | vxge_bVALn(bits, 32, 32) | |
459 | #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \ | |
460 | vxge_bVALn(bits, 32, 32) | |
461 | #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \ | |
462 | vxge_bVALn(bits, 0, 32) | |
463 | #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \ | |
464 | vxge_bVALn(bits, 32, 32) | |
465 | #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \ | |
466 | vxge_bVALn(bits, 0, 32) | |
467 | #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \ | |
468 | vxge_bVALn(bits, 32, 32) | |
469 | #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \ | |
470 | vxge_bVALn(bits, 0, 32) | |
471 | #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \ | |
472 | vxge_bVALn(bits, 32, 32) | |
473 | #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\ | |
474 | ) vxge_bVALn(bits, 48, 16) | |
475 | #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16) | |
476 | #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \ | |
477 | vxge_bVALn(bits, 16, 16) | |
478 | #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \ | |
479 | vxge_bVALn(bits, 32, 16) | |
480 | #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16) | |
481 | #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \ | |
482 | vxge_bVALn(bits, 16, 16) | |
483 | #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \ | |
484 | vxge_bVALn(bits, 32, 16) | |
485 | ||
486 | #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \ | |
487 | vxge_bVALn(bits, 0, 32) | |
488 | #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \ | |
489 | vxge_bVALn(bits, 32, 32) | |
490 | #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\ | |
491 | ) vxge_bVALn(bits, 32, 32) | |
492 | #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\ | |
493 | ) vxge_bVALn(bits, 32, 32) | |
494 | #define \ | |
495 | VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ | |
496 | vxge_bVALn(bits, 32, 32) | |
497 | #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \ | |
498 | vxge_bVALn(bits, 0, 32) | |
499 | #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \ | |
500 | vxge_bVALn(bits, 32, 32) | |
501 | #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \ | |
502 | vxge_bVALn(bits, 0, 32) | |
503 | #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \ | |
504 | vxge_bVALn(bits, 32, 32) | |
505 | #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \ | |
506 | vxge_bVALn(bits, 0, 32) | |
507 | #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \ | |
508 | vxge_bVALn(bits, 32, 32) | |
509 | #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \ | |
510 | vxge_bVALn(bits, 32, 32) | |
511 | #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \ | |
512 | vxge_bVALn(bits, 32, 32) | |
513 | ||
514 | #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32) | |
515 | #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32) | |
516 | #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32) | |
517 | #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32) | |
518 | #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32) | |
519 | #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16) | |
520 | #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16) | |
521 | #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16) | |
522 | #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16) | |
523 | #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL(bits, 16, 16) | |
524 | #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16) | |
525 | ||
526 | #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \ | |
527 | vxge_bVALn(bits, 32, 32) | |
528 | ||
529 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \ | |
530 | vxge_bVALn(bits, 0, 8) | |
531 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \ | |
532 | vxge_bVALn(bits, 8, 8) | |
533 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \ | |
534 | vxge_bVALn(bits, 16, 8) | |
535 | ||
536 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \ | |
537 | vxge_bVALn(bits, 0, 8) | |
538 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \ | |
539 | vxge_bVALn(bits, 8, 8) | |
540 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \ | |
541 | vxge_bVALn(bits, 16, 8) | |
542 | ||
543 | #define VXGE_HW_CONFIG_PRIV_H | |
544 | ||
545 | #define VXGE_HW_SWAPPER_INITIAL_VALUE 0x0123456789abcdefULL | |
546 | #define VXGE_HW_SWAPPER_BYTE_SWAPPED 0xefcdab8967452301ULL | |
547 | #define VXGE_HW_SWAPPER_BIT_FLIPPED 0x80c4a2e691d5b3f7ULL | |
548 | #define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED 0xf7b3d591e6a2c480ULL | |
549 | ||
550 | #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL | |
551 | #define VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE 0x0000000000000000ULL | |
552 | ||
553 | #define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL | |
554 | #define VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE 0x0000000000000000ULL | |
555 | ||
556 | #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE 0xFFFFFFFFFFFFFFFFULL | |
557 | #define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE 0x0000000000000000ULL | |
558 | ||
559 | #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE 0xFFFFFFFFFFFFFFFFULL | |
560 | #define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE 0x0000000000000000ULL | |
561 | ||
562 | /* | |
563 | * The registers are memory mapped and are native big-endian byte order. The | |
564 | * little-endian hosts are handled by enabling hardware byte-swapping for | |
565 | * register and dma operations. | |
566 | */ | |
567 | struct vxge_hw_legacy_reg { | |
568 | ||
569 | u8 unused00010[0x00010]; | |
570 | ||
571 | /*0x00010*/ u64 toc_swapper_fb; | |
572 | #define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
573 | /*0x00018*/ u64 pifm_rd_swap_en; | |
574 | #define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vxge_vBIT(val, 0, 64) | |
575 | /*0x00020*/ u64 pifm_rd_flip_en; | |
576 | #define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vxge_vBIT(val, 0, 64) | |
577 | /*0x00028*/ u64 pifm_wr_swap_en; | |
578 | #define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vxge_vBIT(val, 0, 64) | |
579 | /*0x00030*/ u64 pifm_wr_flip_en; | |
580 | #define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vxge_vBIT(val, 0, 64) | |
581 | /*0x00038*/ u64 toc_first_pointer; | |
582 | #define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
583 | /*0x00040*/ u64 host_access_en; | |
584 | #define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vxge_vBIT(val, 0, 64) | |
585 | ||
586 | } __packed; | |
587 | ||
588 | struct vxge_hw_toc_reg { | |
589 | ||
590 | u8 unused00050[0x00050]; | |
591 | ||
592 | /*0x00050*/ u64 toc_common_pointer; | |
593 | #define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
594 | /*0x00058*/ u64 toc_memrepair_pointer; | |
595 | #define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
596 | /*0x00060*/ u64 toc_pcicfgmgmt_pointer[17]; | |
597 | #define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
598 | u8 unused001e0[0x001e0-0x000e8]; | |
599 | ||
600 | /*0x001e0*/ u64 toc_mrpcim_pointer; | |
601 | #define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
602 | /*0x001e8*/ u64 toc_srpcim_pointer[17]; | |
603 | #define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
604 | u8 unused00278[0x00278-0x00270]; | |
605 | ||
606 | /*0x00278*/ u64 toc_vpmgmt_pointer[17]; | |
607 | #define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
608 | u8 unused00390[0x00390-0x00300]; | |
609 | ||
610 | /*0x00390*/ u64 toc_vpath_pointer[17]; | |
611 | #define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val) vxge_vBIT(val, 0, 64) | |
612 | u8 unused004a0[0x004a0-0x00418]; | |
613 | ||
614 | /*0x004a0*/ u64 toc_kdfc; | |
615 | #define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) | |
616 | #define VXGE_HW_TOC_KDFC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) | |
617 | /*0x004a8*/ u64 toc_usdc; | |
618 | #define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val) vxge_vBIT(val, 0, 61) | |
619 | #define VXGE_HW_TOC_USDC_INITIAL_BIR(val) vxge_vBIT(val, 61, 3) | |
620 | /*0x004b0*/ u64 toc_kdfc_vpath_stride; | |
621 | #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val) \ | |
622 | vxge_vBIT(val, 0, 64) | |
623 | /*0x004b8*/ u64 toc_kdfc_fifo_stride; | |
624 | #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val) \ | |
625 | vxge_vBIT(val, 0, 64) | |
626 | ||
627 | } __packed; | |
628 | ||
629 | struct vxge_hw_common_reg { | |
630 | ||
631 | u8 unused00a00[0x00a00]; | |
632 | ||
633 | /*0x00a00*/ u64 prc_status1; | |
634 | #define VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT(n) vxge_mBIT(n) | |
635 | /*0x00a08*/ u64 rxdcm_reset_in_progress; | |
636 | #define VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) | |
637 | /*0x00a10*/ u64 replicq_flush_in_progress; | |
638 | #define VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) | |
639 | /*0x00a18*/ u64 rxpe_cmds_reset_in_progress; | |
640 | #define VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) | |
641 | /*0x00a20*/ u64 mxp_cmds_reset_in_progress; | |
642 | #define VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) | |
643 | /*0x00a28*/ u64 noffload_reset_in_progress; | |
644 | #define VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) vxge_mBIT(n) | |
645 | /*0x00a30*/ u64 rd_req_in_progress; | |
646 | #define VXGE_HW_RD_REQ_IN_PROGRESS_VP(n) vxge_mBIT(n) | |
647 | /*0x00a38*/ u64 rd_req_outstanding; | |
648 | #define VXGE_HW_RD_REQ_OUTSTANDING_VP(n) vxge_mBIT(n) | |
649 | /*0x00a40*/ u64 kdfc_reset_in_progress; | |
650 | #define VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP(n) vxge_mBIT(n) | |
651 | u8 unused00b00[0x00b00-0x00a48]; | |
652 | ||
653 | /*0x00b00*/ u64 one_cfg_vp; | |
654 | #define VXGE_HW_ONE_CFG_VP_RDY(n) vxge_mBIT(n) | |
655 | /*0x00b08*/ u64 one_common; | |
656 | #define VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n) vxge_mBIT(n) | |
657 | u8 unused00b80[0x00b80-0x00b10]; | |
658 | ||
659 | /*0x00b80*/ u64 tim_int_en; | |
660 | #define VXGE_HW_TIM_INT_EN_TIM_VP(n) vxge_mBIT(n) | |
661 | /*0x00b88*/ u64 tim_set_int_en; | |
662 | #define VXGE_HW_TIM_SET_INT_EN_VP(n) vxge_mBIT(n) | |
663 | /*0x00b90*/ u64 tim_clr_int_en; | |
664 | #define VXGE_HW_TIM_CLR_INT_EN_VP(n) vxge_mBIT(n) | |
665 | /*0x00b98*/ u64 tim_mask_int_during_reset; | |
666 | #define VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH(n) vxge_mBIT(n) | |
667 | /*0x00ba0*/ u64 tim_reset_in_progress; | |
668 | #define VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH(n) vxge_mBIT(n) | |
669 | /*0x00ba8*/ u64 tim_outstanding_bmap; | |
670 | #define VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH(n) vxge_mBIT(n) | |
671 | u8 unused00c00[0x00c00-0x00bb0]; | |
672 | ||
673 | /*0x00c00*/ u64 msg_reset_in_progress; | |
674 | #define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vxge_vBIT(val, 0, 17) | |
675 | /*0x00c08*/ u64 msg_mxp_mr_ready; | |
676 | #define VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED(n) vxge_mBIT(n) | |
677 | /*0x00c10*/ u64 msg_uxp_mr_ready; | |
678 | #define VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED(n) vxge_mBIT(n) | |
679 | /*0x00c18*/ u64 msg_dmq_noni_rtl_prefetch; | |
680 | #define VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n) vxge_mBIT(n) | |
681 | /*0x00c20*/ u64 msg_umq_rtl_bwr; | |
682 | #define VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n) vxge_mBIT(n) | |
683 | u8 unused00d00[0x00d00-0x00c28]; | |
684 | ||
685 | /*0x00d00*/ u64 cmn_rsthdlr_cfg0; | |
686 | #define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vxge_vBIT(val, 0, 17) | |
687 | /*0x00d08*/ u64 cmn_rsthdlr_cfg1; | |
688 | #define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vxge_vBIT(val, 0, 17) | |
689 | /*0x00d10*/ u64 cmn_rsthdlr_cfg2; | |
690 | #define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vxge_vBIT(val, 0, 17) | |
691 | /*0x00d18*/ u64 cmn_rsthdlr_cfg3; | |
692 | #define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vxge_vBIT(val, 0, 17) | |
693 | /*0x00d20*/ u64 cmn_rsthdlr_cfg4; | |
694 | #define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vxge_vBIT(val, 0, 17) | |
695 | u8 unused00d40[0x00d40-0x00d28]; | |
696 | ||
697 | /*0x00d40*/ u64 cmn_rsthdlr_cfg8; | |
698 | #define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vxge_vBIT(val, 0, 17) | |
699 | /*0x00d48*/ u64 stats_cfg0; | |
700 | #define VXGE_HW_STATS_CFG0_STATS_ENABLE(val) vxge_vBIT(val, 0, 17) | |
701 | u8 unused00da8[0x00da8-0x00d50]; | |
702 | ||
703 | /*0x00da8*/ u64 clear_msix_mask_vect[4]; | |
704 | #define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) \ | |
705 | vxge_vBIT(val, 0, 17) | |
706 | /*0x00dc8*/ u64 set_msix_mask_vect[4]; | |
707 | #define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vxge_vBIT(val, 0, 17) | |
708 | /*0x00de8*/ u64 clear_msix_mask_all_vect; | |
709 | #define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val) \ | |
710 | vxge_vBIT(val, 0, 17) | |
711 | /*0x00df0*/ u64 set_msix_mask_all_vect; | |
712 | #define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val) \ | |
713 | vxge_vBIT(val, 0, 17) | |
714 | /*0x00df8*/ u64 mask_vector[4]; | |
715 | #define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val) vxge_vBIT(val, 0, 17) | |
716 | /*0x00e18*/ u64 msix_pending_vector[4]; | |
717 | #define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) \ | |
718 | vxge_vBIT(val, 0, 17) | |
719 | /*0x00e38*/ u64 clr_msix_one_shot_vec[4]; | |
720 | #define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val) \ | |
721 | vxge_vBIT(val, 0, 17) | |
722 | /*0x00e58*/ u64 titan_asic_id; | |
723 | #define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vxge_vBIT(val, 0, 16) | |
724 | #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vxge_vBIT(val, 48, 8) | |
725 | #define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vxge_vBIT(val, 56, 8) | |
726 | /*0x00e60*/ u64 titan_general_int_status; | |
727 | #define VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT vxge_mBIT(0) | |
728 | #define VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT vxge_mBIT(1) | |
729 | #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT vxge_mBIT(2) | |
730 | #define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val) \ | |
731 | vxge_vBIT(val, 3, 17) | |
732 | u8 unused00e70[0x00e70-0x00e68]; | |
733 | ||
734 | /*0x00e70*/ u64 titan_mask_all_int; | |
735 | #define VXGE_HW_TITAN_MASK_ALL_INT_ALARM vxge_mBIT(7) | |
736 | #define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC vxge_mBIT(15) | |
737 | u8 unused00e80[0x00e80-0x00e78]; | |
738 | ||
739 | /*0x00e80*/ u64 tim_int_status0; | |
740 | #define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val) vxge_vBIT(val, 0, 64) | |
741 | /*0x00e88*/ u64 tim_int_mask0; | |
742 | #define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val) vxge_vBIT(val, 0, 64) | |
743 | /*0x00e90*/ u64 tim_int_status1; | |
744 | #define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val) vxge_vBIT(val, 0, 4) | |
745 | /*0x00e98*/ u64 tim_int_mask1; | |
746 | #define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val) vxge_vBIT(val, 0, 4) | |
747 | /*0x00ea0*/ u64 rti_int_status; | |
748 | #define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val) vxge_vBIT(val, 0, 17) | |
749 | /*0x00ea8*/ u64 rti_int_mask; | |
750 | #define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val) vxge_vBIT(val, 0, 17) | |
751 | /*0x00eb0*/ u64 adapter_status; | |
752 | #define VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY vxge_mBIT(0) | |
753 | #define VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY vxge_mBIT(1) | |
754 | #define VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY vxge_mBIT(2) | |
755 | #define VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY vxge_mBIT(3) | |
756 | #define VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT vxge_mBIT(4) | |
757 | #define VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT vxge_mBIT(5) | |
758 | #define VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT vxge_mBIT(6) | |
759 | #define VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY vxge_mBIT(7) | |
760 | #define VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY vxge_mBIT(8) | |
761 | #define VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING vxge_mBIT(9) | |
762 | #define VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK vxge_mBIT(10) | |
763 | #define VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK vxge_mBIT(11) | |
764 | #define VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK vxge_mBIT(12) | |
765 | #define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val) vxge_vBIT(val, 24, 8) | |
766 | #define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val) vxge_vBIT(val, 44, 8) | |
767 | /*0x00eb8*/ u64 gen_ctrl; | |
768 | #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS vxge_mBIT(0) | |
769 | #define VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS vxge_mBIT(1) | |
770 | #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS vxge_mBIT(2) | |
771 | #define VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS vxge_mBIT(3) | |
772 | #define VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS vxge_mBIT(4) | |
773 | #define VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS vxge_mBIT(5) | |
774 | #define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val) vxge_vBIT(val, 6, 4) | |
775 | u8 unused00ed0[0x00ed0-0x00ec0]; | |
776 | ||
777 | /*0x00ed0*/ u64 adapter_ready; | |
778 | #define VXGE_HW_ADAPTER_READY_ADAPTER_READY vxge_mBIT(63) | |
779 | /*0x00ed8*/ u64 outstanding_read; | |
780 | #define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val) vxge_vBIT(val, 0, 17) | |
781 | /*0x00ee0*/ u64 vpath_rst_in_prog; | |
782 | #define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val) vxge_vBIT(val, 0, 17) | |
783 | /*0x00ee8*/ u64 vpath_reg_modified; | |
784 | #define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vxge_vBIT(val, 0, 17) | |
785 | u8 unused00fc0[0x00fc0-0x00ef0]; | |
786 | ||
787 | /*0x00fc0*/ u64 cp_reset_in_progress; | |
788 | #define VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH(n) vxge_mBIT(n) | |
789 | u8 unused01080[0x01080-0x00fc8]; | |
790 | ||
791 | /*0x01080*/ u64 xgmac_ready; | |
792 | #define VXGE_HW_XGMAC_READY_XMACJ_READY(val) vxge_vBIT(val, 0, 17) | |
793 | u8 unused010c0[0x010c0-0x01088]; | |
794 | ||
795 | /*0x010c0*/ u64 fbif_ready; | |
796 | #define VXGE_HW_FBIF_READY_FAU_READY(val) vxge_vBIT(val, 0, 17) | |
797 | u8 unused01100[0x01100-0x010c8]; | |
798 | ||
799 | /*0x01100*/ u64 vplane_assignments; | |
800 | #define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vxge_vBIT(val, 3, 5) | |
801 | /*0x01108*/ u64 vpath_assignments; | |
802 | #define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vxge_vBIT(val, 0, 17) | |
803 | /*0x01110*/ u64 resource_assignments; | |
804 | #define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) \ | |
805 | vxge_vBIT(val, 0, 17) | |
806 | /*0x01118*/ u64 host_type_assignments; | |
807 | #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val) \ | |
808 | vxge_vBIT(val, 5, 3) | |
809 | u8 unused01128[0x01128-0x01120]; | |
810 | ||
811 | /*0x01128*/ u64 max_resource_assignments; | |
812 | #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) \ | |
813 | vxge_vBIT(val, 3, 5) | |
814 | #define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) \ | |
815 | vxge_vBIT(val, 11, 5) | |
816 | /*0x01130*/ u64 pf_vpath_assignments; | |
817 | #define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) \ | |
818 | vxge_vBIT(val, 0, 17) | |
819 | u8 unused01200[0x01200-0x01138]; | |
820 | ||
821 | /*0x01200*/ u64 rts_access_icmp; | |
822 | #define VXGE_HW_RTS_ACCESS_ICMP_EN(val) vxge_vBIT(val, 0, 17) | |
823 | /*0x01208*/ u64 rts_access_tcpsyn; | |
824 | #define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val) vxge_vBIT(val, 0, 17) | |
825 | /*0x01210*/ u64 rts_access_zl4pyld; | |
826 | #define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val) vxge_vBIT(val, 0, 17) | |
827 | /*0x01218*/ u64 rts_access_l4prtcl_tcp; | |
828 | #define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val) vxge_vBIT(val, 0, 17) | |
829 | /*0x01220*/ u64 rts_access_l4prtcl_udp; | |
830 | #define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val) vxge_vBIT(val, 0, 17) | |
831 | /*0x01228*/ u64 rts_access_l4prtcl_flex; | |
832 | #define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val) vxge_vBIT(val, 0, 17) | |
833 | /*0x01230*/ u64 rts_access_ipfrag; | |
834 | #define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val) vxge_vBIT(val, 0, 17) | |
835 | ||
836 | } __packed; | |
837 | ||
838 | struct vxge_hw_memrepair_reg { | |
839 | u64 unused1; | |
840 | u64 unused2; | |
841 | } __packed; | |
842 | ||
843 | struct vxge_hw_pcicfgmgmt_reg { | |
844 | ||
845 | /*0x00000*/ u64 resource_no; | |
846 | #define VXGE_HW_RESOURCE_NO_PFN_OR_VF BIT(3) | |
847 | /*0x00008*/ u64 bargrp_pf_or_vf_bar0_mask; | |
848 | #define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val) \ | |
849 | vxge_vBIT(val, 2, 6) | |
850 | /*0x00010*/ u64 bargrp_pf_or_vf_bar1_mask; | |
851 | #define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val) \ | |
852 | vxge_vBIT(val, 2, 6) | |
853 | /*0x00018*/ u64 bargrp_pf_or_vf_bar2_mask; | |
854 | #define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val) \ | |
855 | vxge_vBIT(val, 2, 6) | |
856 | /*0x00020*/ u64 msixgrp_no; | |
857 | #define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val) vxge_vBIT(val, 5, 11) | |
858 | ||
859 | } __packed; | |
860 | ||
861 | struct vxge_hw_mrpcim_reg { | |
862 | /*0x00000*/ u64 g3fbct_int_status; | |
863 | #define VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) | |
864 | /*0x00008*/ u64 g3fbct_int_mask; | |
865 | /*0x00010*/ u64 g3fbct_err_reg; | |
866 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) | |
867 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) | |
868 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) | |
869 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) | |
870 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) | |
871 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) | |
872 | #define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) | |
873 | /*0x00018*/ u64 g3fbct_err_mask; | |
874 | /*0x00020*/ u64 g3fbct_err_alarm; | |
875 | ||
876 | u8 unused00a00[0x00a00-0x00028]; | |
877 | ||
878 | /*0x00a00*/ u64 wrdma_int_status; | |
879 | #define VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT vxge_mBIT(0) | |
880 | #define VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT vxge_mBIT(1) | |
881 | #define VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT vxge_mBIT(2) | |
882 | #define VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT vxge_mBIT(3) | |
883 | #define VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT vxge_mBIT(6) | |
884 | #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT vxge_mBIT(8) | |
885 | #define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT vxge_mBIT(9) | |
886 | #define VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT vxge_mBIT(12) | |
887 | #define VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT vxge_mBIT(13) | |
888 | #define VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT vxge_mBIT(14) | |
889 | #define VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT vxge_mBIT(15) | |
890 | #define VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT vxge_mBIT(16) | |
891 | #define VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT vxge_mBIT(17) | |
892 | /*0x00a08*/ u64 wrdma_int_mask; | |
893 | /*0x00a10*/ u64 rc_alarm_reg; | |
894 | #define VXGE_HW_RC_ALARM_REG_FTC_SM_ERR vxge_mBIT(0) | |
895 | #define VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR vxge_mBIT(1) | |
896 | #define VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR vxge_mBIT(2) | |
897 | #define VXGE_HW_RC_ALARM_REG_BTC_SM_ERR vxge_mBIT(3) | |
898 | #define VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR vxge_mBIT(4) | |
899 | #define VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR vxge_mBIT(5) | |
900 | #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR vxge_mBIT(6) | |
901 | #define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR vxge_mBIT(7) | |
902 | #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR vxge_mBIT(8) | |
903 | #define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR vxge_mBIT(9) | |
904 | #define VXGE_HW_RC_ALARM_REG_RMM_SM_ERR vxge_mBIT(10) | |
905 | #define VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR vxge_mBIT(12) | |
906 | /*0x00a18*/ u64 rc_alarm_mask; | |
907 | /*0x00a20*/ u64 rc_alarm_alarm; | |
908 | /*0x00a28*/ u64 rxdrm_sm_err_reg; | |
909 | #define VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) | |
910 | /*0x00a30*/ u64 rxdrm_sm_err_mask; | |
911 | /*0x00a38*/ u64 rxdrm_sm_err_alarm; | |
912 | /*0x00a40*/ u64 rxdcm_sm_err_reg; | |
913 | #define VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) | |
914 | /*0x00a48*/ u64 rxdcm_sm_err_mask; | |
915 | /*0x00a50*/ u64 rxdcm_sm_err_alarm; | |
916 | /*0x00a58*/ u64 rxdwm_sm_err_reg; | |
917 | #define VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP(n) vxge_mBIT(n) | |
918 | /*0x00a60*/ u64 rxdwm_sm_err_mask; | |
919 | /*0x00a68*/ u64 rxdwm_sm_err_alarm; | |
920 | /*0x00a70*/ u64 rda_err_reg; | |
921 | #define VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM vxge_mBIT(0) | |
922 | #define VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR vxge_mBIT(1) | |
923 | #define VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR vxge_mBIT(2) | |
924 | #define VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR vxge_mBIT(3) | |
925 | #define VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR vxge_mBIT(4) | |
926 | #define VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR vxge_mBIT(5) | |
927 | #define VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR vxge_mBIT(6) | |
928 | #define VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR vxge_mBIT(7) | |
929 | /*0x00a78*/ u64 rda_err_mask; | |
930 | /*0x00a80*/ u64 rda_err_alarm; | |
931 | /*0x00a88*/ u64 rda_ecc_db_reg; | |
932 | #define VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR(n) vxge_mBIT(n) | |
933 | /*0x00a90*/ u64 rda_ecc_db_mask; | |
934 | /*0x00a98*/ u64 rda_ecc_db_alarm; | |
935 | /*0x00aa0*/ u64 rda_ecc_sg_reg; | |
936 | #define VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR(n) vxge_mBIT(n) | |
937 | /*0x00aa8*/ u64 rda_ecc_sg_mask; | |
938 | /*0x00ab0*/ u64 rda_ecc_sg_alarm; | |
939 | /*0x00ab8*/ u64 rqa_err_reg; | |
940 | #define VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM vxge_mBIT(0) | |
941 | /*0x00ac0*/ u64 rqa_err_mask; | |
942 | /*0x00ac8*/ u64 rqa_err_alarm; | |
943 | /*0x00ad0*/ u64 frf_alarm_reg; | |
944 | #define VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n) vxge_mBIT(n) | |
945 | /*0x00ad8*/ u64 frf_alarm_mask; | |
946 | /*0x00ae0*/ u64 frf_alarm_alarm; | |
947 | /*0x00ae8*/ u64 rocrc_alarm_reg; | |
948 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB vxge_mBIT(0) | |
949 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG vxge_mBIT(1) | |
950 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR vxge_mBIT(2) | |
951 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB vxge_mBIT(3) | |
952 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG vxge_mBIT(4) | |
953 | #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB vxge_mBIT(5) | |
954 | #define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG vxge_mBIT(6) | |
955 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB vxge_mBIT(11) | |
956 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG vxge_mBIT(12) | |
957 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR vxge_mBIT(13) | |
958 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR vxge_mBIT(14) | |
959 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR vxge_mBIT(15) | |
960 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR vxge_mBIT(16) | |
961 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR vxge_mBIT(17) | |
962 | #define VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR vxge_mBIT(18) | |
963 | #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW vxge_mBIT(19) | |
964 | #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW vxge_mBIT(20) | |
965 | #define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW vxge_mBIT(21) | |
966 | #define VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR vxge_mBIT(22) | |
967 | /*0x00af0*/ u64 rocrc_alarm_mask; | |
968 | /*0x00af8*/ u64 rocrc_alarm_alarm; | |
969 | /*0x00b00*/ u64 wde0_alarm_reg; | |
970 | #define VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR vxge_mBIT(0) | |
971 | #define VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR vxge_mBIT(1) | |
972 | #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR vxge_mBIT(2) | |
973 | #define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR vxge_mBIT(3) | |
974 | #define VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR vxge_mBIT(4) | |
975 | /*0x00b08*/ u64 wde0_alarm_mask; | |
976 | /*0x00b10*/ u64 wde0_alarm_alarm; | |
977 | /*0x00b18*/ u64 wde1_alarm_reg; | |
978 | #define VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR vxge_mBIT(0) | |
979 | #define VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR vxge_mBIT(1) | |
980 | #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR vxge_mBIT(2) | |
981 | #define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR vxge_mBIT(3) | |
982 | #define VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR vxge_mBIT(4) | |
983 | /*0x00b20*/ u64 wde1_alarm_mask; | |
984 | /*0x00b28*/ u64 wde1_alarm_alarm; | |
985 | /*0x00b30*/ u64 wde2_alarm_reg; | |
986 | #define VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR vxge_mBIT(0) | |
987 | #define VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR vxge_mBIT(1) | |
988 | #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR vxge_mBIT(2) | |
989 | #define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR vxge_mBIT(3) | |
990 | #define VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR vxge_mBIT(4) | |
991 | /*0x00b38*/ u64 wde2_alarm_mask; | |
992 | /*0x00b40*/ u64 wde2_alarm_alarm; | |
993 | /*0x00b48*/ u64 wde3_alarm_reg; | |
994 | #define VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR vxge_mBIT(0) | |
995 | #define VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR vxge_mBIT(1) | |
996 | #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR vxge_mBIT(2) | |
997 | #define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR vxge_mBIT(3) | |
998 | #define VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR vxge_mBIT(4) | |
999 | /*0x00b50*/ u64 wde3_alarm_mask; | |
1000 | /*0x00b58*/ u64 wde3_alarm_alarm; | |
1001 | ||
1002 | u8 unused00be8[0x00be8-0x00b60]; | |
1003 | ||
1004 | /*0x00be8*/ u64 rx_w_round_robin_0; | |
1005 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vxge_vBIT(val, 3, 5) | |
1006 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5) | |
1007 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vxge_vBIT(val, 19, 5) | |
1008 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vxge_vBIT(val, 27, 5) | |
1009 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vxge_vBIT(val, 35, 5) | |
1010 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vxge_vBIT(val, 43, 5) | |
1011 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vxge_vBIT(val, 51, 5) | |
1012 | #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vxge_vBIT(val, 59, 5) | |
1013 | /*0x00bf0*/ u64 rx_w_round_robin_1; | |
1014 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vxge_vBIT(val, 3, 5) | |
1015 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5) | |
1016 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) \ | |
1017 | vxge_vBIT(val, 19, 5) | |
1018 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) \ | |
1019 | vxge_vBIT(val, 27, 5) | |
1020 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) \ | |
1021 | vxge_vBIT(val, 35, 5) | |
1022 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) \ | |
1023 | vxge_vBIT(val, 43, 5) | |
1024 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) \ | |
1025 | vxge_vBIT(val, 51, 5) | |
1026 | #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) \ | |
1027 | vxge_vBIT(val, 59, 5) | |
1028 | /*0x00bf8*/ u64 rx_w_round_robin_2; | |
1029 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vxge_vBIT(val, 3, 5) | |
1030 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \ | |
1031 | vxge_vBIT(val, 11, 5) | |
1032 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) \ | |
1033 | vxge_vBIT(val, 19, 5) | |
1034 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) \ | |
1035 | vxge_vBIT(val, 27, 5) | |
1036 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) \ | |
1037 | vxge_vBIT(val, 35, 5) | |
1038 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) \ | |
1039 | vxge_vBIT(val, 43, 5) | |
1040 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) \ | |
1041 | vxge_vBIT(val, 51, 5) | |
1042 | #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) \ | |
1043 | vxge_vBIT(val, 59, 5) | |
1044 | /*0x00c00*/ u64 rx_w_round_robin_3; | |
1045 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vxge_vBIT(val, 3, 5) | |
1046 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \ | |
1047 | vxge_vBIT(val, 11, 5) | |
1048 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) \ | |
1049 | vxge_vBIT(val, 19, 5) | |
1050 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) \ | |
1051 | vxge_vBIT(val, 27, 5) | |
1052 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) \ | |
1053 | vxge_vBIT(val, 35, 5) | |
1054 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) \ | |
1055 | vxge_vBIT(val, 43, 5) | |
1056 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) \ | |
1057 | vxge_vBIT(val, 51, 5) | |
1058 | #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) \ | |
1059 | vxge_vBIT(val, 59, 5) | |
1060 | /*0x00c08*/ u64 rx_w_round_robin_4; | |
1061 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vxge_vBIT(val, 3, 5) | |
1062 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \ | |
1063 | vxge_vBIT(val, 11, 5) | |
1064 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) \ | |
1065 | vxge_vBIT(val, 19, 5) | |
1066 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) \ | |
1067 | vxge_vBIT(val, 27, 5) | |
1068 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) \ | |
1069 | vxge_vBIT(val, 35, 5) | |
1070 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) \ | |
1071 | vxge_vBIT(val, 43, 5) | |
1072 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) \ | |
1073 | vxge_vBIT(val, 51, 5) | |
1074 | #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) \ | |
1075 | vxge_vBIT(val, 59, 5) | |
1076 | /*0x00c10*/ u64 rx_w_round_robin_5; | |
1077 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vxge_vBIT(val, 3, 5) | |
1078 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \ | |
1079 | vxge_vBIT(val, 11, 5) | |
1080 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) \ | |
1081 | vxge_vBIT(val, 19, 5) | |
1082 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) \ | |
1083 | vxge_vBIT(val, 27, 5) | |
1084 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) \ | |
1085 | vxge_vBIT(val, 35, 5) | |
1086 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) \ | |
1087 | vxge_vBIT(val, 43, 5) | |
1088 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) \ | |
1089 | vxge_vBIT(val, 51, 5) | |
1090 | #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) \ | |
1091 | vxge_vBIT(val, 59, 5) | |
1092 | /*0x00c18*/ u64 rx_w_round_robin_6; | |
1093 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vxge_vBIT(val, 3, 5) | |
1094 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \ | |
1095 | vxge_vBIT(val, 11, 5) | |
1096 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) \ | |
1097 | vxge_vBIT(val, 19, 5) | |
1098 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) \ | |
1099 | vxge_vBIT(val, 27, 5) | |
1100 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) \ | |
1101 | vxge_vBIT(val, 35, 5) | |
1102 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) \ | |
1103 | vxge_vBIT(val, 43, 5) | |
1104 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) \ | |
1105 | vxge_vBIT(val, 51, 5) | |
1106 | #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) \ | |
1107 | vxge_vBIT(val, 59, 5) | |
1108 | /*0x00c20*/ u64 rx_w_round_robin_7; | |
1109 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vxge_vBIT(val, 3, 5) | |
1110 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \ | |
1111 | vxge_vBIT(val, 11, 5) | |
1112 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) \ | |
1113 | vxge_vBIT(val, 19, 5) | |
1114 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) \ | |
1115 | vxge_vBIT(val, 27, 5) | |
1116 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) \ | |
1117 | vxge_vBIT(val, 35, 5) | |
1118 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) \ | |
1119 | vxge_vBIT(val, 43, 5) | |
1120 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) \ | |
1121 | vxge_vBIT(val, 51, 5) | |
1122 | #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) \ | |
1123 | vxge_vBIT(val, 59, 5) | |
1124 | /*0x00c28*/ u64 rx_w_round_robin_8; | |
1125 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vxge_vBIT(val, 3, 5) | |
1126 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \ | |
1127 | vxge_vBIT(val, 11, 5) | |
1128 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) \ | |
1129 | vxge_vBIT(val, 19, 5) | |
1130 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) \ | |
1131 | vxge_vBIT(val, 27, 5) | |
1132 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) \ | |
1133 | vxge_vBIT(val, 35, 5) | |
1134 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) \ | |
1135 | vxge_vBIT(val, 43, 5) | |
1136 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) \ | |
1137 | vxge_vBIT(val, 51, 5) | |
1138 | #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) \ | |
1139 | vxge_vBIT(val, 59, 5) | |
1140 | /*0x00c30*/ u64 rx_w_round_robin_9; | |
1141 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vxge_vBIT(val, 3, 5) | |
1142 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \ | |
1143 | vxge_vBIT(val, 11, 5) | |
1144 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) \ | |
1145 | vxge_vBIT(val, 19, 5) | |
1146 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) \ | |
1147 | vxge_vBIT(val, 27, 5) | |
1148 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) \ | |
1149 | vxge_vBIT(val, 35, 5) | |
1150 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) \ | |
1151 | vxge_vBIT(val, 43, 5) | |
1152 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) \ | |
1153 | vxge_vBIT(val, 51, 5) | |
1154 | #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) \ | |
1155 | vxge_vBIT(val, 59, 5) | |
1156 | /*0x00c38*/ u64 rx_w_round_robin_10; | |
1157 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) \ | |
1158 | vxge_vBIT(val, 3, 5) | |
1159 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \ | |
1160 | vxge_vBIT(val, 11, 5) | |
1161 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) \ | |
1162 | vxge_vBIT(val, 19, 5) | |
1163 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) \ | |
1164 | vxge_vBIT(val, 27, 5) | |
1165 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) \ | |
1166 | vxge_vBIT(val, 35, 5) | |
1167 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) \ | |
1168 | vxge_vBIT(val, 43, 5) | |
1169 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) \ | |
1170 | vxge_vBIT(val, 51, 5) | |
1171 | #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) \ | |
1172 | vxge_vBIT(val, 59, 5) | |
1173 | /*0x00c40*/ u64 rx_w_round_robin_11; | |
1174 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) \ | |
1175 | vxge_vBIT(val, 3, 5) | |
1176 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \ | |
1177 | vxge_vBIT(val, 11, 5) | |
1178 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) \ | |
1179 | vxge_vBIT(val, 19, 5) | |
1180 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) \ | |
1181 | vxge_vBIT(val, 27, 5) | |
1182 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) \ | |
1183 | vxge_vBIT(val, 35, 5) | |
1184 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) \ | |
1185 | vxge_vBIT(val, 43, 5) | |
1186 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) \ | |
1187 | vxge_vBIT(val, 51, 5) | |
1188 | #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) \ | |
1189 | vxge_vBIT(val, 59, 5) | |
1190 | /*0x00c48*/ u64 rx_w_round_robin_12; | |
1191 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) \ | |
1192 | vxge_vBIT(val, 3, 5) | |
1193 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \ | |
1194 | vxge_vBIT(val, 11, 5) | |
1195 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) \ | |
1196 | vxge_vBIT(val, 19, 5) | |
1197 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) \ | |
1198 | vxge_vBIT(val, 27, 5) | |
1199 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) \ | |
1200 | vxge_vBIT(val, 35, 5) | |
1201 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) \ | |
1202 | vxge_vBIT(val, 43, 5) | |
1203 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) \ | |
1204 | vxge_vBIT(val, 51, 5) | |
1205 | #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) \ | |
1206 | vxge_vBIT(val, 59, 5) | |
1207 | /*0x00c50*/ u64 rx_w_round_robin_13; | |
1208 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) \ | |
1209 | vxge_vBIT(val, 3, 5) | |
1210 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \ | |
1211 | vxge_vBIT(val, 11, 5) | |
1212 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) \ | |
1213 | vxge_vBIT(val, 19, 5) | |
1214 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) \ | |
1215 | vxge_vBIT(val, 27, 5) | |
1216 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) \ | |
1217 | vxge_vBIT(val, 35, 5) | |
1218 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) \ | |
1219 | vxge_vBIT(val, 43, 5) | |
1220 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) \ | |
1221 | vxge_vBIT(val, 51, 5) | |
1222 | #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) \ | |
1223 | vxge_vBIT(val, 59, 5) | |
1224 | /*0x00c58*/ u64 rx_w_round_robin_14; | |
1225 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) \ | |
1226 | vxge_vBIT(val, 3, 5) | |
1227 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \ | |
1228 | vxge_vBIT(val, 11, 5) | |
1229 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) \ | |
1230 | vxge_vBIT(val, 19, 5) | |
1231 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) \ | |
1232 | vxge_vBIT(val, 27, 5) | |
1233 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) \ | |
1234 | vxge_vBIT(val, 35, 5) | |
1235 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) \ | |
1236 | vxge_vBIT(val, 43, 5) | |
1237 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) \ | |
1238 | vxge_vBIT(val, 51, 5) | |
1239 | #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) \ | |
1240 | vxge_vBIT(val, 59, 5) | |
1241 | /*0x00c60*/ u64 rx_w_round_robin_15; | |
1242 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) \ | |
1243 | vxge_vBIT(val, 3, 5) | |
1244 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \ | |
1245 | vxge_vBIT(val, 11, 5) | |
1246 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) \ | |
1247 | vxge_vBIT(val, 19, 5) | |
1248 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) \ | |
1249 | vxge_vBIT(val, 27, 5) | |
1250 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) \ | |
1251 | vxge_vBIT(val, 35, 5) | |
1252 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) \ | |
1253 | vxge_vBIT(val, 43, 5) | |
1254 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) \ | |
1255 | vxge_vBIT(val, 51, 5) | |
1256 | #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) \ | |
1257 | vxge_vBIT(val, 59, 5) | |
1258 | /*0x00c68*/ u64 rx_w_round_robin_16; | |
1259 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) \ | |
1260 | vxge_vBIT(val, 3, 5) | |
1261 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \ | |
1262 | vxge_vBIT(val, 11, 5) | |
1263 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) \ | |
1264 | vxge_vBIT(val, 19, 5) | |
1265 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) \ | |
1266 | vxge_vBIT(val, 27, 5) | |
1267 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) \ | |
1268 | vxge_vBIT(val, 35, 5) | |
1269 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) \ | |
1270 | vxge_vBIT(val, 43, 5) | |
1271 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) \ | |
1272 | vxge_vBIT(val, 51, 5) | |
1273 | #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) \ | |
1274 | vxge_vBIT(val, 59, 5) | |
1275 | /*0x00c70*/ u64 rx_w_round_robin_17; | |
1276 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) \ | |
1277 | vxge_vBIT(val, 3, 5) | |
1278 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \ | |
1279 | vxge_vBIT(val, 11, 5) | |
1280 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) \ | |
1281 | vxge_vBIT(val, 19, 5) | |
1282 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) \ | |
1283 | vxge_vBIT(val, 27, 5) | |
1284 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) \ | |
1285 | vxge_vBIT(val, 35, 5) | |
1286 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) \ | |
1287 | vxge_vBIT(val, 43, 5) | |
1288 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) \ | |
1289 | vxge_vBIT(val, 51, 5) | |
1290 | #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) \ | |
1291 | vxge_vBIT(val, 59, 5) | |
1292 | /*0x00c78*/ u64 rx_w_round_robin_18; | |
1293 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) \ | |
1294 | vxge_vBIT(val, 3, 5) | |
1295 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \ | |
1296 | vxge_vBIT(val, 11, 5) | |
1297 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) \ | |
1298 | vxge_vBIT(val, 19, 5) | |
1299 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) \ | |
1300 | vxge_vBIT(val, 27, 5) | |
1301 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) \ | |
1302 | vxge_vBIT(val, 35, 5) | |
1303 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) \ | |
1304 | vxge_vBIT(val, 43, 5) | |
1305 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) \ | |
1306 | vxge_vBIT(val, 51, 5) | |
1307 | #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) \ | |
1308 | vxge_vBIT(val, 59, 5) | |
1309 | /*0x00c80*/ u64 rx_w_round_robin_19; | |
1310 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) \ | |
1311 | vxge_vBIT(val, 3, 5) | |
1312 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \ | |
1313 | vxge_vBIT(val, 11, 5) | |
1314 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) \ | |
1315 | vxge_vBIT(val, 19, 5) | |
1316 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) \ | |
1317 | vxge_vBIT(val, 27, 5) | |
1318 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) \ | |
1319 | vxge_vBIT(val, 35, 5) | |
1320 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) \ | |
1321 | vxge_vBIT(val, 43, 5) | |
1322 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) \ | |
1323 | vxge_vBIT(val, 51, 5) | |
1324 | #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) \ | |
1325 | vxge_vBIT(val, 59, 5) | |
1326 | /*0x00c88*/ u64 rx_w_round_robin_20; | |
1327 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) \ | |
1328 | vxge_vBIT(val, 3, 5) | |
1329 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \ | |
1330 | vxge_vBIT(val, 11, 5) | |
1331 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) \ | |
1332 | vxge_vBIT(val, 19, 5) | |
1333 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) \ | |
1334 | vxge_vBIT(val, 27, 5) | |
1335 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) \ | |
1336 | vxge_vBIT(val, 35, 5) | |
1337 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) \ | |
1338 | vxge_vBIT(val, 43, 5) | |
1339 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) \ | |
1340 | vxge_vBIT(val, 51, 5) | |
1341 | #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) \ | |
1342 | vxge_vBIT(val, 59, 5) | |
1343 | /*0x00c90*/ u64 rx_w_round_robin_21; | |
1344 | #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) \ | |
1345 | vxge_vBIT(val, 3, 5) | |
1346 | #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \ | |
1347 | vxge_vBIT(val, 11, 5) | |
1348 | #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) \ | |
1349 | vxge_vBIT(val, 19, 5) | |
1350 | ||
1351 | #define VXGE_HW_WRR_RING_SERVICE_STATES 171 | |
1352 | #define VXGE_HW_WRR_RING_COUNT 22 | |
1353 | ||
1354 | /*0x00c98*/ u64 rx_queue_priority_0; | |
1355 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vxge_vBIT(val, 3, 5) | |
1356 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5) | |
1357 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vxge_vBIT(val, 19, 5) | |
1358 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vxge_vBIT(val, 27, 5) | |
1359 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vxge_vBIT(val, 35, 5) | |
1360 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vxge_vBIT(val, 43, 5) | |
1361 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vxge_vBIT(val, 51, 5) | |
1362 | #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vxge_vBIT(val, 59, 5) | |
1363 | /*0x00ca0*/ u64 rx_queue_priority_1; | |
1364 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vxge_vBIT(val, 3, 5) | |
1365 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5) | |
1366 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vxge_vBIT(val, 19, 5) | |
1367 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vxge_vBIT(val, 27, 5) | |
1368 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vxge_vBIT(val, 35, 5) | |
1369 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vxge_vBIT(val, 43, 5) | |
1370 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vxge_vBIT(val, 51, 5) | |
1371 | #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vxge_vBIT(val, 59, 5) | |
1372 | /*0x00ca8*/ u64 rx_queue_priority_2; | |
1373 | #define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vxge_vBIT(val, 3, 5) | |
1374 | u8 unused00cc8[0x00cc8-0x00cb0]; | |
1375 | ||
1376 | /*0x00cc8*/ u64 replication_queue_priority; | |
1377 | #define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val) \ | |
1378 | vxge_vBIT(val, 59, 5) | |
1379 | /*0x00cd0*/ u64 rx_queue_select; | |
1380 | #define VXGE_HW_RX_QUEUE_SELECT_NUMBER(n) vxge_mBIT(n) | |
1381 | #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE vxge_mBIT(15) | |
1382 | #define VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY vxge_mBIT(23) | |
1383 | /*0x00cd8*/ u64 rqa_vpbp_ctrl; | |
1384 | #define VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS vxge_mBIT(15) | |
1385 | #define VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS vxge_mBIT(23) | |
1386 | #define VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS vxge_mBIT(31) | |
1387 | /*0x00ce0*/ u64 rx_multi_cast_ctrl; | |
1388 | #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS vxge_mBIT(0) | |
1389 | #define VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS vxge_mBIT(1) | |
1390 | #define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) \ | |
1391 | vxge_vBIT(val, 2, 30) | |
1392 | #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32) | |
1393 | /*0x00ce8*/ u64 wde_prm_ctrl; | |
1394 | #define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vxge_vBIT(val, 2, 10) | |
1395 | #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14) | |
1396 | #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW vxge_mBIT(32) | |
1397 | #define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY vxge_mBIT(33) | |
1398 | #define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val) vxge_vBIT(val, 46, 2) | |
1399 | /*0x00cf0*/ u64 noa_ctrl; | |
1400 | #define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 3, 5) | |
1401 | #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5) | |
1402 | #define VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS vxge_mBIT(16) | |
1403 | #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vxge_vBIT(val, 37, 4) | |
1404 | #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vxge_vBIT(val, 45, 4) | |
1405 | #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vxge_vBIT(val, 53, 4) | |
1406 | #define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vxge_vBIT(val, 60, 4) | |
1407 | /*0x00cf8*/ u64 phase_cfg; | |
1408 | #define VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN vxge_mBIT(0) | |
1409 | #define VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN vxge_mBIT(3) | |
1410 | #define VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN vxge_mBIT(7) | |
1411 | #define VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN vxge_mBIT(11) | |
1412 | #define VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN vxge_mBIT(15) | |
1413 | #define VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN vxge_mBIT(19) | |
1414 | #define VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN vxge_mBIT(23) | |
1415 | #define VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN vxge_mBIT(27) | |
1416 | #define VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN vxge_mBIT(31) | |
1417 | #define VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN vxge_mBIT(35) | |
1418 | #define VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN vxge_mBIT(39) | |
1419 | #define VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN vxge_mBIT(43) | |
1420 | /*0x00d00*/ u64 rcq_bypq_cfg; | |
1421 | #define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vxge_vBIT(val, 10, 22) | |
1422 | #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9) | |
1423 | #define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vxge_vBIT(val, 55, 9) | |
1424 | u8 unused00e00[0x00e00-0x00d08]; | |
1425 | ||
1426 | /*0x00e00*/ u64 doorbell_int_status; | |
1427 | #define VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT vxge_mBIT(7) | |
1428 | #define VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT vxge_mBIT(15) | |
1429 | /*0x00e08*/ u64 doorbell_int_mask; | |
1430 | /*0x00e10*/ u64 kdfc_err_reg; | |
1431 | #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) | |
1432 | #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) | |
1433 | #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) | |
1434 | #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) | |
1435 | #define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) | |
1436 | /*0x00e18*/ u64 kdfc_err_mask; | |
1437 | /*0x00e20*/ u64 kdfc_err_reg_alarm; | |
1438 | #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR vxge_mBIT(7) | |
1439 | #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR vxge_mBIT(15) | |
1440 | #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM vxge_mBIT(23) | |
1441 | #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 vxge_mBIT(32) | |
1442 | #define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR vxge_mBIT(39) | |
1443 | u8 unused00e40[0x00e40-0x00e28]; | |
1444 | /*0x00e40*/ u64 kdfc_vp_partition_0; | |
1445 | #define VXGE_HW_KDFC_VP_PARTITION_0_ENABLE vxge_mBIT(0) | |
1446 | #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val) vxge_vBIT(val, 5, 3) | |
1447 | #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15) | |
1448 | #define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val) vxge_vBIT(val, 37, 3) | |
1449 | #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val) vxge_vBIT(val, 49, 15) | |
1450 | /*0x00e48*/ u64 kdfc_vp_partition_1; | |
1451 | #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val) vxge_vBIT(val, 5, 3) | |
1452 | #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15) | |
1453 | #define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val) vxge_vBIT(val, 37, 3) | |
1454 | #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val) vxge_vBIT(val, 49, 15) | |
1455 | /*0x00e50*/ u64 kdfc_vp_partition_2; | |
1456 | #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val) vxge_vBIT(val, 5, 3) | |
1457 | #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15) | |
1458 | #define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val) vxge_vBIT(val, 37, 3) | |
1459 | #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val) vxge_vBIT(val, 49, 15) | |
1460 | /*0x00e58*/ u64 kdfc_vp_partition_3; | |
1461 | #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val) vxge_vBIT(val, 5, 3) | |
1462 | #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15) | |
1463 | #define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val) vxge_vBIT(val, 37, 3) | |
1464 | #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val) vxge_vBIT(val, 49, 15) | |
1465 | /*0x00e60*/ u64 kdfc_vp_partition_4; | |
1466 | #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val) vxge_vBIT(val, 17, 15) | |
1467 | #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15) | |
1468 | /*0x00e68*/ u64 kdfc_vp_partition_5; | |
1469 | #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val) vxge_vBIT(val, 17, 15) | |
1470 | #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15) | |
1471 | /*0x00e70*/ u64 kdfc_vp_partition_6; | |
1472 | #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val) vxge_vBIT(val, 17, 15) | |
1473 | #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15) | |
1474 | /*0x00e78*/ u64 kdfc_vp_partition_7; | |
1475 | #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val) vxge_vBIT(val, 17, 15) | |
1476 | #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15) | |
1477 | /*0x00e80*/ u64 kdfc_vp_partition_8; | |
1478 | #define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val) vxge_vBIT(val, 17, 15) | |
1479 | /*0x00e88*/ u64 kdfc_w_round_robin_0; | |
1480 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vxge_vBIT(val, 3, 5) | |
1481 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5) | |
1482 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vxge_vBIT(val, 19, 5) | |
1483 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vxge_vBIT(val, 27, 5) | |
1484 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vxge_vBIT(val, 35, 5) | |
1485 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vxge_vBIT(val, 43, 5) | |
1486 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vxge_vBIT(val, 51, 5) | |
1487 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vxge_vBIT(val, 59, 5) | |
1488 | ||
1489 | u8 unused0f28[0x0f28-0x0e90]; | |
1490 | ||
1491 | /*0x00f28*/ u64 kdfc_w_round_robin_20; | |
1492 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vxge_vBIT(val, 3, 5) | |
1493 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5) | |
1494 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vxge_vBIT(val, 19, 5) | |
1495 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vxge_vBIT(val, 27, 5) | |
1496 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vxge_vBIT(val, 35, 5) | |
1497 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vxge_vBIT(val, 43, 5) | |
1498 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vxge_vBIT(val, 51, 5) | |
1499 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vxge_vBIT(val, 59, 5) | |
1500 | ||
1501 | #define VXGE_HW_WRR_FIFO_COUNT 20 | |
1502 | ||
1503 | u8 unused0fc8[0x0fc8-0x0f30]; | |
1504 | ||
1505 | /*0x00fc8*/ u64 kdfc_w_round_robin_40; | |
1506 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vxge_vBIT(val, 3, 5) | |
1507 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5) | |
1508 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vxge_vBIT(val, 19, 5) | |
1509 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vxge_vBIT(val, 27, 5) | |
1510 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vxge_vBIT(val, 35, 5) | |
1511 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vxge_vBIT(val, 43, 5) | |
1512 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vxge_vBIT(val, 51, 5) | |
1513 | #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vxge_vBIT(val, 59, 5) | |
1514 | ||
1515 | u8 unused1068[0x01068-0x0fd0]; | |
1516 | ||
1517 | /*0x01068*/ u64 kdfc_entry_type_sel_0; | |
1518 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vxge_vBIT(val, 6, 2) | |
1519 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2) | |
1520 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vxge_vBIT(val, 22, 2) | |
1521 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vxge_vBIT(val, 30, 2) | |
1522 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vxge_vBIT(val, 38, 2) | |
1523 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vxge_vBIT(val, 46, 2) | |
1524 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vxge_vBIT(val, 54, 2) | |
1525 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vxge_vBIT(val, 62, 2) | |
1526 | /*0x01070*/ u64 kdfc_entry_type_sel_1; | |
1527 | #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vxge_vBIT(val, 6, 2) | |
1528 | /*0x01078*/ u64 kdfc_fifo_0_ctrl; | |
1529 | #define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) | |
1530 | #define VXGE_HW_WEIGHTED_RR_SERVICE_STATES 176 | |
1531 | #define VXGE_HW_WRR_FIFO_SERVICE_STATES 153 | |
1532 | ||
1533 | u8 unused1100[0x01100-0x1080]; | |
1534 | ||
1535 | /*0x01100*/ u64 kdfc_fifo_17_ctrl; | |
1536 | #define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vxge_vBIT(val, 3, 5) | |
1537 | ||
1538 | u8 unused1600[0x01600-0x1108]; | |
1539 | ||
1540 | /*0x01600*/ u64 rxmac_int_status; | |
1541 | #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT vxge_mBIT(3) | |
1542 | #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT vxge_mBIT(7) | |
1543 | #define VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT \ | |
1544 | vxge_mBIT(11) | |
1545 | /*0x01608*/ u64 rxmac_int_mask; | |
1546 | u8 unused01618[0x01618-0x01610]; | |
1547 | ||
1548 | /*0x01618*/ u64 rxmac_gen_err_reg; | |
1549 | /*0x01620*/ u64 rxmac_gen_err_mask; | |
1550 | /*0x01628*/ u64 rxmac_gen_err_alarm; | |
1551 | /*0x01630*/ u64 rxmac_ecc_err_reg; | |
1552 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val) \ | |
1553 | vxge_vBIT(val, 0, 4) | |
1554 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \ | |
1555 | vxge_vBIT(val, 4, 4) | |
1556 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val) \ | |
1557 | vxge_vBIT(val, 8, 4) | |
1558 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val) \ | |
1559 | vxge_vBIT(val, 12, 4) | |
1560 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val) \ | |
1561 | vxge_vBIT(val, 16, 4) | |
1562 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val) \ | |
1563 | vxge_vBIT(val, 20, 4) | |
1564 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val) \ | |
1565 | vxge_vBIT(val, 24, 2) | |
1566 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val) \ | |
1567 | vxge_vBIT(val, 26, 2) | |
1568 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val) \ | |
1569 | vxge_vBIT(val, 28, 2) | |
1570 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val) \ | |
1571 | vxge_vBIT(val, 30, 2) | |
1572 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR vxge_mBIT(32) | |
1573 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR vxge_mBIT(33) | |
1574 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR vxge_mBIT(34) | |
1575 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR vxge_mBIT(35) | |
1576 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR vxge_mBIT(36) | |
1577 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR vxge_mBIT(37) | |
1578 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR vxge_mBIT(38) | |
1579 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR vxge_mBIT(39) | |
1580 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val) \ | |
1581 | vxge_vBIT(val, 40, 7) | |
1582 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val) \ | |
1583 | vxge_vBIT(val, 47, 7) | |
1584 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val) \ | |
1585 | vxge_vBIT(val, 54, 3) | |
1586 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val) \ | |
1587 | vxge_vBIT(val, 57, 3) | |
1588 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR \ | |
1589 | vxge_mBIT(60) | |
1590 | #define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR \ | |
1591 | vxge_mBIT(61) | |
1592 | /*0x01638*/ u64 rxmac_ecc_err_mask; | |
1593 | /*0x01640*/ u64 rxmac_ecc_err_alarm; | |
1594 | /*0x01648*/ u64 rxmac_various_err_reg; | |
1595 | #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR vxge_mBIT(0) | |
1596 | #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR vxge_mBIT(1) | |
1597 | #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR vxge_mBIT(2) | |
1598 | #define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR vxge_mBIT(3) | |
1599 | /*0x01650*/ u64 rxmac_various_err_mask; | |
1600 | /*0x01658*/ u64 rxmac_various_err_alarm; | |
1601 | /*0x01660*/ u64 rxmac_gen_cfg; | |
1602 | #define VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL vxge_mBIT(11) | |
1603 | /*0x01668*/ u64 rxmac_authorize_all_addr; | |
1604 | #define VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) vxge_mBIT(n) | |
1605 | /*0x01670*/ u64 rxmac_authorize_all_vid; | |
1606 | #define VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP(n) vxge_mBIT(n) | |
1607 | u8 unused016c0[0x016c0-0x01678]; | |
1608 | ||
1609 | /*0x016c0*/ u64 rxmac_red_rate_repl_queue; | |
1610 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vxge_vBIT(val, 0, 4) | |
1611 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4) | |
1612 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vxge_vBIT(val, 8, 4) | |
1613 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vxge_vBIT(val, 12, 4) | |
1614 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vxge_vBIT(val, 16, 4) | |
1615 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vxge_vBIT(val, 20, 4) | |
1616 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vxge_vBIT(val, 24, 4) | |
1617 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vxge_vBIT(val, 28, 4) | |
1618 | #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN vxge_mBIT(35) | |
1619 | u8 unused016e0[0x016e0-0x016c8]; | |
1620 | ||
1621 | /*0x016e0*/ u64 rxmac_cfg0_port[3]; | |
1622 | #define VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN vxge_mBIT(3) | |
1623 | #define VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS vxge_mBIT(7) | |
1624 | #define VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM vxge_mBIT(11) | |
1625 | #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR vxge_mBIT(15) | |
1626 | #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR vxge_mBIT(19) | |
1627 | #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR vxge_mBIT(23) | |
1628 | #define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH vxge_mBIT(27) | |
1629 | #define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vxge_vBIT(val, 50, 14) | |
1630 | u8 unused01710[0x01710-0x016f8]; | |
1631 | ||
1632 | /*0x01710*/ u64 rxmac_cfg2_port[3]; | |
1633 | #define VXGE_HW_RXMAC_CFG2_PORT_PROM_EN vxge_mBIT(3) | |
1634 | /*0x01728*/ u64 rxmac_pause_cfg_port[3]; | |
1635 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN vxge_mBIT(3) | |
1636 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN vxge_mBIT(7) | |
1637 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vxge_vBIT(val, 9, 3) | |
1638 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR vxge_mBIT(15) | |
1639 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vxge_vBIT(val, 20, 16) | |
1640 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR vxge_mBIT(39) | |
1641 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR vxge_mBIT(43) | |
1642 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN vxge_mBIT(47) | |
1643 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vxge_vBIT(val, 48, 8) | |
1644 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL vxge_mBIT(59) | |
1645 | u8 unused01758[0x01758-0x01740]; | |
1646 | ||
1647 | /*0x01758*/ u64 rxmac_red_cfg0_port[3]; | |
1648 | #define VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP(n) vxge_mBIT(n) | |
1649 | /*0x01770*/ u64 rxmac_red_cfg1_port[3]; | |
1650 | #define VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN vxge_mBIT(3) | |
1651 | #define VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE vxge_mBIT(11) | |
1652 | /*0x01788*/ u64 rxmac_red_cfg2_port[3]; | |
1653 | #define VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n) vxge_mBIT(n) | |
1654 | /*0x017a0*/ u64 rxmac_link_util_port[3]; | |
1655 | #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) \ | |
1656 | vxge_vBIT(val, 1, 7) | |
1657 | #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) | |
1658 | #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) \ | |
1659 | vxge_vBIT(val, 12, 4) | |
1660 | #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) | |
1661 | #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR vxge_mBIT(23) | |
1662 | u8 unused017d0[0x017d0-0x017b8]; | |
1663 | ||
1664 | /*0x017d0*/ u64 rxmac_status_port[3]; | |
1665 | #define VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD vxge_mBIT(3) | |
1666 | u8 unused01800[0x01800-0x017e8]; | |
1667 | ||
1668 | /*0x01800*/ u64 rxmac_rx_pa_cfg0; | |
1669 | #define VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR vxge_mBIT(3) | |
1670 | #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N vxge_mBIT(7) | |
1671 | #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO vxge_mBIT(18) | |
1672 | #define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(19) | |
1673 | #define VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING vxge_mBIT(23) | |
1674 | #define VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN vxge_mBIT(27) | |
1675 | #define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE vxge_mBIT(35) | |
1676 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR vxge_mBIT(39) | |
1677 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR vxge_mBIT(43) | |
1678 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR vxge_mBIT(47) | |
1679 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR vxge_mBIT(51) | |
1680 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR vxge_mBIT(55) | |
1681 | #define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR vxge_mBIT(59) | |
1682 | #define VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN vxge_mBIT(63) | |
1683 | /*0x01808*/ u64 rxmac_rx_pa_cfg1; | |
1684 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH vxge_mBIT(3) | |
1685 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH vxge_mBIT(7) | |
1686 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH vxge_mBIT(11) | |
1687 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH vxge_mBIT(15) | |
1688 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF vxge_mBIT(19) | |
1689 | #define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG vxge_mBIT(23) | |
1690 | u8 unused01828[0x01828-0x01810]; | |
1691 | ||
1692 | /*0x01828*/ u64 rts_mgr_cfg0; | |
1693 | #define VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY vxge_mBIT(3) | |
1694 | #define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vxge_vBIT(val, 24, 8) | |
1695 | #define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH vxge_mBIT(35) | |
1696 | #define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH vxge_mBIT(39) | |
1697 | #define VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH vxge_mBIT(43) | |
1698 | #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH vxge_mBIT(47) | |
1699 | #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH vxge_mBIT(51) | |
1700 | #define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH vxge_mBIT(55) | |
1701 | #define VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH vxge_mBIT(59) | |
1702 | /*0x01830*/ u64 rts_mgr_cfg1; | |
1703 | #define VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE vxge_mBIT(3) | |
1704 | #define VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE vxge_mBIT(7) | |
1705 | /*0x01838*/ u64 rts_mgr_criteria_priority; | |
1706 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vxge_vBIT(val, 5, 3) | |
1707 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3) | |
1708 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vxge_vBIT(val, 13, 3) | |
1709 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vxge_vBIT(val, 17, 3) | |
1710 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vxge_vBIT(val, 21, 3) | |
1711 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val) vxge_vBIT(val, 25, 3) | |
1712 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vxge_vBIT(val, 29, 3) | |
1713 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vxge_vBIT(val, 33, 3) | |
1714 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vxge_vBIT(val, 37, 3) | |
1715 | /*0x01840*/ u64 rts_mgr_da_pause_cfg; | |
1716 | #define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vxge_vBIT(val, 0, 17) | |
1717 | /*0x01848*/ u64 rts_mgr_da_slow_proto_cfg; | |
1718 | #define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) \ | |
1719 | vxge_vBIT(val, 0, 17) | |
1720 | u8 unused01890[0x01890-0x01850]; | |
1721 | /*0x01890*/ u64 rts_mgr_cbasin_cfg; | |
1722 | u8 unused01968[0x01968-0x01898]; | |
1723 | ||
1724 | /*0x01968*/ u64 dbg_stat_rx_any_frms; | |
1725 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) | |
1726 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) | |
1727 | #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) \ | |
1728 | vxge_vBIT(val, 16, 8) | |
1729 | u8 unused01a00[0x01a00-0x01970]; | |
1730 | ||
1731 | /*0x01a00*/ u64 rxmac_red_rate_vp[17]; | |
1732 | #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val) vxge_vBIT(val, 0, 4) | |
1733 | #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4) | |
1734 | #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val) vxge_vBIT(val, 8, 4) | |
1735 | #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val) vxge_vBIT(val, 12, 4) | |
1736 | #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val) vxge_vBIT(val, 16, 4) | |
1737 | #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val) vxge_vBIT(val, 20, 4) | |
1738 | #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val) vxge_vBIT(val, 24, 4) | |
1739 | #define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val) vxge_vBIT(val, 28, 4) | |
1740 | u8 unused01e00[0x01e00-0x01a88]; | |
1741 | ||
1742 | /*0x01e00*/ u64 xgmac_int_status; | |
1743 | #define VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT vxge_mBIT(3) | |
1744 | #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0 \ | |
1745 | vxge_mBIT(7) | |
1746 | #define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1 \ | |
1747 | vxge_mBIT(11) | |
1748 | #define VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT vxge_mBIT(15) | |
1749 | #define VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT vxge_mBIT(19) | |
1750 | #define VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT vxge_mBIT(23) | |
1751 | /*0x01e08*/ u64 xgmac_int_mask; | |
1752 | /*0x01e10*/ u64 xmac_gen_err_reg; | |
1753 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED \ | |
1754 | vxge_mBIT(7) | |
1755 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED \ | |
1756 | vxge_mBIT(11) | |
1757 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU vxge_mBIT(15) | |
1758 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED \ | |
1759 | vxge_mBIT(19) | |
1760 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED \ | |
1761 | vxge_mBIT(23) | |
1762 | #define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU vxge_mBIT(27) | |
1763 | #define VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED vxge_mBIT(31) | |
1764 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val) \ | |
1765 | vxge_vBIT(val, 40, 2) | |
1766 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \ | |
1767 | vxge_vBIT(val, 42, 2) | |
1768 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val) \ | |
1769 | vxge_vBIT(val, 44, 2) | |
1770 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val) \ | |
1771 | vxge_vBIT(val, 46, 2) | |
1772 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val) \ | |
1773 | vxge_vBIT(val, 48, 2) | |
1774 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val) \ | |
1775 | vxge_vBIT(val, 50, 2) | |
1776 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val) \ | |
1777 | vxge_vBIT(val, 52, 2) | |
1778 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val) \ | |
1779 | vxge_vBIT(val, 54, 2) | |
1780 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val) \ | |
1781 | vxge_vBIT(val, 56, 2) | |
1782 | #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val) \ | |
1783 | vxge_vBIT(val, 58, 2) | |
1784 | #define VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR vxge_mBIT(63) | |
1785 | /*0x01e18*/ u64 xmac_gen_err_mask; | |
1786 | /*0x01e20*/ u64 xmac_gen_err_alarm; | |
3255da41 | 1787 | /*0x01e28*/ u64 xmac_link_err_port0_reg; |
66d97fed RV |
1788 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN vxge_mBIT(3) |
1789 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP vxge_mBIT(7) | |
1790 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN vxge_mBIT(11) | |
1791 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP vxge_mBIT(15) | |
1792 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT \ | |
1793 | vxge_mBIT(19) | |
1794 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK vxge_mBIT(23) | |
1795 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN vxge_mBIT(27) | |
1796 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP vxge_mBIT(31) | |
1797 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE vxge_mBIT(35) | |
1798 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV vxge_mBIT(39) | |
1799 | #define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE \ | |
1800 | vxge_mBIT(47) | |
3255da41 SH |
1801 | /*0x01e30*/ u64 xmac_link_err_port0_mask; |
1802 | /*0x01e38*/ u64 xmac_link_err_port0_alarm; | |
1803 | /*0x01e40*/ u64 xmac_link_err_port1_reg; | |
1804 | /*0x01e48*/ u64 xmac_link_err_port1_mask; | |
1805 | /*0x01e50*/ u64 xmac_link_err_port1_alarm; | |
66d97fed RV |
1806 | /*0x01e58*/ u64 xgxs_gen_err_reg; |
1807 | #define VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR vxge_mBIT(63) | |
1808 | /*0x01e60*/ u64 xgxs_gen_err_mask; | |
1809 | /*0x01e68*/ u64 xgxs_gen_err_alarm; | |
1810 | /*0x01e70*/ u64 asic_ntwk_err_reg; | |
1811 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN vxge_mBIT(3) | |
1812 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP vxge_mBIT(7) | |
1813 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN vxge_mBIT(11) | |
1814 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP vxge_mBIT(15) | |
1815 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT vxge_mBIT(19) | |
1816 | #define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) | |
1817 | /*0x01e78*/ u64 asic_ntwk_err_mask; | |
1818 | /*0x01e80*/ u64 asic_ntwk_err_alarm; | |
1819 | /*0x01e88*/ u64 asic_gpio_err_reg; | |
1820 | #define VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) vxge_mBIT(n) | |
1821 | /*0x01e90*/ u64 asic_gpio_err_mask; | |
1822 | /*0x01e98*/ u64 asic_gpio_err_alarm; | |
1823 | /*0x01ea0*/ u64 xgmac_gen_status; | |
1824 | #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK vxge_mBIT(3) | |
1825 | #define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE vxge_mBIT(11) | |
1826 | /*0x01ea8*/ u64 xgmac_gen_fw_memo_status; | |
1827 | #define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val) \ | |
1828 | vxge_vBIT(val, 0, 17) | |
1829 | /*0x01eb0*/ u64 xgmac_gen_fw_memo_mask; | |
1830 | #define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vxge_vBIT(val, 0, 64) | |
1831 | /*0x01eb8*/ u64 xgmac_gen_fw_vpath_to_vsport_status; | |
1832 | #define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val) \ | |
1833 | vxge_vBIT(val, 0, 17) | |
1834 | /*0x01ec0*/ u64 xgmac_main_cfg_port[2]; | |
1835 | #define VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN vxge_mBIT(3) | |
1836 | u8 unused01f40[0x01f40-0x01ed0]; | |
1837 | ||
1838 | /*0x01f40*/ u64 xmac_gen_cfg; | |
1839 | #define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vxge_vBIT(val, 2, 2) | |
1840 | #define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT vxge_mBIT(7) | |
1841 | #define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR vxge_mBIT(27) | |
1842 | #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vxge_vBIT(val, 28, 4) | |
1843 | #define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vxge_vBIT(val, 32, 4) | |
1844 | /*0x01f48*/ u64 xmac_timestamp; | |
1845 | #define VXGE_HW_XMAC_TIMESTAMP_EN vxge_mBIT(3) | |
1846 | #define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val) vxge_vBIT(val, 6, 2) | |
1847 | #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4) | |
1848 | #define VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART vxge_mBIT(19) | |
1849 | #define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vxge_vBIT(val, 32, 16) | |
1850 | /*0x01f50*/ u64 xmac_stats_gen_cfg; | |
1851 | #define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vxge_vBIT(val, 4, 4) | |
1852 | #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4) | |
1853 | #define VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING vxge_mBIT(15) | |
1854 | /*0x01f58*/ u64 xmac_stats_sys_cmd; | |
1855 | #define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val) vxge_vBIT(val, 5, 3) | |
1856 | #define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE vxge_mBIT(15) | |
1857 | #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vxge_vBIT(val, 27, 5) | |
1858 | #define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) | |
1859 | /*0x01f60*/ u64 xmac_stats_sys_data; | |
1860 | #define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) | |
1861 | u8 unused01f80[0x01f80-0x01f68]; | |
1862 | ||
1863 | /*0x01f80*/ u64 asic_ntwk_ctrl; | |
1864 | #define VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK vxge_mBIT(3) | |
1865 | #define VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT vxge_mBIT(11) | |
1866 | #define VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT vxge_mBIT(15) | |
1867 | /*0x01f88*/ u64 asic_ntwk_cfg_show_port_info; | |
1868 | #define VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) vxge_mBIT(n) | |
1869 | /*0x01f90*/ u64 asic_ntwk_cfg_port_num; | |
1870 | #define VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP(n) vxge_mBIT(n) | |
1871 | /*0x01f98*/ u64 xmac_cfg_port[3]; | |
1872 | #define VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK vxge_mBIT(3) | |
1873 | #define VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK vxge_mBIT(7) | |
1874 | #define VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV vxge_mBIT(11) | |
1875 | #define VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV vxge_mBIT(15) | |
1876 | /*0x01fb0*/ u64 xmac_station_addr_port[2]; | |
1877 | #define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vxge_vBIT(val, 0, 48) | |
1878 | u8 unused02020[0x02020-0x01fc0]; | |
1879 | ||
1880 | /*0x02020*/ u64 lag_cfg; | |
1881 | #define VXGE_HW_LAG_CFG_EN vxge_mBIT(3) | |
1882 | #define VXGE_HW_LAG_CFG_MODE(val) vxge_vBIT(val, 6, 2) | |
1883 | #define VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV vxge_mBIT(11) | |
1884 | #define VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV vxge_mBIT(15) | |
1885 | #define VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM vxge_mBIT(19) | |
1886 | /*0x02028*/ u64 lag_status; | |
1887 | #define VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK vxge_mBIT(3) | |
1888 | #define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) \ | |
1889 | vxge_vBIT(val, 8, 8) | |
1890 | /*0x02030*/ u64 lag_active_passive_cfg; | |
1891 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY vxge_mBIT(3) | |
1892 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES vxge_mBIT(7) | |
1893 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM vxge_mBIT(11) | |
1894 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK vxge_mBIT(15) | |
1895 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN vxge_mBIT(19) | |
1896 | #define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val) \ | |
1897 | vxge_vBIT(val, 32, 16) | |
1898 | u8 unused02040[0x02040-0x02038]; | |
1899 | ||
1900 | /*0x02040*/ u64 lag_lacp_cfg; | |
1901 | #define VXGE_HW_LAG_LACP_CFG_EN vxge_mBIT(3) | |
1902 | #define VXGE_HW_LAG_LACP_CFG_LACP_BEGIN vxge_mBIT(7) | |
1903 | #define VXGE_HW_LAG_LACP_CFG_DISCARD_LACP vxge_mBIT(11) | |
1904 | #define VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK vxge_mBIT(15) | |
1905 | /*0x02048*/ u64 lag_timer_cfg_1; | |
1906 | #define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val) vxge_vBIT(val, 0, 16) | |
1907 | #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16) | |
1908 | #define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vxge_vBIT(val, 32, 16) | |
1909 | #define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vxge_vBIT(val, 48, 16) | |
1910 | /*0x02050*/ u64 lag_timer_cfg_2; | |
1911 | #define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val) vxge_vBIT(val, 0, 16) | |
1912 | #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16) | |
1913 | #define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vxge_vBIT(val, 32, 16) | |
1914 | #define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vxge_vBIT(val, 48, 16) | |
1915 | /*0x02058*/ u64 lag_sys_id; | |
1916 | #define VXGE_HW_LAG_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) | |
1917 | #define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR vxge_mBIT(51) | |
1918 | #define VXGE_HW_LAG_SYS_ID_ADDR_SEL vxge_mBIT(55) | |
1919 | /*0x02060*/ u64 lag_sys_cfg; | |
1920 | #define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) | |
1921 | u8 unused02070[0x02070-0x02068]; | |
1922 | ||
1923 | /*0x02070*/ u64 lag_aggr_addr_cfg[2]; | |
1924 | #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val) vxge_vBIT(val, 0, 48) | |
1925 | #define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR vxge_mBIT(51) | |
1926 | #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL vxge_mBIT(55) | |
1927 | /*0x02080*/ u64 lag_aggr_id_cfg[2]; | |
1928 | #define VXGE_HW_LAG_AGGR_ID_CFG_ID(val) vxge_vBIT(val, 0, 16) | |
1929 | /*0x02090*/ u64 lag_aggr_admin_key[2]; | |
1930 | #define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) | |
1931 | /*0x020a0*/ u64 lag_aggr_alt_admin_key; | |
1932 | #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vxge_vBIT(val, 0, 16) | |
1933 | #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR vxge_mBIT(19) | |
1934 | /*0x020a8*/ u64 lag_aggr_oper_key[2]; | |
1935 | #define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) | |
1936 | /*0x020b8*/ u64 lag_aggr_partner_sys_id[2]; | |
1937 | #define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vxge_vBIT(val, 0, 48) | |
1938 | /*0x020c8*/ u64 lag_aggr_partner_info[2]; | |
1939 | #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vxge_vBIT(val, 0, 16) | |
1940 | #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \ | |
1941 | vxge_vBIT(val, 16, 16) | |
1942 | /*0x020d8*/ u64 lag_aggr_state[2]; | |
1943 | #define VXGE_HW_LAG_AGGR_STATE_LAGC_TX vxge_mBIT(3) | |
1944 | #define VXGE_HW_LAG_AGGR_STATE_LAGC_RX vxge_mBIT(7) | |
1945 | #define VXGE_HW_LAG_AGGR_STATE_LAGC_READY vxge_mBIT(11) | |
1946 | #define VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL vxge_mBIT(15) | |
1947 | u8 unused020f0[0x020f0-0x020e8]; | |
1948 | ||
1949 | /*0x020f0*/ u64 lag_port_cfg[2]; | |
1950 | #define VXGE_HW_LAG_PORT_CFG_EN vxge_mBIT(3) | |
1951 | #define VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO vxge_mBIT(7) | |
1952 | #define VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR vxge_mBIT(11) | |
1953 | #define VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO vxge_mBIT(15) | |
1954 | /*0x02100*/ u64 lag_port_actor_admin_cfg[2]; | |
1955 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vxge_vBIT(val, 0, 16) | |
1956 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16) | |
1957 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vxge_vBIT(val, 32, 16) | |
1958 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vxge_vBIT(val, 48, 16) | |
1959 | /*0x02110*/ u64 lag_port_actor_admin_state[2]; | |
1960 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) | |
1961 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) | |
1962 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION vxge_mBIT(11) | |
1963 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) | |
1964 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING vxge_mBIT(19) | |
1965 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) | |
1966 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED vxge_mBIT(27) | |
1967 | #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED vxge_mBIT(31) | |
1968 | /*0x02120*/ u64 lag_port_partner_admin_sys_id[2]; | |
1969 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vxge_vBIT(val, 0, 48) | |
1970 | /*0x02130*/ u64 lag_port_partner_admin_cfg[2]; | |
1971 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vxge_vBIT(val, 0, 16) | |
1972 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16) | |
1973 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) \ | |
1974 | vxge_vBIT(val, 32, 16) | |
1975 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) \ | |
1976 | vxge_vBIT(val, 48, 16) | |
1977 | /*0x02140*/ u64 lag_port_partner_admin_state[2]; | |
1978 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY vxge_mBIT(3) | |
1979 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT vxge_mBIT(7) | |
1980 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION vxge_mBIT(11) | |
1981 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION vxge_mBIT(15) | |
1982 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING vxge_mBIT(19) | |
1983 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING vxge_mBIT(23) | |
1984 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED vxge_mBIT(27) | |
1985 | #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED vxge_mBIT(31) | |
1986 | /*0x02150*/ u64 lag_port_to_aggr[2]; | |
1987 | #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vxge_vBIT(val, 0, 16) | |
1988 | #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID vxge_mBIT(19) | |
1989 | /*0x02160*/ u64 lag_port_actor_oper_key[2]; | |
1990 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vxge_vBIT(val, 0, 16) | |
1991 | /*0x02170*/ u64 lag_port_actor_oper_state[2]; | |
1992 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) | |
1993 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) | |
1994 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) | |
1995 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION vxge_mBIT(15) | |
1996 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) | |
1997 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) | |
1998 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) | |
1999 | #define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) | |
2000 | /*0x02180*/ u64 lag_port_partner_oper_sys_id[2]; | |
2001 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) \ | |
2002 | vxge_vBIT(val, 0, 48) | |
2003 | /*0x02190*/ u64 lag_port_partner_oper_info[2]; | |
2004 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) \ | |
2005 | vxge_vBIT(val, 0, 16) | |
2006 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \ | |
2007 | vxge_vBIT(val, 16, 16) | |
2008 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) \ | |
2009 | vxge_vBIT(val, 32, 16) | |
2010 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) \ | |
2011 | vxge_vBIT(val, 48, 16) | |
2012 | /*0x021a0*/ u64 lag_port_partner_oper_state[2]; | |
2013 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY vxge_mBIT(3) | |
2014 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT vxge_mBIT(7) | |
2015 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION vxge_mBIT(11) | |
2016 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION \ | |
2017 | vxge_mBIT(15) | |
2018 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING vxge_mBIT(19) | |
2019 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING vxge_mBIT(23) | |
2020 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED vxge_mBIT(27) | |
2021 | #define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED vxge_mBIT(31) | |
2022 | /*0x021b0*/ u64 lag_port_state_vars[2]; | |
2023 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY vxge_mBIT(3) | |
2024 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vxge_vBIT(val, 6, 2) | |
2025 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM vxge_mBIT(11) | |
2026 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED vxge_mBIT(15) | |
2027 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED vxge_mBIT(18) | |
2028 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED vxge_mBIT(19) | |
2029 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT vxge_mBIT(23) | |
2030 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN vxge_mBIT(27) | |
2031 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN vxge_mBIT(31) | |
2032 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH \ | |
2033 | vxge_mBIT(32) | |
2034 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH \ | |
2035 | vxge_mBIT(33) | |
2036 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH vxge_mBIT(34) | |
2037 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH vxge_mBIT(35) | |
2038 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vxge_vBIT(val, 37, 3) | |
2039 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) \ | |
2040 | vxge_vBIT(val, 41, 3) | |
2041 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vxge_vBIT(val, 44, 4) | |
2042 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE vxge_mBIT(54) | |
2043 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE vxge_mBIT(55) | |
2044 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val) \ | |
2045 | vxge_vBIT(val, 56, 4) | |
2046 | #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val) \ | |
2047 | vxge_vBIT(val, 60, 4) | |
2048 | /*0x021c0*/ u64 lag_port_timer_cntr[2]; | |
2049 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val) vxge_vBIT(val, 0, 8) | |
2050 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \ | |
2051 | vxge_vBIT(val, 8, 8) | |
2052 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val) vxge_vBIT(val, 16, 8) | |
2053 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vxge_vBIT(val, 24, 8) | |
2054 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val) \ | |
2055 | vxge_vBIT(val, 32, 8) | |
2056 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val) \ | |
2057 | vxge_vBIT(val, 40, 8) | |
2058 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val) \ | |
2059 | vxge_vBIT(val, 48, 8) | |
2060 | #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val) \ | |
2061 | vxge_vBIT(val, 56, 8) | |
2062 | u8 unused02208[0x02700-0x021d0]; | |
2063 | ||
2064 | /*0x02700*/ u64 rtdma_int_status; | |
2065 | #define VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT vxge_mBIT(1) | |
2066 | #define VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT vxge_mBIT(2) | |
2067 | #define VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT vxge_mBIT(4) | |
2068 | #define VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT vxge_mBIT(5) | |
2069 | /*0x02708*/ u64 rtdma_int_mask; | |
2070 | /*0x02710*/ u64 pda_alarm_reg; | |
2071 | #define VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR vxge_mBIT(0) | |
2072 | #define VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR vxge_mBIT(1) | |
2073 | /*0x02718*/ u64 pda_alarm_mask; | |
2074 | /*0x02720*/ u64 pda_alarm_alarm; | |
2075 | /*0x02728*/ u64 pcc_error_reg; | |
2076 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) vxge_mBIT(n) | |
2077 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) vxge_mBIT(n) | |
2078 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n) vxge_mBIT(n) | |
2079 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n) vxge_mBIT(n) | |
2080 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n) vxge_mBIT(n) | |
2081 | #define VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR(n) vxge_mBIT(n) | |
2082 | /*0x02730*/ u64 pcc_error_mask; | |
2083 | /*0x02738*/ u64 pcc_error_alarm; | |
2084 | /*0x02740*/ u64 lso_error_reg; | |
2085 | #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT(n) vxge_mBIT(n) | |
2086 | #define VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n) vxge_mBIT(n) | |
2087 | /*0x02748*/ u64 lso_error_mask; | |
2088 | /*0x02750*/ u64 lso_error_alarm; | |
2089 | /*0x02758*/ u64 sm_error_reg; | |
2090 | #define VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM vxge_mBIT(15) | |
2091 | /*0x02760*/ u64 sm_error_mask; | |
2092 | /*0x02768*/ u64 sm_error_alarm; | |
2093 | ||
2094 | u8 unused027a8[0x027a8-0x02770]; | |
2095 | ||
2096 | /*0x027a8*/ u64 txd_ownership_ctrl; | |
2097 | #define VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP vxge_mBIT(7) | |
2098 | /*0x027b0*/ u64 pcc_cfg; | |
2099 | #define VXGE_HW_PCC_CFG_PCC_ENABLE(n) vxge_mBIT(n) | |
2100 | #define VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N(n) vxge_mBIT(n) | |
2101 | /*0x027b8*/ u64 pcc_control; | |
2102 | #define VXGE_HW_PCC_CONTROL_FE_ENABLE(val) vxge_vBIT(val, 6, 2) | |
2103 | #define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN vxge_mBIT(15) | |
2104 | #define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR vxge_mBIT(31) | |
2105 | /*0x027c0*/ u64 pda_status1; | |
2106 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val) vxge_vBIT(val, 4, 4) | |
2107 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4) | |
2108 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val) vxge_vBIT(val, 20, 4) | |
2109 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val) vxge_vBIT(val, 28, 4) | |
2110 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val) vxge_vBIT(val, 36, 4) | |
2111 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val) vxge_vBIT(val, 44, 4) | |
2112 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val) vxge_vBIT(val, 52, 4) | |
2113 | #define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val) vxge_vBIT(val, 60, 4) | |
2114 | /*0x027c8*/ u64 rtdma_bw_timer; | |
2115 | #define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val) vxge_vBIT(val, 12, 4) | |
2116 | ||
2117 | u8 unused02900[0x02900-0x027d0]; | |
2118 | /*0x02900*/ u64 g3cmct_int_status; | |
2119 | #define VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) | |
2120 | /*0x02908*/ u64 g3cmct_int_mask; | |
2121 | /*0x02910*/ u64 g3cmct_err_reg; | |
2122 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR vxge_mBIT(4) | |
2123 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC vxge_mBIT(5) | |
2124 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC vxge_mBIT(6) | |
2125 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC vxge_mBIT(7) | |
2126 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC vxge_mBIT(29) | |
2127 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC vxge_mBIT(30) | |
2128 | #define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC vxge_mBIT(31) | |
2129 | /*0x02918*/ u64 g3cmct_err_mask; | |
2130 | /*0x02920*/ u64 g3cmct_err_alarm; | |
2131 | u8 unused03000[0x03000-0x02928]; | |
2132 | ||
2133 | /*0x03000*/ u64 mc_int_status; | |
2134 | #define VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT vxge_mBIT(3) | |
2135 | #define VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT vxge_mBIT(7) | |
2136 | #define VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT vxge_mBIT(11) | |
2137 | #define VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT vxge_mBIT(15) | |
2138 | /*0x03008*/ u64 mc_int_mask; | |
2139 | /*0x03010*/ u64 mc_err_reg; | |
2140 | #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A vxge_mBIT(3) | |
2141 | #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B vxge_mBIT(4) | |
2142 | #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR vxge_mBIT(5) | |
2143 | #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 vxge_mBIT(6) | |
2144 | #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 vxge_mBIT(7) | |
2145 | #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A vxge_mBIT(10) | |
2146 | #define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B vxge_mBIT(11) | |
2147 | #define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR vxge_mBIT(12) | |
2148 | #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 vxge_mBIT(13) | |
2149 | #define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 vxge_mBIT(14) | |
2150 | #define VXGE_HW_MC_ERR_REG_MC_SM_ERR vxge_mBIT(15) | |
2151 | /*0x03018*/ u64 mc_err_mask; | |
2152 | /*0x03020*/ u64 mc_err_alarm; | |
2153 | /*0x03028*/ u64 grocrc_alarm_reg; | |
2154 | #define VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR vxge_mBIT(3) | |
2155 | #define VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR vxge_mBIT(7) | |
2156 | /*0x03030*/ u64 grocrc_alarm_mask; | |
2157 | /*0x03038*/ u64 grocrc_alarm_alarm; | |
2158 | u8 unused03100[0x03100-0x03040]; | |
2159 | ||
2160 | /*0x03100*/ u64 rx_thresh_cfg_repl; | |
2161 | #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) | |
2162 | #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) | |
2163 | #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val) vxge_vBIT(val, 16, 8) | |
2164 | #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val) vxge_vBIT(val, 24, 8) | |
2165 | #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val) vxge_vBIT(val, 32, 8) | |
2166 | #define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val) vxge_vBIT(val, 40, 8) | |
2167 | #define VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN vxge_mBIT(62) | |
2168 | #define VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ vxge_mBIT(63) | |
2169 | u8 unused033b8[0x033b8-0x03108]; | |
2170 | ||
2171 | /*0x033b8*/ u64 fbmc_ecc_cfg; | |
2172 | #define VXGE_HW_FBMC_ECC_CFG_ENABLE(val) vxge_vBIT(val, 3, 5) | |
2173 | u8 unused03400[0x03400-0x033c0]; | |
2174 | ||
2175 | /*0x03400*/ u64 pcipif_int_status; | |
2176 | #define VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT vxge_mBIT(3) | |
2177 | #define VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT vxge_mBIT(7) | |
2178 | #define VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT vxge_mBIT(11) | |
2179 | #define VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT vxge_mBIT(15) | |
2180 | #define VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT \ | |
2181 | vxge_mBIT(19) | |
2182 | /*0x03408*/ u64 pcipif_int_mask; | |
2183 | /*0x03410*/ u64 dbecc_err_reg; | |
2184 | #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR vxge_mBIT(3) | |
2185 | #define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR vxge_mBIT(7) | |
2186 | #define VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR vxge_mBIT(11) | |
2187 | #define VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR vxge_mBIT(15) | |
2188 | #define VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR vxge_mBIT(19) | |
2189 | #define VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR vxge_mBIT(23) | |
2190 | /*0x03418*/ u64 dbecc_err_mask; | |
2191 | /*0x03420*/ u64 dbecc_err_alarm; | |
2192 | /*0x03428*/ u64 sbecc_err_reg; | |
2193 | #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR vxge_mBIT(3) | |
2194 | #define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR vxge_mBIT(7) | |
2195 | #define VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR vxge_mBIT(11) | |
2196 | #define VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR vxge_mBIT(15) | |
2197 | #define VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR vxge_mBIT(19) | |
2198 | #define VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR vxge_mBIT(23) | |
2199 | /*0x03430*/ u64 sbecc_err_mask; | |
2200 | /*0x03438*/ u64 sbecc_err_alarm; | |
2201 | /*0x03440*/ u64 general_err_reg; | |
2202 | #define VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG vxge_mBIT(3) | |
2203 | #define VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG vxge_mBIT(7) | |
2204 | #define VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR vxge_mBIT(11) | |
2205 | #define VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE vxge_mBIT(15) | |
2206 | #define VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET vxge_mBIT(19) | |
2207 | #define VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET vxge_mBIT(23) | |
2208 | #define VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP vxge_mBIT(27) | |
2209 | /*0x03448*/ u64 general_err_mask; | |
2210 | /*0x03450*/ u64 general_err_alarm; | |
2211 | /*0x03458*/ u64 srpcim_msg_reg; | |
2212 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT \ | |
2213 | vxge_mBIT(0) | |
2214 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT \ | |
2215 | vxge_mBIT(1) | |
2216 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT \ | |
2217 | vxge_mBIT(2) | |
2218 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT \ | |
2219 | vxge_mBIT(3) | |
2220 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT \ | |
2221 | vxge_mBIT(4) | |
2222 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT \ | |
2223 | vxge_mBIT(5) | |
2224 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT \ | |
2225 | vxge_mBIT(6) | |
2226 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT \ | |
2227 | vxge_mBIT(7) | |
2228 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT \ | |
2229 | vxge_mBIT(8) | |
2230 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT \ | |
2231 | vxge_mBIT(9) | |
2232 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT \ | |
2233 | vxge_mBIT(10) | |
2234 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT \ | |
2235 | vxge_mBIT(11) | |
2236 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT \ | |
2237 | vxge_mBIT(12) | |
2238 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT \ | |
2239 | vxge_mBIT(13) | |
2240 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT \ | |
2241 | vxge_mBIT(14) | |
2242 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT \ | |
2243 | vxge_mBIT(15) | |
2244 | #define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT \ | |
2245 | vxge_mBIT(16) | |
2246 | /*0x03460*/ u64 srpcim_msg_mask; | |
2247 | /*0x03468*/ u64 srpcim_msg_alarm; | |
2248 | u8 unused03600[0x03600-0x03470]; | |
2249 | ||
2250 | /*0x03600*/ u64 gcmg1_int_status; | |
2251 | #define VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT vxge_mBIT(0) | |
2252 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT vxge_mBIT(1) | |
2253 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT vxge_mBIT(2) | |
2254 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT vxge_mBIT(3) | |
2255 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT vxge_mBIT(4) | |
2256 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT vxge_mBIT(5) | |
2257 | #define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT vxge_mBIT(6) | |
2258 | #define VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT vxge_mBIT(7) | |
2259 | #define VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT vxge_mBIT(8) | |
2260 | /*0x03608*/ u64 gcmg1_int_mask; | |
2261 | u8 unused03a00[0x03a00-0x03610]; | |
2262 | ||
2263 | /*0x03a00*/ u64 pcmg1_int_status; | |
2264 | #define VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT vxge_mBIT(0) | |
2265 | #define VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT vxge_mBIT(1) | |
2266 | #define VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT vxge_mBIT(2) | |
2267 | #define VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT vxge_mBIT(3) | |
2268 | /*0x03a08*/ u64 pcmg1_int_mask; | |
2269 | u8 unused04000[0x04000-0x03a10]; | |
2270 | ||
2271 | /*0x04000*/ u64 one_int_status; | |
2272 | #define VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT vxge_mBIT(7) | |
2273 | #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT \ | |
2274 | vxge_mBIT(13) | |
2275 | #define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT \ | |
2276 | vxge_mBIT(14) | |
2277 | #define VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT vxge_mBIT(15) | |
2278 | #define VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT vxge_mBIT(23) | |
2279 | #define VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT vxge_mBIT(31) | |
2280 | #define VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT vxge_mBIT(39) | |
2281 | #define VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT vxge_mBIT(47) | |
2282 | #define VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT vxge_mBIT(55) | |
2283 | /*0x04008*/ u64 one_int_mask; | |
2284 | u8 unused04818[0x04818-0x04010]; | |
2285 | ||
2286 | /*0x04818*/ u64 noa_wct_ctrl; | |
2287 | #define VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM vxge_mBIT(0) | |
2288 | /*0x04820*/ u64 rc_cfg2; | |
2289 | #define VXGE_HW_RC_CFG2_BUFF1_SIZE(val) vxge_vBIT(val, 0, 16) | |
2290 | #define VXGE_HW_RC_CFG2_BUFF2_SIZE(val) vxge_vBIT(val, 16, 16) | |
2291 | #define VXGE_HW_RC_CFG2_BUFF3_SIZE(val) vxge_vBIT(val, 32, 16) | |
2292 | #define VXGE_HW_RC_CFG2_BUFF4_SIZE(val) vxge_vBIT(val, 48, 16) | |
2293 | /*0x04828*/ u64 rc_cfg3; | |
2294 | #define VXGE_HW_RC_CFG3_BUFF5_SIZE(val) vxge_vBIT(val, 0, 16) | |
2295 | /*0x04830*/ u64 rx_multi_cast_ctrl1; | |
2296 | #define VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE vxge_mBIT(7) | |
2297 | #define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vxge_vBIT(val, 11, 5) | |
2298 | /*0x04838*/ u64 rxdm_dbg_rd; | |
2299 | #define VXGE_HW_RXDM_DBG_RD_ADDR(val) vxge_vBIT(val, 0, 12) | |
2300 | #define VXGE_HW_RXDM_DBG_RD_ENABLE vxge_mBIT(31) | |
2301 | /*0x04840*/ u64 rxdm_dbg_rd_data; | |
2302 | #define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vxge_vBIT(val, 0, 64) | |
2303 | /*0x04848*/ u64 rqa_top_prty_for_vh[17]; | |
2304 | #define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ | |
2305 | vxge_vBIT(val, 59, 5) | |
2306 | u8 unused04900[0x04900-0x048d0]; | |
2307 | ||
2308 | /*0x04900*/ u64 tim_status; | |
2309 | #define VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS vxge_mBIT(0) | |
2310 | /*0x04908*/ u64 tim_ecc_enable; | |
2311 | #define VXGE_HW_TIM_ECC_ENABLE_VBLS_N vxge_mBIT(7) | |
2312 | #define VXGE_HW_TIM_ECC_ENABLE_BMAP_N vxge_mBIT(15) | |
2313 | #define VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N vxge_mBIT(23) | |
2314 | /*0x04910*/ u64 tim_bp_ctrl; | |
2315 | #define VXGE_HW_TIM_BP_CTRL_RD_XON vxge_mBIT(7) | |
2316 | #define VXGE_HW_TIM_BP_CTRL_WR_XON vxge_mBIT(15) | |
2317 | #define VXGE_HW_TIM_BP_CTRL_ROCRC_BYP vxge_mBIT(23) | |
2318 | /*0x04918*/ u64 tim_resource_assignment_vh[17]; | |
2319 | #define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) | |
2320 | /*0x049a0*/ u64 tim_bmap_mapping_vp_err[17]; | |
2321 | #define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vxge_vBIT(val, 3, 5) | |
2322 | u8 unused04b00[0x04b00-0x04a28]; | |
2323 | ||
2324 | /*0x04b00*/ u64 gcmg2_int_status; | |
2325 | #define VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT vxge_mBIT(7) | |
2326 | #define VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT vxge_mBIT(15) | |
2327 | #define VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT vxge_mBIT(23) | |
2328 | /*0x04b08*/ u64 gcmg2_int_mask; | |
2329 | /*0x04b10*/ u64 gxtmc_err_reg; | |
2330 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vxge_vBIT(val, 0, 4) | |
2331 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vxge_vBIT(val, 4, 4) | |
2332 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR vxge_mBIT(8) | |
2333 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(9) | |
2334 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(10) | |
2335 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(11) | |
2336 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(12) | |
2337 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR vxge_mBIT(13) | |
2338 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR vxge_mBIT(14) | |
2339 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR vxge_mBIT(15) | |
2340 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR vxge_mBIT(16) | |
2341 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR vxge_mBIT(17) | |
2342 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR vxge_mBIT(18) | |
2343 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR vxge_mBIT(19) | |
2344 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR vxge_mBIT(20) | |
2345 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW \ | |
2346 | vxge_mBIT(21) | |
2347 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW \ | |
2348 | vxge_mBIT(22) | |
2349 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR vxge_mBIT(23) | |
2350 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW \ | |
2351 | vxge_mBIT(24) | |
2352 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW \ | |
2353 | vxge_mBIT(25) | |
2354 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR vxge_mBIT(26) | |
2355 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR vxge_mBIT(27) | |
2356 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR vxge_mBIT(28) | |
2357 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR vxge_mBIT(29) | |
2358 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR vxge_mBIT(30) | |
2359 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR vxge_mBIT(31) | |
2360 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR vxge_mBIT(32) | |
2361 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR vxge_mBIT(33) | |
2362 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR vxge_mBIT(34) | |
2363 | #define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR vxge_mBIT(35) | |
2364 | /*0x04b18*/ u64 gxtmc_err_mask; | |
2365 | /*0x04b20*/ u64 gxtmc_err_alarm; | |
2366 | /*0x04b28*/ u64 cmc_err_reg; | |
2367 | #define VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR vxge_mBIT(0) | |
2368 | /*0x04b30*/ u64 cmc_err_mask; | |
2369 | /*0x04b38*/ u64 cmc_err_alarm; | |
2370 | /*0x04b40*/ u64 gcp_err_reg; | |
2371 | #define VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(0) | |
2372 | #define VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(1) | |
2373 | #define VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(2) | |
2374 | #define VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(3) | |
2375 | /*0x04b48*/ u64 gcp_err_mask; | |
2376 | /*0x04b50*/ u64 gcp_err_alarm; | |
2377 | u8 unused04f00[0x04f00-0x04b58]; | |
2378 | ||
2379 | /*0x04f00*/ u64 pcmg2_int_status; | |
2380 | #define VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT vxge_mBIT(7) | |
2381 | #define VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT vxge_mBIT(15) | |
2382 | #define VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT vxge_mBIT(23) | |
2383 | /*0x04f08*/ u64 pcmg2_int_mask; | |
2384 | /*0x04f10*/ u64 pxtmc_err_reg; | |
2385 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vxge_vBIT(val, 0, 2) | |
2386 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR vxge_mBIT(2) | |
2387 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR vxge_mBIT(3) | |
2388 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR vxge_mBIT(4) | |
2389 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR vxge_mBIT(5) | |
2390 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR vxge_mBIT(6) | |
2391 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR vxge_mBIT(7) | |
2392 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR vxge_mBIT(8) | |
2393 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR vxge_mBIT(9) | |
2394 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR vxge_mBIT(10) | |
2395 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR vxge_mBIT(11) | |
2396 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR vxge_mBIT(12) | |
2397 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR vxge_mBIT(13) | |
2398 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR vxge_mBIT(14) | |
2399 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR vxge_mBIT(15) | |
2400 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR vxge_mBIT(16) | |
2401 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR vxge_mBIT(17) | |
2402 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR vxge_mBIT(18) | |
2403 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR vxge_mBIT(19) | |
2404 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR vxge_mBIT(20) | |
2405 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR vxge_mBIT(21) | |
2406 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR vxge_mBIT(22) | |
2407 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR vxge_mBIT(23) | |
2408 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR vxge_mBIT(24) | |
2409 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR vxge_mBIT(25) | |
2410 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR vxge_mBIT(26) | |
2411 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR vxge_mBIT(27) | |
2412 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR vxge_mBIT(28) | |
2413 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR vxge_mBIT(29) | |
2414 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR vxge_mBIT(30) | |
2415 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR vxge_mBIT(31) | |
2416 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR vxge_mBIT(32) | |
2417 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR vxge_mBIT(33) | |
2418 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR vxge_mBIT(34) | |
2419 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR vxge_mBIT(35) | |
2420 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR vxge_mBIT(36) | |
2421 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR vxge_mBIT(37) | |
2422 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR vxge_mBIT(38) | |
2423 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR vxge_mBIT(39) | |
2424 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR vxge_mBIT(40) | |
2425 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR vxge_mBIT(41) | |
2426 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR vxge_mBIT(42) | |
2427 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR vxge_mBIT(43) | |
2428 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR vxge_mBIT(44) | |
2429 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR vxge_mBIT(45) | |
2430 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR vxge_mBIT(46) | |
2431 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR vxge_mBIT(47) | |
2432 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR vxge_mBIT(48) | |
2433 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR vxge_mBIT(49) | |
2434 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR vxge_mBIT(50) | |
2435 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR vxge_mBIT(51) | |
2436 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR vxge_mBIT(52) | |
2437 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR vxge_mBIT(53) | |
2438 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vxge_vBIT(val, 54, 2) | |
2439 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR vxge_mBIT(56) | |
2440 | #define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR vxge_mBIT(57) | |
2441 | /*0x04f18*/ u64 pxtmc_err_mask; | |
2442 | /*0x04f20*/ u64 pxtmc_err_alarm; | |
2443 | /*0x04f28*/ u64 cp_err_reg; | |
2444 | #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vxge_vBIT(val, 0, 8) | |
2445 | #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vxge_vBIT(val, 8, 2) | |
2446 | #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR vxge_mBIT(10) | |
2447 | #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR vxge_mBIT(11) | |
2448 | #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR vxge_mBIT(12) | |
2449 | #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR vxge_mBIT(13) | |
2450 | #define VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR vxge_mBIT(14) | |
2451 | #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR vxge_mBIT(15) | |
2452 | #define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vxge_vBIT(val, 16, 2) | |
2453 | #define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vxge_vBIT(val, 24, 8) | |
2454 | #define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vxge_vBIT(val, 32, 2) | |
2455 | #define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR vxge_mBIT(34) | |
2456 | #define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR vxge_mBIT(35) | |
2457 | #define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR vxge_mBIT(36) | |
2458 | #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR vxge_mBIT(37) | |
2459 | #define VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR vxge_mBIT(38) | |
2460 | #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR vxge_mBIT(39) | |
2461 | #define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vxge_vBIT(val, 40, 2) | |
2462 | #define VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR vxge_mBIT(48) | |
2463 | #define VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR vxge_mBIT(49) | |
2464 | #define VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR vxge_mBIT(50) | |
2465 | #define VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR vxge_mBIT(51) | |
2466 | #define VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR vxge_mBIT(52) | |
2467 | #define VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR vxge_mBIT(53) | |
2468 | #define VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR vxge_mBIT(54) | |
2469 | #define VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR vxge_mBIT(55) | |
2470 | #define VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR vxge_mBIT(56) | |
2471 | #define VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR vxge_mBIT(57) | |
2472 | #define VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(60) | |
2473 | #define VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(61) | |
2474 | #define VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR vxge_mBIT(62) | |
2475 | #define VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR vxge_mBIT(63) | |
2476 | /*0x04f30*/ u64 cp_err_mask; | |
2477 | /*0x04f38*/ u64 cp_err_alarm; | |
2478 | u8 unused04fe8[0x04f50-0x04f40]; | |
2479 | ||
2480 | /*0x04f50*/ u64 cp_exc_reg; | |
2481 | #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT vxge_mBIT(47) | |
2482 | #define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT vxge_mBIT(55) | |
2483 | #define VXGE_HW_CP_EXC_REG_CP_CP_SERR vxge_mBIT(63) | |
2484 | /*0x04f58*/ u64 cp_exc_mask; | |
2485 | /*0x04f60*/ u64 cp_exc_alarm; | |
2486 | /*0x04f68*/ u64 cp_exc_cause; | |
2487 | #define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val) vxge_vBIT(val, 32, 32) | |
2488 | u8 unused05200[0x05200-0x04f70]; | |
2489 | ||
2490 | /*0x05200*/ u64 msg_int_status; | |
2491 | #define VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT vxge_mBIT(7) | |
2492 | #define VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT vxge_mBIT(60) | |
2493 | #define VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT vxge_mBIT(61) | |
2494 | #define VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT vxge_mBIT(62) | |
2495 | #define VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT vxge_mBIT(63) | |
2496 | /*0x05208*/ u64 msg_int_mask; | |
2497 | /*0x05210*/ u64 tim_err_reg; | |
2498 | #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR vxge_mBIT(4) | |
2499 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR vxge_mBIT(5) | |
2500 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR vxge_mBIT(6) | |
2501 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR vxge_mBIT(7) | |
2502 | #define VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR vxge_mBIT(12) | |
2503 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR vxge_mBIT(13) | |
2504 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR vxge_mBIT(14) | |
2505 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR vxge_mBIT(15) | |
2506 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR vxge_mBIT(18) | |
2507 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR vxge_mBIT(19) | |
2508 | #define VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR vxge_mBIT(20) | |
2509 | #define VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR vxge_mBIT(22) | |
2510 | #define VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR vxge_mBIT(23) | |
2511 | #define VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH vxge_mBIT(46) | |
2512 | #define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) vxge_mBIT(n) | |
2513 | /*0x05218*/ u64 tim_err_mask; | |
2514 | /*0x05220*/ u64 tim_err_alarm; | |
2515 | /*0x05228*/ u64 msg_err_reg; | |
2516 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(0) | |
2517 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR vxge_mBIT(1) | |
2518 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR \ | |
2519 | vxge_mBIT(2) | |
2520 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR \ | |
2521 | vxge_mBIT(3) | |
2522 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR vxge_mBIT(4) | |
2523 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR vxge_mBIT(5) | |
2524 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(6) | |
2525 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR vxge_mBIT(7) | |
2526 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR vxge_mBIT(8) | |
2527 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR vxge_mBIT(10) | |
2528 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR vxge_mBIT(12) | |
2529 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR vxge_mBIT(14) | |
2530 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR vxge_mBIT(16) | |
2531 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR vxge_mBIT(17) | |
2532 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR vxge_mBIT(18) | |
2533 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR vxge_mBIT(19) | |
2534 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR vxge_mBIT(20) | |
2535 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR vxge_mBIT(21) | |
2536 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR vxge_mBIT(26) | |
2537 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR vxge_mBIT(27) | |
2538 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR vxge_mBIT(29) | |
2539 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR vxge_mBIT(31) | |
2540 | #define VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR vxge_mBIT(33) | |
2541 | #define VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR vxge_mBIT(34) | |
2542 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR vxge_mBIT(35) | |
2543 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR \ | |
2544 | vxge_mBIT(36) | |
2545 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR vxge_mBIT(38) | |
2546 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR vxge_mBIT(39) | |
2547 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR vxge_mBIT(41) | |
2548 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR vxge_mBIT(43) | |
2549 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR vxge_mBIT(45) | |
2550 | #define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR vxge_mBIT(47) | |
2551 | #define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR vxge_mBIT(48) | |
2552 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR vxge_mBIT(49) | |
2553 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR vxge_mBIT(50) | |
2554 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR vxge_mBIT(51) | |
2555 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR vxge_mBIT(52) | |
2556 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR vxge_mBIT(53) | |
2557 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR vxge_mBIT(54) | |
2558 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR vxge_mBIT(55) | |
2559 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR vxge_mBIT(56) | |
2560 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR vxge_mBIT(57) | |
2561 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR vxge_mBIT(58) | |
2562 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR vxge_mBIT(59) | |
2563 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR vxge_mBIT(60) | |
2564 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR vxge_mBIT(61) | |
2565 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR vxge_mBIT(62) | |
2566 | #define VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR vxge_mBIT(63) | |
2567 | /*0x05230*/ u64 msg_err_mask; | |
2568 | /*0x05238*/ u64 msg_err_alarm; | |
2569 | u8 unused05340[0x05340-0x05240]; | |
2570 | ||
2571 | /*0x05340*/ u64 msg_exc_reg; | |
2572 | #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT vxge_mBIT(50) | |
2573 | #define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT vxge_mBIT(51) | |
2574 | #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT vxge_mBIT(54) | |
2575 | #define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT vxge_mBIT(55) | |
2576 | #define VXGE_HW_MSG_EXC_REG_MP_MXP_SERR vxge_mBIT(62) | |
2577 | #define VXGE_HW_MSG_EXC_REG_UP_UXP_SERR vxge_mBIT(63) | |
2578 | /*0x05348*/ u64 msg_exc_mask; | |
2579 | /*0x05350*/ u64 msg_exc_alarm; | |
2580 | /*0x05358*/ u64 msg_exc_cause; | |
2581 | #define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val) vxge_vBIT(val, 0, 32) | |
2582 | #define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val) vxge_vBIT(val, 32, 32) | |
2583 | u8 unused05368[0x05380-0x05360]; | |
2584 | ||
2585 | /*0x05380*/ u64 msg_err2_reg; | |
2586 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR \ | |
2587 | vxge_mBIT(0) | |
2588 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR \ | |
2589 | vxge_mBIT(1) | |
2590 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR \ | |
2591 | vxge_mBIT(2) | |
2592 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR \ | |
2593 | vxge_mBIT(3) | |
2594 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR vxge_mBIT(4) | |
2595 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR \ | |
2596 | vxge_mBIT(5) | |
2597 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR vxge_mBIT(6) | |
2598 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(7) | |
2599 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR vxge_mBIT(8) | |
2600 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR vxge_mBIT(9) | |
2601 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR vxge_mBIT(10) | |
2602 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR vxge_mBIT(11) | |
2603 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR \ | |
2604 | vxge_mBIT(12) | |
2605 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR \ | |
2606 | vxge_mBIT(13) | |
2607 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR \ | |
2608 | vxge_mBIT(14) | |
2609 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR \ | |
2610 | vxge_mBIT(15) | |
2611 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR \ | |
2612 | vxge_mBIT(16) | |
2613 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR \ | |
2614 | vxge_mBIT(17) | |
2615 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR \ | |
2616 | vxge_mBIT(18) | |
2617 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR \ | |
2618 | vxge_mBIT(19) | |
2619 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR \ | |
2620 | vxge_mBIT(20) | |
2621 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR \ | |
2622 | vxge_mBIT(21) | |
2623 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR \ | |
2624 | vxge_mBIT(22) | |
2625 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR \ | |
2626 | vxge_mBIT(23) | |
2627 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR \ | |
2628 | vxge_mBIT(24) | |
2629 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR \ | |
2630 | vxge_mBIT(25) | |
2631 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR \ | |
2632 | vxge_mBIT(26) | |
2633 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR \ | |
2634 | vxge_mBIT(27) | |
2635 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR \ | |
2636 | vxge_mBIT(28) | |
2637 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR vxge_mBIT(29) | |
2638 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ | |
2639 | vxge_mBIT(30) | |
2640 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ | |
2641 | vxge_mBIT(31) | |
2642 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR \ | |
2643 | vxge_mBIT(32) | |
2644 | #define VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(33) | |
2645 | #define VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR vxge_mBIT(34) | |
2646 | #define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR vxge_mBIT(62) | |
2647 | #define VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR vxge_mBIT(63) | |
2648 | /*0x05388*/ u64 msg_err2_mask; | |
2649 | /*0x05390*/ u64 msg_err2_alarm; | |
2650 | /*0x05398*/ u64 msg_err3_reg; | |
2651 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0 vxge_mBIT(0) | |
2652 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1 vxge_mBIT(1) | |
2653 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2 vxge_mBIT(2) | |
2654 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3 vxge_mBIT(3) | |
2655 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4 vxge_mBIT(4) | |
2656 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5 vxge_mBIT(5) | |
2657 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6 vxge_mBIT(6) | |
2658 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7 vxge_mBIT(7) | |
2659 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0 vxge_mBIT(8) | |
2660 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1 vxge_mBIT(9) | |
2661 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0 vxge_mBIT(16) | |
2662 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1 vxge_mBIT(17) | |
2663 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2 vxge_mBIT(18) | |
2664 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3 vxge_mBIT(19) | |
2665 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4 vxge_mBIT(20) | |
2666 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5 vxge_mBIT(21) | |
2667 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6 vxge_mBIT(22) | |
2668 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7 vxge_mBIT(23) | |
2669 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0 vxge_mBIT(24) | |
2670 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1 vxge_mBIT(25) | |
2671 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 vxge_mBIT(32) | |
2672 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 vxge_mBIT(33) | |
2673 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 vxge_mBIT(34) | |
2674 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 vxge_mBIT(35) | |
2675 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 vxge_mBIT(36) | |
2676 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 vxge_mBIT(37) | |
2677 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 vxge_mBIT(38) | |
2678 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 vxge_mBIT(39) | |
2679 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 vxge_mBIT(40) | |
2680 | #define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 vxge_mBIT(41) | |
2681 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 vxge_mBIT(48) | |
2682 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 vxge_mBIT(49) | |
2683 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 vxge_mBIT(50) | |
2684 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 vxge_mBIT(51) | |
2685 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 vxge_mBIT(52) | |
2686 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 vxge_mBIT(53) | |
2687 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 vxge_mBIT(54) | |
2688 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 vxge_mBIT(55) | |
2689 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 vxge_mBIT(56) | |
2690 | #define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1 vxge_mBIT(57) | |
2691 | /*0x053a0*/ u64 msg_err3_mask; | |
2692 | /*0x053a8*/ u64 msg_err3_alarm; | |
2693 | u8 unused05600[0x05600-0x053b0]; | |
2694 | ||
2695 | /*0x05600*/ u64 fau_gen_err_reg; | |
2696 | #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP vxge_mBIT(3) | |
2697 | #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP vxge_mBIT(7) | |
2698 | #define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP vxge_mBIT(11) | |
2699 | #define VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION vxge_mBIT(15) | |
2700 | /*0x05608*/ u64 fau_gen_err_mask; | |
2701 | /*0x05610*/ u64 fau_gen_err_alarm; | |
2702 | /*0x05618*/ u64 fau_ecc_err_reg; | |
2703 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR vxge_mBIT(0) | |
2704 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR vxge_mBIT(1) | |
2705 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val) \ | |
2706 | vxge_vBIT(val, 2, 2) | |
2707 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val) \ | |
2708 | vxge_vBIT(val, 4, 2) | |
2709 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR vxge_mBIT(6) | |
2710 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR vxge_mBIT(7) | |
2711 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val) \ | |
2712 | vxge_vBIT(val, 8, 2) | |
2713 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val) \ | |
2714 | vxge_vBIT(val, 10, 2) | |
2715 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR vxge_mBIT(12) | |
2716 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR vxge_mBIT(13) | |
2717 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val) \ | |
2718 | vxge_vBIT(val, 14, 2) | |
2719 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val) \ | |
2720 | vxge_vBIT(val, 16, 2) | |
2721 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) \ | |
2722 | vxge_vBIT(val, 18, 2) | |
2723 | #define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) \ | |
2724 | vxge_vBIT(val, 20, 2) | |
2725 | #define VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR vxge_mBIT(31) | |
2726 | /*0x05620*/ u64 fau_ecc_err_mask; | |
2727 | /*0x05628*/ u64 fau_ecc_err_alarm; | |
2728 | u8 unused05658[0x05658-0x05630]; | |
2729 | /*0x05658*/ u64 fau_pa_cfg; | |
2730 | #define VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM vxge_mBIT(3) | |
2731 | #define VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF vxge_mBIT(7) | |
2732 | #define VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM vxge_mBIT(11) | |
2733 | u8 unused05668[0x05668-0x05660]; | |
2734 | ||
2735 | /*0x05668*/ u64 dbg_stats_fau_rx_path; | |
2736 | #define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) \ | |
2737 | vxge_vBIT(val, 32, 32) | |
2738 | u8 unused056c0[0x056c0-0x05670]; | |
2739 | ||
2740 | /*0x056c0*/ u64 fau_lag_cfg; | |
2741 | #define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val) vxge_vBIT(val, 2, 2) | |
2742 | #define VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS vxge_mBIT(7) | |
2743 | u8 unused05800[0x05800-0x056c8]; | |
2744 | ||
2745 | /*0x05800*/ u64 tpa_int_status; | |
2746 | #define VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT vxge_mBIT(15) | |
2747 | #define VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT vxge_mBIT(23) | |
2748 | #define VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT vxge_mBIT(31) | |
2749 | /*0x05808*/ u64 tpa_int_mask; | |
2750 | /*0x05810*/ u64 orp_err_reg; | |
2751 | #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR vxge_mBIT(3) | |
2752 | #define VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR vxge_mBIT(7) | |
2753 | #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR vxge_mBIT(11) | |
2754 | #define VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR vxge_mBIT(15) | |
2755 | #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR vxge_mBIT(19) | |
2756 | #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR vxge_mBIT(23) | |
2757 | #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR vxge_mBIT(27) | |
2758 | #define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR vxge_mBIT(31) | |
2759 | #define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR vxge_mBIT(35) | |
2760 | #define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR vxge_mBIT(39) | |
2761 | #define VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR vxge_mBIT(43) | |
2762 | #define VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR vxge_mBIT(47) | |
2763 | /*0x05818*/ u64 orp_err_mask; | |
2764 | /*0x05820*/ u64 orp_err_alarm; | |
2765 | /*0x05828*/ u64 ptm_alarm_reg; | |
2766 | #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR vxge_mBIT(3) | |
2767 | #define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR vxge_mBIT(7) | |
2768 | #define VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR vxge_mBIT(11) | |
2769 | #define VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR vxge_mBIT(15) | |
2770 | #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vxge_vBIT(val, 18, 2) | |
2771 | #define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vxge_vBIT(val, 22, 2) | |
2772 | /*0x05830*/ u64 ptm_alarm_mask; | |
2773 | /*0x05838*/ u64 ptm_alarm_alarm; | |
2774 | /*0x05840*/ u64 tpa_error_reg; | |
2775 | #define VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM vxge_mBIT(3) | |
2776 | #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR vxge_mBIT(7) | |
2777 | #define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR vxge_mBIT(11) | |
2778 | /*0x05848*/ u64 tpa_error_mask; | |
2779 | /*0x05850*/ u64 tpa_error_alarm; | |
2780 | /*0x05858*/ u64 tpa_global_cfg; | |
2781 | #define VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N vxge_mBIT(7) | |
2782 | #define VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N vxge_mBIT(35) | |
2783 | u8 unused05868[0x05870-0x05860]; | |
2784 | ||
2785 | /*0x05870*/ u64 ptm_ecc_cfg; | |
2786 | #define VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N vxge_mBIT(3) | |
2787 | /*0x05878*/ u64 ptm_phase_cfg; | |
2788 | #define VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN vxge_mBIT(3) | |
2789 | #define VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN vxge_mBIT(7) | |
2790 | u8 unused05898[0x05898-0x05880]; | |
2791 | ||
2792 | /*0x05898*/ u64 dbg_stats_tpa_tx_path; | |
2793 | #define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) \ | |
2794 | vxge_vBIT(val, 32, 32) | |
2795 | u8 unused05900[0x05900-0x058a0]; | |
2796 | ||
2797 | /*0x05900*/ u64 tmac_int_status; | |
2798 | #define VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT vxge_mBIT(3) | |
2799 | #define VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT vxge_mBIT(7) | |
2800 | /*0x05908*/ u64 tmac_int_mask; | |
2801 | /*0x05910*/ u64 txmac_gen_err_reg; | |
2802 | #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP vxge_mBIT(3) | |
2803 | #define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT vxge_mBIT(7) | |
2804 | /*0x05918*/ u64 txmac_gen_err_mask; | |
2805 | /*0x05920*/ u64 txmac_gen_err_alarm; | |
2806 | /*0x05928*/ u64 txmac_ecc_err_reg; | |
2807 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR vxge_mBIT(3) | |
2808 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR vxge_mBIT(7) | |
2809 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR vxge_mBIT(11) | |
2810 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR vxge_mBIT(15) | |
2811 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR vxge_mBIT(19) | |
2812 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR vxge_mBIT(23) | |
2813 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR vxge_mBIT(27) | |
2814 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR vxge_mBIT(31) | |
2815 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR vxge_mBIT(35) | |
2816 | #define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR vxge_mBIT(39) | |
2817 | /*0x05930*/ u64 txmac_ecc_err_mask; | |
2818 | /*0x05938*/ u64 txmac_ecc_err_alarm; | |
2819 | u8 unused05978[0x05978-0x05940]; | |
2820 | ||
2821 | /*0x05978*/ u64 dbg_stat_tx_any_frms; | |
2822 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vxge_vBIT(val, 0, 8) | |
2823 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) | |
2824 | #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) \ | |
2825 | vxge_vBIT(val, 16, 8) | |
2826 | u8 unused059a0[0x059a0-0x05980]; | |
2827 | ||
2828 | /*0x059a0*/ u64 txmac_link_util_port[3]; | |
2829 | #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) \ | |
2830 | vxge_vBIT(val, 1, 7) | |
2831 | #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) | |
2832 | #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) \ | |
2833 | vxge_vBIT(val, 12, 4) | |
2834 | #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vxge_vBIT(val, 16, 4) | |
2835 | #define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR vxge_mBIT(23) | |
2836 | /*0x059b8*/ u64 txmac_cfg0_port[3]; | |
2837 | #define VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN vxge_mBIT(3) | |
2838 | #define VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD vxge_mBIT(7) | |
2839 | #define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val) vxge_vBIT(val, 8, 8) | |
2840 | /*0x059d0*/ u64 txmac_cfg1_port[3]; | |
2841 | #define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val) vxge_vBIT(val, 40, 8) | |
2842 | /*0x059e8*/ u64 txmac_status_port[3]; | |
2843 | #define VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT vxge_mBIT(3) | |
2844 | u8 unused05a20[0x05a20-0x05a00]; | |
2845 | ||
2846 | /*0x05a20*/ u64 lag_distrib_dest; | |
2847 | #define VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH(n) vxge_mBIT(n) | |
2848 | /*0x05a28*/ u64 lag_marker_cfg; | |
2849 | #define VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN vxge_mBIT(3) | |
2850 | #define VXGE_HW_LAG_MARKER_CFG_RESP_EN vxge_mBIT(7) | |
2851 | #define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val) vxge_vBIT(val, 16, 16) | |
2852 | #define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val) \ | |
2853 | vxge_vBIT(val, 32, 16) | |
2854 | #define VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP vxge_mBIT(51) | |
2855 | /*0x05a30*/ u64 lag_tx_cfg; | |
2856 | #define VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS vxge_mBIT(3) | |
2857 | #define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vxge_vBIT(val, 6, 2) | |
2858 | #define VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL vxge_mBIT(11) | |
2859 | #define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val) vxge_vBIT(val, 16, 16) | |
2860 | /*0x05a38*/ u64 lag_tx_status; | |
2861 | #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) \ | |
2862 | vxge_vBIT(val, 0, 8) | |
2863 | #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val) \ | |
2864 | vxge_vBIT(val, 8, 8) | |
2865 | #define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val) \ | |
2866 | vxge_vBIT(val, 16, 8) | |
2867 | u8 unused05d48[0x05d48-0x05a40]; | |
2868 | ||
2869 | /*0x05d48*/ u64 srpcim_to_mrpcim_vplane_rmsg[17]; | |
2870 | #define \ | |
2871 | VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)\ | |
2872 | vxge_vBIT(val, 0, 64) | |
2873 | u8 unused06420[0x06420-0x05dd0]; | |
2874 | ||
2875 | /*0x06420*/ u64 mrpcim_to_srpcim_vplane_wmsg[17]; | |
2876 | #define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val) \ | |
2877 | vxge_vBIT(val, 0, 64) | |
2878 | /*0x064a8*/ u64 mrpcim_to_srpcim_vplane_wmsg_trig[17]; | |
2879 | ||
2880 | /*0x06530*/ u64 debug_stats0; | |
2881 | #define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val) vxge_vBIT(val, 0, 32) | |
2882 | #define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val) vxge_vBIT(val, 32, 32) | |
2883 | /*0x06538*/ u64 debug_stats1; | |
2884 | #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val) vxge_vBIT(val, 0, 32) | |
2885 | #define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val) vxge_vBIT(val, 32, 32) | |
2886 | /*0x06540*/ u64 debug_stats2; | |
2887 | #define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val) vxge_vBIT(val, 0, 32) | |
2888 | /*0x06548*/ u64 debug_stats3_vplane[17]; | |
2889 | #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val) vxge_vBIT(val, 0, 16) | |
2890 | #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vxge_vBIT(val, 16, 16) | |
2891 | #define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vxge_vBIT(val, 32, 16) | |
2892 | /*0x065d0*/ u64 debug_stats4_vplane[17]; | |
2893 | #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val) vxge_vBIT(val, 0, 16) | |
2894 | #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vxge_vBIT(val, 16, 16) | |
2895 | #define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vxge_vBIT(val, 32, 16) | |
2896 | ||
2897 | u8 unused07000[0x07000-0x06658]; | |
2898 | ||
2899 | /*0x07000*/ u64 mrpcim_general_int_status; | |
2900 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(0) | |
2901 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(1) | |
2902 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT vxge_mBIT(2) | |
2903 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(3) | |
2904 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT vxge_mBIT(4) | |
2905 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT vxge_mBIT(5) | |
2906 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT vxge_mBIT(6) | |
2907 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT vxge_mBIT(7) | |
2908 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT vxge_mBIT(8) | |
2909 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT vxge_mBIT(9) | |
2910 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT vxge_mBIT(10) | |
2911 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT vxge_mBIT(11) | |
2912 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT vxge_mBIT(12) | |
2913 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(13) | |
2914 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT vxge_mBIT(14) | |
2915 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT vxge_mBIT(15) | |
2916 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT vxge_mBIT(16) | |
2917 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT vxge_mBIT(17) | |
2918 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT vxge_mBIT(18) | |
2919 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT vxge_mBIT(19) | |
2920 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT vxge_mBIT(20) | |
2921 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT vxge_mBIT(21) | |
2922 | #define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT vxge_mBIT(22) | |
2923 | /*0x07008*/ u64 mrpcim_general_int_mask; | |
2924 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT vxge_mBIT(0) | |
2925 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT vxge_mBIT(1) | |
2926 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT vxge_mBIT(2) | |
2927 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(3) | |
2928 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT vxge_mBIT(4) | |
2929 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT vxge_mBIT(5) | |
2930 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT vxge_mBIT(6) | |
2931 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT vxge_mBIT(7) | |
2932 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT vxge_mBIT(8) | |
2933 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT vxge_mBIT(9) | |
2934 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT vxge_mBIT(10) | |
2935 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT vxge_mBIT(11) | |
2936 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT vxge_mBIT(12) | |
2937 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(13) | |
2938 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT vxge_mBIT(14) | |
2939 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT vxge_mBIT(15) | |
2940 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT vxge_mBIT(16) | |
2941 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_FBMC_INT vxge_mBIT(17) | |
2942 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT vxge_mBIT(18) | |
2943 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TPA_INT vxge_mBIT(19) | |
2944 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_DRBELL_INT vxge_mBIT(20) | |
2945 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_ONE_INT vxge_mBIT(21) | |
2946 | #define VXGE_HW_MRPCIM_GENERAL_INT_MASK_MSG_INT vxge_mBIT(22) | |
2947 | /*0x07010*/ u64 mrpcim_ppif_int_status; | |
2948 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT vxge_mBIT(3) | |
2949 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT vxge_mBIT(7) | |
2950 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT vxge_mBIT(11) | |
2951 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT vxge_mBIT(15) | |
2952 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT vxge_mBIT(19) | |
2953 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT vxge_mBIT(27) | |
2954 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\ | |
2955 | vxge_mBIT(31) | |
2956 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\ | |
2957 | vxge_mBIT(32) | |
2958 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\ | |
2959 | vxge_mBIT(33) | |
2960 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\ | |
2961 | vxge_mBIT(34) | |
2962 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\ | |
2963 | vxge_mBIT(35) | |
2964 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\ | |
2965 | vxge_mBIT(36) | |
2966 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\ | |
2967 | vxge_mBIT(37) | |
2968 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\ | |
2969 | vxge_mBIT(38) | |
2970 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\ | |
2971 | vxge_mBIT(39) | |
2972 | #define VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\ | |
2973 | vxge_mBIT(40) | |
2974 | #define \ | |
2975 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT \ | |
2976 | vxge_mBIT(41) | |
2977 | #define \ | |
2978 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT \ | |
2979 | vxge_mBIT(42) | |
2980 | #define \ | |
2981 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT \ | |
2982 | vxge_mBIT(43) | |
2983 | #define \ | |
2984 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT \ | |
2985 | vxge_mBIT(44) | |
2986 | #define \ | |
2987 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT \ | |
2988 | vxge_mBIT(45) | |
2989 | #define \ | |
2990 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT \ | |
2991 | vxge_mBIT(46) | |
2992 | #define \ | |
2993 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT \ | |
2994 | vxge_mBIT(47) | |
2995 | #define \ | |
2996 | VXGE_HW_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_VPATH_TO_MRPCIM_ALARM_INT \ | |
2997 | vxge_mBIT(55) | |
2998 | /*0x07018*/ u64 mrpcim_ppif_int_mask; | |
2999 | u8 unused07028[0x07028-0x07020]; | |
3000 | ||
3001 | /*0x07028*/ u64 ini_errors_reg; | |
3002 | #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG vxge_mBIT(3) | |
3003 | #define VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT vxge_mBIT(7) | |
3004 | #define VXGE_HW_INI_ERRORS_REG_DCPL_FSM_ERR vxge_mBIT(11) | |
3005 | #define VXGE_HW_INI_ERRORS_REG_DCPL_POISON vxge_mBIT(12) | |
3006 | #define VXGE_HW_INI_ERRORS_REG_DCPL_UNSUPPORTED vxge_mBIT(15) | |
3007 | #define VXGE_HW_INI_ERRORS_REG_DCPL_ABORT vxge_mBIT(19) | |
3008 | #define VXGE_HW_INI_ERRORS_REG_INI_TLP_ABORT vxge_mBIT(23) | |
3009 | #define VXGE_HW_INI_ERRORS_REG_INI_DLLP_ABORT vxge_mBIT(27) | |
3010 | #define VXGE_HW_INI_ERRORS_REG_INI_ECRC_ERR vxge_mBIT(31) | |
3011 | #define VXGE_HW_INI_ERRORS_REG_INI_BUF_DB_ERR vxge_mBIT(35) | |
3012 | #define VXGE_HW_INI_ERRORS_REG_INI_BUF_SG_ERR vxge_mBIT(39) | |
3013 | #define VXGE_HW_INI_ERRORS_REG_INI_DATA_OVERFLOW vxge_mBIT(43) | |
3014 | #define VXGE_HW_INI_ERRORS_REG_INI_HDR_OVERFLOW vxge_mBIT(47) | |
3015 | #define VXGE_HW_INI_ERRORS_REG_INI_MRD_SYS_DROP vxge_mBIT(51) | |
3016 | #define VXGE_HW_INI_ERRORS_REG_INI_MWR_SYS_DROP vxge_mBIT(55) | |
3017 | #define VXGE_HW_INI_ERRORS_REG_INI_MRD_CLIENT_DROP vxge_mBIT(59) | |
3018 | #define VXGE_HW_INI_ERRORS_REG_INI_MWR_CLIENT_DROP vxge_mBIT(63) | |
3019 | /*0x07030*/ u64 ini_errors_mask; | |
3020 | /*0x07038*/ u64 ini_errors_alarm; | |
3021 | /*0x07040*/ u64 dma_errors_reg; | |
3022 | #define VXGE_HW_DMA_ERRORS_REG_RDARB_FSM_ERR vxge_mBIT(3) | |
3023 | #define VXGE_HW_DMA_ERRORS_REG_WRARB_FSM_ERR vxge_mBIT(7) | |
3024 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW vxge_mBIT(8) | |
3025 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW vxge_mBIT(9) | |
3026 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW vxge_mBIT(10) | |
3027 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW vxge_mBIT(11) | |
3028 | #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW vxge_mBIT(12) | |
3029 | #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW vxge_mBIT(13) | |
3030 | #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW vxge_mBIT(14) | |
3031 | #define VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW vxge_mBIT(15) | |
3032 | #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW vxge_mBIT(16) | |
3033 | #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW vxge_mBIT(17) | |
3034 | #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW vxge_mBIT(18) | |
3035 | #define VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW vxge_mBIT(19) | |
3036 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW vxge_mBIT(20) | |
3037 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW vxge_mBIT(21) | |
3038 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW vxge_mBIT(22) | |
3039 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW vxge_mBIT(23) | |
3040 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW vxge_mBIT(24) | |
3041 | #define VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW vxge_mBIT(25) | |
3042 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW vxge_mBIT(28) | |
3043 | #define VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW vxge_mBIT(29) | |
3044 | #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR vxge_mBIT(32) | |
3045 | #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR vxge_mBIT(33) | |
3046 | #define VXGE_HW_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR vxge_mBIT(34) | |
3047 | /*0x07048*/ u64 dma_errors_mask; | |
3048 | /*0x07050*/ u64 dma_errors_alarm; | |
3049 | /*0x07058*/ u64 tgt_errors_reg; | |
3050 | #define VXGE_HW_TGT_ERRORS_REG_TGT_VENDOR_MSG vxge_mBIT(0) | |
3051 | #define VXGE_HW_TGT_ERRORS_REG_TGT_MSG_UNLOCK vxge_mBIT(1) | |
3052 | #define VXGE_HW_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE vxge_mBIT(2) | |
3053 | #define VXGE_HW_TGT_ERRORS_REG_TGT_BOOT_WRITE vxge_mBIT(3) | |
3054 | #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE vxge_mBIT(4) | |
3055 | #define VXGE_HW_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE vxge_mBIT(5) | |
3056 | #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_READ vxge_mBIT(6) | |
3057 | #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_READ vxge_mBIT(7) | |
3058 | #define VXGE_HW_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE vxge_mBIT(8) | |
3059 | #define VXGE_HW_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE vxge_mBIT(9) | |
3060 | #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON vxge_mBIT(10) | |
3061 | #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON vxge_mBIT(11) | |
3062 | #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON vxge_mBIT(12) | |
3063 | #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON vxge_mBIT(13) | |
3064 | #define VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON vxge_mBIT(14) | |
3065 | #define VXGE_HW_TGT_ERRORS_REG_TGT_NOT_MEM_TLP vxge_mBIT(15) | |
3066 | #define VXGE_HW_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP vxge_mBIT(16) | |
3067 | #define VXGE_HW_TGT_ERRORS_REG_TGT_REQ_FSM_ERR vxge_mBIT(17) | |
3068 | #define VXGE_HW_TGT_ERRORS_REG_TGT_CPL_FSM_ERR vxge_mBIT(18) | |
3069 | #define VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR vxge_mBIT(19) | |
3070 | #define VXGE_HW_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR vxge_mBIT(20) | |
3071 | #define VXGE_HW_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR vxge_mBIT(21) | |
3072 | /*0x07060*/ u64 tgt_errors_mask; | |
3073 | /*0x07068*/ u64 tgt_errors_alarm; | |
3074 | /*0x07070*/ u64 config_errors_reg; | |
3075 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND vxge_mBIT(3) | |
3076 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND vxge_mBIT(7) | |
3077 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT vxge_mBIT(11) | |
3078 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE vxge_mBIT(15) | |
3079 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR vxge_mBIT(19) | |
3080 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REQ_COLLISION vxge_mBIT(23) | |
3081 | #define VXGE_HW_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR vxge_mBIT(27) | |
3082 | #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT vxge_mBIT(31) | |
3083 | #define VXGE_HW_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT vxge_mBIT(35) | |
3084 | #define VXGE_HW_CONFIG_ERRORS_REG_CFGM_FSM_ERR vxge_mBIT(39) | |
3085 | #define VXGE_HW_CONFIG_ERRORS_REG_RIC_FSM_ERR vxge_mBIT(43) | |
3086 | #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS vxge_mBIT(47) | |
3087 | #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TIMEOUT vxge_mBIT(51) | |
3088 | #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_FSM_ERR vxge_mBIT(55) | |
3089 | #define VXGE_HW_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR vxge_mBIT(59) | |
3090 | #define VXGE_HW_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT vxge_mBIT(63) | |
3091 | /*0x07078*/ u64 config_errors_mask; | |
3092 | /*0x07080*/ u64 config_errors_alarm; | |
3093 | u8 unused07090[0x07090-0x07088]; | |
3094 | ||
3095 | /*0x07090*/ u64 crdt_errors_reg; | |
3096 | #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR vxge_mBIT(11) | |
3097 | #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL \ | |
3098 | vxge_mBIT(15) | |
3099 | #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(19) | |
3100 | #define VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL \ | |
3101 | vxge_mBIT(23) | |
3102 | #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR vxge_mBIT(35) | |
3103 | #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL vxge_mBIT(39) | |
3104 | #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL vxge_mBIT(43) | |
3105 | #define VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL \ | |
3106 | vxge_mBIT(47) | |
3107 | /*0x07098*/ u64 crdt_errors_mask; | |
3108 | /*0x070a0*/ u64 crdt_errors_alarm; | |
3109 | u8 unused070b0[0x070b0-0x070a8]; | |
3110 | ||
3111 | /*0x070b0*/ u64 mrpcim_general_errors_reg; | |
3112 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR vxge_mBIT(3) | |
3113 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR vxge_mBIT(7) | |
3114 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR vxge_mBIT(11) | |
3115 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR vxge_mBIT(15) | |
3116 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR vxge_mBIT(19) | |
3117 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR vxge_mBIT(23) | |
3118 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR vxge_mBIT(27) | |
3119 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR vxge_mBIT(31) | |
3120 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(35) | |
3121 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR vxge_mBIT(39) | |
3122 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW vxge_mBIT(43) | |
3123 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_DURING_SW_RESET \ | |
3124 | vxge_mBIT(47) | |
3125 | #define VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR vxge_mBIT(51) | |
3126 | /*0x070b8*/ u64 mrpcim_general_errors_mask; | |
3127 | /*0x070c0*/ u64 mrpcim_general_errors_alarm; | |
3128 | u8 unused070d0[0x070d0-0x070c8]; | |
3129 | ||
3130 | /*0x070d0*/ u64 pll_errors_reg; | |
3131 | #define VXGE_HW_PLL_ERRORS_REG_CORE_CMG_PLL_OOL vxge_mBIT(3) | |
3132 | #define VXGE_HW_PLL_ERRORS_REG_CORE_FB_PLL_OOL vxge_mBIT(7) | |
3133 | #define VXGE_HW_PLL_ERRORS_REG_CORE_X_PLL_OOL vxge_mBIT(11) | |
3134 | /*0x070d8*/ u64 pll_errors_mask; | |
3135 | /*0x070e0*/ u64 pll_errors_alarm; | |
3136 | /*0x070e8*/ u64 srpcim_to_mrpcim_alarm_reg; | |
3137 | #define VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM(val) \ | |
3138 | vxge_vBIT(val, 0, 17) | |
3139 | /*0x070f0*/ u64 srpcim_to_mrpcim_alarm_mask; | |
3140 | /*0x070f8*/ u64 srpcim_to_mrpcim_alarm_alarm; | |
3141 | /*0x07100*/ u64 vpath_to_mrpcim_alarm_reg; | |
3142 | #define VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM(val) \ | |
3143 | vxge_vBIT(val, 0, 17) | |
3144 | /*0x07108*/ u64 vpath_to_mrpcim_alarm_mask; | |
3145 | /*0x07110*/ u64 vpath_to_mrpcim_alarm_alarm; | |
3146 | u8 unused07128[0x07128-0x07118]; | |
3147 | ||
3148 | /*0x07128*/ u64 crdt_errors_vplane_reg[17]; | |
3149 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR \ | |
3150 | vxge_mBIT(3) | |
3151 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR \ | |
3152 | vxge_mBIT(7) | |
3153 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR \ | |
3154 | vxge_mBIT(11) | |
3155 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR \ | |
3156 | vxge_mBIT(15) | |
3157 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR \ | |
3158 | vxge_mBIT(19) | |
3159 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR \ | |
3160 | vxge_mBIT(23) | |
3161 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR \ | |
3162 | vxge_mBIT(27) | |
3163 | #define VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR \ | |
3164 | vxge_mBIT(31) | |
3165 | /*0x07130*/ u64 crdt_errors_vplane_mask[17]; | |
3166 | /*0x07138*/ u64 crdt_errors_vplane_alarm[17]; | |
3167 | u8 unused072f0[0x072f0-0x072c0]; | |
3168 | ||
3169 | /*0x072f0*/ u64 mrpcim_rst_in_prog; | |
3170 | #define VXGE_HW_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG vxge_mBIT(7) | |
3171 | /*0x072f8*/ u64 mrpcim_reg_modified; | |
3172 | #define VXGE_HW_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED vxge_mBIT(7) | |
3173 | ||
3174 | u8 unused07378[0x07378-0x07300]; | |
3175 | ||
3176 | /*0x07378*/ u64 write_arb_pending; | |
3177 | #define VXGE_HW_WRITE_ARB_PENDING_WRARB_WRDMA vxge_mBIT(3) | |
3178 | #define VXGE_HW_WRITE_ARB_PENDING_WRARB_RTDMA vxge_mBIT(7) | |
3179 | #define VXGE_HW_WRITE_ARB_PENDING_WRARB_MSG vxge_mBIT(11) | |
3180 | #define VXGE_HW_WRITE_ARB_PENDING_WRARB_STATSB vxge_mBIT(15) | |
3181 | #define VXGE_HW_WRITE_ARB_PENDING_WRARB_INTCTL vxge_mBIT(19) | |
3182 | /*0x07380*/ u64 read_arb_pending; | |
3183 | #define VXGE_HW_READ_ARB_PENDING_RDARB_WRDMA vxge_mBIT(3) | |
3184 | #define VXGE_HW_READ_ARB_PENDING_RDARB_RTDMA vxge_mBIT(7) | |
3185 | #define VXGE_HW_READ_ARB_PENDING_RDARB_DBLGEN vxge_mBIT(11) | |
3186 | /*0x07388*/ u64 dmaif_dmadbl_pending; | |
3187 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR vxge_mBIT(0) | |
3188 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD vxge_mBIT(1) | |
3189 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR vxge_mBIT(2) | |
3190 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD vxge_mBIT(3) | |
3191 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR vxge_mBIT(4) | |
3192 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR vxge_mBIT(5) | |
3193 | #define VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) \ | |
3194 | vxge_vBIT(val, 13, 51) | |
3195 | /*0x07390*/ u64 wrcrdtarb_status0_vplane[17]; | |
3196 | #define VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val) \ | |
3197 | vxge_vBIT(val, 0, 8) | |
3198 | /*0x07418*/ u64 wrcrdtarb_status1_vplane[17]; | |
3199 | #define VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val) \ | |
3200 | vxge_vBIT(val, 4, 12) | |
3201 | u8 unused07500[0x07500-0x074a0]; | |
3202 | ||
3203 | /*0x07500*/ u64 mrpcim_general_cfg1; | |
3204 | #define VXGE_HW_MRPCIM_GENERAL_CFG1_CLEAR_SERR vxge_mBIT(7) | |
3205 | /*0x07508*/ u64 mrpcim_general_cfg2; | |
3206 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD vxge_mBIT(3) | |
3207 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD vxge_mBIT(7) | |
3208 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD vxge_mBIT(11) | |
3209 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR vxge_mBIT(15) | |
3210 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD vxge_mBIT(19) | |
3211 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX vxge_mBIT(23) | |
3212 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB vxge_mBIT(27) | |
3213 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR vxge_mBIT(31) | |
3214 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE vxge_mBIT(43) | |
3215 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val) \ | |
3216 | vxge_vBIT(val, 47, 5) | |
3217 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR vxge_mBIT(55) | |
3218 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA vxge_mBIT(59) | |
3219 | #define VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS vxge_mBIT(63) | |
3220 | /*0x07510*/ u64 mrpcim_general_cfg3; | |
3221 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN vxge_mBIT(0) | |
3222 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN vxge_mBIT(3) | |
3223 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN vxge_mBIT(7) | |
3224 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN vxge_mBIT(11) | |
3225 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN vxge_mBIT(15) | |
3226 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN vxge_mBIT(19) | |
3227 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vxge_vBIT(val, 20, 16) | |
3228 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) \ | |
3229 | vxge_vBIT(val, 36, 16) | |
3230 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN vxge_mBIT(55) | |
3231 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vxge_vBIT(val, 56, 2) | |
3232 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N vxge_mBIT(59) | |
3233 | #define VXGE_HW_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN vxge_mBIT(63) | |
3234 | /*0x07518*/ u64 mrpcim_stats_start_host_addr; | |
3235 | #define VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ | |
3236 | vxge_vBIT(val, 0, 57) | |
3237 | ||
3238 | u8 unused07950[0x07950-0x07520]; | |
3239 | ||
3240 | /*0x07950*/ u64 rdcrdtarb_cfg0; | |
3241 | #define VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) \ | |
3242 | vxge_vBIT(val, 18, 6) | |
3243 | #define VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) \ | |
3244 | vxge_vBIT(val, 26, 6) | |
3245 | #define VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) \ | |
3246 | vxge_vBIT(val, 34, 6) | |
3247 | #define VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT(val) vxge_vBIT(val, 48, 4) | |
3248 | #define VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vxge_vBIT(val, 54, 6) | |
3249 | #define VXGE_HW_RDCRDTARB_CFG0_EN_XON vxge_mBIT(63) | |
3250 | u8 unused07be8[0x07be8-0x07958]; | |
3251 | ||
3252 | /*0x07be8*/ u64 bf_sw_reset; | |
3253 | #define VXGE_HW_BF_SW_RESET_BF_SW_RESET(val) vxge_vBIT(val, 0, 8) | |
3254 | /*0x07bf0*/ u64 sw_reset_status; | |
3255 | #define VXGE_HW_SW_RESET_STATUS_RESET_CMPLT vxge_mBIT(7) | |
3256 | #define VXGE_HW_SW_RESET_STATUS_INIT_CMPLT vxge_mBIT(15) | |
3257 | u8 unused07d30[0x07d30-0x07bf8]; | |
3258 | ||
3259 | /*0x07d30*/ u64 mrpcim_debug_stats0; | |
3260 | #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vxge_vBIT(val, 0, 32) | |
3261 | #define VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vxge_vBIT(val, 32, 32) | |
3262 | /*0x07d38*/ u64 mrpcim_debug_stats1_vplane[17]; | |
3263 | #define VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val) \ | |
3264 | vxge_vBIT(val, 32, 32) | |
3265 | /*0x07dc0*/ u64 mrpcim_debug_stats2_vplane[17]; | |
3266 | #define VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val) \ | |
3267 | vxge_vBIT(val, 32, 32) | |
3268 | /*0x07e48*/ u64 mrpcim_debug_stats3_vplane[17]; | |
3269 | #define VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val) \ | |
3270 | vxge_vBIT(val, 32, 32) | |
3271 | /*0x07ed0*/ u64 mrpcim_debug_stats4; | |
3272 | #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vxge_vBIT(val, 0, 32) | |
3273 | #define VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) \ | |
3274 | vxge_vBIT(val, 32, 32) | |
3275 | /*0x07ed8*/ u64 genstats_count01; | |
3276 | #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vxge_vBIT(val, 0, 32) | |
3277 | #define VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vxge_vBIT(val, 32, 32) | |
3278 | /*0x07ee0*/ u64 genstats_count23; | |
3279 | #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vxge_vBIT(val, 0, 32) | |
3280 | #define VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vxge_vBIT(val, 32, 32) | |
3281 | /*0x07ee8*/ u64 genstats_count4; | |
3282 | #define VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vxge_vBIT(val, 32, 32) | |
3283 | /*0x07ef0*/ u64 genstats_count5; | |
3284 | #define VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vxge_vBIT(val, 32, 32) | |
3285 | ||
3286 | u8 unused07f08[0x07f08-0x07ef8]; | |
3287 | ||
3288 | /*0x07f08*/ u64 genstats_cfg[6]; | |
3289 | #define VXGE_HW_GENSTATS_CFG_DTYPE_SEL(val) vxge_vBIT(val, 3, 5) | |
3290 | #define VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL(val) vxge_vBIT(val, 9, 3) | |
3291 | #define VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL(val) vxge_vBIT(val, 14, 2) | |
3292 | #define VXGE_HW_GENSTATS_CFG_VPATH_SEL(val) vxge_vBIT(val, 31, 17) | |
3293 | /*0x07f38*/ u64 genstat_64bit_cfg; | |
3294 | #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0 vxge_mBIT(3) | |
3295 | #define VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2 vxge_mBIT(7) | |
3296 | u8 unused08000[0x08000-0x07f40]; | |
3297 | /*0x08000*/ u64 gcmg3_int_status; | |
3298 | #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT vxge_mBIT(0) | |
3299 | #define VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT vxge_mBIT(1) | |
3300 | #define VXGE_HW_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT vxge_mBIT(2) | |
3301 | #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT vxge_mBIT(3) | |
3302 | #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT vxge_mBIT(4) | |
3303 | #define VXGE_HW_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT vxge_mBIT(5) | |
3304 | #define VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT vxge_mBIT(6) | |
3305 | /*0x08008*/ u64 gcmg3_int_mask; | |
3306 | u8 unused09000[0x09000-0x8010]; | |
3307 | ||
3308 | /*0x09000*/ u64 g3ifcmd_fb_int_status; | |
3309 | #define VXGE_HW_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) | |
3310 | /*0x09008*/ u64 g3ifcmd_fb_int_mask; | |
3311 | /*0x09010*/ u64 g3ifcmd_fb_err_reg; | |
3312 | #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) | |
3313 | #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) | |
3314 | #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ | |
3315 | vxge_vBIT(val, 24, 8) | |
3316 | #define VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) | |
3317 | /*0x09018*/ u64 g3ifcmd_fb_err_mask; | |
3318 | /*0x09020*/ u64 g3ifcmd_fb_err_alarm; | |
3319 | ||
3320 | u8 unused09400[0x09400-0x09028]; | |
3321 | ||
3322 | /*0x09400*/ u64 g3ifcmd_cmu_int_status; | |
3323 | #define VXGE_HW_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) | |
3324 | /*0x09408*/ u64 g3ifcmd_cmu_int_mask; | |
3325 | /*0x09410*/ u64 g3ifcmd_cmu_err_reg; | |
3326 | #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) | |
3327 | #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) | |
3328 | #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ | |
3329 | vxge_vBIT(val, 24, 8) | |
3330 | #define VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) | |
3331 | /*0x09418*/ u64 g3ifcmd_cmu_err_mask; | |
3332 | /*0x09420*/ u64 g3ifcmd_cmu_err_alarm; | |
3333 | ||
3334 | u8 unused09800[0x09800-0x09428]; | |
3335 | ||
3336 | /*0x09800*/ u64 g3ifcmd_cml_int_status; | |
3337 | #define VXGE_HW_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT vxge_mBIT(0) | |
3338 | /*0x09808*/ u64 g3ifcmd_cml_int_mask; | |
3339 | /*0x09810*/ u64 g3ifcmd_cml_err_reg; | |
3340 | #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK vxge_mBIT(6) | |
3341 | #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR vxge_mBIT(7) | |
3342 | #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) \ | |
3343 | vxge_vBIT(val, 24, 8) | |
3344 | #define VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT vxge_mBIT(55) | |
3345 | /*0x09818*/ u64 g3ifcmd_cml_err_mask; | |
3346 | /*0x09820*/ u64 g3ifcmd_cml_err_alarm; | |
3347 | u8 unused09b00[0x09b00-0x09828]; | |
3348 | ||
3349 | /*0x09b00*/ u64 vpath_to_vplane_map[17]; | |
3350 | #define VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) \ | |
3351 | vxge_vBIT(val, 3, 5) | |
3352 | u8 unused09c30[0x09c30-0x09b88]; | |
3353 | ||
3354 | /*0x09c30*/ u64 xgxs_cfg_port[2]; | |
3355 | #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vxge_vBIT(val, 16, 4) | |
3356 | #define VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vxge_vBIT(val, 20, 4) | |
3357 | #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_0 vxge_mBIT(27) | |
3358 | #define VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1(val) vxge_vBIT(val, 29, 3) | |
3359 | #define VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vxge_vBIT(val, 32, 4) | |
3360 | #define VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vxge_vBIT(val, 36, 4) | |
3361 | #define VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vxge_vBIT(val, 40, 4) | |
3362 | #define VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vxge_vBIT(val, 44, 4) | |
3363 | /*0x09c40*/ u64 xgxs_rxber_cfg_port[2]; | |
3364 | #define VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vxge_vBIT(val, 0, 4) | |
3365 | #define VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) \ | |
3366 | vxge_vBIT(val, 16, 48) | |
3367 | /*0x09c50*/ u64 xgxs_rxber_status_port[2]; | |
3368 | #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val) \ | |
3369 | vxge_vBIT(val, 0, 16) | |
3370 | #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val) \ | |
3371 | vxge_vBIT(val, 16, 16) | |
3372 | #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val) \ | |
3373 | vxge_vBIT(val, 32, 16) | |
3374 | #define VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val) \ | |
3375 | vxge_vBIT(val, 48, 16) | |
3376 | /*0x09c60*/ u64 xgxs_status_port[2]; | |
3377 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vxge_vBIT(val, 0, 4) | |
3378 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vxge_vBIT(val, 4, 4) | |
3379 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) | |
3380 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) \ | |
3381 | vxge_vBIT(val, 12, 4) | |
3382 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vxge_vBIT(val, 16, 4) | |
3383 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR vxge_mBIT(23) | |
3384 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vxge_vBIT(val, 24, 8) | |
3385 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) \ | |
3386 | vxge_vBIT(val, 32, 4) | |
3387 | #define VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) \ | |
3388 | vxge_vBIT(val, 36, 4) | |
3389 | /*0x09c70*/ u64 xgxs_pma_reset_port[2]; | |
3390 | #define VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vxge_vBIT(val, 0, 8) | |
3391 | u8 unused09c90[0x09c90-0x09c80]; | |
3392 | ||
3393 | /*0x09c90*/ u64 xgxs_static_cfg_port[2]; | |
3394 | #define VXGE_HW_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES vxge_mBIT(3) | |
3395 | u8 unused09d40[0x09d40-0x09ca0]; | |
3396 | ||
3397 | /*0x09d40*/ u64 xgxs_info_port[2]; | |
3398 | #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0(val) vxge_vBIT(val, 0, 32) | |
3399 | #define VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1(val) vxge_vBIT(val, 32, 32) | |
3400 | /*0x09d50*/ u64 ratemgmt_cfg_port[2]; | |
3401 | #define VXGE_HW_RATEMGMT_CFG_PORT_MODE(val) vxge_vBIT(val, 2, 2) | |
3402 | #define VXGE_HW_RATEMGMT_CFG_PORT_RATE vxge_mBIT(7) | |
3403 | #define VXGE_HW_RATEMGMT_CFG_PORT_FIXED_USE_FSM vxge_mBIT(11) | |
3404 | #define VXGE_HW_RATEMGMT_CFG_PORT_ANTP_USE_FSM vxge_mBIT(15) | |
3405 | #define VXGE_HW_RATEMGMT_CFG_PORT_ANBE_USE_FSM vxge_mBIT(19) | |
3406 | /*0x09d60*/ u64 ratemgmt_status_port[2]; | |
3407 | #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE vxge_mBIT(3) | |
3408 | #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_RATE vxge_mBIT(7) | |
3409 | #define VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY vxge_mBIT(11) | |
3410 | u8 unused09d80[0x09d80-0x09d70]; | |
3411 | ||
3412 | /*0x09d80*/ u64 ratemgmt_fixed_cfg_port[2]; | |
3413 | #define VXGE_HW_RATEMGMT_FIXED_CFG_PORT_RESTART vxge_mBIT(7) | |
3414 | /*0x09d90*/ u64 ratemgmt_antp_cfg_port[2]; | |
3415 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_RESTART vxge_mBIT(7) | |
3416 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY vxge_mBIT(11) | |
3417 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL vxge_mBIT(15) | |
3418 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val) \ | |
3419 | vxge_vBIT(val, 16, 4) | |
3420 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE(val) \ | |
3421 | vxge_vBIT(val, 20, 4) | |
3422 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE(val) \ | |
3423 | vxge_vBIT(val, 24, 4) | |
3424 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G vxge_mBIT(31) | |
3425 | #define VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G vxge_mBIT(35) | |
3426 | /*0x09da0*/ u64 ratemgmt_anbe_cfg_port[2]; | |
3427 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_RESTART vxge_mBIT(7) | |
3428 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE \ | |
3429 | vxge_mBIT(11) | |
3430 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE \ | |
3431 | vxge_mBIT(15) | |
3432 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vxge_vBIT(val, 16, 4) | |
3433 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vxge_vBIT(val, 20, 4) | |
3434 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vxge_vBIT(val, 24, 4) | |
3435 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4 vxge_mBIT(31) | |
3436 | #define VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX vxge_mBIT(35) | |
3437 | /*0x09db0*/ u64 anbe_cfg_port[2]; | |
3438 | #define VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS(val) vxge_vBIT(val, 0, 8) | |
3439 | #define VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vxge_vBIT(val, 10, 2) | |
3440 | #define VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vxge_vBIT(val, 14, 2) | |
3441 | /*0x09dc0*/ u64 anbe_mgr_ctrl_port[2]; | |
3442 | #define VXGE_HW_ANBE_MGR_CTRL_PORT_WE vxge_mBIT(3) | |
3443 | #define VXGE_HW_ANBE_MGR_CTRL_PORT_STROBE vxge_mBIT(7) | |
3444 | #define VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR(val) vxge_vBIT(val, 15, 9) | |
3445 | #define VXGE_HW_ANBE_MGR_CTRL_PORT_DATA(val) vxge_vBIT(val, 32, 32) | |
3446 | u8 unused09de0[0x09de0-0x09dd0]; | |
3447 | ||
3448 | /*0x09de0*/ u64 anbe_fw_mstr_port[2]; | |
3449 | #define VXGE_HW_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES vxge_mBIT(3) | |
3450 | #define VXGE_HW_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES vxge_mBIT(7) | |
3451 | /*0x09df0*/ u64 anbe_hwfsm_gen_status_port[2]; | |
3452 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD \ | |
3453 | vxge_mBIT(3) | |
3454 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME \ | |
3455 | vxge_mBIT(7) | |
3456 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD \ | |
3457 | vxge_mBIT(11) | |
3458 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME \ | |
3459 | vxge_mBIT(15) | |
3460 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val) \ | |
3461 | vxge_vBIT(val, 18, 6) | |
3462 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED \ | |
3463 | vxge_mBIT(27) | |
3464 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED \ | |
3465 | vxge_mBIT(35) | |
3466 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE \ | |
3467 | vxge_mBIT(39) | |
3468 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NP_BEFORE_BP \ | |
3469 | vxge_mBIT(43) | |
3470 | #define \ | |
3471 | VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_BP \ | |
3472 | vxge_mBIT(47) | |
3473 | #define \ | |
3474 | VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_NP \ | |
3475 | vxge_mBIT(51) | |
3476 | #define \ | |
3477 | VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MODE_WHEN_AN_COMPLETE \ | |
3478 | vxge_mBIT(55) | |
3479 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val) \ | |
3480 | vxge_vBIT(val, 56, 4) | |
3481 | #define VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val) \ | |
3482 | vxge_vBIT(val, 60, 4) | |
3483 | /*0x09e00*/ u64 anbe_hwfsm_bp_status_port[2]; | |
3484 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE \ | |
3485 | vxge_mBIT(32) | |
3486 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY \ | |
3487 | vxge_mBIT(33) | |
3488 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE \ | |
3489 | vxge_mBIT(40) | |
3490 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE \ | |
3491 | vxge_mBIT(41) | |
3492 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE \ | |
3493 | vxge_mBIT(42) | |
3494 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val) \ | |
3495 | vxge_vBIT(val, 43, 5) | |
3496 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(48) | |
3497 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(49) | |
3498 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT \ | |
3499 | vxge_mBIT(50) | |
3500 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR vxge_mBIT(51) | |
3501 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE vxge_mBIT(53) | |
3502 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val) \ | |
3503 | vxge_vBIT(val, 54, 5) | |
3504 | #define VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ | |
3505 | vxge_vBIT(val, 59, 5) | |
3506 | /*0x09e10*/ u64 anbe_hwfsm_np_status_port[2]; | |
3507 | #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val) \ | |
3508 | vxge_vBIT(val, 16, 16) | |
3509 | #define VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val) \ | |
3510 | vxge_vBIT(val, 32, 32) | |
3511 | u8 unused09e30[0x09e30-0x09e20]; | |
3512 | ||
3513 | /*0x09e30*/ u64 antp_gen_cfg_port[2]; | |
3514 | /*0x09e40*/ u64 antp_hwfsm_gen_status_port[2]; | |
3515 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G vxge_mBIT(3) | |
3516 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G vxge_mBIT(7) | |
3517 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val) \ | |
3518 | vxge_vBIT(val, 10, 6) | |
3519 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE \ | |
3520 | vxge_mBIT(23) | |
3521 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP \ | |
3522 | vxge_mBIT(27) | |
3523 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP vxge_mBIT(31) | |
3524 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE \ | |
3525 | vxge_mBIT(35) | |
3526 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD \ | |
3527 | vxge_mBIT(43) | |
3528 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD vxge_mBIT(47) | |
3529 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE \ | |
3530 | vxge_mBIT(51) | |
3531 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE vxge_mBIT(55) | |
3532 | #define VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN \ | |
3533 | vxge_mBIT(59) | |
3534 | /*0x09e50*/ u64 antp_hwfsm_bp_status_port[2]; | |
3535 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP vxge_mBIT(0) | |
3536 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK vxge_mBIT(1) | |
3537 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF vxge_mBIT(2) | |
3538 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP vxge_mBIT(3) | |
3539 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val) \ | |
3540 | vxge_vBIT(val, 4, 7) | |
3541 | #define VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val) \ | |
3542 | vxge_vBIT(val, 11, 5) | |
3543 | /*0x09e60*/ u64 antp_hwfsm_xnp_status_port[2]; | |
3544 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP vxge_mBIT(0) | |
3545 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK vxge_mBIT(1) | |
3546 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP vxge_mBIT(2) | |
3547 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2 vxge_mBIT(3) | |
3548 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE vxge_mBIT(4) | |
3549 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val) \ | |
3550 | vxge_vBIT(val, 5, 11) | |
3551 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val) \ | |
3552 | vxge_vBIT(val, 16, 16) | |
3553 | #define VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val) \ | |
3554 | vxge_vBIT(val, 32, 16) | |
3555 | /*0x09e70*/ u64 mdio_mgr_access_port[2]; | |
3556 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE BIT(3) | |
3557 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vxge_vBIT(val, 5, 3) | |
3558 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD(val) vxge_vBIT(val, 11, 5) | |
3559 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR(val) vxge_vBIT(val, 16, 16) | |
3560 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA(val) vxge_vBIT(val, 32, 16) | |
3561 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vxge_vBIT(val, 49, 2) | |
3562 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PREAMBLE vxge_mBIT(51) | |
3563 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD(val) vxge_vBIT(val, 55, 5) | |
3564 | #define VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_TWO vxge_mBIT(63) | |
3565 | u8 unused0a200[0x0a200-0x09e80]; | |
3566 | /*0x0a200*/ u64 xmac_vsport_choices_vh[17]; | |
3567 | #define VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) | |
3568 | u8 unused0a400[0x0a400-0x0a288]; | |
3569 | ||
3570 | /*0x0a400*/ u64 rx_thresh_cfg_vp[17]; | |
3571 | #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vxge_vBIT(val, 0, 8) | |
3572 | #define VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) | |
3573 | #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0(val) vxge_vBIT(val, 16, 8) | |
3574 | #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1(val) vxge_vBIT(val, 24, 8) | |
3575 | #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2(val) vxge_vBIT(val, 32, 8) | |
3576 | #define VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3(val) vxge_vBIT(val, 40, 8) | |
3577 | u8 unused0ac90[0x0ac90-0x0a488]; | |
3578 | } __packed; | |
3579 | ||
3580 | /*VXGE_HW_SRPCIM_REGS_H*/ | |
3581 | struct vxge_hw_srpcim_reg { | |
3582 | ||
3583 | /*0x00000*/ u64 tim_mr2sr_resource_assignment_vh; | |
3584 | #define VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) \ | |
3585 | vxge_vBIT(val, 0, 32) | |
3586 | u8 unused00100[0x00100-0x00008]; | |
3587 | ||
3588 | /*0x00100*/ u64 srpcim_pcipif_int_status; | |
3589 | #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT BIT(3) | |
3590 | #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT BIT(7) | |
3591 | #define VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT \ | |
3592 | BIT(11) | |
3593 | /*0x00108*/ u64 srpcim_pcipif_int_mask; | |
3594 | /*0x00110*/ u64 mrpcim_msg_reg; | |
3595 | #define VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT BIT(3) | |
3596 | /*0x00118*/ u64 mrpcim_msg_mask; | |
3597 | /*0x00120*/ u64 mrpcim_msg_alarm; | |
3598 | /*0x00128*/ u64 vpath_msg_reg; | |
3599 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT BIT(0) | |
3600 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT BIT(1) | |
3601 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT BIT(2) | |
3602 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT BIT(3) | |
3603 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT BIT(4) | |
3604 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT BIT(5) | |
3605 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT BIT(6) | |
3606 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT BIT(7) | |
3607 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT BIT(8) | |
3608 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT BIT(9) | |
3609 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT BIT(10) | |
3610 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT BIT(11) | |
3611 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT BIT(12) | |
3612 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT BIT(13) | |
3613 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT BIT(14) | |
3614 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT BIT(15) | |
3615 | #define VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT BIT(16) | |
3616 | /*0x00130*/ u64 vpath_msg_mask; | |
3617 | /*0x00138*/ u64 vpath_msg_alarm; | |
3618 | u8 unused00160[0x00160-0x00140]; | |
3619 | ||
3620 | /*0x00160*/ u64 srpcim_to_mrpcim_wmsg; | |
3621 | #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val) \ | |
3622 | vxge_vBIT(val, 0, 64) | |
3623 | /*0x00168*/ u64 srpcim_to_mrpcim_wmsg_trig; | |
3624 | #define VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG BIT(0) | |
3625 | /*0x00170*/ u64 mrpcim_to_srpcim_rmsg; | |
3626 | #define VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val) \ | |
3627 | vxge_vBIT(val, 0, 64) | |
3628 | /*0x00178*/ u64 vpath_to_srpcim_rmsg_sel; | |
3629 | #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL(val) \ | |
3630 | vxge_vBIT(val, 0, 5) | |
3631 | /*0x00180*/ u64 vpath_to_srpcim_rmsg; | |
3632 | #define VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val) \ | |
3633 | vxge_vBIT(val, 0, 64) | |
3634 | u8 unused00200[0x00200-0x00188]; | |
3635 | ||
3636 | /*0x00200*/ u64 srpcim_general_int_status; | |
3637 | #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT BIT(0) | |
3638 | #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT BIT(3) | |
3639 | #define VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT BIT(7) | |
3640 | u8 unused00210[0x00210-0x00208]; | |
3641 | ||
3642 | /*0x00210*/ u64 srpcim_general_int_mask; | |
3643 | #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT BIT(0) | |
3644 | #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT BIT(3) | |
3645 | #define VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT BIT(7) | |
3646 | u8 unused00220[0x00220-0x00218]; | |
3647 | ||
3648 | /*0x00220*/ u64 srpcim_ppif_int_status; | |
3649 | ||
3650 | /*0x00228*/ u64 srpcim_ppif_int_mask; | |
3651 | /*0x00230*/ u64 srpcim_gen_errors_reg; | |
3652 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR BIT(3) | |
3653 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR BIT(7) | |
3654 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR BIT(11) | |
3655 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT BIT(15) | |
3656 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET BIT(19) | |
3657 | #define VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS BIT(23) | |
3658 | /*0x00238*/ u64 srpcim_gen_errors_mask; | |
3659 | /*0x00240*/ u64 srpcim_gen_errors_alarm; | |
3660 | /*0x00248*/ u64 mrpcim_to_srpcim_alarm_reg; | |
3661 | #define VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM BIT(3) | |
3662 | /*0x00250*/ u64 mrpcim_to_srpcim_alarm_mask; | |
3663 | /*0x00258*/ u64 mrpcim_to_srpcim_alarm_alarm; | |
3664 | /*0x00260*/ u64 vpath_to_srpcim_alarm_reg; | |
3665 | ||
3666 | /*0x00268*/ u64 vpath_to_srpcim_alarm_mask; | |
3667 | /*0x00270*/ u64 vpath_to_srpcim_alarm_alarm; | |
3668 | u8 unused00280[0x00280-0x00278]; | |
3669 | ||
3670 | /*0x00280*/ u64 pf_sw_reset; | |
3671 | #define VXGE_HW_PF_SW_RESET_PF_SW_RESET(val) vxge_vBIT(val, 0, 8) | |
3672 | /*0x00288*/ u64 srpcim_general_cfg1; | |
3673 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN BIT(19) | |
3674 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN BIT(23) | |
3675 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN BIT(27) | |
3676 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN BIT(31) | |
3677 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN BIT(35) | |
3678 | #define VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN BIT(39) | |
3679 | /*0x00290*/ u64 srpcim_interrupt_cfg1; | |
3680 | #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) | |
3681 | #define VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS(val) vxge_vBIT(val, 9, 3) | |
3682 | u8 unused002a8[0x002a8-0x00298]; | |
3683 | ||
3684 | /*0x002a8*/ u64 srpcim_clear_msix_mask; | |
3685 | #define VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK BIT(0) | |
3686 | /*0x002b0*/ u64 srpcim_set_msix_mask; | |
3687 | #define VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK BIT(0) | |
3688 | /*0x002b8*/ u64 srpcim_clr_msix_one_shot; | |
3689 | #define VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT BIT(0) | |
3690 | /*0x002c0*/ u64 srpcim_rst_in_prog; | |
3691 | #define VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG BIT(7) | |
3692 | /*0x002c8*/ u64 srpcim_reg_modified; | |
3693 | #define VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED BIT(7) | |
3694 | /*0x002d0*/ u64 tgt_pf_illegal_access; | |
3695 | #define VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) | |
3696 | /*0x002d8*/ u64 srpcim_msix_status; | |
3697 | #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK BIT(3) | |
3698 | #define VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR BIT(7) | |
3699 | u8 unused00880[0x00880-0x002e0]; | |
3700 | ||
3701 | /*0x00880*/ u64 xgmac_sr_int_status; | |
3702 | #define VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT BIT(3) | |
3703 | /*0x00888*/ u64 xgmac_sr_int_mask; | |
3704 | /*0x00890*/ u64 asic_ntwk_sr_err_reg; | |
3705 | #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT BIT(3) | |
3706 | #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK BIT(7) | |
3707 | #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED \ | |
3708 | BIT(11) | |
3709 | #define VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED BIT(15) | |
3710 | /*0x00898*/ u64 asic_ntwk_sr_err_mask; | |
3711 | /*0x008a0*/ u64 asic_ntwk_sr_err_alarm; | |
3712 | u8 unused008c0[0x008c0-0x008a8]; | |
3713 | ||
3714 | /*0x008c0*/ u64 xmac_vsport_choices_sr_clone; | |
3715 | #define VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val) \ | |
3716 | vxge_vBIT(val, 0, 17) | |
3717 | u8 unused00900[0x00900-0x008c8]; | |
3718 | ||
3719 | /*0x00900*/ u64 mr_rqa_top_prty_for_vh; | |
3720 | #define VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) \ | |
3721 | vxge_vBIT(val, 59, 5) | |
3722 | /*0x00908*/ u64 umq_vh_data_list_empty; | |
3723 | #define VXGE_HW_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY \ | |
3724 | BIT(0) | |
3725 | /*0x00910*/ u64 wde_cfg; | |
3726 | #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START BIT(0) | |
3727 | #define VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END BIT(1) | |
3728 | #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_START BIT(2) | |
3729 | #define VXGE_HW_WDE_CFG_NS0_FORCE_QB_END BIT(3) | |
3730 | #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START BIT(4) | |
3731 | #define VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END BIT(5) | |
3732 | #define VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN BIT(6) | |
3733 | #define VXGE_HW_WDE_CFG_NS0_QB_OPT_EN BIT(7) | |
3734 | #define VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN BIT(8) | |
3735 | #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START BIT(9) | |
3736 | #define VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END BIT(10) | |
3737 | #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_START BIT(11) | |
3738 | #define VXGE_HW_WDE_CFG_NS1_FORCE_QB_END BIT(12) | |
3739 | #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START BIT(13) | |
3740 | #define VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END BIT(14) | |
3741 | #define VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN BIT(15) | |
3742 | #define VXGE_HW_WDE_CFG_NS1_QB_OPT_EN BIT(16) | |
3743 | #define VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN BIT(17) | |
3744 | #define VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR BIT(19) | |
3745 | #define VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE(val) vxge_vBIT(val, 30, 2) | |
3746 | #define VXGE_HW_WDE_CFG_MEM_WORD_SIZE(val) vxge_vBIT(val, 46, 2) | |
3747 | ||
3748 | } __packed; | |
3749 | ||
3750 | /*VXGE_HW_VPMGMT_REGS_H*/ | |
3751 | struct vxge_hw_vpmgmt_reg { | |
3752 | ||
3753 | u8 unused00040[0x00040-0x00000]; | |
3754 | ||
3755 | /*0x00040*/ u64 vpath_to_func_map_cfg1; | |
3756 | #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1(val) \ | |
3757 | vxge_vBIT(val, 3, 5) | |
3758 | /*0x00048*/ u64 vpath_is_first; | |
3759 | #define VXGE_HW_VPATH_IS_FIRST_VPATH_IS_FIRST vxge_mBIT(3) | |
3760 | /*0x00050*/ u64 srpcim_to_vpath_wmsg; | |
3761 | #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val) \ | |
3762 | vxge_vBIT(val, 0, 64) | |
3763 | /*0x00058*/ u64 srpcim_to_vpath_wmsg_trig; | |
3764 | #define VXGE_HW_SRPCIM_TO_VPATH_WMSG_TRIG_SRPCIM_TO_VPATH_WMSG_TRIG \ | |
3765 | vxge_mBIT(0) | |
3766 | u8 unused00100[0x00100-0x00060]; | |
3767 | ||
3768 | /*0x00100*/ u64 tim_vpath_assignment; | |
3769 | #define VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) | |
3770 | u8 unused00140[0x00140-0x00108]; | |
3771 | ||
3772 | /*0x00140*/ u64 rqa_top_prty_for_vp; | |
3773 | #define VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) \ | |
3774 | vxge_vBIT(val, 59, 5) | |
3775 | u8 unused001c0[0x001c0-0x00148]; | |
3776 | ||
3777 | /*0x001c0*/ u64 rxmac_rx_pa_cfg0_vpmgmt_clone; | |
3778 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR vxge_mBIT(3) | |
3779 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N vxge_mBIT(7) | |
3780 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO vxge_mBIT(18) | |
3781 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS \ | |
3782 | vxge_mBIT(19) | |
3783 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING \ | |
3784 | vxge_mBIT(23) | |
3785 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN vxge_mBIT(27) | |
3786 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE vxge_mBIT(35) | |
3787 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR \ | |
3788 | vxge_mBIT(39) | |
3789 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR \ | |
3790 | vxge_mBIT(43) | |
3791 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR \ | |
3792 | vxge_mBIT(47) | |
3793 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR \ | |
3794 | vxge_mBIT(51) | |
3795 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR \ | |
3796 | vxge_mBIT(55) | |
3797 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR \ | |
3798 | vxge_mBIT(59) | |
3799 | #define VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN vxge_mBIT(63) | |
3800 | /*0x001c8*/ u64 rts_mgr_cfg0_vpmgmt_clone; | |
3801 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY vxge_mBIT(3) | |
3802 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE(val) \ | |
3803 | vxge_vBIT(val, 24, 8) | |
3804 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH vxge_mBIT(35) | |
3805 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH vxge_mBIT(39) | |
3806 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH vxge_mBIT(43) | |
3807 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH vxge_mBIT(47) | |
3808 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH vxge_mBIT(51) | |
3809 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH vxge_mBIT(55) | |
3810 | #define VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH vxge_mBIT(59) | |
3811 | /*0x001d0*/ u64 rts_mgr_criteria_priority_vpmgmt_clone; | |
3812 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val) \ | |
3813 | vxge_vBIT(val, 5, 3) | |
3814 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val) \ | |
3815 | vxge_vBIT(val, 9, 3) | |
3816 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN(val) \ | |
3817 | vxge_vBIT(val, 13, 3) | |
3818 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN(val) \ | |
3819 | vxge_vBIT(val, 17, 3) | |
3820 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val) \ | |
3821 | vxge_vBIT(val, 21, 3) | |
3822 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val) \ | |
3823 | vxge_vBIT(val, 25, 3) | |
3824 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val) \ | |
3825 | vxge_vBIT(val, 29, 3) | |
3826 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD(val) \ | |
3827 | vxge_vBIT(val, 33, 3) | |
3828 | #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL(val) \ | |
3829 | vxge_vBIT(val, 37, 3) | |
3830 | /*0x001d8*/ u64 rxmac_cfg0_port_vpmgmt_clone[3]; | |
3831 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN vxge_mBIT(3) | |
3832 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS vxge_mBIT(7) | |
3833 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM vxge_mBIT(11) | |
3834 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR vxge_mBIT(15) | |
3835 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR vxge_mBIT(19) | |
3836 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR vxge_mBIT(23) | |
3837 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH \ | |
3838 | vxge_mBIT(27) | |
3839 | #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN(val) \ | |
3840 | vxge_vBIT(val, 50, 14) | |
3841 | /*0x001f0*/ u64 rxmac_pause_cfg_port_vpmgmt_clone[3]; | |
3842 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN vxge_mBIT(3) | |
3843 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN vxge_mBIT(7) | |
3844 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val) \ | |
3845 | vxge_vBIT(val, 9, 3) | |
3846 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR vxge_mBIT(15) | |
3847 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val) \ | |
3848 | vxge_vBIT(val, 20, 16) | |
3849 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR \ | |
3850 | vxge_mBIT(39) | |
3851 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR \ | |
3852 | vxge_mBIT(43) | |
3853 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN vxge_mBIT(47) | |
3854 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val) \ | |
3855 | vxge_vBIT(val, 48, 8) | |
3856 | #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL \ | |
3857 | vxge_mBIT(59) | |
3858 | u8 unused00240[0x00240-0x00208]; | |
3859 | ||
3860 | /*0x00240*/ u64 xmac_vsport_choices_vp; | |
3861 | #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vxge_vBIT(val, 0, 17) | |
3862 | u8 unused00260[0x00260-0x00248]; | |
3863 | ||
3864 | /*0x00260*/ u64 xgmac_gen_status_vpmgmt_clone; | |
3865 | #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK vxge_mBIT(3) | |
3866 | #define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE \ | |
3867 | vxge_mBIT(11) | |
3868 | /*0x00268*/ u64 xgmac_status_port_vpmgmt_clone[2]; | |
3869 | #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT \ | |
3870 | vxge_mBIT(3) | |
3871 | #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT vxge_mBIT(7) | |
3872 | #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL \ | |
3873 | vxge_mBIT(11) | |
3874 | #define VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK vxge_mBIT(15) | |
3875 | /*0x00278*/ u64 xmac_gen_cfg_vpmgmt_clone; | |
3876 | #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val) \ | |
3877 | vxge_vBIT(val, 2, 2) | |
3878 | #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT \ | |
3879 | vxge_mBIT(7) | |
3880 | #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR vxge_mBIT(27) | |
3881 | #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val) \ | |
3882 | vxge_vBIT(val, 28, 4) | |
3883 | #define VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val) \ | |
3884 | vxge_vBIT(val, 32, 4) | |
3885 | /*0x00280*/ u64 xmac_timestamp_vpmgmt_clone; | |
3886 | #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_EN vxge_mBIT(3) | |
3887 | #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val) \ | |
3888 | vxge_vBIT(val, 6, 2) | |
3889 | #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val) vxge_vBIT(val, 12, 4) | |
3890 | #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART vxge_mBIT(19) | |
3891 | #define VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val) \ | |
3892 | vxge_vBIT(val, 32, 16) | |
3893 | /*0x00288*/ u64 xmac_stats_gen_cfg_vpmgmt_clone; | |
3894 | #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val) \ | |
3895 | vxge_vBIT(val, 4, 4) | |
3896 | #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val) \ | |
3897 | vxge_vBIT(val, 8, 4) | |
3898 | #define VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING vxge_mBIT(15) | |
3899 | /*0x00290*/ u64 xmac_cfg_port_vpmgmt_clone[3]; | |
3900 | #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK vxge_mBIT(3) | |
3901 | #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK \ | |
3902 | vxge_mBIT(7) | |
3903 | #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV vxge_mBIT(11) | |
3904 | #define VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV vxge_mBIT(15) | |
3905 | u8 unused002c0[0x002c0-0x002a8]; | |
3906 | ||
3907 | /*0x002c0*/ u64 txmac_gen_cfg0_vpmgmt_clone; | |
3908 | #define VXGE_HW_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT vxge_mBIT(7) | |
3909 | /*0x002c8*/ u64 txmac_cfg0_port_vpmgmt_clone[3]; | |
3910 | #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN vxge_mBIT(3) | |
3911 | #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD vxge_mBIT(7) | |
3912 | #define VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE(val) vxge_vBIT(val, 8, 8) | |
3913 | u8 unused00300[0x00300-0x002e0]; | |
3914 | ||
3915 | /*0x00300*/ u64 wol_mp_crc; | |
3916 | #define VXGE_HW_WOL_MP_CRC_CRC(val) vxge_vBIT(val, 0, 32) | |
3917 | #define VXGE_HW_WOL_MP_CRC_RC_EN vxge_mBIT(63) | |
3918 | /*0x00308*/ u64 wol_mp_mask_a; | |
3919 | #define VXGE_HW_WOL_MP_MASK_A_MASK(val) vxge_vBIT(val, 0, 64) | |
3920 | /*0x00310*/ u64 wol_mp_mask_b; | |
3921 | #define VXGE_HW_WOL_MP_MASK_B_MASK(val) vxge_vBIT(val, 0, 64) | |
3922 | u8 unused00360[0x00360-0x00318]; | |
3923 | ||
3924 | /*0x00360*/ u64 fau_pa_cfg_vpmgmt_clone; | |
3925 | #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM vxge_mBIT(3) | |
3926 | #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF vxge_mBIT(7) | |
3927 | #define VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM vxge_mBIT(11) | |
3928 | /*0x00368*/ u64 rx_datapath_util_vp_clone; | |
3929 | #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val) \ | |
3930 | vxge_vBIT(val, 7, 9) | |
3931 | #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) \ | |
3932 | vxge_vBIT(val, 16, 4) | |
3933 | #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val) \ | |
3934 | vxge_vBIT(val, 20, 4) | |
3935 | #define VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val) \ | |
3936 | vxge_vBIT(val, 24, 4) | |
3937 | u8 unused00380[0x00380-0x00370]; | |
3938 | ||
3939 | /*0x00380*/ u64 tx_datapath_util_vp_clone; | |
3940 | #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val) \ | |
3941 | vxge_vBIT(val, 7, 9) | |
3942 | #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) \ | |
3943 | vxge_vBIT(val, 16, 4) | |
3944 | #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val) \ | |
3945 | vxge_vBIT(val, 20, 4) | |
3946 | #define VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) \ | |
3947 | vxge_vBIT(val, 24, 4) | |
3948 | ||
3949 | } __packed; | |
3950 | ||
3951 | struct vxge_hw_vpath_reg { | |
3952 | ||
3953 | u8 unused00300[0x00300]; | |
3954 | ||
3955 | /*0x00300*/ u64 usdc_vpath; | |
3956 | #define VXGE_HW_USDC_VPATH_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 32) | |
3957 | u8 unused00a00[0x00a00-0x00308]; | |
3958 | ||
3959 | /*0x00a00*/ u64 wrdma_alarm_status; | |
3960 | #define VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT vxge_mBIT(1) | |
3961 | /*0x00a08*/ u64 wrdma_alarm_mask; | |
3962 | u8 unused00a30[0x00a30-0x00a10]; | |
3963 | ||
3964 | /*0x00a30*/ u64 prc_alarm_reg; | |
3965 | #define VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP vxge_mBIT(0) | |
3966 | #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR vxge_mBIT(1) | |
3967 | #define VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT vxge_mBIT(2) | |
3968 | #define VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR vxge_mBIT(3) | |
3969 | /*0x00a38*/ u64 prc_alarm_mask; | |
3970 | /*0x00a40*/ u64 prc_alarm_alarm; | |
3971 | /*0x00a48*/ u64 prc_cfg1; | |
3972 | #define VXGE_HW_PRC_CFG1_RX_TIMER_VAL(val) vxge_vBIT(val, 3, 29) | |
3973 | #define VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE vxge_mBIT(34) | |
3974 | #define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE vxge_mBIT(35) | |
3975 | #define VXGE_HW_PRC_CFG1_GREEDY_RETURN vxge_mBIT(36) | |
3976 | #define VXGE_HW_PRC_CFG1_QUICK_SHOT vxge_mBIT(37) | |
3977 | #define VXGE_HW_PRC_CFG1_RX_TIMER_CI vxge_mBIT(39) | |
3978 | #define VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vxge_vBIT(val, 40, 2) | |
3979 | u8 unused00a60[0x00a60-0x00a50]; | |
3980 | ||
3981 | /*0x00a60*/ u64 prc_cfg4; | |
3982 | #define VXGE_HW_PRC_CFG4_IN_SVC vxge_mBIT(7) | |
3983 | #define VXGE_HW_PRC_CFG4_RING_MODE(val) vxge_vBIT(val, 14, 2) | |
3984 | #define VXGE_HW_PRC_CFG4_RXD_NO_SNOOP vxge_mBIT(22) | |
3985 | #define VXGE_HW_PRC_CFG4_FRM_NO_SNOOP vxge_mBIT(23) | |
3986 | #define VXGE_HW_PRC_CFG4_RTH_DISABLE vxge_mBIT(31) | |
3987 | #define VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP vxge_mBIT(32) | |
3988 | #define VXGE_HW_PRC_CFG4_SIGNAL_BENIGN_OVFLW vxge_mBIT(36) | |
3989 | #define VXGE_HW_PRC_CFG4_BIMODAL_INTERRUPT vxge_mBIT(37) | |
3990 | #define VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL(val) vxge_vBIT(val, 40, 24) | |
3991 | /*0x00a68*/ u64 prc_cfg5; | |
3992 | #define VXGE_HW_PRC_CFG5_RXD0_ADD(val) vxge_vBIT(val, 0, 61) | |
3993 | /*0x00a70*/ u64 prc_cfg6; | |
3994 | #define VXGE_HW_PRC_CFG6_FRM_PAD_EN vxge_mBIT(0) | |
3995 | #define VXGE_HW_PRC_CFG6_QSIZE_ALIGNED_RXD vxge_mBIT(2) | |
3996 | #define VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN vxge_mBIT(5) | |
3997 | #define VXGE_HW_PRC_CFG6_L3_CPC_TRSFR_CODE_EN vxge_mBIT(8) | |
3998 | #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN vxge_mBIT(9) | |
3999 | #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9) | |
4000 | #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9) | |
4001 | /*0x00a78*/ u64 prc_cfg7; | |
4002 | #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2) | |
4003 | #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) | |
4004 | #define VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN vxge_mBIT(12) | |
4005 | #define VXGE_HW_PRC_CFG7_NO_HDR_SEPARATION vxge_mBIT(14) | |
4006 | #define VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vxge_vBIT(val, 20, 4) | |
4007 | #define VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK(val) vxge_vBIT(val, 27, 5) | |
4008 | /*0x00a80*/ u64 tim_dest_addr; | |
4009 | #define VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vxge_vBIT(val, 0, 64) | |
4010 | /*0x00a88*/ u64 prc_rxd_doorbell; | |
4011 | #define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val) vxge_vBIT(val, 48, 16) | |
4012 | /*0x00a90*/ u64 rqa_prty_for_vp; | |
4013 | #define VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vxge_vBIT(val, 59, 5) | |
4014 | /*0x00a98*/ u64 rxdmem_size; | |
4015 | #define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val) vxge_vBIT(val, 51, 13) | |
4016 | /*0x00aa0*/ u64 frm_in_progress_cnt; | |
4017 | #define VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val) \ | |
4018 | vxge_vBIT(val, 59, 5) | |
4019 | /*0x00aa8*/ u64 rx_multi_cast_stats; | |
4020 | #define VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vxge_vBIT(val, 48, 16) | |
4021 | /*0x00ab0*/ u64 rx_frm_transferred; | |
4022 | #define VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) \ | |
4023 | vxge_vBIT(val, 32, 32) | |
4024 | /*0x00ab8*/ u64 rxd_returned; | |
4025 | #define VXGE_HW_RXD_RETURNED_RXD_RETURNED(val) vxge_vBIT(val, 48, 16) | |
4026 | u8 unused00c00[0x00c00-0x00ac0]; | |
4027 | ||
4028 | /*0x00c00*/ u64 kdfc_fifo_trpl_partition; | |
4029 | #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val) vxge_vBIT(val, 17, 15) | |
4030 | #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15) | |
4031 | #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val) vxge_vBIT(val, 49, 15) | |
4032 | /*0x00c08*/ u64 kdfc_fifo_trpl_ctrl; | |
4033 | #define VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE vxge_mBIT(7) | |
4034 | /*0x00c10*/ u64 kdfc_trpl_fifo_0_ctrl; | |
4035 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val) vxge_vBIT(val, 14, 2) | |
4036 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN vxge_mBIT(22) | |
4037 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN vxge_mBIT(23) | |
4038 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) | |
4039 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC vxge_mBIT(28) | |
4040 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD vxge_mBIT(29) | |
4041 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP vxge_mBIT(30) | |
4042 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD vxge_mBIT(31) | |
4043 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) | |
4044 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) | |
4045 | #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) | |
4046 | /*0x00c18*/ u64 kdfc_trpl_fifo_1_ctrl; | |
4047 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE(val) vxge_vBIT(val, 14, 2) | |
4048 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN vxge_mBIT(22) | |
4049 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN vxge_mBIT(23) | |
4050 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) | |
4051 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC vxge_mBIT(28) | |
4052 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD vxge_mBIT(29) | |
4053 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP vxge_mBIT(30) | |
4054 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD vxge_mBIT(31) | |
4055 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) | |
4056 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) | |
4057 | #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) | |
4058 | /*0x00c20*/ u64 kdfc_trpl_fifo_2_ctrl; | |
4059 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN vxge_mBIT(22) | |
4060 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN vxge_mBIT(23) | |
4061 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val) vxge_vBIT(val, 26, 2) | |
4062 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC vxge_mBIT(28) | |
4063 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD vxge_mBIT(29) | |
4064 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP vxge_mBIT(30) | |
4065 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD vxge_mBIT(31) | |
4066 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT(val) vxge_vBIT(val, 32, 8) | |
4067 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val) vxge_vBIT(val, 41, 7) | |
4068 | #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val) vxge_vBIT(val, 48, 16) | |
4069 | /*0x00c28*/ u64 kdfc_trpl_fifo_0_wb_address; | |
4070 | #define VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) | |
4071 | /*0x00c30*/ u64 kdfc_trpl_fifo_1_wb_address; | |
4072 | #define VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) | |
4073 | /*0x00c38*/ u64 kdfc_trpl_fifo_2_wb_address; | |
4074 | #define VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val) vxge_vBIT(val, 0, 64) | |
4075 | /*0x00c40*/ u64 kdfc_trpl_fifo_offset; | |
4076 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val) vxge_vBIT(val, 1, 15) | |
4077 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15) | |
4078 | #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val) vxge_vBIT(val, 33, 15) | |
4079 | /*0x00c48*/ u64 kdfc_drbl_triplet_total; | |
4080 | #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) \ | |
4081 | vxge_vBIT(val, 17, 15) | |
4082 | u8 unused00c60[0x00c60-0x00c50]; | |
4083 | ||
4084 | /*0x00c60*/ u64 usdc_drbl_ctrl; | |
4085 | #define VXGE_HW_USDC_DRBL_CTRL_FLIP_EN vxge_mBIT(22) | |
4086 | #define VXGE_HW_USDC_DRBL_CTRL_SWAP_EN vxge_mBIT(23) | |
4087 | /*0x00c68*/ u64 usdc_vp_ready; | |
4088 | #define VXGE_HW_USDC_VP_READY_USDC_HTN_READY vxge_mBIT(7) | |
4089 | #define VXGE_HW_USDC_VP_READY_USDC_SRQ_READY vxge_mBIT(15) | |
4090 | #define VXGE_HW_USDC_VP_READY_USDC_CQRQ_READY vxge_mBIT(23) | |
4091 | /*0x00c70*/ u64 kdfc_status; | |
4092 | #define VXGE_HW_KDFC_STATUS_KDFC_WRR_0_READY vxge_mBIT(0) | |
4093 | #define VXGE_HW_KDFC_STATUS_KDFC_WRR_1_READY vxge_mBIT(1) | |
4094 | #define VXGE_HW_KDFC_STATUS_KDFC_WRR_2_READY vxge_mBIT(2) | |
4095 | u8 unused00c80[0x00c80-0x00c78]; | |
4096 | ||
4097 | /*0x00c80*/ u64 xmac_rpa_vcfg; | |
4098 | #define VXGE_HW_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH vxge_mBIT(3) | |
4099 | #define VXGE_HW_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH vxge_mBIT(7) | |
4100 | #define VXGE_HW_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH vxge_mBIT(11) | |
4101 | #define VXGE_HW_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH vxge_mBIT(15) | |
4102 | #define VXGE_HW_XMAC_RPA_VCFG_L4_INCL_CF vxge_mBIT(19) | |
4103 | #define VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG vxge_mBIT(23) | |
4104 | /*0x00c88*/ u64 rxmac_vcfg0; | |
4105 | #define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val) vxge_vBIT(val, 2, 14) | |
4106 | #define VXGE_HW_RXMAC_VCFG0_RTS_USE_MIN_LEN vxge_mBIT(19) | |
4107 | #define VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val) vxge_vBIT(val, 26, 14) | |
4108 | #define VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN vxge_mBIT(43) | |
4109 | #define VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN vxge_mBIT(47) | |
4110 | #define VXGE_HW_RXMAC_VCFG0_BCAST_EN vxge_mBIT(51) | |
4111 | #define VXGE_HW_RXMAC_VCFG0_ALL_VID_EN vxge_mBIT(55) | |
4112 | /*0x00c90*/ u64 rxmac_vcfg1; | |
4113 | #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val) vxge_vBIT(val, 42, 2) | |
4114 | #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE vxge_mBIT(47) | |
4115 | #define VXGE_HW_RXMAC_VCFG1_CONTRIB_L2_FLOW vxge_mBIT(51) | |
4116 | /*0x00c98*/ u64 rts_access_steer_ctrl; | |
4117 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val) vxge_vBIT(val, 1, 7) | |
4118 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4) | |
4119 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE vxge_mBIT(15) | |
4120 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL vxge_mBIT(23) | |
4121 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL vxge_mBIT(27) | |
4122 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS vxge_mBIT(0) | |
4123 | #define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val) vxge_vBIT(val, 40, 8) | |
4124 | /*0x00ca0*/ u64 rts_access_steer_data0; | |
4125 | #define VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA(val) vxge_vBIT(val, 0, 64) | |
4126 | /*0x00ca8*/ u64 rts_access_steer_data1; | |
4127 | #define VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA(val) vxge_vBIT(val, 0, 64) | |
4128 | u8 unused00d00[0x00d00-0x00cb0]; | |
4129 | ||
4130 | /*0x00d00*/ u64 xmac_vsport_choice; | |
4131 | #define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val) vxge_vBIT(val, 3, 5) | |
4132 | /*0x00d08*/ u64 xmac_stats_cfg; | |
4133 | /*0x00d10*/ u64 xmac_stats_access_cmd; | |
4134 | #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(val) vxge_vBIT(val, 6, 2) | |
4135 | #define VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE vxge_mBIT(15) | |
4136 | #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val) vxge_vBIT(val, 32, 8) | |
4137 | /*0x00d18*/ u64 xmac_stats_access_data; | |
4138 | #define VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vxge_vBIT(val, 0, 64) | |
4139 | /*0x00d20*/ u64 asic_ntwk_vp_ctrl; | |
4140 | #define VXGE_HW_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK vxge_mBIT(3) | |
4141 | #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO vxge_mBIT(55) | |
4142 | #define VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM vxge_mBIT(63) | |
4143 | u8 unused00d30[0x00d30-0x00d28]; | |
4144 | ||
4145 | /*0x00d30*/ u64 xgmac_vp_int_status; | |
4146 | #define VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT \ | |
4147 | vxge_mBIT(3) | |
4148 | /*0x00d38*/ u64 xgmac_vp_int_mask; | |
4149 | /*0x00d40*/ u64 asic_ntwk_vp_err_reg; | |
4150 | #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT vxge_mBIT(3) | |
4151 | #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK vxge_mBIT(7) | |
4152 | #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR \ | |
4153 | vxge_mBIT(11) | |
4154 | #define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR \ | |
4155 | vxge_mBIT(15) | |
4156 | #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT \ | |
4157 | vxge_mBIT(19) | |
4158 | #define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK vxge_mBIT(23) | |
4159 | /*0x00d48*/ u64 asic_ntwk_vp_err_mask; | |
4160 | /*0x00d50*/ u64 asic_ntwk_vp_err_alarm; | |
4161 | u8 unused00d80[0x00d80-0x00d58]; | |
4162 | ||
4163 | /*0x00d80*/ u64 rtdma_bw_ctrl; | |
4164 | #define VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN vxge_mBIT(39) | |
4165 | #define VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW(val) vxge_vBIT(val, 46, 18) | |
4166 | /*0x00d88*/ u64 rtdma_rd_optimization_ctrl; | |
4167 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT vxge_mBIT(3) | |
4168 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vxge_vBIT(val, 6, 2) | |
4169 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8) | |
4170 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE vxge_mBIT(19) | |
4171 | #define VXGE_HW_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ | |
4172 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val) \ | |
4173 | vxge_vBIT(val, 21, 3) | |
4174 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN vxge_mBIT(28) | |
4175 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val) \ | |
4176 | vxge_vBIT(val, 29, 3) | |
4177 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN vxge_mBIT(35) | |
4178 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) \ | |
4179 | vxge_vBIT(val, 37, 3) | |
4180 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE vxge_mBIT(43) | |
4181 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val) \ | |
4182 | vxge_vBIT(val, 51, 5) | |
4183 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN vxge_mBIT(59) | |
4184 | #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) \ | |
4185 | vxge_vBIT(val, 61, 3) | |
4186 | /*0x00d90*/ u64 pda_pcc_job_monitor; | |
4187 | #define VXGE_HW_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS vxge_mBIT(7) | |
4188 | /*0x00d98*/ u64 tx_protocol_assist_cfg; | |
4189 | #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN vxge_mBIT(6) | |
4190 | #define VXGE_HW_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING vxge_mBIT(7) | |
4191 | u8 unused01000[0x01000-0x00da0]; | |
4192 | ||
4193 | /*0x01000*/ u64 tim_cfg1_int_num[4]; | |
4194 | #define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val) vxge_vBIT(val, 6, 26) | |
4195 | #define VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN vxge_mBIT(35) | |
4196 | #define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN vxge_mBIT(36) | |
4197 | #define VXGE_HW_TIM_CFG1_INT_NUM_TXD_CNT_EN vxge_mBIT(37) | |
4198 | #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC vxge_mBIT(38) | |
4199 | #define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI vxge_mBIT(39) | |
4200 | #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val) vxge_vBIT(val, 41, 7) | |
4201 | #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val) vxge_vBIT(val, 49, 7) | |
4202 | #define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val) vxge_vBIT(val, 57, 7) | |
4203 | /*0x01020*/ u64 tim_cfg2_int_num[4]; | |
4204 | #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val) vxge_vBIT(val, 0, 16) | |
4205 | #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16) | |
4206 | #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val) vxge_vBIT(val, 32, 16) | |
4207 | #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val) vxge_vBIT(val, 48, 16) | |
4208 | /*0x01040*/ u64 tim_cfg3_int_num[4]; | |
4209 | #define VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI vxge_mBIT(0) | |
4210 | #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val) vxge_vBIT(val, 1, 4) | |
4211 | #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26) | |
4212 | #define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val) vxge_vBIT(val, 32, 6) | |
4213 | #define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val) vxge_vBIT(val, 38, 26) | |
4214 | /*0x01060*/ u64 tim_wrkld_clc; | |
4215 | #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val) vxge_vBIT(val, 0, 32) | |
4216 | #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5) | |
4217 | #define VXGE_HW_TIM_WRKLD_CLC_CNT_FRM_BYTE vxge_mBIT(40) | |
4218 | #define VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(val) vxge_vBIT(val, 41, 2) | |
4219 | #define VXGE_HW_TIM_WRKLD_CLC_CNT_LNK_EN vxge_mBIT(43) | |
4220 | #define VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL(val) vxge_vBIT(val, 57, 7) | |
4221 | /*0x01068*/ u64 tim_bitmap; | |
4222 | #define VXGE_HW_TIM_BITMAP_MASK(val) vxge_vBIT(val, 0, 32) | |
4223 | #define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN vxge_mBIT(32) | |
4224 | #define VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN vxge_mBIT(33) | |
4225 | /*0x01070*/ u64 tim_ring_assn; | |
4226 | #define VXGE_HW_TIM_RING_ASSN_INT_NUM(val) vxge_vBIT(val, 6, 2) | |
4227 | /*0x01078*/ u64 tim_remap; | |
4228 | #define VXGE_HW_TIM_REMAP_TX_EN vxge_mBIT(5) | |
4229 | #define VXGE_HW_TIM_REMAP_RX_EN vxge_mBIT(6) | |
4230 | #define VXGE_HW_TIM_REMAP_OFFLOAD_EN vxge_mBIT(7) | |
4231 | #define VXGE_HW_TIM_REMAP_TO_VPATH_NUM(val) vxge_vBIT(val, 11, 5) | |
4232 | /*0x01080*/ u64 tim_vpath_map; | |
4233 | #define VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT(val) vxge_vBIT(val, 0, 32) | |
4234 | /*0x01088*/ u64 tim_pci_cfg; | |
4235 | #define VXGE_HW_TIM_PCI_CFG_ADD_PAD vxge_mBIT(7) | |
4236 | #define VXGE_HW_TIM_PCI_CFG_NO_SNOOP vxge_mBIT(15) | |
4237 | #define VXGE_HW_TIM_PCI_CFG_RELAXED vxge_mBIT(23) | |
4238 | #define VXGE_HW_TIM_PCI_CFG_CTL_STR vxge_mBIT(31) | |
4239 | u8 unused01100[0x01100-0x01090]; | |
4240 | ||
4241 | /*0x01100*/ u64 sgrp_assign; | |
4242 | #define VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN(val) vxge_vBIT(val, 0, 64) | |
4243 | /*0x01108*/ u64 sgrp_aoa_and_result; | |
4244 | #define VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val) \ | |
4245 | vxge_vBIT(val, 0, 64) | |
4246 | /*0x01110*/ u64 rpe_pci_cfg; | |
4247 | #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE vxge_mBIT(7) | |
4248 | #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE vxge_mBIT(8) | |
4249 | #define VXGE_HW_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE vxge_mBIT(9) | |
4250 | #define VXGE_HW_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE vxge_mBIT(10) | |
4251 | #define VXGE_HW_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE vxge_mBIT(11) | |
4252 | #define VXGE_HW_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE vxge_mBIT(12) | |
4253 | #define VXGE_HW_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE vxge_mBIT(13) | |
4254 | #define VXGE_HW_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE vxge_mBIT(14) | |
4255 | #define VXGE_HW_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE vxge_mBIT(15) | |
4256 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_DATA vxge_mBIT(18) | |
4257 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_NONLL_CQE vxge_mBIT(19) | |
4258 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_LL_CQE vxge_mBIT(20) | |
4259 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRQ_IR vxge_mBIT(21) | |
4260 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQSQ_IR vxge_mBIT(22) | |
4261 | #define VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRR_IR vxge_mBIT(23) | |
4262 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_DATA vxge_mBIT(26) | |
4263 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_NONLL_CQE vxge_mBIT(27) | |
4264 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_LL_CQE vxge_mBIT(28) | |
4265 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRQ_IR vxge_mBIT(29) | |
4266 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQSQ_IR vxge_mBIT(30) | |
4267 | #define VXGE_HW_RPE_PCI_CFG_RELAXED_CQRR_IR vxge_mBIT(31) | |
4268 | /*0x01118*/ u64 rpe_lro_cfg; | |
4269 | #define VXGE_HW_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR vxge_mBIT(7) | |
4270 | #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG vxge_mBIT(11) | |
4271 | #define VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG vxge_mBIT(15) | |
4272 | #define VXGE_HW_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE vxge_mBIT(23) | |
4273 | /*0x01120*/ u64 pe_mr2vp_ack_blk_limit; | |
4274 | #define VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val) vxge_vBIT(val, 32, 32) | |
4275 | /*0x01128*/ u64 pe_mr2vp_rirr_lirr_blk_limit; | |
4276 | #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val) \ | |
4277 | vxge_vBIT(val, 0, 32) | |
4278 | #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \ | |
4279 | vxge_vBIT(val, 32, 32) | |
4280 | /*0x01130*/ u64 txpe_pci_nce_cfg; | |
4281 | #define VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vxge_vBIT(val, 0, 32) | |
4282 | #define VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE vxge_mBIT(55) | |
4283 | #define VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI vxge_mBIT(63) | |
4284 | u8 unused01180[0x01180-0x01138]; | |
4285 | ||
4286 | /*0x01180*/ u64 msg_qpad_en_cfg; | |
4287 | #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_BWR_READ vxge_mBIT(3) | |
4288 | #define VXGE_HW_MSG_QPAD_EN_CFG_DMQ_BWR_READ vxge_mBIT(7) | |
4289 | #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_READ vxge_mBIT(11) | |
4290 | #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_READ vxge_mBIT(15) | |
4291 | #define VXGE_HW_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE vxge_mBIT(19) | |
4292 | #define VXGE_HW_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE vxge_mBIT(23) | |
4293 | #define VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE vxge_mBIT(27) | |
4294 | #define VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE vxge_mBIT(31) | |
4295 | /*0x01188*/ u64 msg_pci_cfg; | |
4296 | #define VXGE_HW_MSG_PCI_CFG_GENDMA_NO_SNOOP vxge_mBIT(3) | |
4297 | #define VXGE_HW_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP vxge_mBIT(7) | |
4298 | #define VXGE_HW_MSG_PCI_CFG_UMQ_NO_SNOOP vxge_mBIT(11) | |
4299 | #define VXGE_HW_MSG_PCI_CFG_DMQ_NO_SNOOP vxge_mBIT(15) | |
4300 | /*0x01190*/ u64 umqdmq_ir_init; | |
4301 | #define VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vxge_vBIT(val, 0, 64) | |
4302 | /*0x01198*/ u64 dmq_ir_int; | |
4303 | #define VXGE_HW_DMQ_IR_INT_IMMED_ENABLE vxge_mBIT(6) | |
4304 | #define VXGE_HW_DMQ_IR_INT_EVENT_ENABLE vxge_mBIT(7) | |
4305 | #define VXGE_HW_DMQ_IR_INT_NUMBER(val) vxge_vBIT(val, 9, 7) | |
4306 | #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16) | |
4307 | /*0x011a0*/ u64 dmq_bwr_init_add; | |
4308 | #define VXGE_HW_DMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) | |
4309 | /*0x011a8*/ u64 dmq_bwr_init_byte; | |
4310 | #define VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) | |
4311 | /*0x011b0*/ u64 dmq_ir; | |
4312 | #define VXGE_HW_DMQ_IR_POLICY(val) vxge_vBIT(val, 0, 8) | |
4313 | /*0x011b8*/ u64 umq_int; | |
4314 | #define VXGE_HW_UMQ_INT_IMMED_ENABLE vxge_mBIT(6) | |
4315 | #define VXGE_HW_UMQ_INT_EVENT_ENABLE vxge_mBIT(7) | |
4316 | #define VXGE_HW_UMQ_INT_NUMBER(val) vxge_vBIT(val, 9, 7) | |
4317 | #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16) | |
4318 | /*0x011c0*/ u64 umq_mr2vp_bwr_pfch_init; | |
4319 | #define VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val) vxge_vBIT(val, 0, 8) | |
4320 | /*0x011c8*/ u64 umq_bwr_pfch_ctrl; | |
4321 | #define VXGE_HW_UMQ_BWR_PFCH_CTRL_POLL_EN vxge_mBIT(3) | |
4322 | /*0x011d0*/ u64 umq_mr2vp_bwr_eol; | |
4323 | #define VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val) vxge_vBIT(val, 32, 32) | |
4324 | /*0x011d8*/ u64 umq_bwr_init_add; | |
4325 | #define VXGE_HW_UMQ_BWR_INIT_ADD_HOST(val) vxge_vBIT(val, 0, 64) | |
4326 | /*0x011e0*/ u64 umq_bwr_init_byte; | |
4327 | #define VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT(val) vxge_vBIT(val, 0, 32) | |
4328 | /*0x011e8*/ u64 gendma_int; | |
4329 | #define VXGE_HW_GENDMA_INT_IMMED_ENABLE vxge_mBIT(6) | |
4330 | #define VXGE_HW_GENDMA_INT_EVENT_ENABLE vxge_mBIT(7) | |
4331 | #define VXGE_HW_GENDMA_INT_NUMBER(val) vxge_vBIT(val, 9, 7) | |
4332 | #define VXGE_HW_GENDMA_INT_BITMAP(val) vxge_vBIT(val, 16, 16) | |
4333 | /*0x011f0*/ u64 umqdmq_ir_init_notify; | |
4334 | #define VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE vxge_mBIT(3) | |
4335 | /*0x011f8*/ u64 dmq_init_notify; | |
4336 | #define VXGE_HW_DMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) | |
4337 | /*0x01200*/ u64 umq_init_notify; | |
4338 | #define VXGE_HW_UMQ_INIT_NOTIFY_PULSE vxge_mBIT(3) | |
4339 | u8 unused01380[0x01380-0x01208]; | |
4340 | ||
4341 | /*0x01380*/ u64 tpa_cfg; | |
4342 | #define VXGE_HW_TPA_CFG_IGNORE_FRAME_ERR vxge_mBIT(3) | |
4343 | #define VXGE_HW_TPA_CFG_IPV6_STOP_SEARCHING vxge_mBIT(7) | |
4344 | #define VXGE_HW_TPA_CFG_L4_PSHDR_PRESENT vxge_mBIT(11) | |
4345 | #define VXGE_HW_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS vxge_mBIT(15) | |
4346 | u8 unused01400[0x01400-0x01388]; | |
4347 | ||
4348 | /*0x01400*/ u64 tx_vp_reset_discarded_frms; | |
4349 | #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val) \ | |
4350 | vxge_vBIT(val, 48, 16) | |
4351 | u8 unused01480[0x01480-0x01408]; | |
4352 | ||
4353 | /*0x01480*/ u64 fau_rpa_vcfg; | |
4354 | #define VXGE_HW_FAU_RPA_VCFG_L4_COMP_CSUM vxge_mBIT(7) | |
4355 | #define VXGE_HW_FAU_RPA_VCFG_L3_INCL_CF vxge_mBIT(11) | |
4356 | #define VXGE_HW_FAU_RPA_VCFG_L3_COMP_CSUM vxge_mBIT(15) | |
4357 | u8 unused014d0[0x014d0-0x01488]; | |
4358 | ||
4359 | /*0x014d0*/ u64 dbg_stats_rx_mpa; | |
4360 | #define VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vxge_vBIT(val, 0, 16) | |
4361 | #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16) | |
4362 | #define VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vxge_vBIT(val, 32, 16) | |
4363 | /*0x014d8*/ u64 dbg_stats_rx_fau; | |
4364 | #define VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vxge_vBIT(val, 0, 16) | |
4365 | #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \ | |
4366 | vxge_vBIT(val, 16, 16) | |
4367 | #define VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) \ | |
4368 | vxge_vBIT(val, 32, 32) | |
4369 | u8 unused014f0[0x014f0-0x014e0]; | |
4370 | ||
4371 | /*0x014f0*/ u64 fbmc_vp_rdy; | |
4372 | #define VXGE_HW_FBMC_VP_RDY_QUEUE_SPAV_FM vxge_mBIT(0) | |
4373 | u8 unused01e00[0x01e00-0x014f8]; | |
4374 | ||
4375 | /*0x01e00*/ u64 vpath_pcipif_int_status; | |
4376 | #define \ | |
4377 | VXGE_HW_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_SRPCIM_MSG_TO_VPATH_INT \ | |
4378 | vxge_mBIT(3) | |
4379 | #define VXGE_HW_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_VPATH_SPARE_R1_INT \ | |
4380 | vxge_mBIT(7) | |
4381 | /*0x01e08*/ u64 vpath_pcipif_int_mask; | |
4382 | u8 unused01e20[0x01e20-0x01e10]; | |
4383 | ||
4384 | /*0x01e20*/ u64 srpcim_msg_to_vpath_reg; | |
4385 | #define VXGE_HW_SRPCIM_MSG_TO_VPATH_REG_SWIF_SRPCIM_TO_VPATH_RMSG_INT \ | |
4386 | vxge_mBIT(3) | |
4387 | /*0x01e28*/ u64 srpcim_msg_to_vpath_mask; | |
4388 | /*0x01e30*/ u64 srpcim_msg_to_vpath_alarm; | |
4389 | u8 unused01ea0[0x01ea0-0x01e38]; | |
4390 | ||
4391 | /*0x01ea0*/ u64 vpath_to_srpcim_wmsg; | |
4392 | #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG(val) \ | |
4393 | vxge_vBIT(val, 0, 64) | |
4394 | /*0x01ea8*/ u64 vpath_to_srpcim_wmsg_trig; | |
4395 | #define VXGE_HW_VPATH_TO_SRPCIM_WMSG_TRIG_VPATH_TO_SRPCIM_WMSG_TRIG \ | |
4396 | vxge_mBIT(0) | |
4397 | u8 unused02000[0x02000-0x01eb0]; | |
4398 | ||
4399 | /*0x02000*/ u64 vpath_general_int_status; | |
4400 | #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT vxge_mBIT(3) | |
4401 | #define VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT vxge_mBIT(7) | |
4402 | #define VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT vxge_mBIT(15) | |
4403 | #define VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT vxge_mBIT(19) | |
4404 | /*0x02008*/ u64 vpath_general_int_mask; | |
4405 | #define VXGE_HW_VPATH_GENERAL_INT_MASK_PIC_INT vxge_mBIT(3) | |
4406 | #define VXGE_HW_VPATH_GENERAL_INT_MASK_PCI_INT vxge_mBIT(7) | |
4407 | #define VXGE_HW_VPATH_GENERAL_INT_MASK_WRDMA_INT vxge_mBIT(15) | |
4408 | #define VXGE_HW_VPATH_GENERAL_INT_MASK_XMAC_INT vxge_mBIT(19) | |
4409 | /*0x02010*/ u64 vpath_ppif_int_status; | |
4410 | #define VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT \ | |
4411 | vxge_mBIT(3) | |
4412 | #define VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT \ | |
4413 | vxge_mBIT(7) | |
4414 | #define VXGE_HW_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_PCI_CONFIG_INT \ | |
4415 | vxge_mBIT(11) | |
4416 | #define \ | |
4417 | VXGE_HW_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_MRPCIM_TO_VPATH_ALARM_INT \ | |
4418 | vxge_mBIT(15) | |
4419 | #define \ | |
4420 | VXGE_HW_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_SRPCIM_TO_VPATH_ALARM_INT \ | |
4421 | vxge_mBIT(19) | |
4422 | /*0x02018*/ u64 vpath_ppif_int_mask; | |
4423 | /*0x02020*/ u64 kdfcctl_errors_reg; | |
4424 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR vxge_mBIT(3) | |
4425 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR vxge_mBIT(7) | |
4426 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR vxge_mBIT(11) | |
4427 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON vxge_mBIT(15) | |
4428 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON vxge_mBIT(19) | |
4429 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON vxge_mBIT(23) | |
4430 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR vxge_mBIT(31) | |
4431 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR vxge_mBIT(35) | |
4432 | #define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR vxge_mBIT(39) | |
4433 | /*0x02028*/ u64 kdfcctl_errors_mask; | |
4434 | /*0x02030*/ u64 kdfcctl_errors_alarm; | |
4435 | u8 unused02040[0x02040-0x02038]; | |
4436 | ||
4437 | /*0x02040*/ u64 general_errors_reg; | |
4438 | #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW vxge_mBIT(3) | |
4439 | #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW vxge_mBIT(7) | |
4440 | #define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW vxge_mBIT(11) | |
4441 | #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR vxge_mBIT(15) | |
4442 | #define VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ vxge_mBIT(19) | |
4443 | #define VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS vxge_mBIT(27) | |
4444 | #define VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET vxge_mBIT(31) | |
4445 | /*0x02048*/ u64 general_errors_mask; | |
4446 | /*0x02050*/ u64 general_errors_alarm; | |
4447 | /*0x02058*/ u64 pci_config_errors_reg; | |
4448 | #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_STATUS_ERR vxge_mBIT(3) | |
4449 | #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_UNCOR_ERR vxge_mBIT(7) | |
4450 | #define VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_COR_ERR vxge_mBIT(11) | |
4451 | /*0x02060*/ u64 pci_config_errors_mask; | |
4452 | /*0x02068*/ u64 pci_config_errors_alarm; | |
4453 | /*0x02070*/ u64 mrpcim_to_vpath_alarm_reg; | |
4454 | #define VXGE_HW_MRPCIM_TO_VPATH_ALARM_REG_PPIF_MRPCIM_TO_VPATH_ALARM \ | |
4455 | vxge_mBIT(3) | |
4456 | /*0x02078*/ u64 mrpcim_to_vpath_alarm_mask; | |
4457 | /*0x02080*/ u64 mrpcim_to_vpath_alarm_alarm; | |
4458 | /*0x02088*/ u64 srpcim_to_vpath_alarm_reg; | |
4459 | #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM(val) \ | |
4460 | vxge_vBIT(val, 0, 17) | |
4461 | /*0x02090*/ u64 srpcim_to_vpath_alarm_mask; | |
4462 | /*0x02098*/ u64 srpcim_to_vpath_alarm_alarm; | |
4463 | u8 unused02108[0x02108-0x020a0]; | |
4464 | ||
4465 | /*0x02108*/ u64 kdfcctl_status; | |
4466 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val) vxge_vBIT(val, 0, 8) | |
4467 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8) | |
4468 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val) vxge_vBIT(val, 16, 8) | |
4469 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val) vxge_vBIT(val, 24, 8) | |
4470 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val) vxge_vBIT(val, 32, 8) | |
4471 | #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val) vxge_vBIT(val, 40, 8) | |
4472 | /*0x02110*/ u64 rsthdlr_status; | |
4473 | #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET vxge_mBIT(3) | |
4474 | #define VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vxge_vBIT(val, 6, 2) | |
4475 | /*0x02118*/ u64 fifo0_status; | |
4476 | #define VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val) vxge_vBIT(val, 0, 12) | |
4477 | /*0x02120*/ u64 fifo1_status; | |
4478 | #define VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val) vxge_vBIT(val, 0, 12) | |
4479 | /*0x02128*/ u64 fifo2_status; | |
4480 | #define VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val) vxge_vBIT(val, 0, 12) | |
4481 | u8 unused02158[0x02158-0x02130]; | |
4482 | ||
4483 | /*0x02158*/ u64 tgt_illegal_access; | |
4484 | #define VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vxge_vBIT(val, 1, 7) | |
4485 | u8 unused02200[0x02200-0x02160]; | |
4486 | ||
4487 | /*0x02200*/ u64 vpath_general_cfg1; | |
4488 | #define VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE(val) vxge_vBIT(val, 1, 3) | |
4489 | #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN vxge_mBIT(7) | |
4490 | #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_FLIPEN vxge_mBIT(11) | |
4491 | #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN vxge_mBIT(15) | |
4492 | #define VXGE_HW_VPATH_GENERAL_CFG1_CTL_FLIPEN vxge_mBIT(23) | |
4493 | #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN vxge_mBIT(51) | |
4494 | #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN vxge_mBIT(55) | |
4495 | #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN vxge_mBIT(59) | |
4496 | #define VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN vxge_mBIT(63) | |
4497 | /*0x02208*/ u64 vpath_general_cfg2; | |
4498 | #define VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val) vxge_vBIT(val, 1, 3) | |
4499 | /*0x02210*/ u64 vpath_general_cfg3; | |
4500 | #define VXGE_HW_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA vxge_mBIT(3) | |
4501 | u8 unused02220[0x02220-0x02218]; | |
4502 | ||
4503 | /*0x02220*/ u64 kdfcctl_cfg0; | |
4504 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 vxge_mBIT(1) | |
4505 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 vxge_mBIT(2) | |
4506 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2 vxge_mBIT(3) | |
4507 | #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0 vxge_mBIT(5) | |
4508 | #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1 vxge_mBIT(6) | |
4509 | #define VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2 vxge_mBIT(7) | |
4510 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0 vxge_mBIT(9) | |
4511 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1 vxge_mBIT(10) | |
4512 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2 vxge_mBIT(11) | |
4513 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0 vxge_mBIT(13) | |
4514 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1 vxge_mBIT(14) | |
4515 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2 vxge_mBIT(15) | |
4516 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0 vxge_mBIT(17) | |
4517 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1 vxge_mBIT(18) | |
4518 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2 vxge_mBIT(19) | |
4519 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0 vxge_mBIT(21) | |
4520 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1 vxge_mBIT(22) | |
4521 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2 vxge_mBIT(23) | |
4522 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0 vxge_mBIT(25) | |
4523 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1 vxge_mBIT(26) | |
4524 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2 vxge_mBIT(27) | |
4525 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0 vxge_mBIT(29) | |
4526 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1 vxge_mBIT(30) | |
4527 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2 vxge_mBIT(31) | |
4528 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0 vxge_mBIT(33) | |
4529 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1 vxge_mBIT(34) | |
4530 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2 vxge_mBIT(35) | |
4531 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0 vxge_mBIT(37) | |
4532 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1 vxge_mBIT(38) | |
4533 | #define VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2 vxge_mBIT(39) | |
4534 | ||
4535 | u8 unused02268[0x02268-0x02228]; | |
4536 | ||
4537 | /*0x02268*/ u64 stats_cfg; | |
4538 | #define VXGE_HW_STATS_CFG_START_HOST_ADDR(val) vxge_vBIT(val, 0, 57) | |
4539 | /*0x02270*/ u64 interrupt_cfg0; | |
4540 | #define VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI(val) vxge_vBIT(val, 1, 7) | |
4541 | #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7) | |
4542 | #define VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val) vxge_vBIT(val, 17, 7) | |
4543 | #define VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val) vxge_vBIT(val, 25, 7) | |
4544 | #define VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val) vxge_vBIT(val, 33, 7) | |
4545 | u8 unused02280[0x02280-0x02278]; | |
4546 | ||
4547 | /*0x02280*/ u64 interrupt_cfg2; | |
4548 | #define VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val) vxge_vBIT(val, 1, 7) | |
4549 | /*0x02288*/ u64 one_shot_vect0_en; | |
4550 | #define VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN vxge_mBIT(3) | |
4551 | /*0x02290*/ u64 one_shot_vect1_en; | |
4552 | #define VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN vxge_mBIT(3) | |
4553 | /*0x02298*/ u64 one_shot_vect2_en; | |
4554 | #define VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN vxge_mBIT(3) | |
4555 | /*0x022a0*/ u64 one_shot_vect3_en; | |
4556 | #define VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN vxge_mBIT(3) | |
4557 | u8 unused022b0[0x022b0-0x022a8]; | |
4558 | ||
4559 | /*0x022b0*/ u64 pci_config_access_cfg1; | |
4560 | #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vxge_vBIT(val, 0, 12) | |
4561 | #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 vxge_mBIT(15) | |
4562 | /*0x022b8*/ u64 pci_config_access_cfg2; | |
4563 | #define VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ vxge_mBIT(0) | |
4564 | /*0x022c0*/ u64 pci_config_access_status; | |
4565 | #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR vxge_mBIT(0) | |
4566 | #define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA(val) vxge_vBIT(val, 32, 32) | |
4567 | u8 unused02300[0x02300-0x022c8]; | |
4568 | ||
4569 | /*0x02300*/ u64 vpath_debug_stats0; | |
4570 | #define VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val) vxge_vBIT(val, 0, 32) | |
4571 | /*0x02308*/ u64 vpath_debug_stats1; | |
4572 | #define VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val) vxge_vBIT(val, 0, 32) | |
4573 | /*0x02310*/ u64 vpath_debug_stats2; | |
4574 | #define VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val) vxge_vBIT(val, 0, 32) | |
4575 | /*0x02318*/ u64 vpath_debug_stats3; | |
4576 | #define VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) \ | |
4577 | vxge_vBIT(val, 0, 64) | |
4578 | /*0x02320*/ u64 vpath_debug_stats4; | |
4579 | #define VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) \ | |
4580 | vxge_vBIT(val, 0, 64) | |
4581 | /*0x02328*/ u64 vpath_debug_stats5; | |
4582 | #define VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) | |
4583 | /*0x02330*/ u64 vpath_debug_stats6; | |
4584 | #define VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val) vxge_vBIT(val, 32, 32) | |
4585 | /*0x02338*/ u64 vpath_genstats_count01; | |
4586 | #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val) \ | |
4587 | vxge_vBIT(val, 0, 32) | |
4588 | #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \ | |
4589 | vxge_vBIT(val, 32, 32) | |
4590 | /*0x02340*/ u64 vpath_genstats_count23; | |
4591 | #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val) \ | |
4592 | vxge_vBIT(val, 0, 32) | |
4593 | #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \ | |
4594 | vxge_vBIT(val, 32, 32) | |
4595 | /*0x02348*/ u64 vpath_genstats_count4; | |
4596 | #define VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val) \ | |
4597 | vxge_vBIT(val, 32, 32) | |
4598 | /*0x02350*/ u64 vpath_genstats_count5; | |
4599 | #define VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val) \ | |
4600 | vxge_vBIT(val, 32, 32) | |
4601 | u8 unused02648[0x02648-0x02358]; | |
4602 | } __packed; | |
4603 | ||
4604 | #define VXGE_HW_EEPROM_SIZE (0x01 << 11) | |
4605 | ||
4606 | /* Capability lists */ | |
4607 | #define VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEED 0xf /* Supported Link speeds */ | |
4608 | #define VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH 0x3f0 /* Supported Link speeds. */ | |
4609 | #define VXGE_HW_PCI_EXP_LNKCAP_LW_RES 0x0 /* Reserved. */ | |
4610 | ||
4611 | #endif |