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2f7ca802 SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2007-2008 SMSC | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | *****************************************************************************/ | |
20 | ||
21 | #ifndef _SMSC95XX_H | |
22 | #define _SMSC95XX_H | |
23 | ||
24 | /* Tx command words */ | |
25 | #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) | |
26 | #define TX_CMD_A_FIRST_SEG_ (0x00002000) | |
27 | #define TX_CMD_A_LAST_SEG_ (0x00001000) | |
28 | #define TX_CMD_A_BUF_SIZE_ (0x000007FF) | |
29 | ||
30 | #define TX_CMD_B_CSUM_ENABLE (0x00004000) | |
31 | #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) | |
32 | #define TX_CMD_B_DISABLE_PADDING_ (0x00001000) | |
33 | #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) | |
34 | ||
35 | /* Rx status word */ | |
36 | #define RX_STS_FF_ (0x40000000) /* Filter Fail */ | |
37 | #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */ | |
38 | #define RX_STS_ES_ (0x00008000) /* Error Summary */ | |
39 | #define RX_STS_BF_ (0x00002000) /* Broadcast Frame */ | |
40 | #define RX_STS_LE_ (0x00001000) /* Length Error */ | |
41 | #define RX_STS_RF_ (0x00000800) /* Runt Frame */ | |
42 | #define RX_STS_MF_ (0x00000400) /* Multicast Frame */ | |
43 | #define RX_STS_TL_ (0x00000080) /* Frame too long */ | |
44 | #define RX_STS_CS_ (0x00000040) /* Collision Seen */ | |
45 | #define RX_STS_FT_ (0x00000020) /* Frame Type */ | |
46 | #define RX_STS_RW_ (0x00000010) /* Receive Watchdog */ | |
47 | #define RX_STS_ME_ (0x00000008) /* Mii Error */ | |
48 | #define RX_STS_DB_ (0x00000004) /* Dribbling */ | |
49 | #define RX_STS_CRC_ (0x00000002) /* CRC Error */ | |
50 | ||
51 | /* SCSRs */ | |
52 | #define ID_REV (0x00) | |
53 | #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) | |
54 | #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) | |
55 | #define ID_REV_CHIP_ID_9500_ (0x9500) | |
bbd9f9ee SG |
56 | #define ID_REV_CHIP_ID_9500A_ (0x9E00) |
57 | #define ID_REV_CHIP_ID_9512_ (0xEC00) | |
9ebca507 SG |
58 | #define ID_REV_CHIP_ID_9530_ (0x9530) |
59 | #define ID_REV_CHIP_ID_89530_ (0x9E08) | |
60 | #define ID_REV_CHIP_ID_9730_ (0x9730) | |
2f7ca802 SG |
61 | |
62 | #define INT_STS (0x08) | |
63 | #define INT_STS_TX_STOP_ (0x00020000) | |
64 | #define INT_STS_RX_STOP_ (0x00010000) | |
65 | #define INT_STS_PHY_INT_ (0x00008000) | |
66 | #define INT_STS_TXE_ (0x00004000) | |
67 | #define INT_STS_TDFU_ (0x00002000) | |
68 | #define INT_STS_TDFO_ (0x00001000) | |
69 | #define INT_STS_RXDF_ (0x00000800) | |
70 | #define INT_STS_GPIOS_ (0x000007FF) | |
4436761b | 71 | #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) |
2f7ca802 SG |
72 | |
73 | #define RX_CFG (0x0C) | |
74 | #define RX_FIFO_FLUSH_ (0x00000001) | |
75 | ||
76 | #define TX_CFG (0x10) | |
77 | #define TX_CFG_ON_ (0x00000004) | |
78 | #define TX_CFG_STOP_ (0x00000002) | |
79 | #define TX_CFG_FIFO_FLUSH_ (0x00000001) | |
80 | ||
81 | #define HW_CFG (0x14) | |
82 | #define HW_CFG_BIR_ (0x00001000) | |
83 | #define HW_CFG_LEDB_ (0x00000800) | |
84 | #define HW_CFG_RXDOFF_ (0x00000600) | |
85 | #define HW_CFG_DRP_ (0x00000040) | |
86 | #define HW_CFG_MEF_ (0x00000020) | |
87 | #define HW_CFG_LRST_ (0x00000008) | |
88 | #define HW_CFG_PSEL_ (0x00000004) | |
89 | #define HW_CFG_BCE_ (0x00000002) | |
90 | #define HW_CFG_SRST_ (0x00000001) | |
91 | ||
b5a04475 SG |
92 | #define RX_FIFO_INF (0x18) |
93 | ||
2f7ca802 | 94 | #define PM_CTRL (0x20) |
b5a04475 | 95 | #define PM_CTL_RES_CLR_WKP_STS (0x00000200) |
2f7ca802 SG |
96 | #define PM_CTL_DEV_RDY_ (0x00000080) |
97 | #define PM_CTL_SUS_MODE_ (0x00000060) | |
98 | #define PM_CTL_SUS_MODE_0 (0x00000000) | |
99 | #define PM_CTL_SUS_MODE_1 (0x00000020) | |
b5a04475 SG |
100 | #define PM_CTL_SUS_MODE_2 (0x00000040) |
101 | #define PM_CTL_SUS_MODE_3 (0x00000060) | |
2f7ca802 SG |
102 | #define PM_CTL_PHY_RST_ (0x00000010) |
103 | #define PM_CTL_WOL_EN_ (0x00000008) | |
104 | #define PM_CTL_ED_EN_ (0x00000004) | |
105 | #define PM_CTL_WUPS_ (0x00000003) | |
106 | #define PM_CTL_WUPS_NO_ (0x00000000) | |
107 | #define PM_CTL_WUPS_ED_ (0x00000001) | |
108 | #define PM_CTL_WUPS_WOL_ (0x00000002) | |
109 | #define PM_CTL_WUPS_MULTI_ (0x00000003) | |
110 | ||
111 | #define LED_GPIO_CFG (0x24) | |
f293501c SG |
112 | #define LED_GPIO_CFG_SPD_LED (0x01000000) |
113 | #define LED_GPIO_CFG_LNK_LED (0x00100000) | |
114 | #define LED_GPIO_CFG_FDX_LED (0x00010000) | |
2f7ca802 SG |
115 | |
116 | #define GPIO_CFG (0x28) | |
117 | ||
118 | #define AFC_CFG (0x2C) | |
119 | ||
120 | /* Hi watermark = 15.5Kb (~10 mtu pkts) */ | |
121 | /* low watermark = 3k (~2 mtu pkts) */ | |
122 | /* backpressure duration = ~ 350us */ | |
123 | /* Apply FC on any frame. */ | |
124 | #define AFC_CFG_DEFAULT (0x00F830A1) | |
125 | ||
126 | #define E2P_CMD (0x30) | |
127 | #define E2P_CMD_BUSY_ (0x80000000) | |
128 | #define E2P_CMD_MASK_ (0x70000000) | |
129 | #define E2P_CMD_READ_ (0x00000000) | |
130 | #define E2P_CMD_EWDS_ (0x10000000) | |
131 | #define E2P_CMD_EWEN_ (0x20000000) | |
132 | #define E2P_CMD_WRITE_ (0x30000000) | |
133 | #define E2P_CMD_WRAL_ (0x40000000) | |
134 | #define E2P_CMD_ERASE_ (0x50000000) | |
135 | #define E2P_CMD_ERAL_ (0x60000000) | |
136 | #define E2P_CMD_RELOAD_ (0x70000000) | |
137 | #define E2P_CMD_TIMEOUT_ (0x00000400) | |
138 | #define E2P_CMD_LOADED_ (0x00000200) | |
139 | #define E2P_CMD_ADDR_ (0x000001FF) | |
140 | ||
141 | #define MAX_EEPROM_SIZE (512) | |
142 | ||
143 | #define E2P_DATA (0x34) | |
144 | #define E2P_DATA_MASK_ (0x000000FF) | |
145 | ||
146 | #define BURST_CAP (0x38) | |
147 | ||
148 | #define GPIO_WAKE (0x64) | |
149 | ||
150 | #define INT_EP_CTL (0x68) | |
151 | #define INT_EP_CTL_INTEP_ (0x80000000) | |
152 | #define INT_EP_CTL_MACRTO_ (0x00080000) | |
153 | #define INT_EP_CTL_TX_STOP_ (0x00020000) | |
154 | #define INT_EP_CTL_RX_STOP_ (0x00010000) | |
155 | #define INT_EP_CTL_PHY_INT_ (0x00008000) | |
156 | #define INT_EP_CTL_TXE_ (0x00004000) | |
157 | #define INT_EP_CTL_TDFU_ (0x00002000) | |
158 | #define INT_EP_CTL_TDFO_ (0x00001000) | |
159 | #define INT_EP_CTL_RXDF_ (0x00000800) | |
160 | #define INT_EP_CTL_GPIOS_ (0x000007FF) | |
161 | ||
162 | #define BULK_IN_DLY (0x6C) | |
163 | ||
164 | /* MAC CSRs */ | |
165 | #define MAC_CR (0x100) | |
166 | #define MAC_CR_RXALL_ (0x80000000) | |
167 | #define MAC_CR_RCVOWN_ (0x00800000) | |
168 | #define MAC_CR_LOOPBK_ (0x00200000) | |
169 | #define MAC_CR_FDPX_ (0x00100000) | |
170 | #define MAC_CR_MCPAS_ (0x00080000) | |
171 | #define MAC_CR_PRMS_ (0x00040000) | |
172 | #define MAC_CR_INVFILT_ (0x00020000) | |
173 | #define MAC_CR_PASSBAD_ (0x00010000) | |
174 | #define MAC_CR_HFILT_ (0x00008000) | |
175 | #define MAC_CR_HPFILT_ (0x00002000) | |
176 | #define MAC_CR_LCOLL_ (0x00001000) | |
177 | #define MAC_CR_BCAST_ (0x00000800) | |
178 | #define MAC_CR_DISRTY_ (0x00000400) | |
179 | #define MAC_CR_PADSTR_ (0x00000100) | |
180 | #define MAC_CR_BOLMT_MASK (0x000000C0) | |
181 | #define MAC_CR_DFCHK_ (0x00000020) | |
182 | #define MAC_CR_TXEN_ (0x00000008) | |
183 | #define MAC_CR_RXEN_ (0x00000004) | |
184 | ||
185 | #define ADDRH (0x104) | |
186 | ||
187 | #define ADDRL (0x108) | |
188 | ||
189 | #define HASHH (0x10C) | |
190 | ||
191 | #define HASHL (0x110) | |
192 | ||
193 | #define MII_ADDR (0x114) | |
194 | #define MII_WRITE_ (0x02) | |
195 | #define MII_BUSY_ (0x01) | |
196 | #define MII_READ_ (0x00) /* ~of MII Write bit */ | |
197 | ||
198 | #define MII_DATA (0x118) | |
199 | ||
200 | #define FLOW (0x11C) | |
201 | #define FLOW_FCPT_ (0xFFFF0000) | |
202 | #define FLOW_FCPASS_ (0x00000004) | |
203 | #define FLOW_FCEN_ (0x00000002) | |
204 | #define FLOW_FCBSY_ (0x00000001) | |
205 | ||
206 | #define VLAN1 (0x120) | |
207 | ||
208 | #define VLAN2 (0x124) | |
209 | ||
210 | #define WUFF (0x128) | |
bbd9f9ee SG |
211 | #define LAN9500_WUFF_NUM (4) |
212 | #define LAN9500A_WUFF_NUM (8) | |
2f7ca802 SG |
213 | |
214 | #define WUCSR (0x12C) | |
bbd9f9ee | 215 | #define WUCSR_WFF_PTR_RST_ (0x80000000) |
e0e474a8 SG |
216 | #define WUCSR_GUE_ (0x00000200) |
217 | #define WUCSR_WUFR_ (0x00000040) | |
218 | #define WUCSR_MPR_ (0x00000020) | |
219 | #define WUCSR_WAKE_EN_ (0x00000004) | |
220 | #define WUCSR_MPEN_ (0x00000002) | |
2f7ca802 SG |
221 | |
222 | #define COE_CR (0x130) | |
223 | #define Tx_COE_EN_ (0x00010000) | |
224 | #define Rx_COE_MODE_ (0x00000002) | |
225 | #define Rx_COE_EN_ (0x00000001) | |
226 | ||
227 | /* Vendor-specific PHY Definitions */ | |
228 | ||
e5e3af83 SG |
229 | /* EDPD NLP / crossover time configuration (LAN9500A only) */ |
230 | #define PHY_EDPD_CONFIG (16) | |
231 | #define PHY_EDPD_CONFIG_TX_NLP_EN_ ((u16)0x8000) | |
232 | #define PHY_EDPD_CONFIG_TX_NLP_1000_ ((u16)0x0000) | |
233 | #define PHY_EDPD_CONFIG_TX_NLP_768_ ((u16)0x2000) | |
234 | #define PHY_EDPD_CONFIG_TX_NLP_512_ ((u16)0x4000) | |
235 | #define PHY_EDPD_CONFIG_TX_NLP_256_ ((u16)0x6000) | |
236 | #define PHY_EDPD_CONFIG_RX_1_NLP_ ((u16)0x1000) | |
237 | #define PHY_EDPD_CONFIG_RX_NLP_64_ ((u16)0x0000) | |
238 | #define PHY_EDPD_CONFIG_RX_NLP_256_ ((u16)0x0400) | |
239 | #define PHY_EDPD_CONFIG_RX_NLP_512_ ((u16)0x0800) | |
240 | #define PHY_EDPD_CONFIG_RX_NLP_1000_ ((u16)0x0C00) | |
241 | #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ ((u16)0x0001) | |
242 | #define PHY_EDPD_CONFIG_DEFAULT (PHY_EDPD_CONFIG_TX_NLP_EN_ | \ | |
243 | PHY_EDPD_CONFIG_TX_NLP_768_ | \ | |
244 | PHY_EDPD_CONFIG_RX_1_NLP_) | |
245 | ||
2f7ca802 SG |
246 | /* Mode Control/Status Register */ |
247 | #define PHY_MODE_CTRL_STS (17) | |
248 | #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) | |
249 | #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) | |
250 | ||
251 | #define SPECIAL_CTRL_STS (27) | |
252 | #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) | |
253 | #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) | |
254 | #define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) | |
255 | ||
256 | #define PHY_INT_SRC (29) | |
257 | #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) | |
258 | #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) | |
259 | #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) | |
260 | #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) | |
261 | ||
262 | #define PHY_INT_MASK (30) | |
263 | #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) | |
264 | #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) | |
265 | #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) | |
266 | #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) | |
267 | #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ | |
268 | PHY_INT_MASK_LINK_DOWN_) | |
269 | ||
270 | #define PHY_SPECIAL (31) | |
271 | #define PHY_SPECIAL_SPD_ ((u16)0x001C) | |
272 | #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) | |
273 | #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) | |
274 | #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) | |
275 | #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) | |
276 | ||
277 | /* USB Vendor Requests */ | |
278 | #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 | |
279 | #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 | |
280 | #define USB_VENDOR_REQUEST_GET_STATS 0xA2 | |
281 | ||
282 | /* Interrupt Endpoint status word bitfields */ | |
283 | #define INT_ENP_TX_STOP_ ((u32)BIT(17)) | |
284 | #define INT_ENP_RX_STOP_ ((u32)BIT(16)) | |
285 | #define INT_ENP_PHY_INT_ ((u32)BIT(15)) | |
286 | #define INT_ENP_TXE_ ((u32)BIT(14)) | |
287 | #define INT_ENP_TDFU_ ((u32)BIT(13)) | |
288 | #define INT_ENP_TDFO_ ((u32)BIT(12)) | |
289 | #define INT_ENP_RXDF_ ((u32)BIT(11)) | |
290 | ||
291 | #endif /* _SMSC95XX_H */ |