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ce973b14 LY |
1 | /* |
2 | * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. | |
3 | * | |
4 | * Author: Shlomi Gridish <gridish@freescale.com> | |
5 | * | |
6 | * Description: | |
7 | * Internal header file for UCC Gigabit Ethernet unit routines. | |
8 | * | |
9 | * Changelog: | |
10 | * Jun 28, 2006 Li Yang <LeoLi@freescale.com> | |
11 | * - Rearrange code and style fixes | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #ifndef __UCC_GETH_H__ | |
19 | #define __UCC_GETH_H__ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/fsl_devices.h> | |
24 | ||
25 | #include <asm/immap_qe.h> | |
26 | #include <asm/qe.h> | |
27 | ||
28 | #include <asm/ucc.h> | |
29 | #include <asm/ucc_fast.h> | |
30 | ||
728de4c9 KP |
31 | #include "ucc_geth_mii.h" |
32 | ||
ac421852 LY |
33 | #define DRV_DESC "QE UCC Gigabit Ethernet Controller" |
34 | #define DRV_NAME "ucc_geth" | |
35 | #define DRV_VERSION "1.1" | |
36 | ||
ce973b14 LY |
37 | #define NUM_TX_QUEUES 8 |
38 | #define NUM_RX_QUEUES 8 | |
39 | #define NUM_BDS_IN_PREFETCHED_BDS 4 | |
40 | #define TX_IP_OFFSET_ENTRY_MAX 8 | |
41 | #define NUM_OF_PADDRS 4 | |
42 | #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9 | |
43 | #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8 | |
44 | ||
18a8e864 LY |
45 | struct ucc_geth { |
46 | struct ucc_fast uccf; | |
ce973b14 LY |
47 | |
48 | u32 maccfg1; /* mac configuration reg. 1 */ | |
49 | u32 maccfg2; /* mac configuration reg. 2 */ | |
50 | u32 ipgifg; /* interframe gap reg. */ | |
51 | u32 hafdup; /* half-duplex reg. */ | |
52 | u8 res1[0x10]; | |
728de4c9 | 53 | u8 miimng[0x18]; /* MII management structure moved to _mii.h */ |
ce973b14 LY |
54 | u32 ifctl; /* interface control reg */ |
55 | u32 ifstat; /* interface statux reg */ | |
56 | u32 macstnaddr1; /* mac station address part 1 reg */ | |
57 | u32 macstnaddr2; /* mac station address part 2 reg */ | |
58 | u8 res2[0x8]; | |
59 | u32 uempr; /* UCC Ethernet Mac parameter reg */ | |
60 | u32 utbipar; /* UCC tbi address reg */ | |
61 | u16 uescr; /* UCC Ethernet statistics control reg */ | |
62 | u8 res3[0x180 - 0x15A]; | |
63 | u32 tx64; /* Total number of frames (including bad | |
64 | frames) transmitted that were exactly of the | |
65 | minimal length (64 for un tagged, 68 for | |
66 | tagged, or with length exactly equal to the | |
67 | parameter MINLength */ | |
68 | u32 tx127; /* Total number of frames (including bad | |
69 | frames) transmitted that were between | |
70 | MINLength (Including FCS length==4) and 127 | |
71 | octets */ | |
72 | u32 tx255; /* Total number of frames (including bad | |
73 | frames) transmitted that were between 128 | |
74 | (Including FCS length==4) and 255 octets */ | |
75 | u32 rx64; /* Total number of frames received including | |
76 | bad frames that were exactly of the mninimal | |
77 | length (64 bytes) */ | |
78 | u32 rx127; /* Total number of frames (including bad | |
79 | frames) received that were between MINLength | |
80 | (Including FCS length==4) and 127 octets */ | |
81 | u32 rx255; /* Total number of frames (including bad | |
82 | frames) received that were between 128 | |
83 | (Including FCS length==4) and 255 octets */ | |
84 | u32 txok; /* Total number of octets residing in frames | |
85 | that where involved in succesfull | |
86 | transmission */ | |
87 | u16 txcf; /* Total number of PAUSE control frames | |
88 | transmitted by this MAC */ | |
89 | u8 res4[0x2]; | |
90 | u32 tmca; /* Total number of frames that were transmitted | |
91 | succesfully with the group address bit set | |
92 | that are not broadcast frames */ | |
93 | u32 tbca; /* Total number of frames transmitted | |
94 | succesfully that had destination address | |
95 | field equal to the broadcast address */ | |
96 | u32 rxfok; /* Total number of frames received OK */ | |
97 | u32 rxbok; /* Total number of octets received OK */ | |
98 | u32 rbyt; /* Total number of octets received including | |
99 | octets in bad frames. Must be implemented in | |
100 | HW because it includes octets in frames that | |
101 | never even reach the UCC */ | |
102 | u32 rmca; /* Total number of frames that were received | |
103 | succesfully with the group address bit set | |
104 | that are not broadcast frames */ | |
105 | u32 rbca; /* Total number of frames received succesfully | |
106 | that had destination address equal to the | |
107 | broadcast address */ | |
108 | u32 scar; /* Statistics carry register */ | |
109 | u32 scam; /* Statistics caryy mask register */ | |
110 | u8 res5[0x200 - 0x1c4]; | |
18a8e864 | 111 | } __attribute__ ((packed)); |
ce973b14 LY |
112 | |
113 | /* UCC GETH TEMODR Register */ | |
114 | #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics | |
115 | */ | |
116 | #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */ | |
117 | #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4 | |
118 | checksums */ | |
119 | #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance | |
120 | optimization | |
121 | enhancement (mode1) */ | |
122 | #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics | |
123 | */ | |
124 | #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues << | |
125 | shift */ | |
126 | ||
127 | /* UCC GETH TEMODR Register */ | |
128 | #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx | |
129 | statistics */ | |
130 | #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable | |
131 | extended | |
132 | features */ | |
133 | #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation | |
134 | tagged << shift */ | |
135 | #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non | |
136 | tagged << shift */ | |
137 | #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift | |
138 | */ | |
139 | #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx | |
140 | statistics */ | |
141 | #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended | |
142 | filtering | |
143 | vs. | |
144 | mpc82xx-like | |
145 | filtering */ | |
146 | #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues << | |
147 | shift */ | |
148 | #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable | |
149 | dynamic max | |
150 | frame length | |
151 | */ | |
152 | #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable | |
153 | dynamic min | |
154 | frame length | |
155 | */ | |
156 | #define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4 | |
157 | checksums */ | |
158 | #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip | |
159 | address to | |
160 | 4-byte | |
161 | boundary */ | |
162 | ||
163 | /* UCC GETH Event Register */ | |
164 | #define UCCE_MPD 0x80000000 /* Magic packet | |
165 | detection */ | |
166 | #define UCCE_SCAR 0x40000000 | |
167 | #define UCCE_GRA 0x20000000 /* Tx graceful | |
168 | stop | |
169 | complete */ | |
170 | #define UCCE_CBPR 0x10000000 | |
171 | #define UCCE_BSY 0x08000000 | |
172 | #define UCCE_RXC 0x04000000 | |
173 | #define UCCE_TXC 0x02000000 | |
174 | #define UCCE_TXE 0x01000000 | |
175 | #define UCCE_TXB7 0x00800000 | |
176 | #define UCCE_TXB6 0x00400000 | |
177 | #define UCCE_TXB5 0x00200000 | |
178 | #define UCCE_TXB4 0x00100000 | |
179 | #define UCCE_TXB3 0x00080000 | |
180 | #define UCCE_TXB2 0x00040000 | |
181 | #define UCCE_TXB1 0x00020000 | |
182 | #define UCCE_TXB0 0x00010000 | |
183 | #define UCCE_RXB7 0x00008000 | |
184 | #define UCCE_RXB6 0x00004000 | |
185 | #define UCCE_RXB5 0x00002000 | |
186 | #define UCCE_RXB4 0x00001000 | |
187 | #define UCCE_RXB3 0x00000800 | |
188 | #define UCCE_RXB2 0x00000400 | |
189 | #define UCCE_RXB1 0x00000200 | |
190 | #define UCCE_RXB0 0x00000100 | |
191 | #define UCCE_RXF7 0x00000080 | |
192 | #define UCCE_RXF6 0x00000040 | |
193 | #define UCCE_RXF5 0x00000020 | |
194 | #define UCCE_RXF4 0x00000010 | |
195 | #define UCCE_RXF3 0x00000008 | |
196 | #define UCCE_RXF2 0x00000004 | |
197 | #define UCCE_RXF1 0x00000002 | |
198 | #define UCCE_RXF0 0x00000001 | |
199 | ||
200 | #define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0) | |
201 | #define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0) | |
202 | ||
203 | #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\ | |
204 | UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) | |
205 | #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\ | |
206 | UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) | |
207 | #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\ | |
208 | UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) | |
209 | #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\ | |
210 | UCCE_RXC | UCCE_TXC | UCCE_TXE) | |
211 | ||
702ff12c MR |
212 | #define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY) |
213 | #define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE) | |
214 | ||
ce973b14 LY |
215 | /* UCC GETH UPSMR (Protocol Specific Mode Register) */ |
216 | #define UPSMR_ECM 0x04000000 /* Enable CAM | |
217 | Miss or | |
218 | Enable | |
219 | Filtering | |
220 | Miss */ | |
221 | #define UPSMR_HSE 0x02000000 /* Hardware | |
222 | Statistics | |
223 | Enable */ | |
224 | #define UPSMR_PRO 0x00400000 /* Promiscuous*/ | |
225 | #define UPSMR_CAP 0x00200000 /* CAM polarity | |
226 | */ | |
227 | #define UPSMR_RSH 0x00100000 /* Receive | |
228 | Short Frames | |
229 | */ | |
230 | #define UPSMR_RPM 0x00080000 /* Reduced Pin | |
231 | Mode | |
232 | interfaces */ | |
233 | #define UPSMR_R10M 0x00040000 /* RGMII/RMII | |
234 | 10 Mode */ | |
235 | #define UPSMR_RLPB 0x00020000 /* RMII | |
236 | Loopback | |
237 | Mode */ | |
238 | #define UPSMR_TBIM 0x00010000 /* Ten-bit | |
239 | Interface | |
240 | Mode */ | |
241 | #define UPSMR_RMM 0x00001000 /* RMII/RGMII | |
242 | Mode */ | |
243 | #define UPSMR_CAM 0x00000400 /* CAM Address | |
244 | Matching */ | |
245 | #define UPSMR_BRO 0x00000200 /* Broadcast | |
246 | Address */ | |
247 | #define UPSMR_RES1 0x00002000 /* Reserved | |
248 | feild - must | |
249 | be 1 */ | |
250 | ||
251 | /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ | |
252 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control | |
253 | Rx */ | |
254 | #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control | |
255 | Tx */ | |
256 | #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable | |
257 | synchronized | |
258 | to Rx stream | |
259 | */ | |
260 | #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ | |
261 | #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable | |
262 | synchronized | |
263 | to Tx stream | |
264 | */ | |
265 | #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ | |
266 | ||
267 | /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */ | |
268 | #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble | |
269 | Length << | |
270 | shift */ | |
271 | #define MACCFG2_PREL_MASK 0x0000f000 /* Preamble | |
272 | Length mask */ | |
273 | #define MACCFG2_SRP 0x00000080 /* Soft Receive | |
274 | Preamble */ | |
275 | #define MACCFG2_STP 0x00000040 /* Soft | |
276 | Transmit | |
277 | Preamble */ | |
278 | #define MACCFG2_RESERVED_1 0x00000020 /* Reserved - | |
279 | must be set | |
280 | to 1 */ | |
281 | #define MACCFG2_LC 0x00000010 /* Length Check | |
282 | */ | |
283 | #define MACCFG2_MPE 0x00000008 /* Magic packet | |
284 | detect */ | |
285 | #define MACCFG2_FDX 0x00000001 /* Full Duplex */ | |
286 | #define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex | |
287 | mask */ | |
288 | #define MACCFG2_PAD_CRC 0x00000004 | |
289 | #define MACCFG2_CRC_EN 0x00000002 | |
290 | #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither | |
291 | Padding | |
292 | short frames | |
293 | nor CRC */ | |
294 | #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC | |
295 | only */ | |
296 | #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 | |
297 | #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode | |
298 | (MII/RMII/RGMII | |
299 | 10/100bps) */ | |
300 | #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode | |
301 | (GMII/TBI/RTB/RGMII | |
302 | 1000bps ) */ | |
303 | #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask | |
304 | covering all | |
305 | relevant | |
306 | bits */ | |
307 | ||
308 | /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */ | |
309 | #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non | |
310 | back-to-back | |
311 | inter frame | |
312 | gap part 1. | |
313 | << shift */ | |
314 | #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non | |
315 | back-to-back | |
316 | inter frame | |
317 | gap part 2. | |
318 | << shift */ | |
319 | #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG | |
320 | Enforcement | |
321 | << shift */ | |
322 | #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back | |
323 | inter frame | |
324 | gap << shift | |
325 | */ | |
326 | #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back | |
327 | inter frame gap part | |
328 | 1. max val */ | |
329 | #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back | |
330 | inter frame gap part | |
331 | 2. max val */ | |
332 | #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG | |
333 | Enforcement max val */ | |
334 | #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter | |
335 | frame gap max val */ | |
336 | #define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000 | |
337 | #define IPGIFG_NBTB_IPG_MASK 0x007F0000 | |
338 | #define IPGIFG_MIN_IFG_MASK 0x0000FF00 | |
339 | #define IPGIFG_BTB_IPG_MASK 0x0000007F | |
340 | ||
341 | /* UCC GETH HAFDUP (Half Duplex Register) */ | |
342 | #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate | |
343 | Binary | |
344 | Exponential | |
345 | Backoff | |
346 | Truncation | |
347 | << shift */ | |
348 | #define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary | |
349 | Exponential Backoff | |
350 | Truncation max val */ | |
351 | #define HALFDUP_ALT_BEB 0x00080000 /* Alternate | |
352 | Binary | |
353 | Exponential | |
354 | Backoff */ | |
355 | #define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back | |
356 | pressure no | |
357 | backoff */ | |
358 | #define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */ | |
359 | #define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive | |
360 | Defer */ | |
361 | #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum | |
362 | Retransmission | |
363 | << shift */ | |
364 | #define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum | |
365 | Retransmission max | |
366 | val */ | |
367 | #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision | |
368 | Window << | |
369 | shift */ | |
370 | #define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max | |
371 | val */ | |
372 | #define HALFDUP_ALT_BEB_TR_MASK 0x00F00000 | |
373 | #define HALFDUP_RETRANS_MASK 0x0000F000 | |
374 | #define HALFDUP_COL_WINDOW_MASK 0x0000003F | |
375 | ||
376 | /* UCC GETH UCCS (Ethernet Status Register) */ | |
377 | #define UCCS_BPR 0x02 /* Back pressure (in | |
378 | half duplex mode) */ | |
379 | #define UCCS_PAU 0x02 /* Pause state (in full | |
380 | duplex mode) */ | |
381 | #define UCCS_MPD 0x01 /* Magic Packet | |
382 | Detected */ | |
383 | ||
ce973b14 LY |
384 | /* UCC GETH IFSTAT (Interface Status Register) */ |
385 | #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive | |
386 | transmission | |
387 | defer */ | |
388 | ||
389 | /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */ | |
390 | #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station | |
391 | address 6th | |
392 | octet << | |
393 | shift */ | |
394 | #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station | |
395 | address 5th | |
396 | octet << | |
397 | shift */ | |
398 | #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station | |
399 | address 4th | |
400 | octet << | |
401 | shift */ | |
402 | #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station | |
403 | address 3rd | |
404 | octet << | |
405 | shift */ | |
406 | ||
407 | /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */ | |
408 | #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station | |
409 | address 2nd | |
410 | octet << | |
411 | shift */ | |
412 | #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station | |
413 | address 1st | |
414 | octet << | |
415 | shift */ | |
416 | ||
417 | /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */ | |
418 | #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time | |
419 | value << | |
420 | shift */ | |
421 | #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended | |
422 | pause time | |
423 | value << | |
424 | shift */ | |
425 | ||
426 | /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */ | |
427 | #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address | |
428 | << shift */ | |
429 | #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address | |
430 | mask */ | |
431 | ||
432 | /* UCC GETH UESCR (Ethernet Statistics Control Register) */ | |
433 | #define UESCR_AUTOZ 0x8000 /* Automatically zero | |
434 | addressed | |
435 | statistical counter | |
436 | values */ | |
437 | #define UESCR_CLRCNT 0x4000 /* Clear all statistics | |
438 | counters */ | |
439 | #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max | |
440 | Coalescing | |
441 | Value << | |
442 | shift */ | |
443 | #define UESCR_SCOV_SHIFT (15 - 15) /* Status | |
444 | Coalescing | |
445 | Value << | |
446 | shift */ | |
447 | ||
448 | /* UCC GETH UDSR (Data Synchronization Register) */ | |
449 | #define UDSR_MAGIC 0x067E | |
450 | ||
18a8e864 | 451 | struct ucc_geth_thread_data_tx { |
ce973b14 | 452 | u8 res0[104]; |
18a8e864 | 453 | } __attribute__ ((packed)); |
ce973b14 | 454 | |
18a8e864 | 455 | struct ucc_geth_thread_data_rx { |
ce973b14 | 456 | u8 res0[40]; |
18a8e864 | 457 | } __attribute__ ((packed)); |
ce973b14 LY |
458 | |
459 | /* Send Queue Queue-Descriptor */ | |
18a8e864 | 460 | struct ucc_geth_send_queue_qd { |
ce973b14 LY |
461 | u32 bd_ring_base; /* pointer to BD ring base address */ |
462 | u8 res0[0x8]; | |
463 | u32 last_bd_completed_address;/* initialize to last entry in BD ring */ | |
464 | u8 res1[0x30]; | |
18a8e864 | 465 | } __attribute__ ((packed)); |
ce973b14 | 466 | |
18a8e864 LY |
467 | struct ucc_geth_send_queue_mem_region { |
468 | struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES]; | |
469 | } __attribute__ ((packed)); | |
ce973b14 | 470 | |
18a8e864 | 471 | struct ucc_geth_thread_tx_pram { |
ce973b14 | 472 | u8 res0[64]; |
18a8e864 | 473 | } __attribute__ ((packed)); |
ce973b14 | 474 | |
18a8e864 | 475 | struct ucc_geth_thread_rx_pram { |
ce973b14 | 476 | u8 res0[128]; |
18a8e864 | 477 | } __attribute__ ((packed)); |
ce973b14 LY |
478 | |
479 | #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64 | |
480 | #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64 | |
481 | #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96 | |
482 | ||
18a8e864 | 483 | struct ucc_geth_scheduler { |
ce973b14 LY |
484 | u16 cpucount0; /* CPU packet counter */ |
485 | u16 cpucount1; /* CPU packet counter */ | |
486 | u16 cecount0; /* QE packet counter */ | |
487 | u16 cecount1; /* QE packet counter */ | |
488 | u16 cpucount2; /* CPU packet counter */ | |
489 | u16 cpucount3; /* CPU packet counter */ | |
490 | u16 cecount2; /* QE packet counter */ | |
491 | u16 cecount3; /* QE packet counter */ | |
492 | u16 cpucount4; /* CPU packet counter */ | |
493 | u16 cpucount5; /* CPU packet counter */ | |
494 | u16 cecount4; /* QE packet counter */ | |
495 | u16 cecount5; /* QE packet counter */ | |
496 | u16 cpucount6; /* CPU packet counter */ | |
497 | u16 cpucount7; /* CPU packet counter */ | |
498 | u16 cecount6; /* QE packet counter */ | |
499 | u16 cecount7; /* QE packet counter */ | |
500 | u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */ | |
501 | u32 rtsrshadow; /* temporary variable handled by QE */ | |
502 | u32 time; /* temporary variable handled by QE */ | |
503 | u32 ttl; /* temporary variable handled by QE */ | |
504 | u32 mblinterval; /* max burst length interval */ | |
505 | u16 nortsrbytetime; /* normalized value of byte time in tsr units */ | |
506 | u8 fracsiz; /* radix 2 log value of denom. of | |
507 | NorTSRByteTime */ | |
508 | u8 res0[1]; | |
509 | u8 strictpriorityq; /* Strict Priority Mask register */ | |
510 | u8 txasap; /* Transmit ASAP register */ | |
511 | u8 extrabw; /* Extra BandWidth register */ | |
512 | u8 oldwfqmask; /* temporary variable handled by QE */ | |
513 | u8 weightfactor[NUM_TX_QUEUES]; | |
514 | /**< weight factor for queues */ | |
515 | u32 minw; /* temporary variable handled by QE */ | |
516 | u8 res1[0x70 - 0x64]; | |
18a8e864 | 517 | } __attribute__ ((packed)); |
ce973b14 | 518 | |
18a8e864 | 519 | struct ucc_geth_tx_firmware_statistics_pram { |
ce973b14 LY |
520 | u32 sicoltx; /* single collision */ |
521 | u32 mulcoltx; /* multiple collision */ | |
522 | u32 latecoltxfr; /* late collision */ | |
523 | u32 frabortduecol; /* frames aborted due to transmit collision */ | |
524 | u32 frlostinmactxer; /* frames lost due to internal MAC error | |
525 | transmission that are not counted on any | |
526 | other counter */ | |
527 | u32 carriersenseertx; /* carrier sense error */ | |
528 | u32 frtxok; /* frames transmitted OK */ | |
529 | u32 txfrexcessivedefer; /* frames with defferal time greater than | |
530 | specified threshold */ | |
531 | u32 txpkts256; /* total packets (including bad) between 256 | |
532 | and 511 octets */ | |
533 | u32 txpkts512; /* total packets (including bad) between 512 | |
534 | and 1023 octets */ | |
535 | u32 txpkts1024; /* total packets (including bad) between 1024 | |
536 | and 1518 octets */ | |
537 | u32 txpktsjumbo; /* total packets (including bad) between 1024 | |
538 | and MAXLength octets */ | |
18a8e864 | 539 | } __attribute__ ((packed)); |
ce973b14 | 540 | |
18a8e864 | 541 | struct ucc_geth_rx_firmware_statistics_pram { |
ce973b14 LY |
542 | u32 frrxfcser; /* frames with crc error */ |
543 | u32 fraligner; /* frames with alignment error */ | |
544 | u32 inrangelenrxer; /* in range length error */ | |
545 | u32 outrangelenrxer; /* out of range length error */ | |
546 | u32 frtoolong; /* frame too long */ | |
547 | u32 runt; /* runt */ | |
548 | u32 verylongevent; /* very long event */ | |
549 | u32 symbolerror; /* symbol error */ | |
550 | u32 dropbsy; /* drop because of BD not ready */ | |
551 | u8 res0[0x8]; | |
552 | u32 mismatchdrop; /* drop because of MAC filtering (e.g. address | |
553 | or type mismatch) */ | |
554 | u32 underpkts; /* total frames less than 64 octets */ | |
555 | u32 pkts256; /* total frames (including bad) between 256 and | |
556 | 511 octets */ | |
557 | u32 pkts512; /* total frames (including bad) between 512 and | |
558 | 1023 octets */ | |
559 | u32 pkts1024; /* total frames (including bad) between 1024 | |
560 | and 1518 octets */ | |
561 | u32 pktsjumbo; /* total frames (including bad) between 1024 | |
562 | and MAXLength octets */ | |
563 | u32 frlossinmacer; /* frames lost because of internal MAC error | |
564 | that is not counted in any other counter */ | |
565 | u32 pausefr; /* pause frames */ | |
566 | u8 res1[0x4]; | |
567 | u32 removevlan; /* total frames that had their VLAN tag removed | |
568 | */ | |
569 | u32 replacevlan; /* total frames that had their VLAN tag | |
570 | replaced */ | |
571 | u32 insertvlan; /* total frames that had their VLAN tag | |
572 | inserted */ | |
18a8e864 | 573 | } __attribute__ ((packed)); |
ce973b14 | 574 | |
18a8e864 | 575 | struct ucc_geth_rx_interrupt_coalescing_entry { |
ce973b14 LY |
576 | u32 interruptcoalescingmaxvalue; /* interrupt coalescing max |
577 | value */ | |
578 | u32 interruptcoalescingcounter; /* interrupt coalescing counter, | |
579 | initialize to | |
580 | interruptcoalescingmaxvalue */ | |
18a8e864 | 581 | } __attribute__ ((packed)); |
ce973b14 | 582 | |
18a8e864 LY |
583 | struct ucc_geth_rx_interrupt_coalescing_table { |
584 | struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES]; | |
ce973b14 | 585 | /**< interrupt coalescing entry */ |
18a8e864 | 586 | } __attribute__ ((packed)); |
ce973b14 | 587 | |
18a8e864 LY |
588 | struct ucc_geth_rx_prefetched_bds { |
589 | struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */ | |
590 | } __attribute__ ((packed)); | |
ce973b14 | 591 | |
18a8e864 | 592 | struct ucc_geth_rx_bd_queues_entry { |
ce973b14 LY |
593 | u32 bdbaseptr; /* BD base pointer */ |
594 | u32 bdptr; /* BD pointer */ | |
595 | u32 externalbdbaseptr; /* external BD base pointer */ | |
596 | u32 externalbdptr; /* external BD pointer */ | |
18a8e864 | 597 | } __attribute__ ((packed)); |
ce973b14 | 598 | |
18a8e864 | 599 | struct ucc_geth_tx_global_pram { |
ce973b14 LY |
600 | u16 temoder; |
601 | u8 res0[0x38 - 0x02]; | |
602 | u32 sqptr; /* a base pointer to send queue memory region */ | |
603 | u32 schedulerbasepointer; /* a base pointer to scheduler memory | |
604 | region */ | |
605 | u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */ | |
606 | u32 tstate; /* tx internal state. High byte contains | |
607 | function code */ | |
608 | u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; | |
609 | u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */ | |
610 | u32 tqptr; /* a base pointer to the Tx Queues Memory | |
611 | Region */ | |
612 | u8 res2[0x80 - 0x74]; | |
18a8e864 | 613 | } __attribute__ ((packed)); |
ce973b14 LY |
614 | |
615 | /* structure representing Extended Filtering Global Parameters in PRAM */ | |
18a8e864 | 616 | struct ucc_geth_exf_global_pram { |
ce973b14 LY |
617 | u32 l2pcdptr; /* individual address filter, high */ |
618 | u8 res0[0x10 - 0x04]; | |
18a8e864 | 619 | } __attribute__ ((packed)); |
ce973b14 | 620 | |
18a8e864 | 621 | struct ucc_geth_rx_global_pram { |
ce973b14 LY |
622 | u32 remoder; /* ethernet mode reg. */ |
623 | u32 rqptr; /* base pointer to the Rx Queues Memory Region*/ | |
624 | u32 res0[0x1]; | |
625 | u8 res1[0x20 - 0xC]; | |
626 | u16 typeorlen; /* cutoff point less than which, type/len field | |
627 | is considered length */ | |
628 | u8 res2[0x1]; | |
629 | u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/ | |
630 | u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */ | |
631 | u8 res3[0x30 - 0x28]; | |
632 | u32 intcoalescingptr; /* Interrupt coalescing table pointer */ | |
633 | u8 res4[0x36 - 0x34]; | |
634 | u8 rstate; /* rx internal state. High byte contains | |
635 | function code */ | |
636 | u8 res5[0x46 - 0x37]; | |
637 | u16 mrblr; /* max receive buffer length reg. */ | |
638 | u32 rbdqptr; /* base pointer to RxBD parameter table | |
639 | description */ | |
640 | u16 mflr; /* max frame length reg. */ | |
641 | u16 minflr; /* min frame length reg. */ | |
642 | u16 maxd1; /* max dma1 length reg. */ | |
643 | u16 maxd2; /* max dma2 length reg. */ | |
644 | u32 ecamptr; /* external CAM address */ | |
645 | u32 l2qt; /* VLAN priority mapping table. */ | |
646 | u32 l3qt[0x8]; /* IP priority mapping table. */ | |
647 | u16 vlantype; /* vlan type */ | |
648 | u16 vlantci; /* default vlan tci */ | |
649 | u8 addressfiltering[64]; /* address filtering data structure */ | |
650 | u32 exfGlobalParam; /* base address for extended filtering global | |
651 | parameters */ | |
652 | u8 res6[0x100 - 0xC4]; /* Initialize to zero */ | |
18a8e864 | 653 | } __attribute__ ((packed)); |
ce973b14 LY |
654 | |
655 | #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 | |
656 | ||
657 | /* structure representing InitEnet command */ | |
18a8e864 | 658 | struct ucc_geth_init_pram { |
ce973b14 LY |
659 | u8 resinit1; |
660 | u8 resinit2; | |
661 | u8 resinit3; | |
662 | u8 resinit4; | |
663 | u16 resinit5; | |
664 | u8 res1[0x1]; | |
665 | u8 largestexternallookupkeysize; | |
666 | u32 rgftgfrxglobal; | |
667 | u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */ | |
668 | u8 res2[0x38 - 0x30]; | |
669 | u32 txglobal; /* tx global */ | |
670 | u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */ | |
671 | u8 res3[0x1]; | |
18a8e864 | 672 | } __attribute__ ((packed)); |
ce973b14 LY |
673 | |
674 | #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) | |
675 | #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) | |
676 | ||
677 | #define ENET_INIT_PARAM_RISC_MASK 0x0000003f | |
678 | #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 | |
679 | #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 | |
680 | #define ENET_INIT_PARAM_SNUM_SHIFT 24 | |
681 | ||
682 | #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06 | |
683 | #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30 | |
684 | #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff | |
685 | #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00 | |
686 | #define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400 | |
687 | ||
688 | /* structure representing 82xx Address Filtering Enet Address in PRAM */ | |
18a8e864 | 689 | struct ucc_geth_82xx_enet_address { |
ce973b14 LY |
690 | u8 res1[0x2]; |
691 | u16 h; /* address (MSB) */ | |
692 | u16 m; /* address */ | |
693 | u16 l; /* address (LSB) */ | |
18a8e864 | 694 | } __attribute__ ((packed)); |
ce973b14 LY |
695 | |
696 | /* structure representing 82xx Address Filtering PRAM */ | |
18a8e864 | 697 | struct ucc_geth_82xx_address_filtering_pram { |
ce973b14 LY |
698 | u32 iaddr_h; /* individual address filter, high */ |
699 | u32 iaddr_l; /* individual address filter, low */ | |
700 | u32 gaddr_h; /* group address filter, high */ | |
701 | u32 gaddr_l; /* group address filter, low */ | |
18a8e864 LY |
702 | struct ucc_geth_82xx_enet_address taddr; |
703 | struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS]; | |
ce973b14 | 704 | u8 res0[0x40 - 0x38]; |
18a8e864 | 705 | } __attribute__ ((packed)); |
ce973b14 LY |
706 | |
707 | /* GETH Tx firmware statistics structure, used when calling | |
708 | UCC_GETH_GetStatistics. */ | |
18a8e864 | 709 | struct ucc_geth_tx_firmware_statistics { |
ce973b14 LY |
710 | u32 sicoltx; /* single collision */ |
711 | u32 mulcoltx; /* multiple collision */ | |
712 | u32 latecoltxfr; /* late collision */ | |
713 | u32 frabortduecol; /* frames aborted due to transmit collision */ | |
714 | u32 frlostinmactxer; /* frames lost due to internal MAC error | |
715 | transmission that are not counted on any | |
716 | other counter */ | |
717 | u32 carriersenseertx; /* carrier sense error */ | |
718 | u32 frtxok; /* frames transmitted OK */ | |
719 | u32 txfrexcessivedefer; /* frames with defferal time greater than | |
720 | specified threshold */ | |
721 | u32 txpkts256; /* total packets (including bad) between 256 | |
722 | and 511 octets */ | |
723 | u32 txpkts512; /* total packets (including bad) between 512 | |
724 | and 1023 octets */ | |
725 | u32 txpkts1024; /* total packets (including bad) between 1024 | |
726 | and 1518 octets */ | |
727 | u32 txpktsjumbo; /* total packets (including bad) between 1024 | |
728 | and MAXLength octets */ | |
18a8e864 | 729 | } __attribute__ ((packed)); |
ce973b14 LY |
730 | |
731 | /* GETH Rx firmware statistics structure, used when calling | |
732 | UCC_GETH_GetStatistics. */ | |
18a8e864 | 733 | struct ucc_geth_rx_firmware_statistics { |
ce973b14 LY |
734 | u32 frrxfcser; /* frames with crc error */ |
735 | u32 fraligner; /* frames with alignment error */ | |
736 | u32 inrangelenrxer; /* in range length error */ | |
737 | u32 outrangelenrxer; /* out of range length error */ | |
738 | u32 frtoolong; /* frame too long */ | |
739 | u32 runt; /* runt */ | |
740 | u32 verylongevent; /* very long event */ | |
741 | u32 symbolerror; /* symbol error */ | |
742 | u32 dropbsy; /* drop because of BD not ready */ | |
743 | u8 res0[0x8]; | |
744 | u32 mismatchdrop; /* drop because of MAC filtering (e.g. address | |
745 | or type mismatch) */ | |
746 | u32 underpkts; /* total frames less than 64 octets */ | |
747 | u32 pkts256; /* total frames (including bad) between 256 and | |
748 | 511 octets */ | |
749 | u32 pkts512; /* total frames (including bad) between 512 and | |
750 | 1023 octets */ | |
751 | u32 pkts1024; /* total frames (including bad) between 1024 | |
752 | and 1518 octets */ | |
753 | u32 pktsjumbo; /* total frames (including bad) between 1024 | |
754 | and MAXLength octets */ | |
755 | u32 frlossinmacer; /* frames lost because of internal MAC error | |
756 | that is not counted in any other counter */ | |
757 | u32 pausefr; /* pause frames */ | |
758 | u8 res1[0x4]; | |
759 | u32 removevlan; /* total frames that had their VLAN tag removed | |
760 | */ | |
761 | u32 replacevlan; /* total frames that had their VLAN tag | |
762 | replaced */ | |
763 | u32 insertvlan; /* total frames that had their VLAN tag | |
764 | inserted */ | |
18a8e864 | 765 | } __attribute__ ((packed)); |
ce973b14 LY |
766 | |
767 | /* GETH hardware statistics structure, used when calling | |
768 | UCC_GETH_GetStatistics. */ | |
18a8e864 | 769 | struct ucc_geth_hardware_statistics { |
ce973b14 LY |
770 | u32 tx64; /* Total number of frames (including bad |
771 | frames) transmitted that were exactly of the | |
772 | minimal length (64 for un tagged, 68 for | |
773 | tagged, or with length exactly equal to the | |
774 | parameter MINLength */ | |
775 | u32 tx127; /* Total number of frames (including bad | |
776 | frames) transmitted that were between | |
777 | MINLength (Including FCS length==4) and 127 | |
778 | octets */ | |
779 | u32 tx255; /* Total number of frames (including bad | |
780 | frames) transmitted that were between 128 | |
781 | (Including FCS length==4) and 255 octets */ | |
782 | u32 rx64; /* Total number of frames received including | |
783 | bad frames that were exactly of the mninimal | |
784 | length (64 bytes) */ | |
785 | u32 rx127; /* Total number of frames (including bad | |
786 | frames) received that were between MINLength | |
787 | (Including FCS length==4) and 127 octets */ | |
788 | u32 rx255; /* Total number of frames (including bad | |
789 | frames) received that were between 128 | |
790 | (Including FCS length==4) and 255 octets */ | |
791 | u32 txok; /* Total number of octets residing in frames | |
792 | that where involved in succesfull | |
793 | transmission */ | |
794 | u16 txcf; /* Total number of PAUSE control frames | |
795 | transmitted by this MAC */ | |
796 | u32 tmca; /* Total number of frames that were transmitted | |
797 | succesfully with the group address bit set | |
798 | that are not broadcast frames */ | |
799 | u32 tbca; /* Total number of frames transmitted | |
800 | succesfully that had destination address | |
801 | field equal to the broadcast address */ | |
802 | u32 rxfok; /* Total number of frames received OK */ | |
803 | u32 rxbok; /* Total number of octets received OK */ | |
804 | u32 rbyt; /* Total number of octets received including | |
805 | octets in bad frames. Must be implemented in | |
806 | HW because it includes octets in frames that | |
807 | never even reach the UCC */ | |
808 | u32 rmca; /* Total number of frames that were received | |
809 | succesfully with the group address bit set | |
810 | that are not broadcast frames */ | |
811 | u32 rbca; /* Total number of frames received succesfully | |
812 | that had destination address equal to the | |
813 | broadcast address */ | |
18a8e864 | 814 | } __attribute__ ((packed)); |
ce973b14 LY |
815 | |
816 | /* UCC GETH Tx errors returned via TxConf callback */ | |
817 | #define TX_ERRORS_DEF 0x0200 | |
818 | #define TX_ERRORS_EXDEF 0x0100 | |
819 | #define TX_ERRORS_LC 0x0080 | |
820 | #define TX_ERRORS_RL 0x0040 | |
821 | #define TX_ERRORS_RC_MASK 0x003C | |
822 | #define TX_ERRORS_RC_SHIFT 2 | |
823 | #define TX_ERRORS_UN 0x0002 | |
824 | #define TX_ERRORS_CSL 0x0001 | |
825 | ||
826 | /* UCC GETH Rx errors returned via RxStore callback */ | |
827 | #define RX_ERRORS_CMR 0x0200 | |
828 | #define RX_ERRORS_M 0x0100 | |
829 | #define RX_ERRORS_BC 0x0080 | |
830 | #define RX_ERRORS_MC 0x0040 | |
831 | ||
832 | /* Transmit BD. These are in addition to values defined in uccf. */ | |
833 | #define T_VID 0x003c0000 /* insert VLAN id index mask. */ | |
834 | #define T_DEF (((u32) TX_ERRORS_DEF ) << 16) | |
835 | #define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16) | |
836 | #define T_LC (((u32) TX_ERRORS_LC ) << 16) | |
837 | #define T_RL (((u32) TX_ERRORS_RL ) << 16) | |
838 | #define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16) | |
839 | #define T_UN (((u32) TX_ERRORS_UN ) << 16) | |
840 | #define T_CSL (((u32) TX_ERRORS_CSL ) << 16) | |
841 | #define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \ | |
842 | | T_UN | T_CSL) /* transmit errors to report */ | |
843 | ||
844 | /* Receive BD. These are in addition to values defined in uccf. */ | |
845 | #define R_LG 0x00200000 /* Frame length violation. */ | |
846 | #define R_NO 0x00100000 /* Non-octet aligned frame. */ | |
847 | #define R_SH 0x00080000 /* Short frame. */ | |
848 | #define R_CR 0x00040000 /* CRC error. */ | |
849 | #define R_OV 0x00020000 /* Overrun. */ | |
850 | #define R_IPCH 0x00010000 /* IP checksum check failed. */ | |
851 | #define R_CMR (((u32) RX_ERRORS_CMR ) << 16) | |
852 | #define R_M (((u32) RX_ERRORS_M ) << 16) | |
853 | #define R_BC (((u32) RX_ERRORS_BC ) << 16) | |
854 | #define R_MC (((u32) RX_ERRORS_MC ) << 16) | |
855 | #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to | |
856 | report */ | |
857 | #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \ | |
858 | R_OV | R_IPCH) /* receive errors to discard */ | |
859 | ||
860 | /* Alignments */ | |
861 | #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256 | |
862 | #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128 | |
863 | #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128 | |
864 | #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64 | |
865 | #define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values | |
866 | based on num of | |
867 | threads, but always | |
868 | using the maximum is | |
869 | easier */ | |
870 | #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 | |
871 | #define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */ | |
872 | #define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */ | |
873 | #define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */ | |
7563907e | 874 | #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64 |
ce973b14 LY |
875 | #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */ |
876 | #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */ | |
877 | #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This | |
878 | is a | |
879 | guess | |
880 | */ | |
881 | #define UCC_GETH_RX_BD_RING_ALIGNMENT 32 | |
882 | #define UCC_GETH_TX_BD_RING_ALIGNMENT 32 | |
883 | #define UCC_GETH_MRBLR_ALIGNMENT 128 | |
884 | #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4 | |
885 | #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 | |
886 | #define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64 | |
887 | ||
888 | #define UCC_GETH_TAD_EF 0x80 | |
889 | #define UCC_GETH_TAD_V 0x40 | |
890 | #define UCC_GETH_TAD_REJ 0x20 | |
891 | #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2 | |
892 | #define UCC_GETH_TAD_VTAG_OP_SHIFT 6 | |
893 | #define UCC_GETH_TAD_V_NON_VTAG_OP 0x20 | |
894 | #define UCC_GETH_TAD_RQOS_SHIFT 0 | |
895 | #define UCC_GETH_TAD_V_PRIORITY_SHIFT 5 | |
896 | #define UCC_GETH_TAD_CFI 0x10 | |
897 | ||
898 | #define UCC_GETH_VLAN_PRIORITY_MAX 8 | |
899 | #define UCC_GETH_IP_PRIORITY_MAX 64 | |
900 | #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8 | |
901 | #define UCC_GETH_RX_BD_RING_SIZE_MIN 8 | |
902 | #define UCC_GETH_TX_BD_RING_SIZE_MIN 2 | |
ac421852 | 903 | #define UCC_GETH_BD_RING_SIZE_MAX 0xffff |
ce973b14 LY |
904 | |
905 | #define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD | |
906 | ||
907 | /* Driver definitions */ | |
908 | #define TX_BD_RING_LEN 0x10 | |
909 | #define RX_BD_RING_LEN 0x10 | |
910 | #define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN | |
911 | ||
912 | #define TX_RING_MOD_MASK(size) (size-1) | |
913 | #define RX_RING_MOD_MASK(size) (size-1) | |
914 | ||
915 | #define ENET_NUM_OCTETS_PER_ADDRESS 6 | |
916 | #define ENET_GROUP_ADDR 0x01 /* Group address mask | |
917 | for ethernet | |
918 | addresses */ | |
919 | ||
920 | #define TX_TIMEOUT (1*HZ) | |
921 | #define SKB_ALLOC_TIMEOUT 100000 | |
922 | #define PHY_INIT_TIMEOUT 100000 | |
923 | #define PHY_CHANGE_TIME 2 | |
924 | ||
925 | /* Fast Ethernet (10/100 Mbps) */ | |
926 | #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size | |
927 | */ | |
928 | #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ | |
929 | #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ | |
930 | #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size | |
931 | */ | |
932 | #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ | |
933 | #define UCC_GETH_UTFTT_INIT 128 | |
934 | /* Gigabit Ethernet (1000 Mbps) */ | |
935 | #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual | |
936 | FIFO size */ | |
937 | #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ | |
938 | #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ | |
939 | #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual | |
940 | FIFO size */ | |
941 | #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ | |
942 | #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ | |
943 | ||
944 | #define UCC_GETH_REMODER_INIT 0 /* bits that must be | |
945 | set */ | |
946 | #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */ | |
947 | #define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value | |
948 | for this | |
949 | register */ | |
950 | #define UCC_GETH_MACCFG1_INIT 0 | |
951 | #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1) | |
ce973b14 LY |
952 | |
953 | /* Ethernet Address Type. */ | |
18a8e864 | 954 | enum enet_addr_type { |
ce973b14 LY |
955 | ENET_ADDR_TYPE_INDIVIDUAL, |
956 | ENET_ADDR_TYPE_GROUP, | |
957 | ENET_ADDR_TYPE_BROADCAST | |
18a8e864 | 958 | }; |
ce973b14 | 959 | |
ce973b14 | 960 | /* UCC GETH 82xx Ethernet Address Recognition Location */ |
18a8e864 | 961 | enum ucc_geth_enet_address_recognition_location { |
ce973b14 LY |
962 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station |
963 | address */ | |
964 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional | |
965 | station | |
966 | address | |
967 | paddr1 */ | |
968 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional | |
969 | station | |
970 | address | |
971 | paddr2 */ | |
972 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional | |
973 | station | |
974 | address | |
975 | paddr3 */ | |
976 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional | |
977 | station | |
978 | address | |
979 | paddr4 */ | |
980 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */ | |
981 | UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual | |
982 | hash */ | |
18a8e864 | 983 | }; |
ce973b14 LY |
984 | |
985 | /* UCC GETH vlan operation tagged */ | |
18a8e864 | 986 | enum ucc_geth_vlan_operation_tagged { |
ce973b14 LY |
987 | UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */ |
988 | UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG | |
989 | = 0x1, /* Tagged - replace vid portion of q tag */ | |
990 | UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE | |
991 | = 0x2, /* Tagged - if vid0 replace vid with default value */ | |
992 | UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME | |
993 | = 0x3 /* Tagged - extract q tag from frame */ | |
18a8e864 | 994 | }; |
ce973b14 LY |
995 | |
996 | /* UCC GETH vlan operation non-tagged */ | |
18a8e864 | 997 | enum ucc_geth_vlan_operation_non_tagged { |
ce973b14 LY |
998 | UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */ |
999 | UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged - | |
1000 | q tag insert | |
1001 | */ | |
18a8e864 | 1002 | }; |
ce973b14 LY |
1003 | |
1004 | /* UCC GETH Rx Quality of Service Mode */ | |
18a8e864 | 1005 | enum ucc_geth_qos_mode { |
ce973b14 LY |
1006 | UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */ |
1007 | UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue | |
1008 | determined | |
1009 | by L2 | |
1010 | criteria */ | |
1011 | UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue | |
1012 | determined | |
1013 | by L3 | |
1014 | criteria */ | |
18a8e864 | 1015 | }; |
ce973b14 LY |
1016 | |
1017 | /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together | |
1018 | for combined functionality */ | |
18a8e864 | 1019 | enum ucc_geth_statistics_gathering_mode { |
ce973b14 LY |
1020 | UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No |
1021 | statistics | |
1022 | gathering */ | |
1023 | UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable | |
1024 | hardware | |
1025 | statistics | |
1026 | gathering | |
1027 | */ | |
1028 | UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable | |
1029 | firmware | |
1030 | tx | |
1031 | statistics | |
1032 | gathering | |
1033 | */ | |
1034 | UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable | |
1035 | firmware | |
1036 | rx | |
1037 | statistics | |
1038 | gathering | |
1039 | */ | |
18a8e864 | 1040 | }; |
ce973b14 LY |
1041 | |
1042 | /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */ | |
18a8e864 | 1043 | enum ucc_geth_maccfg2_pad_and_crc_mode { |
ce973b14 LY |
1044 | UCC_GETH_PAD_AND_CRC_MODE_NONE |
1045 | = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding | |
1046 | short frames | |
1047 | nor CRC */ | |
1048 | UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY | |
1049 | = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append | |
1050 | CRC only */ | |
1051 | UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC = | |
1052 | MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC | |
18a8e864 | 1053 | }; |
ce973b14 LY |
1054 | |
1055 | /* UCC GETH upsmr Flow Control Mode */ | |
18a8e864 | 1056 | enum ucc_geth_flow_control_mode { |
ce973b14 LY |
1057 | UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic |
1058 | flow control | |
1059 | */ | |
1060 | UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY | |
1061 | = 0x00004000 /* Send pause frame when RxFIFO reaches its | |
1062 | emergency threshold */ | |
18a8e864 | 1063 | }; |
ce973b14 LY |
1064 | |
1065 | /* UCC GETH number of threads */ | |
18a8e864 | 1066 | enum ucc_geth_num_of_threads { |
ce973b14 LY |
1067 | UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */ |
1068 | UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */ | |
1069 | UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */ | |
1070 | UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */ | |
1071 | UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */ | |
18a8e864 | 1072 | }; |
ce973b14 LY |
1073 | |
1074 | /* UCC GETH number of station addresses */ | |
18a8e864 | 1075 | enum ucc_geth_num_of_station_addresses { |
ce973b14 LY |
1076 | UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */ |
1077 | UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */ | |
18a8e864 | 1078 | }; |
ce973b14 LY |
1079 | |
1080 | /* UCC GETH 82xx Ethernet Address Container */ | |
18a8e864 LY |
1081 | struct enet_addr_container { |
1082 | u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */ | |
1083 | enum ucc_geth_enet_address_recognition_location location; /* location in | |
ce973b14 LY |
1084 | 82xx address |
1085 | recognition | |
1086 | hardware */ | |
1087 | struct list_head node; | |
18a8e864 | 1088 | }; |
ce973b14 | 1089 | |
18a8e864 | 1090 | #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node) |
ce973b14 LY |
1091 | |
1092 | /* UCC GETH Termination Action Descriptor (TAD) structure. */ | |
18a8e864 | 1093 | struct ucc_geth_tad_params { |
ce973b14 LY |
1094 | int rx_non_dynamic_extended_features_mode; |
1095 | int reject_frame; | |
18a8e864 LY |
1096 | enum ucc_geth_vlan_operation_tagged vtag_op; |
1097 | enum ucc_geth_vlan_operation_non_tagged vnontag_op; | |
1098 | enum ucc_geth_qos_mode rqos; | |
ce973b14 LY |
1099 | u8 vpri; |
1100 | u16 vid; | |
18a8e864 | 1101 | }; |
ce973b14 LY |
1102 | |
1103 | /* GETH protocol initialization structure */ | |
18a8e864 LY |
1104 | struct ucc_geth_info { |
1105 | struct ucc_fast_info uf_info; | |
ce973b14 LY |
1106 | u8 numQueuesTx; |
1107 | u8 numQueuesRx; | |
1108 | int ipCheckSumCheck; | |
1109 | int ipCheckSumGenerate; | |
1110 | int rxExtendedFiltering; | |
1111 | u32 extendedFilteringChainPointer; | |
1112 | u16 typeorlen; | |
1113 | int dynamicMaxFrameLength; | |
1114 | int dynamicMinFrameLength; | |
1115 | u8 nonBackToBackIfgPart1; | |
1116 | u8 nonBackToBackIfgPart2; | |
1117 | u8 miminumInterFrameGapEnforcement; | |
1118 | u8 backToBackInterFrameGap; | |
1119 | int ipAddressAlignment; | |
1120 | int lengthCheckRx; | |
1121 | u32 mblinterval; | |
1122 | u16 nortsrbytetime; | |
1123 | u8 fracsiz; | |
1124 | u8 strictpriorityq; | |
1125 | u8 txasap; | |
1126 | u8 extrabw; | |
1127 | int miiPreambleSupress; | |
1128 | u8 altBebTruncation; | |
1129 | int altBeb; | |
1130 | int backPressureNoBackoff; | |
1131 | int noBackoff; | |
1132 | int excessDefer; | |
1133 | u8 maxRetransmission; | |
1134 | u8 collisionWindow; | |
1135 | int pro; | |
1136 | int cap; | |
1137 | int rsh; | |
1138 | int rlpb; | |
1139 | int cam; | |
1140 | int bro; | |
1141 | int ecm; | |
1142 | int receiveFlowControl; | |
ac421852 | 1143 | int transmitFlowControl; |
ce973b14 LY |
1144 | u8 maxGroupAddrInHash; |
1145 | u8 maxIndAddrInHash; | |
1146 | u8 prel; | |
1147 | u16 maxFrameLength; | |
1148 | u16 minFrameLength; | |
1149 | u16 maxD1Length; | |
1150 | u16 maxD2Length; | |
1151 | u16 vlantype; | |
1152 | u16 vlantci; | |
1153 | u32 ecamptr; | |
1154 | u32 eventRegMask; | |
1155 | u16 pausePeriod; | |
1156 | u16 extensionField; | |
1157 | u8 phy_address; | |
728de4c9 | 1158 | u32 mdio_bus; |
ce973b14 LY |
1159 | u8 weightfactor[NUM_TX_QUEUES]; |
1160 | u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; | |
1161 | u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; | |
1162 | u8 l3qt[UCC_GETH_IP_PRIORITY_MAX]; | |
1163 | u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX]; | |
1164 | u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX]; | |
1165 | u16 bdRingLenTx[NUM_TX_QUEUES]; | |
1166 | u16 bdRingLenRx[NUM_RX_QUEUES]; | |
18a8e864 LY |
1167 | enum ucc_geth_num_of_station_addresses numStationAddresses; |
1168 | enum qe_fltr_largest_external_tbl_lookup_key_size | |
ce973b14 | 1169 | largestexternallookupkeysize; |
18a8e864 LY |
1170 | enum ucc_geth_statistics_gathering_mode statisticsMode; |
1171 | enum ucc_geth_vlan_operation_tagged vlanOperationTagged; | |
1172 | enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged; | |
1173 | enum ucc_geth_qos_mode rxQoSMode; | |
1174 | enum ucc_geth_flow_control_mode aufc; | |
1175 | enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; | |
1176 | enum ucc_geth_num_of_threads numThreadsTx; | |
1177 | enum ucc_geth_num_of_threads numThreadsRx; | |
1178 | enum qe_risc_allocation riscTx; | |
1179 | enum qe_risc_allocation riscRx; | |
1180 | }; | |
ce973b14 LY |
1181 | |
1182 | /* structure representing UCC GETH */ | |
18a8e864 LY |
1183 | struct ucc_geth_private { |
1184 | struct ucc_geth_info *ug_info; | |
1185 | struct ucc_fast_private *uccf; | |
ce973b14 | 1186 | struct net_device *dev; |
bea3348e | 1187 | struct napi_struct napi; |
ce973b14 | 1188 | struct net_device_stats stats; /* linux network statistics */ |
18a8e864 LY |
1189 | struct ucc_geth *ug_regs; |
1190 | struct ucc_geth_init_pram *p_init_enet_param_shadow; | |
1191 | struct ucc_geth_exf_global_pram *p_exf_glbl_param; | |
ce973b14 | 1192 | u32 exf_glbl_param_offset; |
18a8e864 | 1193 | struct ucc_geth_rx_global_pram *p_rx_glbl_pram; |
ce973b14 | 1194 | u32 rx_glbl_pram_offset; |
18a8e864 | 1195 | struct ucc_geth_tx_global_pram *p_tx_glbl_pram; |
ce973b14 | 1196 | u32 tx_glbl_pram_offset; |
18a8e864 | 1197 | struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg; |
ce973b14 | 1198 | u32 send_q_mem_reg_offset; |
18a8e864 | 1199 | struct ucc_geth_thread_data_tx *p_thread_data_tx; |
ce973b14 | 1200 | u32 thread_dat_tx_offset; |
18a8e864 | 1201 | struct ucc_geth_thread_data_rx *p_thread_data_rx; |
ce973b14 | 1202 | u32 thread_dat_rx_offset; |
18a8e864 | 1203 | struct ucc_geth_scheduler *p_scheduler; |
ce973b14 | 1204 | u32 scheduler_offset; |
18a8e864 | 1205 | struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; |
ce973b14 | 1206 | u32 tx_fw_statistics_pram_offset; |
18a8e864 | 1207 | struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; |
ce973b14 | 1208 | u32 rx_fw_statistics_pram_offset; |
18a8e864 | 1209 | struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl; |
ce973b14 | 1210 | u32 rx_irq_coalescing_tbl_offset; |
18a8e864 | 1211 | struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl; |
ce973b14 LY |
1212 | u32 rx_bd_qs_tbl_offset; |
1213 | u8 *p_tx_bd_ring[NUM_TX_QUEUES]; | |
1214 | u32 tx_bd_ring_offset[NUM_TX_QUEUES]; | |
1215 | u8 *p_rx_bd_ring[NUM_RX_QUEUES]; | |
1216 | u32 rx_bd_ring_offset[NUM_RX_QUEUES]; | |
1217 | u8 *confBd[NUM_TX_QUEUES]; | |
1218 | u8 *txBd[NUM_TX_QUEUES]; | |
1219 | u8 *rxBd[NUM_RX_QUEUES]; | |
1220 | int badFrame[NUM_RX_QUEUES]; | |
1221 | u16 cpucount[NUM_TX_QUEUES]; | |
1222 | volatile u16 *p_cpucount[NUM_TX_QUEUES]; | |
1223 | int indAddrRegUsed[NUM_OF_PADDRS]; | |
18a8e864 | 1224 | u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */ |
ce973b14 LY |
1225 | u8 numGroupAddrInHash; |
1226 | u8 numIndAddrInHash; | |
1227 | u8 numIndAddrInReg; | |
1228 | int rx_extended_features; | |
1229 | int rx_non_dynamic_extended_features; | |
1230 | struct list_head conf_skbs; | |
1231 | struct list_head group_hash_q; | |
1232 | struct list_head ind_hash_q; | |
1233 | u32 saved_uccm; | |
1234 | spinlock_t lock; | |
1235 | /* pointers to arrays of skbuffs for tx and rx */ | |
1236 | struct sk_buff **tx_skbuff[NUM_TX_QUEUES]; | |
1237 | struct sk_buff **rx_skbuff[NUM_RX_QUEUES]; | |
1238 | /* indices pointing to the next free sbk in skb arrays */ | |
1239 | u16 skb_curtx[NUM_TX_QUEUES]; | |
1240 | u16 skb_currx[NUM_RX_QUEUES]; | |
1241 | /* index of the first skb which hasn't been transmitted yet. */ | |
1242 | u16 skb_dirtytx[NUM_TX_QUEUES]; | |
1243 | ||
ce973b14 | 1244 | struct ugeth_mii_info *mii_info; |
728de4c9 KP |
1245 | struct phy_device *phydev; |
1246 | phy_interface_t phy_interface; | |
1247 | int max_speed; | |
1248 | uint32_t msg_enable; | |
ce973b14 LY |
1249 | int oldspeed; |
1250 | int oldduplex; | |
1251 | int oldlink; | |
18a8e864 | 1252 | }; |
ce973b14 LY |
1253 | |
1254 | #endif /* __UCC_GETH_H__ */ |