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[PATCH] Use tulip.h in winbond-840.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / tulip / tulip_core.c
CommitLineData
1da177e4
LT		 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3/*
6b92801b 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
1da177e4
LT		 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
1da177e4
LT		 17
18#define DRV_NAME "tulip"
19#ifdef CONFIG_TULIP_NAPI
20#define DRV_VERSION "1.1.13-NAPI" /* Keep at least for test */
21#else
22#define DRV_VERSION "1.1.13"
23#endif
24#define DRV_RELDATE "May 11, 2002"
25
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "tulip.h"
30#include <linux/init.h>
31#include <linux/etherdevice.h>
32#include <linux/delay.h>
33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/crc32.h>
36#include <asm/unaligned.h>
37#include <asm/uaccess.h>
38
39#ifdef __sparc__
40#include <asm/pbm.h>
41#endif
42
43static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46
47/* A few user-configurable values. */
48
49/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
50static unsigned int max_interrupt_work = 25;
51
52#define MAX_UNITS 8
53/* Used to pass the full-duplex flag, etc. */
54static int full_duplex[MAX_UNITS];
55static int options[MAX_UNITS];
56static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
57
58/* The possible media types that can be set in options[] are: */
59const char * const medianame[32] = {
60 "10baseT", "10base2", "AUI", "100baseTx",
61 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
62 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
63 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
64 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
65 "","","","", "","","","", "","","","Transceiver reset",
66};
67
68/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
69#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
70 || defined(__sparc_) || defined(__ia64__) \
71 || defined(__sh__) || defined(__mips__)
72static int rx_copybreak = 1518;
73#else
74static int rx_copybreak = 100;
75#endif
76
77/*
78 Set the bus performance register.
79 Typical: Set 16 longword cache alignment, no burst limit.
80 Cache alignment bits 15:14 Burst length 13:8
81 0000 No alignment 0x00000000 unlimited 0800 8 longwords
82 4000 8 longwords 0100 1 longword 1000 16 longwords
83 8000 16 longwords 0200 2 longwords 2000 32 longwords
84 C000 32 longwords 0400 4 longwords
85 Warning: many older 486 systems are broken and require setting 0x00A04800
86 8 longword cache alignment, 8 longword burst.
87 ToDo: Non-Intel setting could be better.
88*/
89
90#if defined(__alpha__) || defined(__ia64__)
91static int csr0 = 0x01A00000 | 0xE000;
92#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
93static int csr0 = 0x01A00000 | 0x8000;
94#elif defined(__sparc__) || defined(__hppa__)
95/* The UltraSparc PCI controllers will disconnect at every 64-byte
96 * crossing anyways so it makes no sense to tell Tulip to burst
97 * any more than that.
98 */
99static int csr0 = 0x01A00000 | 0x9000;
100#elif defined(__arm__) || defined(__sh__)
101static int csr0 = 0x01A00000 | 0x4800;
102#elif defined(__mips__)
103static int csr0 = 0x00200000 | 0x4000;
104#else
105#warning Processor architecture undefined!
106static int csr0 = 0x00A00000 | 0x4800;
107#endif
108
109/* Operational parameters that usually are not changed. */
110/* Time in jiffies before concluding the transmitter is hung. */
111#define TX_TIMEOUT (4*HZ)
112
113
114MODULE_AUTHOR("The Linux Kernel Team");
115MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118module_param(tulip_debug, int, 0);
119module_param(max_interrupt_work, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param(csr0, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124
125#define PFX DRV_NAME ": "
126
127#ifdef TULIP_DEBUG
128int tulip_debug = TULIP_DEBUG;
129#else
130int tulip_debug = 1;
131#endif
132
0bb3cf72
FR		 133static void tulip_timer(unsigned long data)
134{
135 struct net_device *dev = (struct net_device *)data;
136 struct tulip_private *tp = netdev_priv(dev);
1da177e4 137
0bb3cf72
FR		 138 if (netif_running(dev))
139 schedule_work(&tp->media_work);
140}
1da177e4
LT		 141
142/*
143 * This table use during operation for capabilities and media timer.
144 *
145 * It is indexed via the values in 'enum chips'
146 */
147
148struct tulip_chip_table tulip_tbl[] = {
149 { }, /* placeholder for array, slot unused currently */
150 { }, /* placeholder for array, slot unused currently */
151
152 /* DC21140 */
153 { "Digital DS21140 Tulip", 128, 0x0001ebef,
0bb3cf72
FR		 154 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 tulip_media_task },
1da177e4
LT		 156
157 /* DC21142, DC21143 */
b892de0b 158 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
1da177e4 159 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
0bb3cf72 160 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
1da177e4
LT		 161
162 /* LC82C168 */
163 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
0bb3cf72 164 HAS_MII | HAS_PNICNWAY, pnic_timer, },
1da177e4
LT		 165
166 /* MX98713 */
167 { "Macronix 98713 PMAC", 128, 0x0001ebef,
0bb3cf72 168 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 169
170 /* MX98715 */
171 { "Macronix 98715 PMAC", 256, 0x0001ebef,
0bb3cf72 172 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 173
174 /* MX98725 */
175 { "Macronix 98725 PMAC", 256, 0x0001ebef,
0bb3cf72 176 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 177
178 /* AX88140 */
179 { "ASIX AX88140", 128, 0x0001fbff,
180 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
0bb3cf72 181 | IS_ASIX, tulip_timer, tulip_media_task },
1da177e4
LT		 182
183 /* PNIC2 */
184 { "Lite-On PNIC-II", 256, 0x0801fbff,
0bb3cf72 185 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
1da177e4
LT		 186
187 /* COMET */
188 { "ADMtek Comet", 256, 0x0001abef,
0bb3cf72 189 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
1da177e4
LT		 190
191 /* COMPEX9881 */
192 { "Compex 9881 PMAC", 128, 0x0001ebef,
0bb3cf72 193 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 194
195 /* I21145 */
196 { "Intel DS21145 Tulip", 128, 0x0801fbff,
197 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
0bb3cf72 198 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
1da177e4
LT		 199
200 /* DM910X */
201 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
202 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
0bb3cf72 203 tulip_timer, tulip_media_task },
1da177e4
LT		 204
205 /* RS7112 */
206 { "Conexant LANfinity", 256, 0x0001ebef,
0bb3cf72 207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
1da177e4 208
1da177e4
LT		 209};
210
211
212static struct pci_device_id tulip_pci_tbl[] = {
213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
218/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
233 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
235 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
237 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
242 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 246 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 247 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
1a449358 248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 249 { } /* terminate list */
250};
251MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
252
253
254/* A full-duplex map for media types. */
255const char tulip_media_cap[32] =
256{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
257
258static void tulip_tx_timeout(struct net_device *dev);
259static void tulip_init_ring(struct net_device *dev);
260static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
261static int tulip_open(struct net_device *dev);
262static int tulip_close(struct net_device *dev);
263static void tulip_up(struct net_device *dev);
264static void tulip_down(struct net_device *dev);
265static struct net_device_stats *tulip_get_stats(struct net_device *dev);
266static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
267static void set_rx_mode(struct net_device *dev);
268#ifdef CONFIG_NET_POLL_CONTROLLER
269static void poll_tulip(struct net_device *dev);
270#endif
271
272static void tulip_set_power_state (struct tulip_private *tp,
273 int sleep, int snooze)
274{
275 if (tp->flags & HAS_ACPI) {
276 u32 tmp, newtmp;
277 pci_read_config_dword (tp->pdev, CFDD, &tmp);
278 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
279 if (sleep)
280 newtmp |= CFDD_Sleep;
281 else if (snooze)
282 newtmp |= CFDD_Snooze;
283 if (tmp != newtmp)
284 pci_write_config_dword (tp->pdev, CFDD, newtmp);
285 }
286
287}
288
289
290static void tulip_up(struct net_device *dev)
291{
292 struct tulip_private *tp = netdev_priv(dev);
293 void __iomem *ioaddr = tp->base_addr;
294 int next_tick = 3*HZ;
295 int i;
296
297 /* Wake the chip from sleep/snooze mode. */
298 tulip_set_power_state (tp, 0, 0);
299
300 /* On some chip revs we must set the MII/SYM port before the reset!? */
301 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
302 iowrite32(0x00040000, ioaddr + CSR6);
303
304 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
305 iowrite32(0x00000001, ioaddr + CSR0);
40c0d879 306 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
1da177e4
LT		 307 udelay(100);
308
309 /* Deassert reset.
310 Wait the specified 50 PCI cycles after a reset by initializing
311 Tx and Rx queues and the address filter list. */
312 iowrite32(tp->csr0, ioaddr + CSR0);
40c0d879 313 pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */
1da177e4
LT		 314 udelay(100);
315
316 if (tulip_debug > 1)
317 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
318
319 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
320 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
321 tp->cur_rx = tp->cur_tx = 0;
322 tp->dirty_rx = tp->dirty_tx = 0;
323
324 if (tp->flags & MC_HASH_ONLY) {
325 u32 addr_low = le32_to_cpu(get_unaligned((u32 *)dev->dev_addr));
326 u32 addr_high = le16_to_cpu(get_unaligned((u16 *)(dev->dev_addr+4)));
327 if (tp->chip_id == AX88140) {
328 iowrite32(0, ioaddr + CSR13);
329 iowrite32(addr_low, ioaddr + CSR14);
330 iowrite32(1, ioaddr + CSR13);
331 iowrite32(addr_high, ioaddr + CSR14);
332 } else if (tp->flags & COMET_MAC_ADDR) {
333 iowrite32(addr_low, ioaddr + 0xA4);
334 iowrite32(addr_high, ioaddr + 0xA8);
335 iowrite32(0, ioaddr + 0xAC);
336 iowrite32(0, ioaddr + 0xB0);
337 }
338 } else {
339 /* This is set_rx_mode(), but without starting the transmitter. */
340 u16 *eaddrs = (u16 *)dev->dev_addr;
341 u16 *setup_frm = &tp->setup_frame[15*6];
342 dma_addr_t mapping;
343
344 /* 21140 bug: you must add the broadcast address. */
345 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
346 /* Fill the final entry of the table with our physical address. */
347 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
348 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
349 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
350
351 mapping = pci_map_single(tp->pdev, tp->setup_frame,
352 sizeof(tp->setup_frame),
353 PCI_DMA_TODEVICE);
354 tp->tx_buffers[tp->cur_tx].skb = NULL;
355 tp->tx_buffers[tp->cur_tx].mapping = mapping;
356
357 /* Put the setup frame on the Tx list. */
358 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
359 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
360 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
361
362 tp->cur_tx++;
363 }
364
365 tp->saved_if_port = dev->if_port;
366 if (dev->if_port == 0)
367 dev->if_port = tp->default_port;
368
369 /* Allow selecting a default media. */
370 i = 0;
371 if (tp->mtable == NULL)
372 goto media_picked;
373 if (dev->if_port) {
374 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
375 (dev->if_port == 12 ? 0 : dev->if_port);
376 for (i = 0; i < tp->mtable->leafcount; i++)
377 if (tp->mtable->mleaf[i].media == looking_for) {
378 printk(KERN_INFO "%s: Using user-specified media %s.\n",
379 dev->name, medianame[dev->if_port]);
380 goto media_picked;
381 }
382 }
383 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
384 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
385 for (i = 0; i < tp->mtable->leafcount; i++)
386 if (tp->mtable->mleaf[i].media == looking_for) {
387 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
388 dev->name, medianame[looking_for]);
389 goto media_picked;
390 }
391 }
392 /* Start sensing first non-full-duplex media. */
393 for (i = tp->mtable->leafcount - 1;
394 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
395 ;
396media_picked:
397
398 tp->csr6 = 0;
399 tp->cur_index = i;
400 tp->nwayset = 0;
401
402 if (dev->if_port) {
403 if (tp->chip_id == DC21143 &&
404 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
405 /* We must reset the media CSRs when we force-select MII mode. */
406 iowrite32(0x0000, ioaddr + CSR13);
407 iowrite32(0x0000, ioaddr + CSR14);
408 iowrite32(0x0008, ioaddr + CSR15);
409 }
410 tulip_select_media(dev, 1);
411 } else if (tp->chip_id == DC21142) {
412 if (tp->mii_cnt) {
413 tulip_select_media(dev, 1);
414 if (tulip_debug > 1)
415 printk(KERN_INFO "%s: Using MII transceiver %d, status "
416 "%4.4x.\n",
417 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
418 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
419 tp->csr6 = csr6_mask_hdcap;
420 dev->if_port = 11;
421 iowrite32(0x0000, ioaddr + CSR13);
422 iowrite32(0x0000, ioaddr + CSR14);
423 } else
424 t21142_start_nway(dev);
425 } else if (tp->chip_id == PNIC2) {
426 /* for initial startup advertise 10/100 Full and Half */
427 tp->sym_advertise = 0x01E0;
428 /* enable autonegotiate end interrupt */
429 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
430 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
431 pnic2_start_nway(dev);
432 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
433 if (tp->mii_cnt) {
434 dev->if_port = 11;
435 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
436 iowrite32(0x0001, ioaddr + CSR15);
437 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
438 pnic_do_nway(dev);
439 else {
440 /* Start with 10mbps to do autonegotiation. */
441 iowrite32(0x32, ioaddr + CSR12);
442 tp->csr6 = 0x00420000;
443 iowrite32(0x0001B078, ioaddr + 0xB8);
444 iowrite32(0x0201B078, ioaddr + 0xB8);
445 next_tick = 1*HZ;
446 }
447 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
448 && ! tp->medialock) {
449 dev->if_port = 0;
450 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
451 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
452 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
453 /* Provided by BOLO, Macronix - 12/10/1998. */
454 dev->if_port = 0;
455 tp->csr6 = 0x01a80200;
456 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
457 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
458 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
459 /* Enable automatic Tx underrun recovery. */
460 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
461 dev->if_port = tp->mii_cnt ? 11 : 0;
462 tp->csr6 = 0x00040000;
463 } else if (tp->chip_id == AX88140) {
464 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
465 } else
466 tulip_select_media(dev, 1);
467
468 /* Start the chip's Tx to process setup frame. */
469 tulip_stop_rxtx(tp);
470 barrier();
471 udelay(5);
472 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
473
474 /* Enable interrupts by setting the interrupt mask. */
475 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
476 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
477 tulip_start_rxtx(tp);
478 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
479
480 if (tulip_debug > 2) {
481 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
482 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
483 ioread32(ioaddr + CSR6));
484 }
485
486 /* Set the timer to switch to check for link beat and perhaps switch
487 to an alternate media type. */
488 tp->timer.expires = RUN_AT(next_tick);
489 add_timer(&tp->timer);
490#ifdef CONFIG_TULIP_NAPI
491 init_timer(&tp->oom_timer);
492 tp->oom_timer.data = (unsigned long)dev;
493 tp->oom_timer.function = oom_timer;
494#endif
495}
496
497static int
498tulip_open(struct net_device *dev)
499{
500 int retval;
501
1fb9df5d 502 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
1da177e4
LT		 503 return retval;
504
505 tulip_init_ring (dev);
506
507 tulip_up (dev);
508
509 netif_start_queue (dev);
510
511 return 0;
512}
513
514
515static void tulip_tx_timeout(struct net_device *dev)
516{
517 struct tulip_private *tp = netdev_priv(dev);
518 void __iomem *ioaddr = tp->base_addr;
519 unsigned long flags;
520
521 spin_lock_irqsave (&tp->lock, flags);
522
523 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
524 /* Do nothing -- the media monitor should handle this. */
525 if (tulip_debug > 1)
526 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
527 dev->name);
528 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
529 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
ea8f400c 530 || tp->chip_id == DM910X) {
1da177e4
LT		 531 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
532 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
533 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
534 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
0bb3cf72
FR		 535 tp->timeout_recovery = 1;
536 schedule_work(&tp->media_work);
537 goto out_unlock;
1da177e4
LT		 538 } else if (tp->chip_id == PNIC2) {
539 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
540 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
541 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
542 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
543 } else {
544 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
545 "%8.8x, resetting...\n",
546 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
547 dev->if_port = 0;
548 }
549
550#if defined(way_too_many_messages)
551 if (tulip_debug > 3) {
552 int i;
553 for (i = 0; i < RX_RING_SIZE; i++) {
554 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
555 int j;
556 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
557 "%2.2x %2.2x %2.2x.\n",
558 i, (unsigned int)tp->rx_ring[i].status,
559 (unsigned int)tp->rx_ring[i].length,
560 (unsigned int)tp->rx_ring[i].buffer1,
561 (unsigned int)tp->rx_ring[i].buffer2,
562 buf[0], buf[1], buf[2]);
563 for (j = 0; buf[j] != 0xee && j < 1600; j++)
564 if (j < 100) printk(" %2.2x", buf[j]);
565 printk(" j=%d.\n", j);
566 }
567 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
568 for (i = 0; i < RX_RING_SIZE; i++)
569 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
570 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
571 for (i = 0; i < TX_RING_SIZE; i++)
572 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
573 printk("\n");
574 }
575#endif
576
0bb3cf72 577 tulip_tx_timeout_complete(tp, ioaddr);
1da177e4 578
0bb3cf72 579out_unlock:
1da177e4
LT		 580 spin_unlock_irqrestore (&tp->lock, flags);
581 dev->trans_start = jiffies;
582 netif_wake_queue (dev);
583}
584
585
586/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
587static void tulip_init_ring(struct net_device *dev)
588{
589 struct tulip_private *tp = netdev_priv(dev);
590 int i;
591
592 tp->susp_rx = 0;
593 tp->ttimer = 0;
594 tp->nir = 0;
595
596 for (i = 0; i < RX_RING_SIZE; i++) {
597 tp->rx_ring[i].status = 0x00000000;
598 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
599 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
600 tp->rx_buffers[i].skb = NULL;
601 tp->rx_buffers[i].mapping = 0;
602 }
603 /* Mark the last entry as wrapping the ring. */
604 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
605 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
606
607 for (i = 0; i < RX_RING_SIZE; i++) {
608 dma_addr_t mapping;
609
610 /* Note the receive buffer must be longword aligned.
611 dev_alloc_skb() provides 16 byte alignment. But do *not*
612 use skb_reserve() to align the IP header! */
613 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
614 tp->rx_buffers[i].skb = skb;
615 if (skb == NULL)
616 break;
689be439 617 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 618 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
619 tp->rx_buffers[i].mapping = mapping;
620 skb->dev = dev; /* Mark as being used by this device. */
621 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
622 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
623 }
624 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
625
626 /* The Tx buffer descriptor is filled in as needed, but we
627 do need to clear the ownership bit. */
628 for (i = 0; i < TX_RING_SIZE; i++) {
629 tp->tx_buffers[i].skb = NULL;
630 tp->tx_buffers[i].mapping = 0;
631 tp->tx_ring[i].status = 0x00000000;
632 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
633 }
634 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
635}
636
637static int
638tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
639{
640 struct tulip_private *tp = netdev_priv(dev);
641 int entry;
642 u32 flag;
643 dma_addr_t mapping;
644
645 spin_lock_irq(&tp->lock);
646
647 /* Calculate the next Tx descriptor entry. */
648 entry = tp->cur_tx % TX_RING_SIZE;
649
650 tp->tx_buffers[entry].skb = skb;
651 mapping = pci_map_single(tp->pdev, skb->data,
652 skb->len, PCI_DMA_TODEVICE);
653 tp->tx_buffers[entry].mapping = mapping;
654 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
655
656 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
657 flag = 0x60000000; /* No interrupt */
658 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
659 flag = 0xe0000000; /* Tx-done intr. */
660 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
661 flag = 0x60000000; /* No Tx-done intr. */
662 } else { /* Leave room for set_rx_mode() to fill entries. */
663 flag = 0xe0000000; /* Tx-done intr. */
664 netif_stop_queue(dev);
665 }
666 if (entry == TX_RING_SIZE-1)
667 flag = 0xe0000000 | DESC_RING_WRAP;
668
669 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
670 /* if we were using Transmit Automatic Polling, we would need a
671 * wmb() here. */
672 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
673 wmb();
674
675 tp->cur_tx++;
676
677 /* Trigger an immediate transmit demand. */
678 iowrite32(0, tp->base_addr + CSR1);
679
680 spin_unlock_irq(&tp->lock);
681
682 dev->trans_start = jiffies;
683
684 return 0;
685}
686
687static void tulip_clean_tx_ring(struct tulip_private *tp)
688{
689 unsigned int dirty_tx;
690
691 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
692 dirty_tx++) {
693 int entry = dirty_tx % TX_RING_SIZE;
694 int status = le32_to_cpu(tp->tx_ring[entry].status);
695
696 if (status < 0) {
697 tp->stats.tx_errors++; /* It wasn't Txed */
698 tp->tx_ring[entry].status = 0;
699 }
700
701 /* Check for Tx filter setup frames. */
702 if (tp->tx_buffers[entry].skb == NULL) {
703 /* test because dummy frames not mapped */
704 if (tp->tx_buffers[entry].mapping)
705 pci_unmap_single(tp->pdev,
706 tp->tx_buffers[entry].mapping,
707 sizeof(tp->setup_frame),
708 PCI_DMA_TODEVICE);
709 continue;
710 }
711
712 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
713 tp->tx_buffers[entry].skb->len,
714 PCI_DMA_TODEVICE);
715
716 /* Free the original skb. */
717 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
718 tp->tx_buffers[entry].skb = NULL;
719 tp->tx_buffers[entry].mapping = 0;
720 }
721}
722
723static void tulip_down (struct net_device *dev)
724{
725 struct tulip_private *tp = netdev_priv(dev);
726 void __iomem *ioaddr = tp->base_addr;
727 unsigned long flags;
728
0bb3cf72
FR		 729 flush_scheduled_work();
730
1da177e4
LT		 731 del_timer_sync (&tp->timer);
732#ifdef CONFIG_TULIP_NAPI
733 del_timer_sync (&tp->oom_timer);
734#endif
735 spin_lock_irqsave (&tp->lock, flags);
736
737 /* Disable interrupts by clearing the interrupt mask. */
738 iowrite32 (0x00000000, ioaddr + CSR7);
739
740 /* Stop the Tx and Rx processes. */
741 tulip_stop_rxtx(tp);
742
743 /* prepare receive buffers */
744 tulip_refill_rx(dev);
745
746 /* release any unconsumed transmit buffers */
747 tulip_clean_tx_ring(tp);
748
749 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
750 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
751
752 spin_unlock_irqrestore (&tp->lock, flags);
753
754 init_timer(&tp->timer);
755 tp->timer.data = (unsigned long)dev;
756 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
757
758 dev->if_port = tp->saved_if_port;
759
760 /* Leave the driver in snooze, not sleep, mode. */
761 tulip_set_power_state (tp, 0, 1);
762}
763
764
765static int tulip_close (struct net_device *dev)
766{
767 struct tulip_private *tp = netdev_priv(dev);
768 void __iomem *ioaddr = tp->base_addr;
769 int i;
770
771 netif_stop_queue (dev);
772
773 tulip_down (dev);
774
775 if (tulip_debug > 1)
776 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
777 dev->name, ioread32 (ioaddr + CSR5));
778
779 free_irq (dev->irq, dev);
780
781 /* Free all the skbuffs in the Rx queue. */
782 for (i = 0; i < RX_RING_SIZE; i++) {
783 struct sk_buff *skb = tp->rx_buffers[i].skb;
784 dma_addr_t mapping = tp->rx_buffers[i].mapping;
785
786 tp->rx_buffers[i].skb = NULL;
787 tp->rx_buffers[i].mapping = 0;
788
789 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
790 tp->rx_ring[i].length = 0;
791 tp->rx_ring[i].buffer1 = 0xBADF00D0; /* An invalid address. */
792 if (skb) {
793 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
794 PCI_DMA_FROMDEVICE);
795 dev_kfree_skb (skb);
796 }
797 }
798 for (i = 0; i < TX_RING_SIZE; i++) {
799 struct sk_buff *skb = tp->tx_buffers[i].skb;
800
801 if (skb != NULL) {
802 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
803 skb->len, PCI_DMA_TODEVICE);
804 dev_kfree_skb (skb);
805 }
806 tp->tx_buffers[i].skb = NULL;
807 tp->tx_buffers[i].mapping = 0;
808 }
809
810 return 0;
811}
812
813static struct net_device_stats *tulip_get_stats(struct net_device *dev)
814{
815 struct tulip_private *tp = netdev_priv(dev);
816 void __iomem *ioaddr = tp->base_addr;
817
818 if (netif_running(dev)) {
819 unsigned long flags;
820
821 spin_lock_irqsave (&tp->lock, flags);
822
823 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
824
825 spin_unlock_irqrestore(&tp->lock, flags);
826 }
827
828 return &tp->stats;
829}
830
831
832static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
833{
834 struct tulip_private *np = netdev_priv(dev);
835 strcpy(info->driver, DRV_NAME);
836 strcpy(info->version, DRV_VERSION);
837 strcpy(info->bus_info, pci_name(np->pdev));
838}
839
840static struct ethtool_ops ops = {
841 .get_drvinfo = tulip_get_drvinfo
842};
843
844/* Provide ioctl() calls to examine the MII xcvr state. */
845static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
846{
847 struct tulip_private *tp = netdev_priv(dev);
848 void __iomem *ioaddr = tp->base_addr;
849 struct mii_ioctl_data *data = if_mii(rq);
850 const unsigned int phy_idx = 0;
851 int phy = tp->phys[phy_idx] & 0x1f;
852 unsigned int regnum = data->reg_num;
853
854 switch (cmd) {
855 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
856 if (tp->mii_cnt)
857 data->phy_id = phy;
858 else if (tp->flags & HAS_NWAY)
859 data->phy_id = 32;
860 else if (tp->chip_id == COMET)
861 data->phy_id = 1;
862 else
863 return -ENODEV;
864
865 case SIOCGMIIREG: /* Read MII PHY register. */
866 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
867 int csr12 = ioread32 (ioaddr + CSR12);
868 int csr14 = ioread32 (ioaddr + CSR14);
869 switch (regnum) {
870 case 0:
871 if (((csr14<<5) & 0x1000) ||
872 (dev->if_port == 5 && tp->nwayset))
873 data->val_out = 0x1000;
874 else
875 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
876 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
877 break;
878 case 1:
879 data->val_out =
880 0x1848 +
881 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
882 ((csr12&0x06) == 6 ? 0 : 4);
883 data->val_out |= 0x6048;
884 break;
885 case 4:
886 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
887 data->val_out =
888 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
889 ((csr14 >> 1) & 0x20) + 1;
890 data->val_out |= ((csr14 >> 9) & 0x03C0);
891 break;
892 case 5: data->val_out = tp->lpar; break;
893 default: data->val_out = 0; break;
894 }
895 } else {
896 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
897 }
898 return 0;
899
900 case SIOCSMIIREG: /* Write MII PHY register. */
901 if (!capable (CAP_NET_ADMIN))
902 return -EPERM;
903 if (regnum & ~0x1f)
904 return -EINVAL;
905 if (data->phy_id == phy) {
906 u16 value = data->val_in;
907 switch (regnum) {
908 case 0: /* Check for autonegotiation on or reset. */
909 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
910 if (tp->full_duplex_lock)
911 tp->full_duplex = (value & 0x0100) ? 1 : 0;
912 break;
913 case 4:
914 tp->advertising[phy_idx] =
915 tp->mii_advertise = data->val_in;
916 break;
917 }
918 }
919 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
920 u16 value = data->val_in;
921 if (regnum == 0) {
922 if ((value & 0x1200) == 0x1200) {
923 if (tp->chip_id == PNIC2) {
924 pnic2_start_nway (dev);
925 } else {
926 t21142_start_nway (dev);
927 }
928 }
929 } else if (regnum == 4)
930 tp->sym_advertise = value;
931 } else {
932 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
933 }
934 return 0;
935 default:
936 return -EOPNOTSUPP;
937 }
938
939 return -EOPNOTSUPP;
940}
941
942
943/* Set or clear the multicast filter for this adaptor.
944 Note that we only use exclusion around actually queueing the
945 new frame, not around filling tp->setup_frame. This is non-deterministic
946 when re-entered but still correct. */
947
948#undef set_bit_le
949#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
950
951static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
952{
953 struct tulip_private *tp = netdev_priv(dev);
954 u16 hash_table[32];
955 struct dev_mc_list *mclist;
956 int i;
957 u16 *eaddrs;
958
959 memset(hash_table, 0, sizeof(hash_table));
960 set_bit_le(255, hash_table); /* Broadcast entry */
961 /* This should work on big-endian machines as well. */
962 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
963 i++, mclist = mclist->next) {
964 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
965
966 set_bit_le(index, hash_table);
967
968 }
969 for (i = 0; i < 32; i++) {
970 *setup_frm++ = hash_table[i];
971 *setup_frm++ = hash_table[i];
972 }
973 setup_frm = &tp->setup_frame[13*6];
974
975 /* Fill the final entry with our physical address. */
976 eaddrs = (u16 *)dev->dev_addr;
977 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
978 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
979 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
980}
981
982static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
983{
984 struct tulip_private *tp = netdev_priv(dev);
985 struct dev_mc_list *mclist;
986 int i;
987 u16 *eaddrs;
988
989 /* We have <= 14 addresses so we can use the wonderful
990 16 address perfect filtering of the Tulip. */
991 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
992 i++, mclist = mclist->next) {
993 eaddrs = (u16 *)mclist->dmi_addr;
994 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
995 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
996 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
997 }
998 /* Fill the unused entries with the broadcast address. */
999 memset(setup_frm, 0xff, (15-i)*12);
1000 setup_frm = &tp->setup_frame[15*6];
1001
1002 /* Fill the final entry with our physical address. */
1003 eaddrs = (u16 *)dev->dev_addr;
1004 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1005 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1006 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1007}
1008
1009
1010static void set_rx_mode(struct net_device *dev)
1011{
1012 struct tulip_private *tp = netdev_priv(dev);
1013 void __iomem *ioaddr = tp->base_addr;
1014 int csr6;
1015
1016 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1017
1018 tp->csr6 &= ~0x00D5;
1019 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1020 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1021 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1022 /* Unconditionally log net taps. */
1023 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1024 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1025 /* Too many to filter well -- accept all multicasts. */
1026 tp->csr6 |= AcceptAllMulticast;
1027 csr6 |= AcceptAllMulticast;
1028 } else if (tp->flags & MC_HASH_ONLY) {
1029 /* Some work-alikes have only a 64-entry hash filter table. */
1030 /* Should verify correctness on big-endian/__powerpc__ */
1031 struct dev_mc_list *mclist;
1032 int i;
1033 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1034 tp->csr6 |= AcceptAllMulticast;
1035 csr6 |= AcceptAllMulticast;
1036 } else {
1037 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1038 int filterbit;
1039 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1040 i++, mclist = mclist->next) {
1041 if (tp->flags & COMET_MAC_ADDR)
1042 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1043 else
1044 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1045 filterbit &= 0x3f;
1046 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1047 if (tulip_debug > 2) {
1048 printk(KERN_INFO "%s: Added filter for %2.2x:%2.2x:%2.2x:"
1049 "%2.2x:%2.2x:%2.2x %8.8x bit %d.\n", dev->name,
1050 mclist->dmi_addr[0], mclist->dmi_addr[1],
1051 mclist->dmi_addr[2], mclist->dmi_addr[3],
1052 mclist->dmi_addr[4], mclist->dmi_addr[5],
1053 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1054 }
1055 }
1056 if (mc_filter[0] == tp->mc_filter[0] &&
1057 mc_filter[1] == tp->mc_filter[1])
1058 ; /* No change. */
1059 else if (tp->flags & IS_ASIX) {
1060 iowrite32(2, ioaddr + CSR13);
1061 iowrite32(mc_filter[0], ioaddr + CSR14);
1062 iowrite32(3, ioaddr + CSR13);
1063 iowrite32(mc_filter[1], ioaddr + CSR14);
1064 } else if (tp->flags & COMET_MAC_ADDR) {
1065 iowrite32(mc_filter[0], ioaddr + 0xAC);
1066 iowrite32(mc_filter[1], ioaddr + 0xB0);
1067 }
1068 tp->mc_filter[0] = mc_filter[0];
1069 tp->mc_filter[1] = mc_filter[1];
1070 }
1071 } else {
1072 unsigned long flags;
1073 u32 tx_flags = 0x08000000 | 192;
1074
1075 /* Note that only the low-address shortword of setup_frame is valid!
1076 The values are doubled for big-endian architectures. */
1077 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1078 build_setup_frame_hash(tp->setup_frame, dev);
1079 tx_flags = 0x08400000 | 192;
1080 } else {
1081 build_setup_frame_perfect(tp->setup_frame, dev);
1082 }
1083
1084 spin_lock_irqsave(&tp->lock, flags);
1085
1086 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1087 /* Same setup recently queued, we need not add it. */
1088 } else {
1089 unsigned int entry;
1090 int dummy = -1;
1091
1092 /* Now add this frame to the Tx list. */
1093
1094 entry = tp->cur_tx++ % TX_RING_SIZE;
1095
1096 if (entry != 0) {
ea8f400c
PC		 1097 /* Avoid a chip errata by prefixing a dummy entry. */
1098 tp->tx_buffers[entry].skb = NULL;
1099 tp->tx_buffers[entry].mapping = 0;
1100 tp->tx_ring[entry].length =
1101 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1102 tp->tx_ring[entry].buffer1 = 0;
1103 /* Must set DescOwned later to avoid race with chip */
1104 dummy = entry;
1105 entry = tp->cur_tx++ % TX_RING_SIZE;
1106
1da177e4
LT		 1107 }
1108
1109 tp->tx_buffers[entry].skb = NULL;
1110 tp->tx_buffers[entry].mapping =
1111 pci_map_single(tp->pdev, tp->setup_frame,
1112 sizeof(tp->setup_frame),
1113 PCI_DMA_TODEVICE);
1114 /* Put the setup frame on the Tx list. */
1115 if (entry == TX_RING_SIZE-1)
1116 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1117 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1118 tp->tx_ring[entry].buffer1 =
1119 cpu_to_le32(tp->tx_buffers[entry].mapping);
1120 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1121 if (dummy >= 0)
1122 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1123 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1124 netif_stop_queue(dev);
1125
1126 /* Trigger an immediate transmit demand. */
1127 iowrite32(0, ioaddr + CSR1);
1128 }
1129
1130 spin_unlock_irqrestore(&tp->lock, flags);
1131 }
1132
1133 iowrite32(csr6, ioaddr + CSR6);
1134}
1135
1136#ifdef CONFIG_TULIP_MWI
1137static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1138 struct net_device *dev)
1139{
1140 struct tulip_private *tp = netdev_priv(dev);
1141 u8 cache;
1142 u16 pci_command;
1143 u32 csr0;
1144
1145 if (tulip_debug > 3)
1146 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1147
1148 tp->csr0 = csr0 = 0;
1149
1150 /* if we have any cache line size at all, we can do MRM */
1151 csr0 |= MRM;
1152
1153 /* ...and barring hardware bugs, MWI */
1154 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1155 csr0 |= MWI;
1156
1157 /* set or disable MWI in the standard PCI command bit.
1158 * Check for the case where mwi is desired but not available
1159 */
1160 if (csr0 & MWI) pci_set_mwi(pdev);
1161 else pci_clear_mwi(pdev);
1162
1163 /* read result from hardware (in case bit refused to enable) */
1164 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1165 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1166 csr0 &= ~MWI;
1167
1168 /* if cache line size hardwired to zero, no MWI */
1169 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1170 if ((csr0 & MWI) && (cache == 0)) {
1171 csr0 &= ~MWI;
1172 pci_clear_mwi(pdev);
1173 }
1174
1175 /* assign per-cacheline-size cache alignment and
1176 * burst length values
1177 */
1178 switch (cache) {
1179 case 8:
1180 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1181 break;
1182 case 16:
1183 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1184 break;
1185 case 32:
1186 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1187 break;
1188 default:
1189 cache = 0;
1190 break;
1191 }
1192
1193 /* if we have a good cache line size, we by now have a good
1194 * csr0, so save it and exit
1195 */
1196 if (cache)
1197 goto out;
1198
1199 /* we don't have a good csr0 or cache line size, disable MWI */
1200 if (csr0 & MWI) {
1201 pci_clear_mwi(pdev);
1202 csr0 &= ~MWI;
1203 }
1204
1205 /* sane defaults for burst length and cache alignment
1206 * originally from de4x5 driver
1207 */
1208 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1209
1210out:
1211 tp->csr0 = csr0;
1212 if (tulip_debug > 2)
1213 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1214 pci_name(pdev), cache, csr0);
1215}
1216#endif
1217
1218/*
1219 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1220 * is the DM910X and the on chip ULi devices
1221 */
f3b197ac 1222
1da177e4
LT		 1223static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1224{
1225 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1226 return 1;
1da177e4
LT		 1227 return 0;
1228}
1229
1230static int __devinit tulip_init_one (struct pci_dev *pdev,
1231 const struct pci_device_id *ent)
1232{
1233 struct tulip_private *tp;
1234 /* See note below on the multiport cards. */
1235 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1236 static struct pci_device_id early_486_chipsets[] = {
1237 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1238 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1239 { },
1240 };
1241 static int last_irq;
1242 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1243 u8 chip_rev;
1244 int i, irq;
1245 unsigned short sum;
1246 unsigned char *ee_data;
1247 struct net_device *dev;
1248 void __iomem *ioaddr;
1249 static int board_idx = -1;
1250 int chip_idx = ent->driver_data;
1251 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1252 unsigned int eeprom_missing = 0;
1253 unsigned int force_csr0 = 0;
1254
1255#ifndef MODULE
1256 static int did_version; /* Already printed version info. */
1257 if (tulip_debug > 0 && did_version++ == 0)
1258 printk (KERN_INFO "%s", version);
1259#endif
1260
1261 board_idx++;
1262
1263 /*
1264 * Lan media wire a tulip chip to a wan interface. Needs a very
1265 * different driver (lmc driver)
1266 */
1267
1268 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1269 printk (KERN_ERR PFX "skipping LMC card.\n");
1270 return -ENODEV;
1271 }
1272
1273 /*
1274 * Early DM9100's need software CRC and the DMFE driver
1275 */
1276
1277 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1278 {
1279 u32 dev_rev;
1280 /* Read Chip revision */
1281 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
1282 if(dev_rev < 0x02000030)
1283 {
1284 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1285 return -ENODEV;
1286 }
1287 }
1288
1289 /*
1290 * Looks for early PCI chipsets where people report hangs
1291 * without the workarounds being on.
1292 */
1293
1294 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1295 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1296 pretty reading but thankfully it's an old 486 chipset.
1297
1298 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1299 Saturn.
1300 */
1301
1302 if (pci_dev_present(early_486_chipsets)) {
1303 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1304 force_csr0 = 1;
1305 }
1306
1307 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1308 if (chip_idx == AX88140) {
1309 if ((csr0 & 0x3f00) == 0)
1310 csr0 |= 0x2000;
1311 }
1312
1313 /* PNIC doesn't have MWI/MRL/MRM... */
1314 if (chip_idx == LC82C168)
1315 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1316
1317 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1318 if (tulip_uli_dm_quirk(pdev)) {
1319 csr0 &= ~0x01f100ff;
1320#if defined(__sparc__)
1321 csr0 = (csr0 & ~0xff00) | 0xe000;
1322#endif
1323 }
1324 /*
1325 * And back to business
1326 */
1327
1328 i = pci_enable_device(pdev);
1329 if (i) {
1330 printk (KERN_ERR PFX
1331 "Cannot enable tulip board #%d, aborting\n",
1332 board_idx);
1333 return i;
1334 }
1335
1336 irq = pdev->irq;
1337
1338 /* alloc_etherdev ensures aligned and zeroed private structures */
1339 dev = alloc_etherdev (sizeof (*tp));
1340 if (!dev) {
1341 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1342 return -ENOMEM;
1343 }
1344
1345 SET_MODULE_OWNER(dev);
1346 SET_NETDEV_DEV(dev, &pdev->dev);
1347 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
7c7459d1 1348 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1da177e4 1349 "aborting\n", pci_name(pdev),
7c7459d1
GKH		 1350 (unsigned long long)pci_resource_len (pdev, 0),
1351 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1352 goto err_out_free_netdev;
1353 }
1354
1355 /* grab all resources from both PIO and MMIO regions, as we
1356 * don't want anyone else messing around with our hardware */
1357 if (pci_request_regions (pdev, "tulip"))
1358 goto err_out_free_netdev;
1359
7f2b1248
GG		 1360 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1361
1da177e4
LT		 1362 if (!ioaddr)
1363 goto err_out_free_res;
1364
1365 pci_read_config_byte (pdev, PCI_REVISION_ID, &chip_rev);
1366
1367 /*
1368 * initialize private data structure 'tp'
1369 * it is zeroed and aligned in alloc_etherdev
1370 */
1371 tp = netdev_priv(dev);
1372
1373 tp->rx_ring = pci_alloc_consistent(pdev,
1374 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1375 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1376 &tp->rx_ring_dma);
1377 if (!tp->rx_ring)
1378 goto err_out_mtable;
1379 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1380 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1381
1382 tp->chip_id = chip_idx;
1383 tp->flags = tulip_tbl[chip_idx].flags;
1384 tp->pdev = pdev;
1385 tp->base_addr = ioaddr;
1386 tp->revision = chip_rev;
1387 tp->csr0 = csr0;
1388 spin_lock_init(&tp->lock);
1389 spin_lock_init(&tp->mii_lock);
1390 init_timer(&tp->timer);
1391 tp->timer.data = (unsigned long)dev;
1392 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1393
0bb3cf72
FR		 1394 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task, dev);
1395
1da177e4
LT		 1396 dev->base_addr = (unsigned long)ioaddr;
1397
1398#ifdef CONFIG_TULIP_MWI
1399 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1400 tulip_mwi_config (pdev, dev);
1401#else
1402 /* MWI is broken for DC21143 rev 65... */
1403 if (chip_idx == DC21143 && chip_rev == 65)
1404 tp->csr0 &= ~MWI;
1405#endif
1406
1407 /* Stop the chip's Tx and Rx processes. */
1408 tulip_stop_rxtx(tp);
1409
1410 pci_set_master(pdev);
1411
1412#ifdef CONFIG_GSC
1413 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1414 switch (pdev->subsystem_device) {
1415 default:
1416 break;
1417 case 0x1061:
1418 case 0x1062:
1419 case 0x1063:
1420 case 0x1098:
1421 case 0x1099:
1422 case 0x10EE:
1423 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1424 chip_name = "GSC DS21140 Tulip";
1425 }
1426 }
1427#endif
1428
1429 /* Clear the missed-packet counter. */
1430 ioread32(ioaddr + CSR8);
1431
1432 /* The station address ROM is read byte serially. The register must
1433 be polled, waiting for the value to be read bit serially from the
1434 EEPROM.
1435 */
1436 ee_data = tp->eeprom;
1437 sum = 0;
1438 if (chip_idx == LC82C168) {
1439 for (i = 0; i < 3; i++) {
1440 int value, boguscnt = 100000;
1441 iowrite32(0x600 | i, ioaddr + 0x98);
1442 do
1443 value = ioread32(ioaddr + CSR9);
1444 while (value < 0 && --boguscnt > 0);
1445 put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
1446 sum += value & 0xffff;
1447 }
1448 } else if (chip_idx == COMET) {
1449 /* No need to read the EEPROM. */
1450 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (u32 *)dev->dev_addr);
1451 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (u16 *)(dev->dev_addr + 4));
1452 for (i = 0; i < 6; i ++)
1453 sum += dev->dev_addr[i];
1454 } else {
1455 /* A serial EEPROM interface, we read now and sort it out later. */
1456 int sa_offset = 0;
1457 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1458
1459 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1460 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1461 ee_data[i] = data & 0xff;
1462 ee_data[i + 1] = data >> 8;
1463 }
1464
1465 /* DEC now has a specification (see Notes) but early board makers
1466 just put the address in the first EEPROM locations. */
1467 /* This does memcmp(ee_data, ee_data+16, 8) */
1468 for (i = 0; i < 8; i ++)
1469 if (ee_data[i] != ee_data[16+i])
1470 sa_offset = 20;
1471 if (chip_idx == CONEXANT) {
1472 /* Check that the tuple type and length is correct. */
1473 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1474 sa_offset = 0x19A;
1475 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1476 ee_data[2] == 0) {
1477 sa_offset = 2; /* Grrr, damn Matrox boards. */
1478 multiport_cnt = 4;
1479 }
1da177e4
LT		 1480#ifdef CONFIG_DDB5477
1481 if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
1482 /* DDB5477 MAC address in first EEPROM locations. */
1483 sa_offset = 0;
1484 /* No media table either */
1485 tp->flags &= ~HAS_MEDIA_TABLE;
1486 }
1487#endif
1488#ifdef CONFIG_MIPS_COBALT
f3b197ac 1489 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1490 ((PCI_SLOT(pdev->devfn) == 7) ||
1491 (PCI_SLOT(pdev->devfn) == 12))) {
1492 /* Cobalt MAC address in first EEPROM locations. */
1493 sa_offset = 0;
12755c16
RB		 1494 /* Ensure our media table fixup get's applied */
1495 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1496 }
1497#endif
1498#ifdef CONFIG_GSC
1499 /* Check to see if we have a broken srom */
1500 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1501 /* pci_vendor_id and subsystem_id are swapped */
1502 ee_data[0] = ee_data[2];
1503 ee_data[1] = ee_data[3];
1504 ee_data[2] = 0x61;
1505 ee_data[3] = 0x10;
1506
1507 /* HSC-PCI boards need to be byte-swaped and shifted
1508 * up 1 word. This shift needs to happen at the end
1509 * of the MAC first because of the 2 byte overlap.
1510 */
1511 for (i = 4; i >= 0; i -= 2) {
1512 ee_data[17 + i + 3] = ee_data[17 + i];
1513 ee_data[16 + i + 5] = ee_data[16 + i];
1514 }
1515 }
1516#endif
1517
1518 for (i = 0; i < 6; i ++) {
1519 dev->dev_addr[i] = ee_data[i + sa_offset];
1520 sum += ee_data[i + sa_offset];
1521 }
1522 }
1523 /* Lite-On boards have the address byte-swapped. */
1524 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1525 && dev->dev_addr[1] == 0x00)
1526 for (i = 0; i < 6; i+=2) {
1527 char tmp = dev->dev_addr[i];
1528 dev->dev_addr[i] = dev->dev_addr[i+1];
1529 dev->dev_addr[i+1] = tmp;
1530 }
1531 /* On the Zynx 315 Etherarray and other multiport boards only the
1532 first Tulip has an EEPROM.
1533 On Sparc systems the mac address is held in the OBP property
1534 "local-mac-address".
1535 The addresses of the subsequent ports are derived from the first.
1536 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1537 that here as well. */
1538 if (sum == 0 || sum == 6*0xff) {
1539#if defined(__sparc__)
1540 struct pcidev_cookie *pcp = pdev->sysdata;
1541#endif
1542 eeprom_missing = 1;
1543 for (i = 0; i < 5; i++)
1544 dev->dev_addr[i] = last_phys_addr[i];
1545 dev->dev_addr[i] = last_phys_addr[i] + 1;
1546#if defined(__sparc__)
de8d28b1
DM		 1547 if (pcp) {
1548 unsigned char *addr;
1549 int len;
1550
1551 addr = of_get_property(pcp->prom_node,
1552 "local-mac-address", &len);
1553 if (addr && len == 6)
1554 memcpy(dev->dev_addr, addr, 6);
1da177e4
LT		 1555 }
1556#endif
b9c4c609 1557#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1558 if (last_irq)
1559 irq = last_irq;
1560#endif
1561 }
1562
1563 for (i = 0; i < 6; i++)
1564 last_phys_addr[i] = dev->dev_addr[i];
1565 last_irq = irq;
1566 dev->irq = irq;
1567
1568 /* The lower four bits are the media type. */
1569 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1570 if (options[board_idx] & MEDIA_MASK)
1571 tp->default_port = options[board_idx] & MEDIA_MASK;
1572 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1573 tp->full_duplex = 1;
1574 if (mtu[board_idx] > 0)
1575 dev->mtu = mtu[board_idx];
1576 }
1577 if (dev->mem_start & MEDIA_MASK)
1578 tp->default_port = dev->mem_start & MEDIA_MASK;
1579 if (tp->default_port) {
1580 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1581 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1582 tp->medialock = 1;
1583 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1584 tp->full_duplex = 1;
1585 }
1586 if (tp->full_duplex)
1587 tp->full_duplex_lock = 1;
1588
1589 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1590 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1591 tp->mii_advertise = media2advert[tp->default_port - 9];
1592 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1593 }
1594
1595 if (tp->flags & HAS_MEDIA_TABLE) {
1596 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1597 tulip_parse_eeprom(dev);
1598 strcpy(dev->name, "eth%d"); /* un-hack */
1599 }
1600
1601 if ((tp->flags & ALWAYS_CHECK_MII) ||
1602 (tp->mtable && tp->mtable->has_mii) ||
1603 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1604 if (tp->mtable && tp->mtable->has_mii) {
1605 for (i = 0; i < tp->mtable->leafcount; i++)
1606 if (tp->mtable->mleaf[i].media == 11) {
1607 tp->cur_index = i;
1608 tp->saved_if_port = dev->if_port;
1609 tulip_select_media(dev, 2);
1610 dev->if_port = tp->saved_if_port;
1611 break;
1612 }
1613 }
1614
1615 /* Find the connected MII xcvrs.
1616 Doing this in open() would allow detecting external xcvrs
1617 later, but takes much time. */
1618 tulip_find_mii (dev, board_idx);
1619 }
1620
1621 /* The Tulip-specific entries in the device structure. */
1622 dev->open = tulip_open;
1623 dev->hard_start_xmit = tulip_start_xmit;
1624 dev->tx_timeout = tulip_tx_timeout;
1625 dev->watchdog_timeo = TX_TIMEOUT;
1626#ifdef CONFIG_TULIP_NAPI
1627 dev->poll = tulip_poll;
1628 dev->weight = 16;
1629#endif
1630 dev->stop = tulip_close;
1631 dev->get_stats = tulip_get_stats;
1632 dev->do_ioctl = private_ioctl;
1633 dev->set_multicast_list = set_rx_mode;
1634#ifdef CONFIG_NET_POLL_CONTROLLER
1635 dev->poll_controller = &poll_tulip;
1636#endif
1637 SET_ETHTOOL_OPS(dev, &ops);
1638
1639 if (register_netdev(dev))
1640 goto err_out_free_ring;
1641
c69f4122
GG		 1642 printk(KERN_INFO "%s: %s rev %d at "
1643#ifdef CONFIG_TULIP_MMIO
1644 "MMIO"
1645#else
1646 "Port"
1647#endif
1648 " %#llx,", dev->name, chip_name, chip_rev,
1649 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1da177e4
LT		 1650 pci_set_drvdata(pdev, dev);
1651
1652 if (eeprom_missing)
1653 printk(" EEPROM not present,");
1654 for (i = 0; i < 6; i++)
1655 printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);
1656 printk(", IRQ %d.\n", irq);
1657
1658 if (tp->chip_id == PNIC2)
1659 tp->link_change = pnic2_lnk_change;
1660 else if (tp->flags & HAS_NWAY)
1661 tp->link_change = t21142_lnk_change;
1662 else if (tp->flags & HAS_PNICNWAY)
1663 tp->link_change = pnic_lnk_change;
1664
1665 /* Reset the xcvr interface and turn on heartbeat. */
1666 switch (chip_idx) {
1667 case DC21140:
1668 case DM910X:
1da177e4
LT		 1669 default:
1670 if (tp->mtable)
1671 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1672 break;
1673 case DC21142:
1674 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1675 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1676 iowrite32(0x0000, ioaddr + CSR13);
1677 iowrite32(0x0000, ioaddr + CSR14);
1678 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1679 } else
1680 t21142_start_nway(dev);
1681 break;
1682 case PNIC2:
1683 /* just do a reset for sanity sake */
1684 iowrite32(0x0000, ioaddr + CSR13);
1685 iowrite32(0x0000, ioaddr + CSR14);
1686 break;
1687 case LC82C168:
1688 if ( ! tp->mii_cnt) {
1689 tp->nway = 1;
1690 tp->nwayset = 0;
1691 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1692 iowrite32(0x30, ioaddr + CSR12);
1693 iowrite32(0x0001F078, ioaddr + CSR6);
1694 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1695 }
1696 break;
1697 case MX98713:
1698 case COMPEX9881:
1699 iowrite32(0x00000000, ioaddr + CSR6);
1700 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1701 iowrite32(0x00000001, ioaddr + CSR13);
1702 break;
1703 case MX98715:
1704 case MX98725:
1705 iowrite32(0x01a80000, ioaddr + CSR6);
1706 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1707 iowrite32(0x00001000, ioaddr + CSR12);
1708 break;
1709 case COMET:
1710 /* No initialization necessary. */
1711 break;
1712 }
1713
1714 /* put the chip in snooze mode until opened */
1715 tulip_set_power_state (tp, 0, 1);
1716
1717 return 0;
1718
1719err_out_free_ring:
1720 pci_free_consistent (pdev,
1721 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1722 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1723 tp->rx_ring, tp->rx_ring_dma);
1724
1725err_out_mtable:
b4558ea9 1726 kfree (tp->mtable);
1da177e4
LT		 1727 pci_iounmap(pdev, ioaddr);
1728
1729err_out_free_res:
1730 pci_release_regions (pdev);
1731
1732err_out_free_netdev:
1733 free_netdev (dev);
1734 return -ENODEV;
1735}
1736
1737
1738#ifdef CONFIG_PM
1739
1740static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1741{
1742 struct net_device *dev = pci_get_drvdata(pdev);
1743
1fe2cb32
AB		 1744 if (!dev)
1745 return -EINVAL;
1746
1747 if (netif_running(dev))
1748 tulip_down(dev);
1749
1750 netif_device_detach(dev);
1751 free_irq(dev->irq, dev);
1752
1753 pci_save_state(pdev);
1754 pci_disable_device(pdev);
1755 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1756
1da177e4
LT		 1757 return 0;
1758}
1759
1760
1761static int tulip_resume(struct pci_dev *pdev)
1762{
1763 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1764 int retval;
1da177e4 1765
1fe2cb32
AB		 1766 if (!dev)
1767 return -EINVAL;
1768
1769 pci_set_power_state(pdev, PCI_D0);
1770 pci_restore_state(pdev);
1771
1772 pci_enable_device(pdev);
1773
1fb9df5d 1774 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1fe2cb32
AB		 1775 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1776 return retval;
1da177e4 1777 }
1fe2cb32
AB		 1778
1779 netif_device_attach(dev);
1780
1781 if (netif_running(dev))
1782 tulip_up(dev);
1783
1da177e4
LT		 1784 return 0;
1785}
1786
1787#endif /* CONFIG_PM */
1788
1789
1790static void __devexit tulip_remove_one (struct pci_dev *pdev)
1791{
1792 struct net_device *dev = pci_get_drvdata (pdev);
1793 struct tulip_private *tp;
1794
1795 if (!dev)
1796 return;
1797
1798 tp = netdev_priv(dev);
1799 unregister_netdev(dev);
1800 pci_free_consistent (pdev,
1801 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1802 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1803 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1804 kfree (tp->mtable);
1da177e4
LT		 1805 pci_iounmap(pdev, tp->base_addr);
1806 free_netdev (dev);
1807 pci_release_regions (pdev);
1808 pci_set_drvdata (pdev, NULL);
1809
1810 /* pci_power_off (pdev, -1); */
1811}
1812
1813#ifdef CONFIG_NET_POLL_CONTROLLER
1814/*
1815 * Polling 'interrupt' - used by things like netconsole to send skbs
1816 * without having to re-enable interrupts. It's not called while
1817 * the interrupt routine is executing.
1818 */
1819
1820static void poll_tulip (struct net_device *dev)
1821{
1822 /* disable_irq here is not very nice, but with the lockless
1823 interrupt handler we have no other choice. */
1824 disable_irq(dev->irq);
1825 tulip_interrupt (dev->irq, dev, NULL);
1826 enable_irq(dev->irq);
1827}
1828#endif
1829
1830static struct pci_driver tulip_driver = {
1831 .name = DRV_NAME,
1832 .id_table = tulip_pci_tbl,
1833 .probe = tulip_init_one,
1834 .remove = __devexit_p(tulip_remove_one),
1835#ifdef CONFIG_PM
1836 .suspend = tulip_suspend,
1837 .resume = tulip_resume,
1838#endif /* CONFIG_PM */
1839};
1840
1841
1842static int __init tulip_init (void)
1843{
1844#ifdef MODULE
1845 printk (KERN_INFO "%s", version);
1846#endif
1847
1848 /* copy module parms into globals */
1849 tulip_rx_copybreak = rx_copybreak;
1850 tulip_max_interrupt_work = max_interrupt_work;
1851
1852 /* probe for and init boards */
29917620 1853 return pci_register_driver(&tulip_driver);
1da177e4
LT		 1854}
1855
1856
1857static void __exit tulip_cleanup (void)
1858{
1859 pci_unregister_driver (&tulip_driver);
1860}
1861
1862
1863module_init(tulip_init);
1864module_exit(tulip_cleanup);
kernel source for telekom puls (alcatel/mediatek)