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1a348ccc AG |
1 | /* |
2 | * Tehuti Networks(R) Network Driver | |
3 | * ethtool interface implementation | |
4 | * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * RX HW/SW interaction overview | |
14 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
15 | * There are 2 types of RX communication channels betwean driver and NIC. | |
16 | * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming | |
17 | * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds | |
18 | * info about buffer's location, size and ID. An ID field is used to identify a | |
19 | * buffer when it's returned with data via RXD Fifo (see below) | |
20 | * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is | |
21 | * filled by HW and is readen by SW. Each descriptor holds status and ID. | |
22 | * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data, | |
23 | * via dma moves it into host memory, builds new RXD descriptor with same ID, | |
24 | * pushes it into RXD Fifo and raises interrupt to indicate new RX data. | |
25 | * | |
26 | * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos. | |
27 | * One holds 1.5K packets and another - 26K packets. Depending on incoming | |
28 | * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is | |
29 | * filled with data, HW builds new RXD descriptor for it and push it into single | |
30 | * RXD Fifo. | |
31 | * | |
32 | * RX SW Data Structures | |
33 | * ~~~~~~~~~~~~~~~~~~~~~ | |
34 | * skb db - used to keep track of all skbs owned by SW and their dma addresses. | |
35 | * For RX case, ownership lasts from allocating new empty skb for RXF until | |
36 | * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own | |
37 | * skb db. Implemented as array with bitmask. | |
38 | * fifo - keeps info about fifo's size and location, relevant HW registers, | |
39 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. | |
40 | * Implemented as simple struct. | |
41 | * | |
42 | * RX SW Execution Flow | |
43 | * ~~~~~~~~~~~~~~~~~~~~ | |
44 | * Upon initialization (ifconfig up) driver creates RX fifos and initializes | |
45 | * relevant registers. At the end of init phase, driver enables interrupts. | |
46 | * NIC sees that there is no RXF buffers and raises | |
47 | * RD_INTR interrupt, isr fills skbs and Rx begins. | |
48 | * Driver has two receive operation modes: | |
49 | * NAPI - interrupt-driven mixed with polling | |
50 | * interrupt-driven only | |
51 | * | |
52 | * Interrupt-driven only flow is following. When buffer is ready, HW raises | |
53 | * interrupt and isr is called. isr collects all available packets | |
54 | * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit. | |
55 | ||
56 | * Rx buffer allocation note | |
57 | * ~~~~~~~~~~~~~~~~~~~~~~~~~ | |
58 | * Driver cares to feed such amount of RxF descriptors that respective amount of | |
59 | * RxD descriptors can not fill entire RxD fifo. The main reason is lack of | |
60 | * overflow check in Bordeaux for RxD fifo free/used size. | |
61 | * FIXME: this is NOT fully implemented, more work should be done | |
62 | * | |
63 | */ | |
64 | ||
65 | #include "tehuti.h" | |
66 | #include "tehuti_fw.h" | |
67 | ||
68 | static struct pci_device_id __devinitdata bdx_pci_tbl[] = { | |
69 | {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
70 | {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
71 | {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
72 | {0} | |
73 | }; | |
74 | ||
75 | MODULE_DEVICE_TABLE(pci, bdx_pci_tbl); | |
76 | ||
77 | /* Definitions needed by ISR or NAPI functions */ | |
78 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f); | |
79 | static void bdx_tx_cleanup(struct bdx_priv *priv); | |
80 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget); | |
81 | ||
82 | /* Definitions needed by FW loading */ | |
83 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size); | |
84 | ||
85 | /* Definitions needed by hw_start */ | |
86 | static int bdx_tx_init(struct bdx_priv *priv); | |
87 | static int bdx_rx_init(struct bdx_priv *priv); | |
88 | ||
89 | /* Definitions needed by bdx_close */ | |
90 | static void bdx_rx_free(struct bdx_priv *priv); | |
91 | static void bdx_tx_free(struct bdx_priv *priv); | |
92 | ||
93 | /* Definitions needed by bdx_probe */ | |
94 | static void bdx_ethtool_ops(struct net_device *netdev); | |
95 | ||
96 | /************************************************************************* | |
97 | * Print Info * | |
98 | *************************************************************************/ | |
99 | ||
100 | static void print_hw_id(struct pci_dev *pdev) | |
101 | { | |
102 | struct pci_nic *nic = pci_get_drvdata(pdev); | |
103 | u16 pci_link_status = 0; | |
104 | u16 pci_ctrl = 0; | |
105 | ||
106 | pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status); | |
107 | pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl); | |
108 | ||
109 | printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME, | |
110 | nic->port_num == 1 ? "" : ", 2-Port"); | |
111 | printk(KERN_INFO | |
112 | "tehuti: srom 0x%x fpga %d build %u lane# %d" | |
113 | " max_pl 0x%x mrrs 0x%x\n", | |
114 | readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF, | |
115 | readl(nic->regs + FPGA_SEED), | |
116 | GET_LINK_STATUS_LANES(pci_link_status), | |
117 | GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl)); | |
118 | } | |
119 | ||
120 | static void print_fw_id(struct pci_nic *nic) | |
121 | { | |
122 | printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER)); | |
123 | } | |
124 | ||
125 | static void print_eth_id(struct net_device *ndev) | |
126 | { | |
127 | printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME, | |
128 | (ndev->if_port == 0) ? 'A' : 'B'); | |
129 | ||
130 | } | |
131 | ||
132 | /************************************************************************* | |
133 | * Code * | |
134 | *************************************************************************/ | |
135 | ||
136 | #define bdx_enable_interrupts(priv) \ | |
137 | do { WRITE_REG(priv, regIMR, IR_RUN); } while (0) | |
138 | #define bdx_disable_interrupts(priv) \ | |
139 | do { WRITE_REG(priv, regIMR, 0); } while (0) | |
140 | ||
141 | /* bdx_fifo_init | |
142 | * create TX/RX descriptor fifo for host-NIC communication. | |
143 | * 1K extra space is allocated at the end of the fifo to simplify | |
144 | * processing of descriptors that wraps around fifo's end | |
145 | * @priv - NIC private structure | |
146 | * @f - fifo to initialize | |
147 | * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB | |
148 | * @reg_XXX - offsets of registers relative to base address | |
149 | * | |
150 | * Returns 0 on success, negative value on failure | |
151 | * | |
152 | */ | |
153 | static int | |
154 | bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type, | |
155 | u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR) | |
156 | { | |
157 | u16 memsz = FIFO_SIZE * (1 << fsz_type); | |
158 | ||
159 | memset(f, 0, sizeof(struct fifo)); | |
160 | /* pci_alloc_consistent gives us 4k-aligned memory */ | |
161 | f->va = pci_alloc_consistent(priv->pdev, | |
162 | memsz + FIFO_EXTRA_SPACE, &f->da); | |
163 | if (!f->va) { | |
164 | ERR("pci_alloc_consistent failed\n"); | |
165 | RET(-ENOMEM); | |
166 | } | |
167 | f->reg_CFG0 = reg_CFG0; | |
168 | f->reg_CFG1 = reg_CFG1; | |
169 | f->reg_RPTR = reg_RPTR; | |
170 | f->reg_WPTR = reg_WPTR; | |
171 | f->rptr = 0; | |
172 | f->wptr = 0; | |
173 | f->memsz = memsz; | |
174 | f->size_mask = memsz - 1; | |
175 | WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); | |
176 | WRITE_REG(priv, reg_CFG1, H32_64(f->da)); | |
177 | ||
178 | RET(0); | |
179 | } | |
180 | ||
181 | /* bdx_fifo_free - free all resources used by fifo | |
182 | * @priv - NIC private structure | |
183 | * @f - fifo to release | |
184 | */ | |
185 | static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f) | |
186 | { | |
187 | ENTER; | |
188 | if (f->va) { | |
189 | pci_free_consistent(priv->pdev, | |
190 | f->memsz + FIFO_EXTRA_SPACE, f->va, f->da); | |
191 | f->va = NULL; | |
192 | } | |
193 | RET(); | |
194 | } | |
195 | ||
196 | /* | |
197 | * bdx_link_changed - notifies OS about hw link state. | |
198 | * @bdx_priv - hw adapter structure | |
199 | */ | |
200 | static void bdx_link_changed(struct bdx_priv *priv) | |
201 | { | |
202 | u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; | |
203 | ||
204 | if (!link) { | |
205 | if (netif_carrier_ok(priv->ndev)) { | |
206 | netif_stop_queue(priv->ndev); | |
207 | netif_carrier_off(priv->ndev); | |
208 | ERR("%s: Link Down\n", priv->ndev->name); | |
209 | } | |
210 | } else { | |
211 | if (!netif_carrier_ok(priv->ndev)) { | |
212 | netif_wake_queue(priv->ndev); | |
213 | netif_carrier_on(priv->ndev); | |
214 | ERR("%s: Link Up\n", priv->ndev->name); | |
215 | } | |
216 | } | |
217 | } | |
218 | ||
219 | static void bdx_isr_extra(struct bdx_priv *priv, u32 isr) | |
220 | { | |
221 | if (isr & IR_RX_FREE_0) { | |
222 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
223 | DBG("RX_FREE_0\n"); | |
224 | } | |
225 | ||
226 | if (isr & IR_LNKCHG0) | |
227 | bdx_link_changed(priv); | |
228 | ||
229 | if (isr & IR_PCIE_LINK) | |
230 | ERR("%s: PCI-E Link Fault\n", priv->ndev->name); | |
231 | ||
232 | if (isr & IR_PCIE_TOUT) | |
233 | ERR("%s: PCI-E Time Out\n", priv->ndev->name); | |
234 | ||
235 | } | |
236 | ||
237 | /* bdx_isr - Interrupt Service Routine for Bordeaux NIC | |
238 | * @irq - interrupt number | |
239 | * @ndev - network device | |
240 | * @regs - CPU registers | |
241 | * | |
242 | * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise | |
243 | * | |
244 | * It reads ISR register to know interrupt reasons, and proceed them one by one. | |
245 | * Reasons of interest are: | |
246 | * RX_DESC - new packet has arrived and RXD fifo holds its descriptor | |
247 | * RX_FREE - number of free Rx buffers in RXF fifo gets low | |
248 | * TX_FREE - packet was transmited and RXF fifo holds its descriptor | |
249 | */ | |
250 | ||
251 | static irqreturn_t bdx_isr_napi(int irq, void *dev) | |
252 | { | |
253 | struct net_device *ndev = dev; | |
254 | struct bdx_priv *priv = ndev->priv; | |
255 | u32 isr; | |
256 | ||
257 | ENTER; | |
258 | isr = (READ_REG(priv, regISR) & IR_RUN); | |
259 | if (unlikely(!isr)) { | |
260 | bdx_enable_interrupts(priv); | |
261 | return IRQ_NONE; /* Not our interrupt */ | |
262 | } | |
263 | ||
264 | if (isr & IR_EXTRA) | |
265 | bdx_isr_extra(priv, isr); | |
266 | ||
267 | if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) { | |
268 | if (likely(netif_rx_schedule_prep(ndev, &priv->napi))) { | |
269 | __netif_rx_schedule(ndev, &priv->napi); | |
270 | RET(IRQ_HANDLED); | |
271 | } else { | |
272 | /* NOTE: we get here if intr has slipped into window | |
273 | * between these lines in bdx_poll: | |
274 | * bdx_enable_interrupts(priv); | |
275 | * return 0; | |
276 | * currently intrs are disabled (since we read ISR), | |
277 | * and we have failed to register next poll. | |
278 | * so we read the regs to trigger chip | |
279 | * and allow further interupts. */ | |
280 | READ_REG(priv, regTXF_WPTR_0); | |
281 | READ_REG(priv, regRXD_WPTR_0); | |
282 | } | |
283 | } | |
284 | ||
285 | bdx_enable_interrupts(priv); | |
286 | RET(IRQ_HANDLED); | |
287 | } | |
288 | ||
289 | static int bdx_poll(struct napi_struct *napi, int budget) | |
290 | { | |
291 | struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi); | |
292 | struct net_device *dev = priv->ndev; | |
293 | int work_done; | |
294 | ||
295 | ENTER; | |
296 | bdx_tx_cleanup(priv); | |
297 | work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget); | |
298 | if ((work_done < budget) || | |
299 | (priv->napi_stop++ >= 30)) { | |
300 | DBG("rx poll is done. backing to isr-driven\n"); | |
301 | ||
302 | /* from time to time we exit to let NAPI layer release | |
303 | * device lock and allow waiting tasks (eg rmmod) to advance) */ | |
304 | priv->napi_stop = 0; | |
305 | ||
306 | netif_rx_complete(dev, napi); | |
307 | bdx_enable_interrupts(priv); | |
308 | } | |
309 | return work_done; | |
310 | } | |
311 | ||
312 | /* bdx_fw_load - loads firmware to NIC | |
313 | * @priv - NIC private structure | |
314 | * Firmware is loaded via TXD fifo, so it must be initialized first. | |
315 | * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC | |
316 | * can have few of them). So all drivers use semaphore register to choose one | |
317 | * that will actually load FW to NIC. | |
318 | */ | |
319 | ||
320 | static int bdx_fw_load(struct bdx_priv *priv) | |
321 | { | |
322 | int master, i; | |
323 | ||
324 | ENTER; | |
325 | master = READ_REG(priv, regINIT_SEMAPHORE); | |
326 | if (!READ_REG(priv, regINIT_STATUS) && master) { | |
327 | bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad)); | |
328 | mdelay(100); | |
329 | } | |
330 | for (i = 0; i < 200; i++) { | |
331 | if (READ_REG(priv, regINIT_STATUS)) | |
332 | break; | |
333 | mdelay(2); | |
334 | } | |
335 | if (master) | |
336 | WRITE_REG(priv, regINIT_SEMAPHORE, 1); | |
337 | ||
338 | if (i == 200) { | |
339 | ERR("%s: firmware loading failed\n", priv->ndev->name); | |
340 | DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n", | |
341 | READ_REG(priv, regVPC), | |
342 | READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i); | |
343 | RET(-EIO); | |
344 | } else { | |
345 | DBG("%s: firmware loading success\n", priv->ndev->name); | |
346 | RET(0); | |
347 | } | |
348 | } | |
349 | ||
350 | static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv) | |
351 | { | |
352 | u32 val; | |
353 | ||
354 | ENTER; | |
355 | DBG("mac0=%x mac1=%x mac2=%x\n", | |
356 | READ_REG(priv, regUNC_MAC0_A), | |
357 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); | |
358 | ||
359 | val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); | |
360 | WRITE_REG(priv, regUNC_MAC2_A, val); | |
361 | val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); | |
362 | WRITE_REG(priv, regUNC_MAC1_A, val); | |
363 | val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); | |
364 | WRITE_REG(priv, regUNC_MAC0_A, val); | |
365 | ||
366 | DBG("mac0=%x mac1=%x mac2=%x\n", | |
367 | READ_REG(priv, regUNC_MAC0_A), | |
368 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); | |
369 | RET(); | |
370 | } | |
371 | ||
372 | /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines | |
373 | * @priv - NIC private structure | |
374 | */ | |
375 | static int bdx_hw_start(struct bdx_priv *priv) | |
376 | { | |
377 | int rc = -EIO; | |
378 | struct net_device *ndev = priv->ndev; | |
379 | ||
380 | ENTER; | |
381 | bdx_link_changed(priv); | |
382 | ||
383 | /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */ | |
384 | WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); | |
385 | WRITE_REG(priv, regPAUSE_QUANT, 0x96); | |
386 | WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010); | |
387 | WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010); | |
388 | WRITE_REG(priv, regRX_FULLNESS, 0); | |
389 | WRITE_REG(priv, regTX_FULLNESS, 0); | |
390 | WRITE_REG(priv, regCTRLST, | |
391 | regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA); | |
392 | ||
393 | WRITE_REG(priv, regVGLB, 0); | |
394 | WRITE_REG(priv, regMAX_FRAME_A, | |
395 | priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL); | |
396 | ||
397 | DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */ | |
398 | WRITE_REG(priv, regRDINTCM0, priv->rdintcm); | |
399 | WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */ | |
400 | ||
401 | DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */ | |
402 | WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */ | |
403 | ||
404 | /* Enable timer interrupt once in 2 secs. */ | |
405 | /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */ | |
406 | bdx_restore_mac(priv->ndev, priv); | |
407 | ||
408 | WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN | | |
409 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB); | |
410 | ||
411 | #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED) | |
412 | if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE, | |
413 | ndev->name, ndev))) | |
414 | goto err_irq; | |
415 | bdx_enable_interrupts(priv); | |
416 | ||
417 | RET(0); | |
418 | ||
419 | err_irq: | |
420 | RET(rc); | |
421 | } | |
422 | ||
423 | static void bdx_hw_stop(struct bdx_priv *priv) | |
424 | { | |
425 | ENTER; | |
426 | bdx_disable_interrupts(priv); | |
427 | free_irq(priv->pdev->irq, priv->ndev); | |
428 | ||
429 | netif_carrier_off(priv->ndev); | |
430 | netif_stop_queue(priv->ndev); | |
431 | ||
432 | RET(); | |
433 | } | |
434 | ||
435 | static int bdx_hw_reset_direct(void __iomem *regs) | |
436 | { | |
437 | u32 val, i; | |
438 | ENTER; | |
439 | ||
440 | /* reset sequences: read, write 1, read, write 0 */ | |
441 | val = readl(regs + regCLKPLL); | |
442 | writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL); | |
443 | udelay(50); | |
444 | val = readl(regs + regCLKPLL); | |
445 | writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL); | |
446 | ||
447 | /* check that the PLLs are locked and reset ended */ | |
448 | for (i = 0; i < 70; i++, mdelay(10)) | |
449 | if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { | |
450 | /* do any PCI-E read transaction */ | |
451 | readl(regs + regRXD_CFG0_0); | |
452 | return 0; | |
453 | } | |
454 | ERR("tehuti: HW reset failed\n"); | |
455 | return 1; /* failure */ | |
456 | } | |
457 | ||
458 | static int bdx_hw_reset(struct bdx_priv *priv) | |
459 | { | |
460 | u32 val, i; | |
461 | ENTER; | |
462 | ||
463 | if (priv->port == 0) { | |
464 | /* reset sequences: read, write 1, read, write 0 */ | |
465 | val = READ_REG(priv, regCLKPLL); | |
466 | WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); | |
467 | udelay(50); | |
468 | val = READ_REG(priv, regCLKPLL); | |
469 | WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); | |
470 | } | |
471 | /* check that the PLLs are locked and reset ended */ | |
472 | for (i = 0; i < 70; i++, mdelay(10)) | |
473 | if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { | |
474 | /* do any PCI-E read transaction */ | |
475 | READ_REG(priv, regRXD_CFG0_0); | |
476 | return 0; | |
477 | } | |
478 | ERR("tehuti: HW reset failed\n"); | |
479 | return 1; /* failure */ | |
480 | } | |
481 | ||
482 | static int bdx_sw_reset(struct bdx_priv *priv) | |
483 | { | |
484 | int i; | |
485 | ||
486 | ENTER; | |
487 | /* 1. load MAC (obsolete) */ | |
488 | /* 2. disable Rx (and Tx) */ | |
489 | WRITE_REG(priv, regGMAC_RXF_A, 0); | |
490 | mdelay(100); | |
491 | /* 3. disable port */ | |
492 | WRITE_REG(priv, regDIS_PORT, 1); | |
493 | /* 4. disable queue */ | |
494 | WRITE_REG(priv, regDIS_QU, 1); | |
495 | /* 5. wait until hw is disabled */ | |
496 | for (i = 0; i < 50; i++) { | |
497 | if (READ_REG(priv, regRST_PORT) & 1) | |
498 | break; | |
499 | mdelay(10); | |
500 | } | |
501 | if (i == 50) | |
502 | ERR("%s: SW reset timeout. continuing anyway\n", | |
503 | priv->ndev->name); | |
504 | ||
505 | /* 6. disable intrs */ | |
506 | WRITE_REG(priv, regRDINTCM0, 0); | |
507 | WRITE_REG(priv, regTDINTCM0, 0); | |
508 | WRITE_REG(priv, regIMR, 0); | |
509 | READ_REG(priv, regISR); | |
510 | ||
511 | /* 7. reset queue */ | |
512 | WRITE_REG(priv, regRST_QU, 1); | |
513 | /* 8. reset port */ | |
514 | WRITE_REG(priv, regRST_PORT, 1); | |
515 | /* 9. zero all read and write pointers */ | |
516 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
517 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); | |
518 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
519 | WRITE_REG(priv, i, 0); | |
520 | /* 10. unseet port disable */ | |
521 | WRITE_REG(priv, regDIS_PORT, 0); | |
522 | /* 11. unset queue disable */ | |
523 | WRITE_REG(priv, regDIS_QU, 0); | |
524 | /* 12. unset queue reset */ | |
525 | WRITE_REG(priv, regRST_QU, 0); | |
526 | /* 13. unset port reset */ | |
527 | WRITE_REG(priv, regRST_PORT, 0); | |
528 | /* 14. enable Rx */ | |
529 | /* skiped. will be done later */ | |
530 | /* 15. save MAC (obsolete) */ | |
531 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
532 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); | |
533 | ||
534 | RET(0); | |
535 | } | |
536 | ||
537 | /* bdx_reset - performs right type of reset depending on hw type */ | |
538 | static int bdx_reset(struct bdx_priv *priv) | |
539 | { | |
540 | ENTER; | |
541 | RET((priv->pdev->device == 0x3009) | |
542 | ? bdx_hw_reset(priv) | |
543 | : bdx_sw_reset(priv)); | |
544 | } | |
545 | ||
546 | /** | |
547 | * bdx_close - Disables a network interface | |
548 | * @netdev: network interface device structure | |
549 | * | |
550 | * Returns 0, this is not allowed to fail | |
551 | * | |
552 | * The close entry point is called when an interface is de-activated | |
553 | * by the OS. The hardware is still under the drivers control, but | |
554 | * needs to be disabled. A global MAC reset is issued to stop the | |
555 | * hardware, and all transmit and receive resources are freed. | |
556 | **/ | |
557 | static int bdx_close(struct net_device *ndev) | |
558 | { | |
559 | struct bdx_priv *priv = NULL; | |
560 | ||
561 | ENTER; | |
562 | priv = ndev->priv; | |
563 | ||
564 | napi_disable(&priv->napi); | |
565 | ||
566 | bdx_reset(priv); | |
567 | bdx_hw_stop(priv); | |
568 | bdx_rx_free(priv); | |
569 | bdx_tx_free(priv); | |
570 | RET(0); | |
571 | } | |
572 | ||
573 | /** | |
574 | * bdx_open - Called when a network interface is made active | |
575 | * @netdev: network interface device structure | |
576 | * | |
577 | * Returns 0 on success, negative value on failure | |
578 | * | |
579 | * The open entry point is called when a network interface is made | |
580 | * active by the system (IFF_UP). At this point all resources needed | |
581 | * for transmit and receive operations are allocated, the interrupt | |
582 | * handler is registered with the OS, the watchdog timer is started, | |
583 | * and the stack is notified that the interface is ready. | |
584 | **/ | |
585 | static int bdx_open(struct net_device *ndev) | |
586 | { | |
587 | struct bdx_priv *priv; | |
588 | int rc; | |
589 | ||
590 | ENTER; | |
591 | priv = ndev->priv; | |
592 | bdx_reset(priv); | |
593 | if (netif_running(ndev)) | |
594 | netif_stop_queue(priv->ndev); | |
595 | ||
596 | if ((rc = bdx_tx_init(priv))) | |
597 | goto err; | |
598 | ||
599 | if ((rc = bdx_rx_init(priv))) | |
600 | goto err; | |
601 | ||
602 | if ((rc = bdx_fw_load(priv))) | |
603 | goto err; | |
604 | ||
605 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
606 | ||
607 | if ((rc = bdx_hw_start(priv))) | |
608 | goto err; | |
609 | ||
610 | napi_enable(&priv->napi); | |
611 | ||
612 | print_fw_id(priv->nic); | |
613 | ||
614 | RET(0); | |
615 | ||
616 | err: | |
617 | bdx_close(ndev); | |
618 | RET(rc); | |
619 | } | |
620 | ||
621 | static void __init bdx_firmware_endianess(void) | |
622 | { | |
623 | int i; | |
c00acf46 | 624 | for (i = 0; i < ARRAY_SIZE(s_firmLoad); i++) |
1a348ccc AG |
625 | s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]); |
626 | } | |
627 | ||
6131a260 FR |
628 | static int bdx_range_check(struct bdx_priv *priv, u32 offset) |
629 | { | |
630 | return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ? | |
631 | -EINVAL : 0; | |
632 | } | |
633 | ||
1a348ccc AG |
634 | static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd) |
635 | { | |
636 | struct bdx_priv *priv = ndev->priv; | |
637 | u32 data[3]; | |
638 | int error; | |
639 | ||
640 | ENTER; | |
641 | ||
642 | DBG("jiffies=%ld cmd=%d\n", jiffies, cmd); | |
643 | if (cmd != SIOCDEVPRIVATE) { | |
644 | error = copy_from_user(data, ifr->ifr_data, sizeof(data)); | |
645 | if (error) { | |
646 | ERR("cant copy from user\n"); | |
647 | RET(error); | |
648 | } | |
649 | DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]); | |
650 | } | |
651 | ||
62035542 | 652 | if (!capable(CAP_SYS_RAWIO)) |
f946dffe JG |
653 | return -EPERM; |
654 | ||
1a348ccc AG |
655 | switch (data[0]) { |
656 | ||
657 | case BDX_OP_READ: | |
6131a260 FR |
658 | error = bdx_range_check(priv, data[1]); |
659 | if (error < 0) | |
660 | return error; | |
1a348ccc AG |
661 | data[2] = READ_REG(priv, data[1]); |
662 | DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2], | |
663 | data[2]); | |
664 | error = copy_to_user(ifr->ifr_data, data, sizeof(data)); | |
665 | if (error) | |
666 | RET(error); | |
667 | break; | |
668 | ||
669 | case BDX_OP_WRITE: | |
6131a260 FR |
670 | error = bdx_range_check(priv, data[1]); |
671 | if (error < 0) | |
672 | return error; | |
1a348ccc AG |
673 | WRITE_REG(priv, data[1], data[2]); |
674 | DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]); | |
675 | break; | |
676 | ||
677 | default: | |
678 | RET(-EOPNOTSUPP); | |
679 | } | |
680 | return 0; | |
681 | } | |
682 | ||
683 | static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) | |
684 | { | |
685 | ENTER; | |
686 | if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15)) | |
687 | RET(bdx_ioctl_priv(ndev, ifr, cmd)); | |
688 | else | |
689 | RET(-EOPNOTSUPP); | |
690 | } | |
691 | ||
692 | /* | |
693 | * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid | |
694 | * by passing VLAN filter table to hardware | |
695 | * @ndev network device | |
696 | * @vid VLAN vid | |
697 | * @op add or kill operation | |
698 | */ | |
699 | static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable) | |
700 | { | |
701 | struct bdx_priv *priv = ndev->priv; | |
702 | u32 reg, bit, val; | |
703 | ||
704 | ENTER; | |
705 | DBG2("vid=%d value=%d\n", (int)vid, enable); | |
706 | if (unlikely(vid >= 4096)) { | |
707 | ERR("tehuti: invalid VID: %u (> 4096)\n", vid); | |
708 | RET(); | |
709 | } | |
710 | reg = regVLAN_0 + (vid / 32) * 4; | |
711 | bit = 1 << vid % 32; | |
712 | val = READ_REG(priv, reg); | |
713 | DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); | |
714 | if (enable) | |
715 | val |= bit; | |
716 | else | |
717 | val &= ~bit; | |
718 | DBG2("new val %x\n", val); | |
719 | WRITE_REG(priv, reg, val); | |
720 | RET(); | |
721 | } | |
722 | ||
723 | /* | |
724 | * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table | |
725 | * @ndev network device | |
726 | * @vid VLAN vid to add | |
727 | */ | |
728 | static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid) | |
729 | { | |
730 | __bdx_vlan_rx_vid(ndev, vid, 1); | |
731 | } | |
732 | ||
733 | /* | |
734 | * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table | |
735 | * @ndev network device | |
736 | * @vid VLAN vid to kill | |
737 | */ | |
738 | static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid) | |
739 | { | |
740 | __bdx_vlan_rx_vid(ndev, vid, 0); | |
741 | } | |
742 | ||
743 | /* | |
744 | * bdx_vlan_rx_register - kernel hook for adding VLAN group | |
745 | * @ndev network device | |
746 | * @grp VLAN group | |
747 | */ | |
748 | static void | |
749 | bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp) | |
750 | { | |
751 | struct bdx_priv *priv = ndev->priv; | |
752 | ||
753 | ENTER; | |
754 | DBG("device='%s', group='%p'\n", ndev->name, grp); | |
755 | priv->vlgrp = grp; | |
756 | RET(); | |
757 | } | |
758 | ||
759 | /** | |
760 | * bdx_change_mtu - Change the Maximum Transfer Unit | |
761 | * @netdev: network interface device structure | |
762 | * @new_mtu: new value for maximum frame size | |
763 | * | |
764 | * Returns 0 on success, negative on failure | |
765 | */ | |
766 | static int bdx_change_mtu(struct net_device *ndev, int new_mtu) | |
767 | { | |
1a348ccc AG |
768 | ENTER; |
769 | ||
770 | if (new_mtu == ndev->mtu) | |
771 | RET(0); | |
772 | ||
773 | /* enforce minimum frame size */ | |
774 | if (new_mtu < ETH_ZLEN) { | |
775 | ERR("%s: %s mtu %d is less then minimal %d\n", | |
776 | BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN); | |
777 | RET(-EINVAL); | |
778 | } | |
779 | ||
780 | ndev->mtu = new_mtu; | |
781 | if (netif_running(ndev)) { | |
782 | bdx_close(ndev); | |
783 | bdx_open(ndev); | |
784 | } | |
785 | RET(0); | |
786 | } | |
787 | ||
788 | static void bdx_setmulti(struct net_device *ndev) | |
789 | { | |
790 | struct bdx_priv *priv = ndev->priv; | |
791 | ||
792 | u32 rxf_val = | |
793 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN; | |
794 | int i; | |
795 | ||
796 | ENTER; | |
797 | /* IMF - imperfect (hash) rx multicat filter */ | |
798 | /* PMF - perfect rx multicat filter */ | |
799 | ||
800 | /* FIXME: RXE(OFF) */ | |
801 | if (ndev->flags & IFF_PROMISC) { | |
802 | rxf_val |= GMAC_RX_FILTER_PRM; | |
803 | } else if (ndev->flags & IFF_ALLMULTI) { | |
804 | /* set IMF to accept all multicast frmaes */ | |
805 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) | |
806 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0); | |
807 | } else if (ndev->mc_count) { | |
808 | u8 hash; | |
809 | struct dev_mc_list *mclist; | |
810 | u32 reg, val; | |
811 | ||
812 | /* set IMF to deny all multicast frames */ | |
813 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) | |
814 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0); | |
815 | /* set PMF to deny all multicast frames */ | |
816 | for (i = 0; i < MAC_MCST_NUM; i++) { | |
817 | WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0); | |
818 | WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0); | |
819 | } | |
820 | ||
821 | /* use PMF to accept first MAC_MCST_NUM (15) addresses */ | |
822 | /* TBD: sort addreses and write them in ascending order | |
823 | * into RX_MAC_MCST regs. we skip this phase now and accept ALL | |
824 | * multicast frames throu IMF */ | |
825 | mclist = ndev->mc_list; | |
826 | ||
827 | /* accept the rest of addresses throu IMF */ | |
828 | for (; mclist; mclist = mclist->next) { | |
829 | hash = 0; | |
830 | for (i = 0; i < ETH_ALEN; i++) | |
831 | hash ^= mclist->dmi_addr[i]; | |
832 | reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); | |
833 | val = READ_REG(priv, reg); | |
834 | val |= (1 << (hash % 32)); | |
835 | WRITE_REG(priv, reg, val); | |
836 | } | |
837 | ||
838 | } else { | |
839 | DBG("only own mac %d\n", ndev->mc_count); | |
840 | rxf_val |= GMAC_RX_FILTER_AB; | |
841 | } | |
842 | WRITE_REG(priv, regGMAC_RXF_A, rxf_val); | |
843 | /* enable RX */ | |
844 | /* FIXME: RXE(ON) */ | |
845 | RET(); | |
846 | } | |
847 | ||
848 | static int bdx_set_mac(struct net_device *ndev, void *p) | |
849 | { | |
850 | struct bdx_priv *priv = ndev->priv; | |
851 | struct sockaddr *addr = p; | |
852 | ||
853 | ENTER; | |
854 | /* | |
855 | if (netif_running(dev)) | |
856 | return -EBUSY | |
857 | */ | |
858 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
859 | bdx_restore_mac(ndev, priv); | |
860 | RET(0); | |
861 | } | |
862 | ||
863 | static int bdx_read_mac(struct bdx_priv *priv) | |
864 | { | |
865 | u16 macAddress[3], i; | |
866 | ENTER; | |
867 | ||
868 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); | |
869 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); | |
870 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); | |
871 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); | |
872 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); | |
873 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); | |
874 | for (i = 0; i < 3; i++) { | |
875 | priv->ndev->dev_addr[i * 2 + 1] = macAddress[i]; | |
876 | priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8; | |
877 | } | |
878 | RET(0); | |
879 | } | |
880 | ||
881 | static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) | |
882 | { | |
883 | u64 val; | |
884 | ||
885 | val = READ_REG(priv, reg); | |
886 | val |= ((u64) READ_REG(priv, reg + 8)) << 32; | |
887 | return val; | |
888 | } | |
889 | ||
890 | /*Do the statistics-update work*/ | |
891 | static void bdx_update_stats(struct bdx_priv *priv) | |
892 | { | |
893 | struct bdx_stats *stats = &priv->hw_stats; | |
894 | u64 *stats_vector = (u64 *) stats; | |
895 | int i; | |
896 | int addr; | |
897 | ||
898 | /*Fill HW structure */ | |
899 | addr = 0x7200; | |
900 | /*First 12 statistics - 0x7200 - 0x72B0 */ | |
901 | for (i = 0; i < 12; i++) { | |
902 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
903 | addr += 0x10; | |
904 | } | |
905 | BDX_ASSERT(addr != 0x72C0); | |
906 | /* 0x72C0-0x72E0 RSRV */ | |
907 | addr = 0x72F0; | |
908 | for (; i < 16; i++) { | |
909 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
910 | addr += 0x10; | |
911 | } | |
912 | BDX_ASSERT(addr != 0x7330); | |
913 | /* 0x7330-0x7360 RSRV */ | |
914 | addr = 0x7370; | |
915 | for (; i < 19; i++) { | |
916 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
917 | addr += 0x10; | |
918 | } | |
919 | BDX_ASSERT(addr != 0x73A0); | |
920 | /* 0x73A0-0x73B0 RSRV */ | |
921 | addr = 0x73C0; | |
922 | for (; i < 23; i++) { | |
923 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
924 | addr += 0x10; | |
925 | } | |
926 | BDX_ASSERT(addr != 0x7400); | |
927 | BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i); | |
928 | } | |
929 | ||
930 | static struct net_device_stats *bdx_get_stats(struct net_device *ndev) | |
931 | { | |
932 | struct bdx_priv *priv = ndev->priv; | |
933 | struct net_device_stats *net_stat = &priv->net_stats; | |
934 | return net_stat; | |
935 | } | |
936 | ||
937 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, | |
938 | u16 rxd_vlan); | |
939 | static void print_rxfd(struct rxf_desc *rxfd); | |
940 | ||
941 | /************************************************************************* | |
942 | * Rx DB * | |
943 | *************************************************************************/ | |
944 | ||
945 | static void bdx_rxdb_destroy(struct rxdb *db) | |
946 | { | |
947 | if (db) | |
948 | vfree(db); | |
949 | } | |
950 | ||
951 | static struct rxdb *bdx_rxdb_create(int nelem) | |
952 | { | |
953 | struct rxdb *db; | |
954 | int i; | |
955 | ||
956 | db = vmalloc(sizeof(struct rxdb) | |
957 | + (nelem * sizeof(int)) | |
958 | + (nelem * sizeof(struct rx_map))); | |
959 | if (likely(db != NULL)) { | |
960 | db->stack = (int *)(db + 1); | |
961 | db->elems = (void *)(db->stack + nelem); | |
962 | db->nelem = nelem; | |
963 | db->top = nelem; | |
964 | for (i = 0; i < nelem; i++) | |
965 | db->stack[i] = nelem - i - 1; /* to make first allocs | |
966 | close to db struct*/ | |
967 | } | |
968 | ||
969 | return db; | |
970 | } | |
971 | ||
972 | static inline int bdx_rxdb_alloc_elem(struct rxdb *db) | |
973 | { | |
974 | BDX_ASSERT(db->top <= 0); | |
975 | return db->stack[--(db->top)]; | |
976 | } | |
977 | ||
978 | static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n) | |
979 | { | |
980 | BDX_ASSERT((n < 0) || (n >= db->nelem)); | |
981 | return db->elems + n; | |
982 | } | |
983 | ||
984 | static inline int bdx_rxdb_available(struct rxdb *db) | |
985 | { | |
986 | return db->top; | |
987 | } | |
988 | ||
989 | static inline void bdx_rxdb_free_elem(struct rxdb *db, int n) | |
990 | { | |
991 | BDX_ASSERT((n >= db->nelem) || (n < 0)); | |
992 | db->stack[(db->top)++] = n; | |
993 | } | |
994 | ||
995 | /************************************************************************* | |
996 | * Rx Init * | |
997 | *************************************************************************/ | |
998 | ||
999 | /* bdx_rx_init - initialize RX all related HW and SW resources | |
1000 | * @priv - NIC private structure | |
1001 | * | |
1002 | * Returns 0 on success, negative value on failure | |
1003 | * | |
1004 | * It creates rxf and rxd fifos, update relevant HW registers, preallocate | |
1005 | * skb for rx. It assumes that Rx is desabled in HW | |
1006 | * funcs are grouped for better cache usage | |
1007 | * | |
1008 | * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be | |
1009 | * filled and packets will be dropped by nic without getting into host or | |
1010 | * cousing interrupt. Anyway, in that condition, host has no chance to proccess | |
1011 | * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles | |
1012 | */ | |
1013 | ||
1014 | /* TBD: ensure proper packet size */ | |
1015 | ||
1016 | static int bdx_rx_init(struct bdx_priv *priv) | |
1017 | { | |
1018 | ENTER; | |
ddfce6bb | 1019 | |
1a348ccc AG |
1020 | if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size, |
1021 | regRXD_CFG0_0, regRXD_CFG1_0, | |
1022 | regRXD_RPTR_0, regRXD_WPTR_0)) | |
1023 | goto err_mem; | |
1024 | if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size, | |
1025 | regRXF_CFG0_0, regRXF_CFG1_0, | |
1026 | regRXF_RPTR_0, regRXF_WPTR_0)) | |
1027 | goto err_mem; | |
1028 | if (! | |
1029 | (priv->rxdb = | |
1030 | bdx_rxdb_create(priv->rxf_fifo0.m.memsz / | |
1031 | sizeof(struct rxf_desc)))) | |
1032 | goto err_mem; | |
1033 | ||
1034 | priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN; | |
1035 | return 0; | |
1036 | ||
1037 | err_mem: | |
1038 | ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name); | |
1039 | return -ENOMEM; | |
1040 | } | |
1041 | ||
1042 | /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo | |
1043 | * @priv - NIC private structure | |
1044 | * @f - RXF fifo | |
1045 | */ | |
1046 | static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f) | |
1047 | { | |
1048 | struct rx_map *dm; | |
1049 | struct rxdb *db = priv->rxdb; | |
1050 | u16 i; | |
1051 | ||
1052 | ENTER; | |
1053 | DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db), | |
1054 | db->nelem - bdx_rxdb_available(db)); | |
1055 | while (bdx_rxdb_available(db) > 0) { | |
1056 | i = bdx_rxdb_alloc_elem(db); | |
1057 | dm = bdx_rxdb_addr_elem(db, i); | |
1058 | dm->dma = 0; | |
1059 | } | |
1060 | for (i = 0; i < db->nelem; i++) { | |
1061 | dm = bdx_rxdb_addr_elem(db, i); | |
1062 | if (dm->dma) { | |
1063 | pci_unmap_single(priv->pdev, | |
1064 | dm->dma, f->m.pktsz, | |
1065 | PCI_DMA_FROMDEVICE); | |
1066 | dev_kfree_skb(dm->skb); | |
1067 | } | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | /* bdx_rx_free - release all Rx resources | |
1072 | * @priv - NIC private structure | |
1073 | * It assumes that Rx is desabled in HW | |
1074 | */ | |
1075 | static void bdx_rx_free(struct bdx_priv *priv) | |
1076 | { | |
1077 | ENTER; | |
1078 | if (priv->rxdb) { | |
1079 | bdx_rx_free_skbs(priv, &priv->rxf_fifo0); | |
1080 | bdx_rxdb_destroy(priv->rxdb); | |
1081 | priv->rxdb = NULL; | |
1082 | } | |
1083 | bdx_fifo_free(priv, &priv->rxf_fifo0.m); | |
1084 | bdx_fifo_free(priv, &priv->rxd_fifo0.m); | |
1085 | ||
1086 | RET(); | |
1087 | } | |
1088 | ||
1089 | /************************************************************************* | |
1090 | * Rx Engine * | |
1091 | *************************************************************************/ | |
1092 | ||
1093 | /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs | |
1094 | * @priv - nic's private structure | |
1095 | * @f - RXF fifo that needs skbs | |
1096 | * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo. | |
1097 | * skb's virtual and physical addresses are stored in skb db. | |
1098 | * To calculate free space, func uses cached values of RPTR and WPTR | |
1099 | * When needed, it also updates RPTR and WPTR. | |
1100 | */ | |
1101 | ||
1102 | /* TBD: do not update WPTR if no desc were written */ | |
1103 | ||
1104 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f) | |
1105 | { | |
1106 | struct sk_buff *skb; | |
1107 | struct rxf_desc *rxfd; | |
1108 | struct rx_map *dm; | |
1109 | int dno, delta, idx; | |
1110 | struct rxdb *db = priv->rxdb; | |
1111 | ||
1112 | ENTER; | |
1113 | dno = bdx_rxdb_available(db) - 1; | |
1114 | while (dno > 0) { | |
1115 | if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) { | |
1116 | ERR("NO MEM: dev_alloc_skb failed\n"); | |
1117 | break; | |
1118 | } | |
1119 | skb->dev = priv->ndev; | |
1120 | skb_reserve(skb, NET_IP_ALIGN); | |
1121 | ||
1122 | idx = bdx_rxdb_alloc_elem(db); | |
1123 | dm = bdx_rxdb_addr_elem(db, idx); | |
1124 | dm->dma = pci_map_single(priv->pdev, | |
1125 | skb->data, f->m.pktsz, | |
1126 | PCI_DMA_FROMDEVICE); | |
1127 | dm->skb = skb; | |
1128 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); | |
1129 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ | |
1130 | rxfd->va_lo = idx; | |
1131 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); | |
1132 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); | |
1133 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); | |
1134 | print_rxfd(rxfd); | |
1135 | ||
1136 | f->m.wptr += sizeof(struct rxf_desc); | |
1137 | delta = f->m.wptr - f->m.memsz; | |
1138 | if (unlikely(delta >= 0)) { | |
1139 | f->m.wptr = delta; | |
1140 | if (delta > 0) { | |
1141 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); | |
1142 | DBG("wrapped descriptor\n"); | |
1143 | } | |
1144 | } | |
1145 | dno--; | |
1146 | } | |
1147 | /*TBD: to do - delayed rxf wptr like in txd */ | |
1148 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1149 | RET(); | |
1150 | } | |
1151 | ||
1152 | static inline void | |
1153 | NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan, | |
1154 | struct sk_buff *skb) | |
1155 | { | |
1156 | ENTER; | |
1157 | DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1), | |
1158 | priv->vlgrp); | |
1159 | if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) { | |
1160 | DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n", | |
1161 | priv->ndev->name, | |
1162 | GET_RXD_VLAN_ID(rxd_vlan), | |
1163 | GET_RXD_VTAG(rxd_val1), | |
1164 | vlan_group_get_device(priv->vlgrp, | |
1165 | GET_RXD_VLAN_ID(rxd_vlan))->name); | |
1166 | /* NAPI variant of receive functions */ | |
1167 | vlan_hwaccel_receive_skb(skb, priv->vlgrp, | |
38b22195 | 1168 | GET_RXD_VLAN_TCI(rxd_vlan)); |
1a348ccc AG |
1169 | } else { |
1170 | netif_receive_skb(skb); | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd) | |
1175 | { | |
1176 | struct rxf_desc *rxfd; | |
1177 | struct rx_map *dm; | |
1178 | struct rxf_fifo *f; | |
1179 | struct rxdb *db; | |
1180 | struct sk_buff *skb; | |
1181 | int delta; | |
1182 | ||
1183 | ENTER; | |
1184 | DBG("priv=%p rxdd=%p\n", priv, rxdd); | |
1185 | f = &priv->rxf_fifo0; | |
1186 | db = priv->rxdb; | |
1187 | DBG("db=%p f=%p\n", db, f); | |
1188 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); | |
1189 | DBG("dm=%p\n", dm); | |
1190 | skb = dm->skb; | |
1191 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); | |
1192 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ | |
1193 | rxfd->va_lo = rxdd->va_lo; | |
1194 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); | |
1195 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); | |
1196 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); | |
1197 | print_rxfd(rxfd); | |
1198 | ||
1199 | f->m.wptr += sizeof(struct rxf_desc); | |
1200 | delta = f->m.wptr - f->m.memsz; | |
1201 | if (unlikely(delta >= 0)) { | |
1202 | f->m.wptr = delta; | |
1203 | if (delta > 0) { | |
1204 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); | |
1205 | DBG("wrapped descriptor\n"); | |
1206 | } | |
1207 | } | |
1208 | RET(); | |
1209 | } | |
1210 | ||
1211 | /* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS | |
1212 | * NOTE: a special treatment is given to non-continous descriptors | |
1213 | * that start near the end, wraps around and continue at the beginning. a second | |
1214 | * part is copied right after the first, and then descriptor is interpreted as | |
1215 | * normal. fifo has an extra space to allow such operations | |
1216 | * @priv - nic's private structure | |
1217 | * @f - RXF fifo that needs skbs | |
1218 | */ | |
1219 | ||
1220 | /* TBD: replace memcpy func call by explicite inline asm */ | |
1221 | ||
1222 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget) | |
1223 | { | |
1224 | struct sk_buff *skb, *skb2; | |
1225 | struct rxd_desc *rxdd; | |
1226 | struct rx_map *dm; | |
1227 | struct rxf_fifo *rxf_fifo; | |
1228 | int tmp_len, size; | |
1229 | int done = 0; | |
1230 | int max_done = BDX_MAX_RX_DONE; | |
1231 | struct rxdb *db = NULL; | |
1232 | /* Unmarshalled descriptor - copy of descriptor in host order */ | |
1233 | u32 rxd_val1; | |
1234 | u16 len; | |
1235 | u16 rxd_vlan; | |
1236 | ||
1237 | ENTER; | |
1238 | max_done = budget; | |
1239 | ||
1a348ccc AG |
1240 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; |
1241 | ||
1242 | size = f->m.wptr - f->m.rptr; | |
1243 | if (size < 0) | |
1244 | size = f->m.memsz + size; /* size is negative :-) */ | |
1245 | ||
1246 | while (size > 0) { | |
1247 | ||
1248 | rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); | |
1249 | rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1); | |
1250 | ||
1251 | len = CPU_CHIP_SWAP16(rxdd->len); | |
1252 | ||
1253 | rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan); | |
1254 | ||
1255 | print_rxdd(rxdd, rxd_val1, len, rxd_vlan); | |
1256 | ||
1257 | tmp_len = GET_RXD_BC(rxd_val1) << 3; | |
1258 | BDX_ASSERT(tmp_len <= 0); | |
1259 | size -= tmp_len; | |
1260 | if (size < 0) /* test for partially arrived descriptor */ | |
1261 | break; | |
1262 | ||
1263 | f->m.rptr += tmp_len; | |
1264 | ||
1265 | tmp_len = f->m.rptr - f->m.memsz; | |
1266 | if (unlikely(tmp_len >= 0)) { | |
1267 | f->m.rptr = tmp_len; | |
1268 | if (tmp_len > 0) { | |
1269 | DBG("wrapped desc rptr=%d tmp_len=%d\n", | |
1270 | f->m.rptr, tmp_len); | |
1271 | memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | if (unlikely(GET_RXD_ERR(rxd_val1))) { | |
1276 | DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1)); | |
1277 | priv->net_stats.rx_errors++; | |
1278 | bdx_recycle_skb(priv, rxdd); | |
1279 | continue; | |
1280 | } | |
1281 | ||
1282 | rxf_fifo = &priv->rxf_fifo0; | |
1283 | db = priv->rxdb; | |
1284 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); | |
1285 | skb = dm->skb; | |
1286 | ||
1287 | if (len < BDX_COPYBREAK && | |
1288 | (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) { | |
1289 | skb_reserve(skb2, NET_IP_ALIGN); | |
1290 | /*skb_put(skb2, len); */ | |
1291 | pci_dma_sync_single_for_cpu(priv->pdev, | |
1292 | dm->dma, rxf_fifo->m.pktsz, | |
1293 | PCI_DMA_FROMDEVICE); | |
1294 | memcpy(skb2->data, skb->data, len); | |
1295 | bdx_recycle_skb(priv, rxdd); | |
1296 | skb = skb2; | |
1297 | } else { | |
1298 | pci_unmap_single(priv->pdev, | |
1299 | dm->dma, rxf_fifo->m.pktsz, | |
1300 | PCI_DMA_FROMDEVICE); | |
1301 | bdx_rxdb_free_elem(db, rxdd->va_lo); | |
1302 | } | |
1303 | ||
1304 | priv->net_stats.rx_bytes += len; | |
1305 | ||
1306 | skb_put(skb, len); | |
1307 | skb->dev = priv->ndev; | |
1308 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1309 | skb->protocol = eth_type_trans(skb, priv->ndev); | |
1310 | ||
1311 | /* Non-IP packets aren't checksum-offloaded */ | |
1312 | if (GET_RXD_PKT_ID(rxd_val1) == 0) | |
1313 | skb->ip_summed = CHECKSUM_NONE; | |
1314 | ||
1315 | NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb); | |
1316 | ||
1317 | if (++done >= max_done) | |
1318 | break; | |
1319 | } | |
1320 | ||
1321 | priv->net_stats.rx_packets += done; | |
1322 | ||
1323 | /* FIXME: do smth to minimize pci accesses */ | |
1324 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); | |
1325 | ||
1326 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
1327 | ||
1328 | RET(done); | |
1329 | } | |
1330 | ||
1331 | /************************************************************************* | |
1332 | * Debug / Temprorary Code * | |
1333 | *************************************************************************/ | |
1334 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, | |
1335 | u16 rxd_vlan) | |
1336 | { | |
1337 | DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d " | |
1338 | "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d " | |
1339 | "va_lo %d va_hi %d\n", | |
1340 | GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1), | |
1341 | GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1), | |
1342 | GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1), | |
1343 | GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan), | |
1344 | GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo, | |
1345 | rxdd->va_hi); | |
1346 | } | |
1347 | ||
1348 | static void print_rxfd(struct rxf_desc *rxfd) | |
1349 | { | |
1350 | DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n" | |
1351 | "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n", | |
1352 | rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len); | |
1353 | } | |
1354 | ||
1355 | /* | |
1356 | * TX HW/SW interaction overview | |
1357 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
1358 | * There are 2 types of TX communication channels betwean driver and NIC. | |
1359 | * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets | |
1360 | * 2) TX Data Fifo - TXD - holds descriptors of full buffers. | |
1361 | * | |
1362 | * Currently NIC supports TSO, checksuming and gather DMA | |
1363 | * UFO and IP fragmentation is on the way | |
1364 | * | |
1365 | * RX SW Data Structures | |
1366 | * ~~~~~~~~~~~~~~~~~~~~~ | |
1367 | * txdb - used to keep track of all skbs owned by SW and their dma addresses. | |
1368 | * For TX case, ownership lasts from geting packet via hard_xmit and until HW | |
1369 | * acknowledges sent by TXF descriptors. | |
1370 | * Implemented as cyclic buffer. | |
1371 | * fifo - keeps info about fifo's size and location, relevant HW registers, | |
1372 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. | |
1373 | * Implemented as simple struct. | |
1374 | * | |
1375 | * TX SW Execution Flow | |
1376 | * ~~~~~~~~~~~~~~~~~~~~ | |
1377 | * OS calls driver's hard_xmit method with packet to sent. | |
1378 | * Driver creates DMA mappings, builds TXD descriptors and kicks HW | |
1379 | * by updating TXD WPTR. | |
1380 | * When packet is sent, HW write us TXF descriptor and SW frees original skb. | |
1381 | * To prevent TXD fifo overflow without reading HW registers every time, | |
1382 | * SW deploys "tx level" technique. | |
1383 | * Upon strart up, tx level is initialized to TXD fifo length. | |
1384 | * For every sent packet, SW gets its TXD descriptor sizei | |
1385 | * (from precalculated array) and substructs it from tx level. | |
1386 | * The size is also stored in txdb. When TXF ack arrives, SW fetch size of | |
1387 | * original TXD descriptor from txdb and adds it to tx level. | |
1388 | * When Tx level drops under some predefined treshhold, the driver | |
1389 | * stops the TX queue. When TX level rises above that level, | |
1390 | * the tx queue is enabled again. | |
1391 | * | |
1392 | * This technique avoids eccessive reading of RPTR and WPTR registers. | |
1393 | * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput. | |
1394 | */ | |
1395 | ||
1396 | /************************************************************************* | |
1397 | * Tx DB * | |
1398 | *************************************************************************/ | |
1399 | static inline int bdx_tx_db_size(struct txdb *db) | |
1400 | { | |
1401 | int taken = db->wptr - db->rptr; | |
1402 | if (taken < 0) | |
1403 | taken = db->size + 1 + taken; /* (size + 1) equals memsz */ | |
1404 | ||
1405 | return db->size - taken; | |
1406 | } | |
1407 | ||
1408 | /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap | |
1409 | * @d - tx data base | |
1410 | * @ptr - read or write pointer | |
1411 | */ | |
1412 | static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr) | |
1413 | { | |
1414 | BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */ | |
1415 | ||
1416 | BDX_ASSERT(*pptr != db->rptr && /* expect either read */ | |
1417 | *pptr != db->wptr); /* or write pointer */ | |
1418 | ||
1419 | BDX_ASSERT(*pptr < db->start || /* pointer has to be */ | |
1420 | *pptr >= db->end); /* in range */ | |
1421 | ||
1422 | ++*pptr; | |
1423 | if (unlikely(*pptr == db->end)) | |
1424 | *pptr = db->start; | |
1425 | } | |
1426 | ||
1427 | /* bdx_tx_db_inc_rptr - increment read pointer | |
1428 | * @d - tx data base | |
1429 | */ | |
1430 | static inline void bdx_tx_db_inc_rptr(struct txdb *db) | |
1431 | { | |
1432 | BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ | |
1433 | __bdx_tx_db_ptr_next(db, &db->rptr); | |
1434 | } | |
1435 | ||
1436 | /* bdx_tx_db_inc_rptr - increment write pointer | |
1437 | * @d - tx data base | |
1438 | */ | |
1439 | static inline void bdx_tx_db_inc_wptr(struct txdb *db) | |
1440 | { | |
1441 | __bdx_tx_db_ptr_next(db, &db->wptr); | |
1442 | BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as | |
1443 | a result of write */ | |
1444 | } | |
1445 | ||
1446 | /* bdx_tx_db_init - creates and initializes tx db | |
1447 | * @d - tx data base | |
1448 | * @sz_type - size of tx fifo | |
1449 | * Returns 0 on success, error code otherwise | |
1450 | */ | |
1451 | static int bdx_tx_db_init(struct txdb *d, int sz_type) | |
1452 | { | |
1453 | int memsz = FIFO_SIZE * (1 << (sz_type + 1)); | |
1454 | ||
1455 | d->start = vmalloc(memsz); | |
1456 | if (!d->start) | |
1457 | return -ENOMEM; | |
1458 | ||
1459 | /* | |
1460 | * In order to differentiate between db is empty and db is full | |
1461 | * states at least one element should always be empty in order to | |
1462 | * avoid rptr == wptr which means db is empty | |
1463 | */ | |
1464 | d->size = memsz / sizeof(struct tx_map) - 1; | |
1465 | d->end = d->start + d->size + 1; /* just after last element */ | |
1466 | ||
1467 | /* all dbs are created equally empty */ | |
1468 | d->rptr = d->start; | |
1469 | d->wptr = d->start; | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /* bdx_tx_db_close - closes tx db and frees all memory | |
1475 | * @d - tx data base | |
1476 | */ | |
1477 | static void bdx_tx_db_close(struct txdb *d) | |
1478 | { | |
1479 | BDX_ASSERT(d == NULL); | |
1480 | ||
1481 | if (d->start) { | |
1482 | vfree(d->start); | |
1483 | d->start = NULL; | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | /************************************************************************* | |
1488 | * Tx Engine * | |
1489 | *************************************************************************/ | |
1490 | ||
1491 | /* sizes of tx desc (including padding if needed) as function | |
1492 | * of skb's frag number */ | |
1493 | static struct { | |
1494 | u16 bytes; | |
1495 | u16 qwords; /* qword = 64 bit */ | |
1496 | } txd_sizes[MAX_SKB_FRAGS + 1]; | |
1497 | ||
1498 | /* txdb_map_skb - creates and stores dma mappings for skb's data blocks | |
1499 | * @priv - NIC private structure | |
1500 | * @skb - socket buffer to map | |
1501 | * | |
1502 | * It makes dma mappings for skb's data blocks and writes them to PBL of | |
1503 | * new tx descriptor. It also stores them in the tx db, so they could be | |
1504 | * unmaped after data was sent. It is reponsibility of a caller to make | |
1505 | * sure that there is enough space in the tx db. Last element holds pointer | |
1506 | * to skb itself and marked with zero length | |
1507 | */ | |
1508 | static inline void | |
1509 | bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb, | |
1510 | struct txd_desc *txdd) | |
1511 | { | |
1512 | struct txdb *db = &priv->txdb; | |
1513 | struct pbl *pbl = &txdd->pbl[0]; | |
1514 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1515 | int i; | |
1516 | ||
1517 | db->wptr->len = skb->len - skb->data_len; | |
1518 | db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, | |
1519 | db->wptr->len, PCI_DMA_TODEVICE); | |
1520 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); | |
1521 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); | |
1522 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); | |
1523 | DBG("=== pbl len: 0x%x ================\n", pbl->len); | |
1524 | DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo); | |
1525 | DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi); | |
1526 | bdx_tx_db_inc_wptr(db); | |
1527 | ||
1528 | for (i = 0; i < nr_frags; i++) { | |
1529 | struct skb_frag_struct *frag; | |
1530 | ||
1531 | frag = &skb_shinfo(skb)->frags[i]; | |
1532 | db->wptr->len = frag->size; | |
1533 | db->wptr->addr.dma = | |
1534 | pci_map_page(priv->pdev, frag->page, frag->page_offset, | |
1535 | frag->size, PCI_DMA_TODEVICE); | |
1536 | ||
1537 | pbl++; | |
1538 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); | |
1539 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); | |
1540 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); | |
1541 | bdx_tx_db_inc_wptr(db); | |
1542 | } | |
1543 | ||
1544 | /* add skb clean up info. */ | |
1545 | db->wptr->len = -txd_sizes[nr_frags].bytes; | |
1546 | db->wptr->addr.skb = skb; | |
1547 | bdx_tx_db_inc_wptr(db); | |
1548 | } | |
1549 | ||
1550 | /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags | |
1551 | * number of frags is used as index to fetch correct descriptors size, | |
1552 | * instead of calculating it each time */ | |
1553 | static void __init init_txd_sizes(void) | |
1554 | { | |
1555 | int i, lwords; | |
1556 | ||
1557 | /* 7 - is number of lwords in txd with one phys buffer | |
1558 | * 3 - is number of lwords used for every additional phys buffer */ | |
1559 | for (i = 0; i < MAX_SKB_FRAGS + 1; i++) { | |
1560 | lwords = 7 + (i * 3); | |
1561 | if (lwords & 1) | |
1562 | lwords++; /* pad it with 1 lword */ | |
1563 | txd_sizes[i].qwords = lwords >> 1; | |
1564 | txd_sizes[i].bytes = lwords << 2; | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | /* bdx_tx_init - initialize all Tx related stuff. | |
1569 | * Namely, TXD and TXF fifos, database etc */ | |
1570 | static int bdx_tx_init(struct bdx_priv *priv) | |
1571 | { | |
1572 | if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size, | |
1573 | regTXD_CFG0_0, | |
1574 | regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0)) | |
1575 | goto err_mem; | |
1576 | if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size, | |
1577 | regTXF_CFG0_0, | |
1578 | regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0)) | |
1579 | goto err_mem; | |
1580 | ||
1581 | /* The TX db has to keep mappings for all packets sent (on TxD) | |
1582 | * and not yet reclaimed (on TxF) */ | |
1583 | if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size))) | |
1584 | goto err_mem; | |
1585 | ||
1586 | priv->tx_level = BDX_MAX_TX_LEVEL; | |
1587 | #ifdef BDX_DELAY_WPTR | |
1588 | priv->tx_update_mark = priv->tx_level - 1024; | |
1589 | #endif | |
1590 | return 0; | |
1591 | ||
1592 | err_mem: | |
1593 | ERR("tehuti: %s: Tx init failed\n", priv->ndev->name); | |
1594 | return -ENOMEM; | |
1595 | } | |
1596 | ||
1597 | /* | |
1598 | * bdx_tx_space - calculates avalable space in TX fifo | |
1599 | * @priv - NIC private structure | |
1600 | * Returns avaliable space in TX fifo in bytes | |
1601 | */ | |
1602 | static inline int bdx_tx_space(struct bdx_priv *priv) | |
1603 | { | |
1604 | struct txd_fifo *f = &priv->txd_fifo0; | |
1605 | int fsize; | |
1606 | ||
1607 | f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR; | |
1608 | fsize = f->m.rptr - f->m.wptr; | |
1609 | if (fsize <= 0) | |
1610 | fsize = f->m.memsz + fsize; | |
1611 | return (fsize); | |
1612 | } | |
1613 | ||
1614 | /* bdx_tx_transmit - send packet to NIC | |
1615 | * @skb - packet to send | |
1616 | * ndev - network device assigned to NIC | |
1617 | * Return codes: | |
1618 | * o NETDEV_TX_OK everything ok. | |
1619 | * o NETDEV_TX_BUSY Cannot transmit packet, try later | |
1620 | * Usually a bug, means queue start/stop flow control is broken in | |
1621 | * the driver. Note: the driver must NOT put the skb in its DMA ring. | |
1622 | * o NETDEV_TX_LOCKED Locking failed, please retry quickly. | |
1623 | */ | |
1624 | static int bdx_tx_transmit(struct sk_buff *skb, struct net_device *ndev) | |
1625 | { | |
1626 | struct bdx_priv *priv = ndev->priv; | |
1627 | struct txd_fifo *f = &priv->txd_fifo0; | |
1628 | int txd_checksum = 7; /* full checksum */ | |
1629 | int txd_lgsnd = 0; | |
1630 | int txd_vlan_id = 0; | |
1631 | int txd_vtag = 0; | |
1632 | int txd_mss = 0; | |
1633 | ||
1634 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1635 | struct txd_desc *txdd; | |
1636 | int len; | |
1637 | unsigned long flags; | |
1638 | ||
1639 | ENTER; | |
1640 | local_irq_save(flags); | |
1641 | if (!spin_trylock(&priv->tx_lock)) { | |
1642 | local_irq_restore(flags); | |
1643 | DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n", | |
1644 | BDX_DRV_NAME, ndev->name); | |
1645 | return NETDEV_TX_LOCKED; | |
1646 | } | |
1647 | ||
1648 | /* build tx descriptor */ | |
1649 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ | |
1650 | txdd = (struct txd_desc *)(f->m.va + f->m.wptr); | |
1651 | if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) | |
1652 | txd_checksum = 0; | |
1653 | ||
1654 | if (skb_shinfo(skb)->gso_size) { | |
1655 | txd_mss = skb_shinfo(skb)->gso_size; | |
1656 | txd_lgsnd = 1; | |
1657 | DBG("skb %p skb len %d gso size = %d\n", skb, skb->len, | |
1658 | txd_mss); | |
1659 | } | |
1660 | ||
1661 | if (vlan_tx_tag_present(skb)) { | |
1662 | /*Cut VLAN ID to 12 bits */ | |
1663 | txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12); | |
1664 | txd_vtag = 1; | |
1665 | } | |
1666 | ||
1667 | txdd->length = CPU_CHIP_SWAP16(skb->len); | |
1668 | txdd->mss = CPU_CHIP_SWAP16(txd_mss); | |
1669 | txdd->txd_val1 = | |
1670 | CPU_CHIP_SWAP32(TXD_W1_VAL | |
1671 | (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag, | |
1672 | txd_lgsnd, txd_vlan_id)); | |
1673 | DBG("=== TxD desc =====================\n"); | |
1674 | DBG("=== w1: 0x%x ================\n", txdd->txd_val1); | |
1675 | DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length); | |
1676 | ||
1677 | bdx_tx_map_skb(priv, skb, txdd); | |
1678 | ||
1679 | /* increment TXD write pointer. In case of | |
1680 | fifo wrapping copy reminder of the descriptor | |
1681 | to the beginning */ | |
1682 | f->m.wptr += txd_sizes[nr_frags].bytes; | |
1683 | len = f->m.wptr - f->m.memsz; | |
1684 | if (unlikely(len >= 0)) { | |
1685 | f->m.wptr = len; | |
1686 | if (len > 0) { | |
1687 | BDX_ASSERT(len > f->m.memsz); | |
1688 | memcpy(f->m.va, f->m.va + f->m.memsz, len); | |
1689 | } | |
1690 | } | |
1691 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ | |
1692 | ||
1693 | priv->tx_level -= txd_sizes[nr_frags].bytes; | |
1694 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); | |
1695 | #ifdef BDX_DELAY_WPTR | |
1696 | if (priv->tx_level > priv->tx_update_mark) { | |
1697 | /* Force memory writes to complete before letting h/w | |
1698 | know there are new descriptors to fetch. | |
1699 | (might be needed on platforms like IA64) | |
1700 | wmb(); */ | |
1701 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1702 | } else { | |
1703 | if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) { | |
1704 | priv->tx_noupd = 0; | |
1705 | WRITE_REG(priv, f->m.reg_WPTR, | |
1706 | f->m.wptr & TXF_WPTR_WR_PTR); | |
1707 | } | |
1708 | } | |
1709 | #else | |
1710 | /* Force memory writes to complete before letting h/w | |
1711 | know there are new descriptors to fetch. | |
1712 | (might be needed on platforms like IA64) | |
1713 | wmb(); */ | |
1714 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1715 | ||
1716 | #endif | |
1717 | ndev->trans_start = jiffies; | |
1718 | ||
1719 | priv->net_stats.tx_packets++; | |
1720 | priv->net_stats.tx_bytes += skb->len; | |
1721 | ||
1722 | if (priv->tx_level < BDX_MIN_TX_LEVEL) { | |
1723 | DBG("%s: %s: TX Q STOP level %d\n", | |
1724 | BDX_DRV_NAME, ndev->name, priv->tx_level); | |
1725 | netif_stop_queue(ndev); | |
1726 | } | |
1727 | ||
1728 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1729 | return NETDEV_TX_OK; | |
1730 | } | |
1731 | ||
1732 | /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ. | |
1733 | * @priv - bdx adapter | |
1734 | * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS | |
1735 | * that those packets were sent | |
1736 | */ | |
1737 | static void bdx_tx_cleanup(struct bdx_priv *priv) | |
1738 | { | |
1739 | struct txf_fifo *f = &priv->txf_fifo0; | |
1740 | struct txdb *db = &priv->txdb; | |
1741 | int tx_level = 0; | |
1742 | ||
1743 | ENTER; | |
1744 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; | |
1745 | BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */ | |
1746 | ||
1747 | while (f->m.wptr != f->m.rptr) { | |
1748 | f->m.rptr += BDX_TXF_DESC_SZ; | |
1749 | f->m.rptr &= f->m.size_mask; | |
1750 | ||
1751 | /* unmap all the fragments */ | |
1752 | /* first has to come tx_maps containing dma */ | |
1753 | BDX_ASSERT(db->rptr->len == 0); | |
1754 | do { | |
1755 | BDX_ASSERT(db->rptr->addr.dma == 0); | |
1756 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, | |
1757 | db->rptr->len, PCI_DMA_TODEVICE); | |
1758 | bdx_tx_db_inc_rptr(db); | |
1759 | } while (db->rptr->len > 0); | |
1760 | tx_level -= db->rptr->len; /* '-' koz len is negative */ | |
1761 | ||
1762 | /* now should come skb pointer - free it */ | |
1a348ccc AG |
1763 | dev_kfree_skb_irq(db->rptr->addr.skb); |
1764 | bdx_tx_db_inc_rptr(db); | |
1765 | } | |
1766 | ||
1767 | /* let h/w know which TXF descriptors were cleaned */ | |
1768 | BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); | |
1769 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); | |
1770 | ||
1771 | /* We reclaimed resources, so in case the Q is stopped by xmit callback, | |
1772 | * we resume the transmition and use tx_lock to synchronize with xmit.*/ | |
1773 | spin_lock(&priv->tx_lock); | |
1774 | priv->tx_level += tx_level; | |
1775 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); | |
1776 | #ifdef BDX_DELAY_WPTR | |
1777 | if (priv->tx_noupd) { | |
1778 | priv->tx_noupd = 0; | |
1779 | WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR, | |
1780 | priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); | |
1781 | } | |
1782 | #endif | |
1783 | ||
1784 | if (unlikely(netif_queue_stopped(priv->ndev) | |
1785 | && netif_carrier_ok(priv->ndev) | |
1786 | && (priv->tx_level >= BDX_MIN_TX_LEVEL))) { | |
1787 | DBG("%s: %s: TX Q WAKE level %d\n", | |
1788 | BDX_DRV_NAME, priv->ndev->name, priv->tx_level); | |
1789 | netif_wake_queue(priv->ndev); | |
1790 | } | |
1791 | spin_unlock(&priv->tx_lock); | |
1792 | } | |
1793 | ||
1794 | /* bdx_tx_free_skbs - frees all skbs from TXD fifo. | |
1795 | * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod | |
1796 | */ | |
1797 | static void bdx_tx_free_skbs(struct bdx_priv *priv) | |
1798 | { | |
1799 | struct txdb *db = &priv->txdb; | |
1800 | ||
1801 | ENTER; | |
1802 | while (db->rptr != db->wptr) { | |
1803 | if (likely(db->rptr->len)) | |
1804 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, | |
1805 | db->rptr->len, PCI_DMA_TODEVICE); | |
1806 | else | |
1807 | dev_kfree_skb(db->rptr->addr.skb); | |
1808 | bdx_tx_db_inc_rptr(db); | |
1809 | } | |
1810 | RET(); | |
1811 | } | |
1812 | ||
1813 | /* bdx_tx_free - frees all Tx resources */ | |
1814 | static void bdx_tx_free(struct bdx_priv *priv) | |
1815 | { | |
1816 | ENTER; | |
1817 | bdx_tx_free_skbs(priv); | |
1818 | bdx_fifo_free(priv, &priv->txd_fifo0.m); | |
1819 | bdx_fifo_free(priv, &priv->txf_fifo0.m); | |
1820 | bdx_tx_db_close(&priv->txdb); | |
1821 | } | |
1822 | ||
1823 | /* bdx_tx_push_desc - push descriptor to TxD fifo | |
1824 | * @priv - NIC private structure | |
1825 | * @data - desc's data | |
1826 | * @size - desc's size | |
1827 | * | |
1828 | * Pushes desc to TxD fifo and overlaps it if needed. | |
1829 | * NOTE: this func does not check for available space. this is responsibility | |
1830 | * of the caller. Neither does it check that data size is smaller then | |
1831 | * fifo size. | |
1832 | */ | |
1833 | static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) | |
1834 | { | |
1835 | struct txd_fifo *f = &priv->txd_fifo0; | |
1836 | int i = f->m.memsz - f->m.wptr; | |
1837 | ||
1838 | if (size == 0) | |
1839 | return; | |
1840 | ||
1841 | if (i > size) { | |
1842 | memcpy(f->m.va + f->m.wptr, data, size); | |
1843 | f->m.wptr += size; | |
1844 | } else { | |
1845 | memcpy(f->m.va + f->m.wptr, data, i); | |
1846 | f->m.wptr = size - i; | |
1847 | memcpy(f->m.va, data + i, f->m.wptr); | |
1848 | } | |
1849 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1850 | } | |
1851 | ||
1852 | /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way | |
1853 | * @priv - NIC private structure | |
1854 | * @data - desc's data | |
1855 | * @size - desc's size | |
1856 | * | |
1857 | * NOTE: this func does check for available space and, if neccessary, waits for | |
1858 | * NIC to read existing data before writing new one. | |
1859 | */ | |
1860 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) | |
1861 | { | |
1862 | int timer = 0; | |
1863 | ENTER; | |
1864 | ||
1865 | while (size > 0) { | |
1866 | /* we substruct 8 because when fifo is full rptr == wptr | |
1867 | which also means that fifo is empty, we can understand | |
1868 | the difference, but could hw do the same ??? :) */ | |
1869 | int avail = bdx_tx_space(priv) - 8; | |
1870 | if (avail <= 0) { | |
1871 | if (timer++ > 300) { /* prevent endless loop */ | |
1872 | DBG("timeout while writing desc to TxD fifo\n"); | |
1873 | break; | |
1874 | } | |
1875 | udelay(50); /* give hw a chance to clean fifo */ | |
1876 | continue; | |
1877 | } | |
1878 | avail = MIN(avail, size); | |
1879 | DBG("about to push %d bytes starting %p size %d\n", avail, | |
1880 | data, size); | |
1881 | bdx_tx_push_desc(priv, data, avail); | |
1882 | size -= avail; | |
1883 | data += avail; | |
1884 | } | |
1885 | RET(); | |
1886 | } | |
1887 | ||
1888 | /** | |
1889 | * bdx_probe - Device Initialization Routine | |
1890 | * @pdev: PCI device information struct | |
1891 | * @ent: entry in bdx_pci_tbl | |
1892 | * | |
1893 | * Returns 0 on success, negative on failure | |
1894 | * | |
1895 | * bdx_probe initializes an adapter identified by a pci_dev structure. | |
1896 | * The OS initialization, configuring of the adapter private structure, | |
1897 | * and a hardware reset occur. | |
1898 | * | |
1899 | * functions and their order used as explained in | |
1900 | * /usr/src/linux/Documentation/DMA-{API,mapping}.txt | |
1901 | * | |
1902 | */ | |
1903 | ||
1904 | /* TBD: netif_msg should be checked and implemented. I disable it for now */ | |
1905 | static int __devinit | |
1906 | bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1907 | { | |
1908 | struct net_device *ndev; | |
1909 | struct bdx_priv *priv; | |
1910 | int err, pci_using_dac, port; | |
1911 | unsigned long pciaddr; | |
1912 | u32 regionSize; | |
1913 | struct pci_nic *nic; | |
1914 | ||
1915 | ENTER; | |
1916 | ||
1917 | nic = vmalloc(sizeof(*nic)); | |
1918 | if (!nic) | |
1919 | RET(-ENOMEM); | |
1920 | ||
1921 | /************** pci *****************/ | |
1922 | if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */ | |
bc2618f7 | 1923 | goto err_pci; /* it's not a problem though */ |
1a348ccc AG |
1924 | |
1925 | if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) && | |
1926 | !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) { | |
1927 | pci_using_dac = 1; | |
1928 | } else { | |
1929 | if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) || | |
1930 | (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { | |
1931 | printk(KERN_ERR "tehuti: No usable DMA configuration" | |
1932 | ", aborting\n"); | |
1933 | goto err_dma; | |
1934 | } | |
1935 | pci_using_dac = 0; | |
1936 | } | |
1937 | ||
1938 | if ((err = pci_request_regions(pdev, BDX_DRV_NAME))) | |
1939 | goto err_dma; | |
1940 | ||
1941 | pci_set_master(pdev); | |
1942 | ||
1943 | pciaddr = pci_resource_start(pdev, 0); | |
1944 | if (!pciaddr) { | |
1945 | err = -EIO; | |
1946 | ERR("tehuti: no MMIO resource\n"); | |
1947 | goto err_out_res; | |
1948 | } | |
1949 | if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) { | |
1950 | err = -EIO; | |
1951 | ERR("tehuti: MMIO resource (%x) too small\n", regionSize); | |
1952 | goto err_out_res; | |
1953 | } | |
1954 | ||
1955 | nic->regs = ioremap(pciaddr, regionSize); | |
1956 | if (!nic->regs) { | |
1957 | err = -EIO; | |
1958 | ERR("tehuti: ioremap failed\n"); | |
1959 | goto err_out_res; | |
1960 | } | |
1961 | ||
1962 | if (pdev->irq < 2) { | |
1963 | err = -EIO; | |
1964 | ERR("tehuti: invalid irq (%d)\n", pdev->irq); | |
1965 | goto err_out_iomap; | |
1966 | } | |
1967 | pci_set_drvdata(pdev, nic); | |
1968 | ||
1969 | if (pdev->device == 0x3014) | |
1970 | nic->port_num = 2; | |
1971 | else | |
1972 | nic->port_num = 1; | |
1973 | ||
1974 | print_hw_id(pdev); | |
1975 | ||
1976 | bdx_hw_reset_direct(nic->regs); | |
1977 | ||
1978 | nic->irq_type = IRQ_INTX; | |
1979 | #ifdef BDX_MSI | |
1980 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) { | |
1981 | if ((err = pci_enable_msi(pdev))) | |
1982 | ERR("Tehuti: Can't eneble msi. error is %d\n", err); | |
1983 | else | |
1984 | nic->irq_type = IRQ_MSI; | |
1985 | } else | |
1986 | DBG("HW does not support MSI\n"); | |
1987 | #endif | |
1988 | ||
1989 | /************** netdev **************/ | |
1990 | for (port = 0; port < nic->port_num; port++) { | |
1991 | if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) { | |
1992 | err = -ENOMEM; | |
1993 | printk(KERN_ERR "tehuti: alloc_etherdev failed\n"); | |
1994 | goto err_out_iomap; | |
1995 | } | |
1996 | ||
1997 | ndev->open = bdx_open; | |
1998 | ndev->stop = bdx_close; | |
1999 | ndev->hard_start_xmit = bdx_tx_transmit; | |
2000 | ndev->do_ioctl = bdx_ioctl; | |
2001 | ndev->set_multicast_list = bdx_setmulti; | |
2002 | ndev->get_stats = bdx_get_stats; | |
2003 | ndev->change_mtu = bdx_change_mtu; | |
2004 | ndev->set_mac_address = bdx_set_mac; | |
2005 | ndev->tx_queue_len = BDX_NDEV_TXQ_LEN; | |
2006 | ndev->vlan_rx_register = bdx_vlan_rx_register; | |
2007 | ndev->vlan_rx_add_vid = bdx_vlan_rx_add_vid; | |
2008 | ndev->vlan_rx_kill_vid = bdx_vlan_rx_kill_vid; | |
2009 | ||
2010 | bdx_ethtool_ops(ndev); /* ethtool interface */ | |
2011 | ||
2012 | /* these fields are used for info purposes only | |
2013 | * so we can have them same for all ports of the board */ | |
2014 | ndev->if_port = port; | |
2015 | ndev->base_addr = pciaddr; | |
2016 | ndev->mem_start = pciaddr; | |
2017 | ndev->mem_end = pciaddr + regionSize; | |
2018 | ndev->irq = pdev->irq; | |
2019 | ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO | |
2020 | | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | | |
2021 | NETIF_F_HW_VLAN_FILTER | |
2022 | /*| NETIF_F_FRAGLIST */ | |
2023 | ; | |
2024 | ||
2025 | if (pci_using_dac) | |
2026 | ndev->features |= NETIF_F_HIGHDMA; | |
2027 | ||
2028 | /************** priv ****************/ | |
2029 | priv = nic->priv[port] = ndev->priv; | |
2030 | ||
2031 | memset(priv, 0, sizeof(struct bdx_priv)); | |
2032 | priv->pBdxRegs = nic->regs + port * 0x8000; | |
2033 | priv->port = port; | |
2034 | priv->pdev = pdev; | |
2035 | priv->ndev = ndev; | |
2036 | priv->nic = nic; | |
2037 | priv->msg_enable = BDX_DEF_MSG_ENABLE; | |
2038 | ||
2039 | netif_napi_add(ndev, &priv->napi, bdx_poll, 64); | |
2040 | ||
2041 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) { | |
2042 | DBG("HW statistics not supported\n"); | |
2043 | priv->stats_flag = 0; | |
2044 | } else { | |
2045 | priv->stats_flag = 1; | |
2046 | } | |
2047 | ||
2048 | /* Initialize fifo sizes. */ | |
2049 | priv->txd_size = 2; | |
2050 | priv->txf_size = 2; | |
2051 | priv->rxd_size = 2; | |
2052 | priv->rxf_size = 3; | |
2053 | ||
2054 | /* Initialize the initial coalescing registers. */ | |
2055 | priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12); | |
2056 | priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12); | |
2057 | ||
2058 | /* ndev->xmit_lock spinlock is not used. | |
2059 | * Private priv->tx_lock is used for synchronization | |
2060 | * between transmit and TX irq cleanup. In addition | |
2061 | * set multicast list callback has to use priv->tx_lock. | |
2062 | */ | |
2063 | #ifdef BDX_LLTX | |
2064 | ndev->features |= NETIF_F_LLTX; | |
2065 | #endif | |
2066 | spin_lock_init(&priv->tx_lock); | |
2067 | ||
2068 | /*bdx_hw_reset(priv); */ | |
2069 | if (bdx_read_mac(priv)) { | |
2070 | printk(KERN_ERR "tehuti: load MAC address failed\n"); | |
2071 | goto err_out_iomap; | |
2072 | } | |
2073 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2074 | if ((err = register_netdev(ndev))) { | |
2075 | printk(KERN_ERR "tehuti: register_netdev failed\n"); | |
2076 | goto err_out_free; | |
2077 | } | |
2078 | netif_carrier_off(ndev); | |
2079 | netif_stop_queue(ndev); | |
2080 | ||
2081 | print_eth_id(ndev); | |
2082 | } | |
2083 | RET(0); | |
2084 | ||
2085 | err_out_free: | |
2086 | free_netdev(ndev); | |
2087 | err_out_iomap: | |
2088 | iounmap(nic->regs); | |
2089 | err_out_res: | |
2090 | pci_release_regions(pdev); | |
2091 | err_dma: | |
2092 | pci_disable_device(pdev); | |
bc2618f7 | 2093 | err_pci: |
1a348ccc AG |
2094 | vfree(nic); |
2095 | ||
2096 | RET(err); | |
2097 | } | |
2098 | ||
2099 | /****************** Ethtool interface *********************/ | |
2100 | /* get strings for tests */ | |
2101 | static const char | |
2102 | bdx_test_names[][ETH_GSTRING_LEN] = { | |
2103 | "No tests defined" | |
2104 | }; | |
2105 | ||
2106 | /* get strings for statistics counters */ | |
2107 | static const char | |
2108 | bdx_stat_names[][ETH_GSTRING_LEN] = { | |
2109 | "InUCast", /* 0x7200 */ | |
2110 | "InMCast", /* 0x7210 */ | |
2111 | "InBCast", /* 0x7220 */ | |
2112 | "InPkts", /* 0x7230 */ | |
2113 | "InErrors", /* 0x7240 */ | |
2114 | "InDropped", /* 0x7250 */ | |
2115 | "FrameTooLong", /* 0x7260 */ | |
2116 | "FrameSequenceErrors", /* 0x7270 */ | |
2117 | "InVLAN", /* 0x7280 */ | |
2118 | "InDroppedDFE", /* 0x7290 */ | |
2119 | "InDroppedIntFull", /* 0x72A0 */ | |
2120 | "InFrameAlignErrors", /* 0x72B0 */ | |
2121 | ||
2122 | /* 0x72C0-0x72E0 RSRV */ | |
2123 | ||
2124 | "OutUCast", /* 0x72F0 */ | |
2125 | "OutMCast", /* 0x7300 */ | |
2126 | "OutBCast", /* 0x7310 */ | |
2127 | "OutPkts", /* 0x7320 */ | |
2128 | ||
2129 | /* 0x7330-0x7360 RSRV */ | |
2130 | ||
2131 | "OutVLAN", /* 0x7370 */ | |
2132 | "InUCastOctects", /* 0x7380 */ | |
2133 | "OutUCastOctects", /* 0x7390 */ | |
2134 | ||
2135 | /* 0x73A0-0x73B0 RSRV */ | |
2136 | ||
2137 | "InBCastOctects", /* 0x73C0 */ | |
2138 | "OutBCastOctects", /* 0x73D0 */ | |
2139 | "InOctects", /* 0x73E0 */ | |
2140 | "OutOctects", /* 0x73F0 */ | |
2141 | }; | |
2142 | ||
2143 | /* | |
2144 | * bdx_get_settings - get device-specific settings | |
2145 | * @netdev | |
2146 | * @ecmd | |
2147 | */ | |
2148 | static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
2149 | { | |
2150 | u32 rdintcm; | |
2151 | u32 tdintcm; | |
2152 | struct bdx_priv *priv = netdev->priv; | |
2153 | ||
2154 | rdintcm = priv->rdintcm; | |
2155 | tdintcm = priv->tdintcm; | |
2156 | ||
2157 | ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); | |
2158 | ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); | |
2159 | ecmd->speed = SPEED_10000; | |
2160 | ecmd->duplex = DUPLEX_FULL; | |
2161 | ecmd->port = PORT_FIBRE; | |
2162 | ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */ | |
2163 | ecmd->autoneg = AUTONEG_DISABLE; | |
2164 | ||
2165 | /* PCK_TH measures in multiples of FIFO bytes | |
2166 | We translate to packets */ | |
2167 | ecmd->maxtxpkt = | |
2168 | ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); | |
2169 | ecmd->maxrxpkt = | |
2170 | ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); | |
2171 | ||
2172 | return 0; | |
2173 | } | |
2174 | ||
2175 | /* | |
2176 | * bdx_get_drvinfo - report driver information | |
2177 | * @netdev | |
2178 | * @drvinfo | |
2179 | */ | |
2180 | static void | |
2181 | bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | |
2182 | { | |
2183 | struct bdx_priv *priv = netdev->priv; | |
2184 | ||
072ee3f9 RK |
2185 | strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver)); |
2186 | strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version)); | |
2187 | strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | |
2188 | strlcat(drvinfo->bus_info, pci_name(priv->pdev), | |
1a348ccc AG |
2189 | sizeof(drvinfo->bus_info)); |
2190 | ||
4c3616cd | 2191 | drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0); |
1a348ccc AG |
2192 | drvinfo->testinfo_len = 0; |
2193 | drvinfo->regdump_len = 0; | |
2194 | drvinfo->eedump_len = 0; | |
2195 | } | |
2196 | ||
2197 | /* | |
2198 | * bdx_get_rx_csum - report whether receive checksums are turned on or off | |
2199 | * @netdev | |
2200 | */ | |
2201 | static u32 bdx_get_rx_csum(struct net_device *netdev) | |
2202 | { | |
2203 | return 1; /* always on */ | |
2204 | } | |
2205 | ||
2206 | /* | |
2207 | * bdx_get_tx_csum - report whether transmit checksums are turned on or off | |
2208 | * @netdev | |
2209 | */ | |
2210 | static u32 bdx_get_tx_csum(struct net_device *netdev) | |
2211 | { | |
2212 | return (netdev->features & NETIF_F_IP_CSUM) != 0; | |
2213 | } | |
2214 | ||
2215 | /* | |
2216 | * bdx_get_coalesce - get interrupt coalescing parameters | |
2217 | * @netdev | |
2218 | * @ecoal | |
2219 | */ | |
2220 | static int | |
2221 | bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) | |
2222 | { | |
2223 | u32 rdintcm; | |
2224 | u32 tdintcm; | |
2225 | struct bdx_priv *priv = netdev->priv; | |
2226 | ||
2227 | rdintcm = priv->rdintcm; | |
2228 | tdintcm = priv->tdintcm; | |
2229 | ||
2230 | /* PCK_TH measures in multiples of FIFO bytes | |
2231 | We translate to packets */ | |
2232 | ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT; | |
2233 | ecoal->rx_max_coalesced_frames = | |
2234 | ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); | |
2235 | ||
2236 | ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT; | |
2237 | ecoal->tx_max_coalesced_frames = | |
2238 | ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); | |
2239 | ||
2240 | /* adaptive parameters ignored */ | |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | /* | |
2245 | * bdx_set_coalesce - set interrupt coalescing parameters | |
2246 | * @netdev | |
2247 | * @ecoal | |
2248 | */ | |
2249 | static int | |
2250 | bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) | |
2251 | { | |
2252 | u32 rdintcm; | |
2253 | u32 tdintcm; | |
2254 | struct bdx_priv *priv = netdev->priv; | |
2255 | int rx_coal; | |
2256 | int tx_coal; | |
2257 | int rx_max_coal; | |
2258 | int tx_max_coal; | |
2259 | ||
2260 | /* Check for valid input */ | |
2261 | rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT; | |
2262 | tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT; | |
2263 | rx_max_coal = ecoal->rx_max_coalesced_frames; | |
2264 | tx_max_coal = ecoal->tx_max_coalesced_frames; | |
2265 | ||
2266 | /* Translate from packets to multiples of FIFO bytes */ | |
2267 | rx_max_coal = | |
2268 | (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1) | |
2269 | / PCK_TH_MULT); | |
2270 | tx_max_coal = | |
2271 | (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1) | |
2272 | / PCK_TH_MULT); | |
2273 | ||
2274 | if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) | |
2275 | || (rx_max_coal > 0xF) || (tx_max_coal > 0xF)) | |
2276 | return -EINVAL; | |
2277 | ||
2278 | rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm), | |
2279 | GET_RXF_TH(priv->rdintcm), rx_max_coal); | |
2280 | tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0, | |
2281 | tx_max_coal); | |
2282 | ||
2283 | priv->rdintcm = rdintcm; | |
2284 | priv->tdintcm = tdintcm; | |
2285 | ||
2286 | WRITE_REG(priv, regRDINTCM0, rdintcm); | |
2287 | WRITE_REG(priv, regTDINTCM0, tdintcm); | |
2288 | ||
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /* Convert RX fifo size to number of pending packets */ | |
2293 | static inline int bdx_rx_fifo_size_to_packets(int rx_size) | |
2294 | { | |
2295 | return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc)); | |
2296 | } | |
2297 | ||
2298 | /* Convert TX fifo size to number of pending packets */ | |
2299 | static inline int bdx_tx_fifo_size_to_packets(int tx_size) | |
2300 | { | |
2301 | return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ); | |
2302 | } | |
2303 | ||
2304 | /* | |
2305 | * bdx_get_ringparam - report ring sizes | |
2306 | * @netdev | |
2307 | * @ring | |
2308 | */ | |
2309 | static void | |
2310 | bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | |
2311 | { | |
2312 | struct bdx_priv *priv = netdev->priv; | |
2313 | ||
2314 | /*max_pending - the maximum-sized FIFO we allow */ | |
2315 | ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3); | |
2316 | ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3); | |
2317 | ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size); | |
2318 | ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size); | |
2319 | } | |
2320 | ||
2321 | /* | |
2322 | * bdx_set_ringparam - set ring sizes | |
2323 | * @netdev | |
2324 | * @ring | |
2325 | */ | |
2326 | static int | |
2327 | bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | |
2328 | { | |
2329 | struct bdx_priv *priv = netdev->priv; | |
2330 | int rx_size = 0; | |
2331 | int tx_size = 0; | |
2332 | ||
2333 | for (; rx_size < 4; rx_size++) { | |
2334 | if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending) | |
2335 | break; | |
2336 | } | |
2337 | if (rx_size == 4) | |
2338 | rx_size = 3; | |
2339 | ||
2340 | for (; tx_size < 4; tx_size++) { | |
2341 | if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending) | |
2342 | break; | |
2343 | } | |
2344 | if (tx_size == 4) | |
2345 | tx_size = 3; | |
2346 | ||
2347 | /*Is there anything to do? */ | |
2348 | if ((rx_size == priv->rxf_size) | |
2349 | && (tx_size == priv->txd_size)) | |
2350 | return 0; | |
2351 | ||
2352 | priv->rxf_size = rx_size; | |
2353 | if (rx_size > 1) | |
2354 | priv->rxd_size = rx_size - 1; | |
2355 | else | |
2356 | priv->rxd_size = rx_size; | |
2357 | ||
2358 | priv->txf_size = priv->txd_size = tx_size; | |
2359 | ||
2360 | if (netif_running(netdev)) { | |
2361 | bdx_close(netdev); | |
2362 | bdx_open(netdev); | |
2363 | } | |
2364 | return 0; | |
2365 | } | |
2366 | ||
2367 | /* | |
2368 | * bdx_get_strings - return a set of strings that describe the requested objects | |
2369 | * @netdev | |
2370 | * @data | |
2371 | */ | |
2372 | static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data) | |
2373 | { | |
2374 | switch (stringset) { | |
2375 | case ETH_SS_TEST: | |
2376 | memcpy(data, *bdx_test_names, sizeof(bdx_test_names)); | |
2377 | break; | |
2378 | case ETH_SS_STATS: | |
2379 | memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names)); | |
2380 | break; | |
2381 | } | |
2382 | } | |
2383 | ||
2384 | /* | |
2385 | * bdx_get_stats_count - return number of 64bit statistics counters | |
2386 | * @netdev | |
2387 | */ | |
2388 | static int bdx_get_stats_count(struct net_device *netdev) | |
2389 | { | |
2390 | struct bdx_priv *priv = netdev->priv; | |
4c3616cd | 2391 | BDX_ASSERT(ARRAY_SIZE(bdx_stat_names) |
1a348ccc | 2392 | != sizeof(struct bdx_stats) / sizeof(u64)); |
4c3616cd | 2393 | return ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0); |
1a348ccc AG |
2394 | } |
2395 | ||
2396 | /* | |
2397 | * bdx_get_ethtool_stats - return device's hardware L2 statistics | |
2398 | * @netdev | |
2399 | * @stats | |
2400 | * @data | |
2401 | */ | |
2402 | static void bdx_get_ethtool_stats(struct net_device *netdev, | |
2403 | struct ethtool_stats *stats, u64 *data) | |
2404 | { | |
2405 | struct bdx_priv *priv = netdev->priv; | |
2406 | ||
2407 | if (priv->stats_flag) { | |
2408 | ||
2409 | /* Update stats from HW */ | |
2410 | bdx_update_stats(priv); | |
2411 | ||
2412 | /* Copy data to user buffer */ | |
2413 | memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats)); | |
2414 | } | |
2415 | } | |
2416 | ||
2417 | /* | |
2418 | * bdx_ethtool_ops - ethtool interface implementation | |
2419 | * @netdev | |
2420 | */ | |
2421 | static void bdx_ethtool_ops(struct net_device *netdev) | |
2422 | { | |
2423 | static struct ethtool_ops bdx_ethtool_ops = { | |
2424 | .get_settings = bdx_get_settings, | |
2425 | .get_drvinfo = bdx_get_drvinfo, | |
2426 | .get_link = ethtool_op_get_link, | |
2427 | .get_coalesce = bdx_get_coalesce, | |
2428 | .set_coalesce = bdx_set_coalesce, | |
2429 | .get_ringparam = bdx_get_ringparam, | |
2430 | .set_ringparam = bdx_set_ringparam, | |
2431 | .get_rx_csum = bdx_get_rx_csum, | |
2432 | .get_tx_csum = bdx_get_tx_csum, | |
2433 | .get_sg = ethtool_op_get_sg, | |
2434 | .get_tso = ethtool_op_get_tso, | |
2435 | .get_strings = bdx_get_strings, | |
2436 | .get_stats_count = bdx_get_stats_count, | |
2437 | .get_ethtool_stats = bdx_get_ethtool_stats, | |
2438 | }; | |
2439 | ||
2440 | SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops); | |
2441 | } | |
2442 | ||
2443 | /** | |
2444 | * bdx_remove - Device Removal Routine | |
2445 | * @pdev: PCI device information struct | |
2446 | * | |
2447 | * bdx_remove is called by the PCI subsystem to alert the driver | |
2448 | * that it should release a PCI device. The could be caused by a | |
2449 | * Hot-Plug event, or because the driver is going to be removed from | |
2450 | * memory. | |
2451 | **/ | |
2452 | static void __devexit bdx_remove(struct pci_dev *pdev) | |
2453 | { | |
2454 | struct pci_nic *nic = pci_get_drvdata(pdev); | |
2455 | struct net_device *ndev; | |
2456 | int port; | |
2457 | ||
2458 | for (port = 0; port < nic->port_num; port++) { | |
2459 | ndev = nic->priv[port]->ndev; | |
2460 | unregister_netdev(ndev); | |
2461 | free_netdev(ndev); | |
2462 | } | |
2463 | ||
2464 | /*bdx_hw_reset_direct(nic->regs); */ | |
2465 | #ifdef BDX_MSI | |
2466 | if (nic->irq_type == IRQ_MSI) | |
2467 | pci_disable_msi(pdev); | |
2468 | #endif | |
2469 | ||
2470 | iounmap(nic->regs); | |
2471 | pci_release_regions(pdev); | |
2472 | pci_disable_device(pdev); | |
2473 | pci_set_drvdata(pdev, NULL); | |
2474 | vfree(nic); | |
2475 | ||
2476 | RET(); | |
2477 | } | |
2478 | ||
2479 | static struct pci_driver bdx_pci_driver = { | |
2480 | .name = BDX_DRV_NAME, | |
2481 | .id_table = bdx_pci_tbl, | |
2482 | .probe = bdx_probe, | |
2483 | .remove = __devexit_p(bdx_remove), | |
2484 | }; | |
2485 | ||
2486 | /* | |
2487 | * print_driver_id - print parameters of the driver build | |
2488 | */ | |
2489 | static void __init print_driver_id(void) | |
2490 | { | |
2491 | printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC, | |
2492 | BDX_DRV_VERSION); | |
2493 | printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME, | |
2494 | BDX_MSI_STRING); | |
2495 | } | |
2496 | ||
2497 | static int __init bdx_module_init(void) | |
2498 | { | |
2499 | ENTER; | |
2500 | bdx_firmware_endianess(); | |
2501 | init_txd_sizes(); | |
2502 | print_driver_id(); | |
2503 | RET(pci_register_driver(&bdx_pci_driver)); | |
2504 | } | |
2505 | ||
2506 | module_init(bdx_module_init); | |
2507 | ||
2508 | static void __exit bdx_module_exit(void) | |
2509 | { | |
2510 | ENTER; | |
2511 | pci_unregister_driver(&bdx_pci_driver); | |
2512 | RET(); | |
2513 | } | |
2514 | ||
2515 | module_exit(bdx_module_exit); | |
2516 | ||
2517 | MODULE_LICENSE("GPL"); | |
2518 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2519 | MODULE_DESCRIPTION(BDX_DRV_DESC); |