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sparc: Annotate of_device_id arrays with const or __initdata.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sunqe.c
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ecba38ab 1/* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
1da177e4
LT		 2 * Once again I am out to prove that every ethernet
3 * controller out there can be most efficiently programmed
4 * if you make it look like a LANCE.
5 *
8e912b33 6 * Copyright (C) 1996, 1999, 2003, 2006, 2008 David S. Miller (davem@davemloft.net)
1da177e4
LT		 7 */
8
1da177e4
LT		 9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/crc32.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/ethtool.h>
26#include <linux/bitops.h>
738f2b7b 27#include <linux/dma-mapping.h>
8e912b33
DM		 28#include <linux/of.h>
29#include <linux/of_device.h>
1da177e4
LT		 30
31#include <asm/system.h>
32#include <asm/io.h>
33#include <asm/dma.h>
34#include <asm/byteorder.h>
35#include <asm/idprom.h>
1da177e4
LT		 36#include <asm/openprom.h>
37#include <asm/oplib.h>
38#include <asm/auxio.h>
39#include <asm/pgtable.h>
40#include <asm/irq.h>
41
42#include "sunqe.h"
43
10158286 44#define DRV_NAME "sunqe"
8e912b33
DM		 45#define DRV_VERSION "4.1"
46#define DRV_RELDATE "August 27, 2008"
ecba38ab 47#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
10158286
TC		 48
49static char version[] =
50 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
51
52MODULE_VERSION(DRV_VERSION);
53MODULE_AUTHOR(DRV_AUTHOR);
54MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
55MODULE_LICENSE("GPL");
56
1da177e4
LT		 57static struct sunqec *root_qec_dev;
58
59static void qe_set_multicast(struct net_device *dev);
60
61#define QEC_RESET_TRIES 200
62
63static inline int qec_global_reset(void __iomem *gregs)
64{
65 int tries = QEC_RESET_TRIES;
66
67 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
68 while (--tries) {
69 u32 tmp = sbus_readl(gregs + GLOB_CTRL);
70 if (tmp & GLOB_CTRL_RESET) {
71 udelay(20);
72 continue;
73 }
74 break;
75 }
76 if (tries)
77 return 0;
78 printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
79 return -1;
80}
81
82#define MACE_RESET_RETRIES 200
83#define QE_RESET_RETRIES 200
84
85static inline int qe_stop(struct sunqe *qep)
86{
87 void __iomem *cregs = qep->qcregs;
88 void __iomem *mregs = qep->mregs;
89 int tries;
90
91 /* Reset the MACE, then the QEC channel. */
92 sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
93 tries = MACE_RESET_RETRIES;
94 while (--tries) {
95 u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
96 if (tmp & MREGS_BCONFIG_RESET) {
97 udelay(20);
98 continue;
99 }
100 break;
101 }
102 if (!tries) {
103 printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
104 return -1;
105 }
106
107 sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
108 tries = QE_RESET_RETRIES;
109 while (--tries) {
110 u32 tmp = sbus_readl(cregs + CREG_CTRL);
111 if (tmp & CREG_CTRL_RESET) {
112 udelay(20);
113 continue;
114 }
115 break;
116 }
117 if (!tries) {
118 printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
119 return -1;
120 }
121 return 0;
122}
123
124static void qe_init_rings(struct sunqe *qep)
125{
126 struct qe_init_block *qb = qep->qe_block;
127 struct sunqe_buffers *qbufs = qep->buffers;
128 __u32 qbufs_dvma = qep->buffers_dvma;
129 int i;
130
131 qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
132 memset(qb, 0, sizeof(struct qe_init_block));
133 memset(qbufs, 0, sizeof(struct sunqe_buffers));
134 for (i = 0; i < RX_RING_SIZE; i++) {
135 qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
136 qb->qe_rxd[i].rx_flags =
137 (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
138 }
139}
140
141static int qe_init(struct sunqe *qep, int from_irq)
142{
143 struct sunqec *qecp = qep->parent;
144 void __iomem *cregs = qep->qcregs;
145 void __iomem *mregs = qep->mregs;
146 void __iomem *gregs = qecp->gregs;
147 unsigned char *e = &qep->dev->dev_addr[0];
148 u32 tmp;
149 int i;
150
151 /* Shut it up. */
152 if (qe_stop(qep))
153 return -EAGAIN;
154
155 /* Setup initial rx/tx init block pointers. */
156 sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
157 sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
158
159 /* Enable/mask the various irq's. */
160 sbus_writel(0, cregs + CREG_RIMASK);
161 sbus_writel(1, cregs + CREG_TIMASK);
162
163 sbus_writel(0, cregs + CREG_QMASK);
164 sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
165
166 /* Setup the FIFO pointers into QEC local memory. */
167 tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
168 sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
169 sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
170
171 tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
172 sbus_readl(gregs + GLOB_RSIZE);
173 sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
174 sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
175
176 /* Clear the channel collision counter. */
177 sbus_writel(0, cregs + CREG_CCNT);
178
179 /* For 10baseT, inter frame space nor throttle seems to be necessary. */
180 sbus_writel(0, cregs + CREG_PIPG);
181
182 /* Now dork with the AMD MACE. */
183 sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
184 sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
185 sbus_writeb(0, mregs + MREGS_RXFCNTL);
186
187 /* The QEC dma's the rx'd packets from local memory out to main memory,
188 * and therefore it interrupts when the packet reception is "complete".
189 * So don't listen for the MACE talking about it.
190 */
191 sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
192 sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
193 sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
194 MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
195 mregs + MREGS_FCONFIG);
196
197 /* Only usable interface on QuadEther is twisted pair. */
198 sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
199
200 /* Tell MACE we are changing the ether address. */
201 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
202 mregs + MREGS_IACONFIG);
203 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
204 barrier();
205 sbus_writeb(e[0], mregs + MREGS_ETHADDR);
206 sbus_writeb(e[1], mregs + MREGS_ETHADDR);
207 sbus_writeb(e[2], mregs + MREGS_ETHADDR);
208 sbus_writeb(e[3], mregs + MREGS_ETHADDR);
209 sbus_writeb(e[4], mregs + MREGS_ETHADDR);
210 sbus_writeb(e[5], mregs + MREGS_ETHADDR);
211
212 /* Clear out the address filter. */
213 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
214 mregs + MREGS_IACONFIG);
215 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
216 barrier();
217 for (i = 0; i < 8; i++)
218 sbus_writeb(0, mregs + MREGS_FILTER);
219
220 /* Address changes are now complete. */
221 sbus_writeb(0, mregs + MREGS_IACONFIG);
222
223 qe_init_rings(qep);
224
225 /* Wait a little bit for the link to come up... */
226 mdelay(5);
227 if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
228 int tries = 50;
229
230 while (tries--) {
231 u8 tmp;
232
233 mdelay(5);
234 barrier();
235 tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
236 if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
237 break;
238 }
239 if (tries == 0)
240 printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
241 }
242
243 /* Missed packet counter is cleared on a read. */
244 sbus_readb(mregs + MREGS_MPCNT);
245
246 /* Reload multicast information, this will enable the receiver
247 * and transmitter.
248 */
249 qe_set_multicast(qep->dev);
250
251 /* QEC should now start to show interrupts. */
252 return 0;
253}
254
255/* Grrr, certain error conditions completely lock up the AMD MACE,
256 * so when we get these we _must_ reset the chip.
257 */
258static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
259{
260 struct net_device *dev = qep->dev;
261 int mace_hwbug_workaround = 0;
262
263 if (qe_status & CREG_STAT_EDEFER) {
264 printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
09f75cd7 265 dev->stats.tx_errors++;
1da177e4
LT		 266 }
267
268 if (qe_status & CREG_STAT_CLOSS) {
269 printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
09f75cd7
JG		 270 dev->stats.tx_errors++;
271 dev->stats.tx_carrier_errors++;
1da177e4
LT		 272 }
273
274 if (qe_status & CREG_STAT_ERETRIES) {
275 printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
09f75cd7 276 dev->stats.tx_errors++;
1da177e4
LT		 277 mace_hwbug_workaround = 1;
278 }
279
280 if (qe_status & CREG_STAT_LCOLL) {
281 printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
09f75cd7
JG		 282 dev->stats.tx_errors++;
283 dev->stats.collisions++;
1da177e4
LT		 284 mace_hwbug_workaround = 1;
285 }
286
287 if (qe_status & CREG_STAT_FUFLOW) {
288 printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
09f75cd7 289 dev->stats.tx_errors++;
1da177e4
LT		 290 mace_hwbug_workaround = 1;
291 }
292
293 if (qe_status & CREG_STAT_JERROR) {
294 printk(KERN_ERR "%s: Jabber error.\n", dev->name);
295 }
296
297 if (qe_status & CREG_STAT_BERROR) {
298 printk(KERN_ERR "%s: Babble error.\n", dev->name);
299 }
300
301 if (qe_status & CREG_STAT_CCOFLOW) {
09f75cd7
JG		 302 dev->stats.tx_errors += 256;
303 dev->stats.collisions += 256;
1da177e4
LT		 304 }
305
306 if (qe_status & CREG_STAT_TXDERROR) {
307 printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
09f75cd7
JG		 308 dev->stats.tx_errors++;
309 dev->stats.tx_aborted_errors++;
1da177e4
LT		 310 mace_hwbug_workaround = 1;
311 }
312
313 if (qe_status & CREG_STAT_TXLERR) {
314 printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
09f75cd7 315 dev->stats.tx_errors++;
1da177e4
LT		 316 mace_hwbug_workaround = 1;
317 }
318
319 if (qe_status & CREG_STAT_TXPERR) {
320 printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
09f75cd7
JG		 321 dev->stats.tx_errors++;
322 dev->stats.tx_aborted_errors++;
1da177e4
LT		 323 mace_hwbug_workaround = 1;
324 }
325
326 if (qe_status & CREG_STAT_TXSERR) {
327 printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
09f75cd7
JG		 328 dev->stats.tx_errors++;
329 dev->stats.tx_aborted_errors++;
1da177e4
LT		 330 mace_hwbug_workaround = 1;
331 }
332
333 if (qe_status & CREG_STAT_RCCOFLOW) {
09f75cd7
JG		 334 dev->stats.rx_errors += 256;
335 dev->stats.collisions += 256;
1da177e4
LT		 336 }
337
338 if (qe_status & CREG_STAT_RUOFLOW) {
09f75cd7
JG		 339 dev->stats.rx_errors += 256;
340 dev->stats.rx_over_errors += 256;
1da177e4
LT		 341 }
342
343 if (qe_status & CREG_STAT_MCOFLOW) {
09f75cd7
JG		 344 dev->stats.rx_errors += 256;
345 dev->stats.rx_missed_errors += 256;
1da177e4
LT		 346 }
347
348 if (qe_status & CREG_STAT_RXFOFLOW) {
349 printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
09f75cd7
JG		 350 dev->stats.rx_errors++;
351 dev->stats.rx_over_errors++;
1da177e4
LT		 352 }
353
354 if (qe_status & CREG_STAT_RLCOLL) {
355 printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
09f75cd7
JG		 356 dev->stats.rx_errors++;
357 dev->stats.collisions++;
1da177e4
LT		 358 }
359
360 if (qe_status & CREG_STAT_FCOFLOW) {
09f75cd7
JG		 361 dev->stats.rx_errors += 256;
362 dev->stats.rx_frame_errors += 256;
1da177e4
LT		 363 }
364
365 if (qe_status & CREG_STAT_CECOFLOW) {
09f75cd7
JG		 366 dev->stats.rx_errors += 256;
367 dev->stats.rx_crc_errors += 256;
1da177e4
LT		 368 }
369
370 if (qe_status & CREG_STAT_RXDROP) {
371 printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
09f75cd7
JG		 372 dev->stats.rx_errors++;
373 dev->stats.rx_dropped++;
374 dev->stats.rx_missed_errors++;
1da177e4
LT		 375 }
376
377 if (qe_status & CREG_STAT_RXSMALL) {
378 printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
09f75cd7
JG		 379 dev->stats.rx_errors++;
380 dev->stats.rx_length_errors++;
1da177e4
LT		 381 }
382
383 if (qe_status & CREG_STAT_RXLERR) {
384 printk(KERN_ERR "%s: Receive late error.\n", dev->name);
09f75cd7 385 dev->stats.rx_errors++;
1da177e4
LT		 386 mace_hwbug_workaround = 1;
387 }
388
389 if (qe_status & CREG_STAT_RXPERR) {
390 printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
09f75cd7
JG		 391 dev->stats.rx_errors++;
392 dev->stats.rx_missed_errors++;
1da177e4
LT		 393 mace_hwbug_workaround = 1;
394 }
395
396 if (qe_status & CREG_STAT_RXSERR) {
397 printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
09f75cd7
JG		 398 dev->stats.rx_errors++;
399 dev->stats.rx_missed_errors++;
1da177e4
LT		 400 mace_hwbug_workaround = 1;
401 }
402
403 if (mace_hwbug_workaround)
404 qe_init(qep, 1);
405 return mace_hwbug_workaround;
406}
407
408/* Per-QE receive interrupt service routine. Just like on the happy meal
409 * we receive directly into skb's with a small packet copy water mark.
410 */
411static void qe_rx(struct sunqe *qep)
412{
413 struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
09f75cd7 414 struct net_device *dev = qep->dev;
1da177e4
LT		 415 struct qe_rxd *this;
416 struct sunqe_buffers *qbufs = qep->buffers;
417 __u32 qbufs_dvma = qep->buffers_dvma;
418 int elem = qep->rx_new, drops = 0;
419 u32 flags;
420
421 this = &rxbase[elem];
422 while (!((flags = this->rx_flags) & RXD_OWN)) {
423 struct sk_buff *skb;
424 unsigned char *this_qbuf =
425 &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
426 __u32 this_qbuf_dvma = qbufs_dvma +
427 qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
428 struct qe_rxd *end_rxd =
429 &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
430 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
431
432 /* Check for errors. */
433 if (len < ETH_ZLEN) {
09f75cd7
JG		 434 dev->stats.rx_errors++;
435 dev->stats.rx_length_errors++;
436 dev->stats.rx_dropped++;
1da177e4
LT		 437 } else {
438 skb = dev_alloc_skb(len + 2);
439 if (skb == NULL) {
440 drops++;
09f75cd7 441 dev->stats.rx_dropped++;
1da177e4 442 } else {
1da177e4
LT		 443 skb_reserve(skb, 2);
444 skb_put(skb, len);
8c7b7faa
DM		 445 skb_copy_to_linear_data(skb, (unsigned char *) this_qbuf,
446 len);
1da177e4
LT		 447 skb->protocol = eth_type_trans(skb, qep->dev);
448 netif_rx(skb);
449 qep->dev->last_rx = jiffies;
09f75cd7
JG		 450 dev->stats.rx_packets++;
451 dev->stats.rx_bytes += len;
1da177e4
LT		 452 }
453 }
454 end_rxd->rx_addr = this_qbuf_dvma;
455 end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
6aa20a22 456
1da177e4
LT		 457 elem = NEXT_RX(elem);
458 this = &rxbase[elem];
459 }
460 qep->rx_new = elem;
461 if (drops)
462 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
463}
464
465static void qe_tx_reclaim(struct sunqe *qep);
466
467/* Interrupts for all QE's get filtered out via the QEC master controller,
468 * so we just run through each qe and check to see who is signaling
469 * and thus needs to be serviced.
470 */
7d12e780 471static irqreturn_t qec_interrupt(int irq, void *dev_id)
1da177e4 472{
c31f28e7 473 struct sunqec *qecp = dev_id;
1da177e4
LT		 474 u32 qec_status;
475 int channel = 0;
476
477 /* Latch the status now. */
478 qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
479 while (channel < 4) {
480 if (qec_status & 0xf) {
481 struct sunqe *qep = qecp->qes[channel];
482 u32 qe_status;
483
484 qe_status = sbus_readl(qep->qcregs + CREG_STAT);
485 if (qe_status & CREG_STAT_ERRORS) {
486 if (qe_is_bolixed(qep, qe_status))
487 goto next;
488 }
489 if (qe_status & CREG_STAT_RXIRQ)
490 qe_rx(qep);
491 if (netif_queue_stopped(qep->dev) &&
492 (qe_status & CREG_STAT_TXIRQ)) {
493 spin_lock(&qep->lock);
494 qe_tx_reclaim(qep);
495 if (TX_BUFFS_AVAIL(qep) > 0) {
496 /* Wake net queue and return to
497 * lazy tx reclaim.
498 */
499 netif_wake_queue(qep->dev);
500 sbus_writel(1, qep->qcregs + CREG_TIMASK);
501 }
502 spin_unlock(&qep->lock);
503 }
504 next:
505 ;
506 }
507 qec_status >>= 4;
508 channel++;
509 }
510
511 return IRQ_HANDLED;
512}
513
514static int qe_open(struct net_device *dev)
515{
516 struct sunqe *qep = (struct sunqe *) dev->priv;
517
518 qep->mconfig = (MREGS_MCONFIG_TXENAB |
519 MREGS_MCONFIG_RXENAB |
520 MREGS_MCONFIG_MBAENAB);
521 return qe_init(qep, 0);
522}
523
524static int qe_close(struct net_device *dev)
525{
526 struct sunqe *qep = (struct sunqe *) dev->priv;
527
528 qe_stop(qep);
529 return 0;
530}
531
532/* Reclaim TX'd frames from the ring. This must always run under
533 * the IRQ protected qep->lock.
534 */
535static void qe_tx_reclaim(struct sunqe *qep)
536{
537 struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
538 int elem = qep->tx_old;
539
540 while (elem != qep->tx_new) {
541 u32 flags = txbase[elem].tx_flags;
542
543 if (flags & TXD_OWN)
544 break;
545 elem = NEXT_TX(elem);
546 }
547 qep->tx_old = elem;
548}
549
550static void qe_tx_timeout(struct net_device *dev)
551{
552 struct sunqe *qep = (struct sunqe *) dev->priv;
553 int tx_full;
554
555 spin_lock_irq(&qep->lock);
556
557 /* Try to reclaim, if that frees up some tx
558 * entries, we're fine.
559 */
560 qe_tx_reclaim(qep);
561 tx_full = TX_BUFFS_AVAIL(qep) <= 0;
562
563 spin_unlock_irq(&qep->lock);
564
565 if (! tx_full)
566 goto out;
567
568 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
569 qe_init(qep, 1);
570
571out:
572 netif_wake_queue(dev);
573}
574
575/* Get a packet queued to go onto the wire. */
576static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
577{
578 struct sunqe *qep = (struct sunqe *) dev->priv;
579 struct sunqe_buffers *qbufs = qep->buffers;
580 __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
581 unsigned char *txbuf;
582 int len, entry;
583
584 spin_lock_irq(&qep->lock);
585
586 qe_tx_reclaim(qep);
587
588 len = skb->len;
589 entry = qep->tx_new;
590
591 txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
592 txbuf_dvma = qbufs_dvma +
593 qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
594
595 /* Avoid a race... */
596 qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
597
d626f62b 598 skb_copy_from_linear_data(skb, txbuf, len);
1da177e4
LT		 599
600 qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
601 qep->qe_block->qe_txd[entry].tx_flags =
602 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
603 qep->tx_new = NEXT_TX(entry);
604
605 /* Get it going. */
606 dev->trans_start = jiffies;
607 sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
608
09f75cd7
JG		 609 dev->stats.tx_packets++;
610 dev->stats.tx_bytes += len;
1da177e4
LT		 611
612 if (TX_BUFFS_AVAIL(qep) <= 0) {
613 /* Halt the net queue and enable tx interrupts.
614 * When the tx queue empties the tx irq handler
615 * will wake up the queue and return us back to
616 * the lazy tx reclaim scheme.
617 */
618 netif_stop_queue(dev);
619 sbus_writel(0, qep->qcregs + CREG_TIMASK);
620 }
621 spin_unlock_irq(&qep->lock);
622
623 dev_kfree_skb(skb);
624
625 return 0;
626}
627
1da177e4
LT		 628static void qe_set_multicast(struct net_device *dev)
629{
630 struct sunqe *qep = (struct sunqe *) dev->priv;
631 struct dev_mc_list *dmi = dev->mc_list;
632 u8 new_mconfig = qep->mconfig;
633 char *addrs;
634 int i;
635 u32 crc;
636
637 /* Lock out others. */
638 netif_stop_queue(dev);
639
640 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
641 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
642 qep->mregs + MREGS_IACONFIG);
643 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
644 barrier();
645 for (i = 0; i < 8; i++)
646 sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
647 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
648 } else if (dev->flags & IFF_PROMISC) {
649 new_mconfig |= MREGS_MCONFIG_PROMISC;
650 } else {
651 u16 hash_table[4];
652 u8 *hbytes = (unsigned char *) &hash_table[0];
653
654 for (i = 0; i < 4; i++)
655 hash_table[i] = 0;
656
657 for (i = 0; i < dev->mc_count; i++) {
658 addrs = dmi->dmi_addr;
659 dmi = dmi->next;
660
661 if (!(*addrs & 1))
662 continue;
663 crc = ether_crc_le(6, addrs);
664 crc >>= 26;
665 hash_table[crc >> 4] |= 1 << (crc & 0xf);
666 }
667 /* Program the qe with the new filter value. */
668 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
669 qep->mregs + MREGS_IACONFIG);
670 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
671 barrier();
672 for (i = 0; i < 8; i++) {
673 u8 tmp = *hbytes++;
674 sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
675 }
676 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
677 }
678
679 /* Any change of the logical address filter, the physical address,
680 * or enabling/disabling promiscuous mode causes the MACE to disable
681 * the receiver. So we must re-enable them here or else the MACE
682 * refuses to listen to anything on the network. Sheesh, took
683 * me a day or two to find this bug.
684 */
685 qep->mconfig = new_mconfig;
686 sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
687
688 /* Let us get going again. */
689 netif_wake_queue(dev);
690}
691
692/* Ethtool support... */
693static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
694{
8e912b33 695 const struct linux_prom_registers *regs;
1da177e4 696 struct sunqe *qep = dev->priv;
8e912b33 697 struct of_device *op;
1da177e4
LT		 698
699 strcpy(info->driver, "sunqe");
700 strcpy(info->version, "3.0");
8e912b33
DM		 701
702 op = qep->op;
703 regs = of_get_property(op->node, "reg", NULL);
704 if (regs)
705 sprintf(info->bus_info, "SBUS:%d", regs->which_io);
706
1da177e4
LT		 707}
708
709static u32 qe_get_link(struct net_device *dev)
710{
711 struct sunqe *qep = dev->priv;
712 void __iomem *mregs = qep->mregs;
713 u8 phyconfig;
714
715 spin_lock_irq(&qep->lock);
716 phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
717 spin_unlock_irq(&qep->lock);
718
719 return (phyconfig & MREGS_PHYCONFIG_LSTAT);
720}
721
7282d491 722static const struct ethtool_ops qe_ethtool_ops = {
1da177e4
LT		 723 .get_drvinfo = qe_get_drvinfo,
724 .get_link = qe_get_link,
725};
726
727/* This is only called once at boot time for each card probed. */
8e912b33 728static void qec_init_once(struct sunqec *qecp, struct of_device *op)
1da177e4
LT		 729{
730 u8 bsizes = qecp->qec_bursts;
731
63237eeb 732 if (sbus_can_burst64() && (bsizes & DMA_BURST64)) {
1da177e4
LT		 733 sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
734 } else if (bsizes & DMA_BURST32) {
735 sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
736 } else {
737 sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
738 }
739
740 /* Packetsize only used in 100baseT BigMAC configurations,
741 * set it to zero just to be on the safe side.
742 */
743 sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
744
745 /* Set the local memsize register, divided up to one piece per QE channel. */
8e912b33 746 sbus_writel((resource_size(&op->resource[1]) >> 2),
1da177e4
LT		 747 qecp->gregs + GLOB_MSIZE);
748
749 /* Divide up the local QEC memory amongst the 4 QE receiver and
750 * transmitter FIFOs. Basically it is (total / 2 / num_channels).
751 */
8e912b33 752 sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
1da177e4 753 qecp->gregs + GLOB_TSIZE);
8e912b33 754 sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
1da177e4
LT		 755 qecp->gregs + GLOB_RSIZE);
756}
757
3edd76ca 758static u8 __devinit qec_get_burst(struct device_node *dp)
1da177e4 759{
1da177e4 760 u8 bsizes, bsizes_more;
1da177e4 761
ecba38ab
DM		 762 /* Find and set the burst sizes for the QEC, since it
763 * does the actual dma for all 4 channels.
764 */
765 bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
766 bsizes &= 0xff;
767 bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
1da177e4 768
ecba38ab
DM		 769 if (bsizes_more != 0xff)
770 bsizes &= bsizes_more;
771 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
772 (bsizes & DMA_BURST32)==0)
773 bsizes = (DMA_BURST32 - 1);
1da177e4 774
ecba38ab
DM		 775 return bsizes;
776}
1da177e4 777
8e912b33 778static struct sunqec * __devinit get_qec(struct of_device *child)
ecba38ab 779{
8e912b33 780 struct of_device *op = to_of_device(child->dev.parent);
ecba38ab 781 struct sunqec *qecp;
1da177e4 782
8e912b33 783 qecp = dev_get_drvdata(&op->dev);
ecba38ab
DM		 784 if (!qecp) {
785 qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
786 if (qecp) {
787 u32 ctrl;
788
8e912b33
DM		 789 qecp->op = op;
790 qecp->gregs = of_ioremap(&op->resource[0], 0,
791 GLOB_REG_SIZE,
792 "QEC Global Registers");
ecba38ab
DM		 793 if (!qecp->gregs)
794 goto fail;
795
796 /* Make sure the QEC is in MACE mode. */
797 ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
798 ctrl &= 0xf0000000;
799 if (ctrl != GLOB_CTRL_MMODE) {
800 printk(KERN_ERR "qec: Not in MACE mode!\n");
801 goto fail;
802 }
1da177e4 803
ecba38ab
DM		 804 if (qec_global_reset(qecp->gregs))
805 goto fail;
1da177e4 806
8e912b33 807 qecp->qec_bursts = qec_get_burst(op->node);
1da177e4 808
8e912b33 809 qec_init_once(qecp, op);
1da177e4 810
8e912b33 811 if (request_irq(op->irqs[0], &qec_interrupt,
1fb9df5d 812 IRQF_SHARED, "qec", (void *) qecp)) {
ecba38ab
DM		 813 printk(KERN_ERR "qec: Can't register irq.\n");
814 goto fail;
815 }
1da177e4 816
8e912b33
DM		 817 dev_set_drvdata(&op->dev, qecp);
818
ecba38ab
DM		 819 qecp->next_module = root_qec_dev;
820 root_qec_dev = qecp;
821 }
1da177e4
LT		 822 }
823
ecba38ab 824 return qecp;
1da177e4 825
ecba38ab
DM		 826fail:
827 if (qecp->gregs)
8e912b33 828 of_iounmap(&op->resource[0], qecp->gregs, GLOB_REG_SIZE);
ecba38ab
DM		 829 kfree(qecp);
830 return NULL;
831}
1da177e4 832
8e912b33 833static int __devinit qec_ether_init(struct of_device *op)
ecba38ab
DM		 834{
835 static unsigned version_printed;
836 struct net_device *dev;
ecba38ab 837 struct sunqec *qecp;
8e912b33 838 struct sunqe *qe;
ecba38ab 839 int i, res;
1da177e4 840
ecba38ab
DM		 841 if (version_printed++ == 0)
842 printk(KERN_INFO "%s", version);
1da177e4 843
ecba38ab
DM		 844 dev = alloc_etherdev(sizeof(struct sunqe));
845 if (!dev)
846 return -ENOMEM;
1da177e4 847
d0dc1129
MN		 848 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
849
ecba38ab 850 qe = netdev_priv(dev);
1da177e4 851
8e912b33
DM		 852 res = -ENODEV;
853
854 i = of_getintprop_default(op->node, "channel#", -1);
855 if (i == -1)
856 goto fail;
ecba38ab
DM		 857 qe->channel = i;
858 spin_lock_init(&qe->lock);
6aa20a22 859
8e912b33 860 qecp = get_qec(op);
ecba38ab
DM		 861 if (!qecp)
862 goto fail;
1da177e4 863
ecba38ab
DM		 864 qecp->qes[qe->channel] = qe;
865 qe->dev = dev;
866 qe->parent = qecp;
8e912b33 867 qe->op = op;
1da177e4 868
ecba38ab 869 res = -ENOMEM;
8e912b33
DM		 870 qe->qcregs = of_ioremap(&op->resource[0], 0,
871 CREG_REG_SIZE, "QEC Channel Registers");
ecba38ab
DM		 872 if (!qe->qcregs) {
873 printk(KERN_ERR "qe: Cannot map channel registers.\n");
874 goto fail;
1da177e4
LT		 875 }
876
8e912b33
DM		 877 qe->mregs = of_ioremap(&op->resource[1], 0,
878 MREGS_REG_SIZE, "QE MACE Registers");
ecba38ab
DM		 879 if (!qe->mregs) {
880 printk(KERN_ERR "qe: Cannot map MACE registers.\n");
881 goto fail;
1da177e4
LT		 882 }
883
8e912b33 884 qe->qe_block = dma_alloc_coherent(&op->dev, PAGE_SIZE,
738f2b7b 885 &qe->qblock_dvma, GFP_ATOMIC);
8e912b33 886 qe->buffers = dma_alloc_coherent(&op->dev, sizeof(struct sunqe_buffers),
738f2b7b 887 &qe->buffers_dvma, GFP_ATOMIC);
ecba38ab
DM		 888 if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
889 qe->buffers == NULL || qe->buffers_dvma == 0)
890 goto fail;
891
892 /* Stop this QE. */
893 qe_stop(qe);
894
8e912b33 895 SET_NETDEV_DEV(dev, &op->dev);
ecba38ab
DM		 896
897 dev->open = qe_open;
898 dev->stop = qe_close;
899 dev->hard_start_xmit = qe_start_xmit;
ecba38ab
DM		 900 dev->set_multicast_list = qe_set_multicast;
901 dev->tx_timeout = qe_tx_timeout;
902 dev->watchdog_timeo = 5*HZ;
8e912b33 903 dev->irq = op->irqs[0];
ecba38ab
DM		 904 dev->dma = 0;
905 dev->ethtool_ops = &qe_ethtool_ops;
906
907 res = register_netdev(dev);
908 if (res)
909 goto fail;
910
8e912b33 911 dev_set_drvdata(&op->dev, qe);
ecba38ab
DM		 912
913 printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel);
914 for (i = 0; i < 6; i++)
915 printk ("%2.2x%c",
916 dev->dev_addr[i],
917 i == 5 ? ' ': ':');
918 printk("\n");
1da177e4 919
1da177e4
LT		 920
921 return 0;
922
ecba38ab
DM		 923fail:
924 if (qe->qcregs)
8e912b33 925 of_iounmap(&op->resource[0], qe->qcregs, CREG_REG_SIZE);
ecba38ab 926 if (qe->mregs)
8e912b33 927 of_iounmap(&op->resource[1], qe->mregs, MREGS_REG_SIZE);
ecba38ab 928 if (qe->qe_block)
8e912b33
DM		 929 dma_free_coherent(&op->dev, PAGE_SIZE,
930 qe->qe_block, qe->qblock_dvma);
ecba38ab 931 if (qe->buffers)
8e912b33 932 dma_free_coherent(&op->dev,
738f2b7b
DM		 933 sizeof(struct sunqe_buffers),
934 qe->buffers,
935 qe->buffers_dvma);
ecba38ab
DM		 936
937 free_netdev(dev);
938
1da177e4
LT		 939 return res;
940}
941
8e912b33 942static int __devinit qec_sbus_probe(struct of_device *op, const struct of_device_id *match)
1da177e4 943{
8e912b33 944 return qec_ether_init(op);
1da177e4
LT		 945}
946
8e912b33 947static int __devexit qec_sbus_remove(struct of_device *op)
1da177e4 948{
8e912b33 949 struct sunqe *qp = dev_get_drvdata(&op->dev);
ecba38ab
DM		 950 struct net_device *net_dev = qp->dev;
951
d0dc1129 952 unregister_netdev(net_dev);
ecba38ab 953
8e912b33
DM		 954 of_iounmap(&op->resource[0], qp->qcregs, CREG_REG_SIZE);
955 of_iounmap(&op->resource[1], qp->mregs, MREGS_REG_SIZE);
956 dma_free_coherent(&op->dev, PAGE_SIZE,
957 qp->qe_block, qp->qblock_dvma);
958 dma_free_coherent(&op->dev, sizeof(struct sunqe_buffers),
959 qp->buffers, qp->buffers_dvma);
ecba38ab
DM		 960
961 free_netdev(net_dev);
962
8e912b33 963 dev_set_drvdata(&op->dev, NULL);
ecba38ab 964
1da177e4
LT		 965 return 0;
966}
967
fd098316 968static const struct of_device_id qec_sbus_match[] = {
ecba38ab
DM		 969 {
970 .name = "qe",
971 },
972 {},
973};
974
975MODULE_DEVICE_TABLE(of, qec_sbus_match);
976
977static struct of_platform_driver qec_sbus_driver = {
978 .name = "qec",
979 .match_table = qec_sbus_match,
980 .probe = qec_sbus_probe,
981 .remove = __devexit_p(qec_sbus_remove),
982};
983
984static int __init qec_init(void)
985{
8e912b33 986 return of_register_driver(&qec_sbus_driver, &of_bus_type);
ecba38ab
DM		 987}
988
989static void __exit qec_exit(void)
1da177e4 990{
ecba38ab 991 of_unregister_driver(&qec_sbus_driver);
1da177e4
LT		 992
993 while (root_qec_dev) {
ecba38ab 994 struct sunqec *next = root_qec_dev->next_module;
8e912b33 995 struct of_device *op = root_qec_dev->op;
ecba38ab 996
8e912b33
DM		 997 free_irq(op->irqs[0], (void *) root_qec_dev);
998 of_iounmap(&op->resource[0], root_qec_dev->gregs,
999 GLOB_REG_SIZE);
1da177e4 1000 kfree(root_qec_dev);
ecba38ab
DM		 1001
1002 root_qec_dev = next;
1da177e4
LT		 1003 }
1004}
1005
ecba38ab
DM		 1006module_init(qec_init);
1007module_exit(qec_exit);
kernel source for telekom puls (alcatel/mediatek)