Commit | Line | Data |
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ecba38ab | 1 | /* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver. |
1da177e4 LT |
2 | * Once again I am out to prove that every ethernet |
3 | * controller out there can be most efficiently programmed | |
4 | * if you make it look like a LANCE. | |
5 | * | |
ecba38ab | 6 | * Copyright (C) 1996, 1999, 2003, 2006 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/types.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/fcntl.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/in.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/crc32.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/skbuff.h> | |
25 | #include <linux/ethtool.h> | |
26 | #include <linux/bitops.h> | |
27 | ||
28 | #include <asm/system.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/dma.h> | |
31 | #include <asm/byteorder.h> | |
32 | #include <asm/idprom.h> | |
33 | #include <asm/sbus.h> | |
34 | #include <asm/openprom.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/auxio.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/irq.h> | |
39 | ||
40 | #include "sunqe.h" | |
41 | ||
10158286 | 42 | #define DRV_NAME "sunqe" |
ecba38ab DM |
43 | #define DRV_VERSION "4.0" |
44 | #define DRV_RELDATE "June 23, 2006" | |
45 | #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)" | |
10158286 TC |
46 | |
47 | static char version[] = | |
48 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; | |
49 | ||
50 | MODULE_VERSION(DRV_VERSION); | |
51 | MODULE_AUTHOR(DRV_AUTHOR); | |
52 | MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver"); | |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
1da177e4 LT |
55 | static struct sunqec *root_qec_dev; |
56 | ||
57 | static void qe_set_multicast(struct net_device *dev); | |
58 | ||
59 | #define QEC_RESET_TRIES 200 | |
60 | ||
61 | static inline int qec_global_reset(void __iomem *gregs) | |
62 | { | |
63 | int tries = QEC_RESET_TRIES; | |
64 | ||
65 | sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL); | |
66 | while (--tries) { | |
67 | u32 tmp = sbus_readl(gregs + GLOB_CTRL); | |
68 | if (tmp & GLOB_CTRL_RESET) { | |
69 | udelay(20); | |
70 | continue; | |
71 | } | |
72 | break; | |
73 | } | |
74 | if (tries) | |
75 | return 0; | |
76 | printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n"); | |
77 | return -1; | |
78 | } | |
79 | ||
80 | #define MACE_RESET_RETRIES 200 | |
81 | #define QE_RESET_RETRIES 200 | |
82 | ||
83 | static inline int qe_stop(struct sunqe *qep) | |
84 | { | |
85 | void __iomem *cregs = qep->qcregs; | |
86 | void __iomem *mregs = qep->mregs; | |
87 | int tries; | |
88 | ||
89 | /* Reset the MACE, then the QEC channel. */ | |
90 | sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG); | |
91 | tries = MACE_RESET_RETRIES; | |
92 | while (--tries) { | |
93 | u8 tmp = sbus_readb(mregs + MREGS_BCONFIG); | |
94 | if (tmp & MREGS_BCONFIG_RESET) { | |
95 | udelay(20); | |
96 | continue; | |
97 | } | |
98 | break; | |
99 | } | |
100 | if (!tries) { | |
101 | printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n"); | |
102 | return -1; | |
103 | } | |
104 | ||
105 | sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL); | |
106 | tries = QE_RESET_RETRIES; | |
107 | while (--tries) { | |
108 | u32 tmp = sbus_readl(cregs + CREG_CTRL); | |
109 | if (tmp & CREG_CTRL_RESET) { | |
110 | udelay(20); | |
111 | continue; | |
112 | } | |
113 | break; | |
114 | } | |
115 | if (!tries) { | |
116 | printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n"); | |
117 | return -1; | |
118 | } | |
119 | return 0; | |
120 | } | |
121 | ||
122 | static void qe_init_rings(struct sunqe *qep) | |
123 | { | |
124 | struct qe_init_block *qb = qep->qe_block; | |
125 | struct sunqe_buffers *qbufs = qep->buffers; | |
126 | __u32 qbufs_dvma = qep->buffers_dvma; | |
127 | int i; | |
128 | ||
129 | qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0; | |
130 | memset(qb, 0, sizeof(struct qe_init_block)); | |
131 | memset(qbufs, 0, sizeof(struct sunqe_buffers)); | |
132 | for (i = 0; i < RX_RING_SIZE; i++) { | |
133 | qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i); | |
134 | qb->qe_rxd[i].rx_flags = | |
135 | (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH)); | |
136 | } | |
137 | } | |
138 | ||
139 | static int qe_init(struct sunqe *qep, int from_irq) | |
140 | { | |
141 | struct sunqec *qecp = qep->parent; | |
142 | void __iomem *cregs = qep->qcregs; | |
143 | void __iomem *mregs = qep->mregs; | |
144 | void __iomem *gregs = qecp->gregs; | |
145 | unsigned char *e = &qep->dev->dev_addr[0]; | |
146 | u32 tmp; | |
147 | int i; | |
148 | ||
149 | /* Shut it up. */ | |
150 | if (qe_stop(qep)) | |
151 | return -EAGAIN; | |
152 | ||
153 | /* Setup initial rx/tx init block pointers. */ | |
154 | sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS); | |
155 | sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS); | |
156 | ||
157 | /* Enable/mask the various irq's. */ | |
158 | sbus_writel(0, cregs + CREG_RIMASK); | |
159 | sbus_writel(1, cregs + CREG_TIMASK); | |
160 | ||
161 | sbus_writel(0, cregs + CREG_QMASK); | |
162 | sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK); | |
163 | ||
164 | /* Setup the FIFO pointers into QEC local memory. */ | |
165 | tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE); | |
166 | sbus_writel(tmp, cregs + CREG_RXRBUFPTR); | |
167 | sbus_writel(tmp, cregs + CREG_RXWBUFPTR); | |
168 | ||
169 | tmp = sbus_readl(cregs + CREG_RXRBUFPTR) + | |
170 | sbus_readl(gregs + GLOB_RSIZE); | |
171 | sbus_writel(tmp, cregs + CREG_TXRBUFPTR); | |
172 | sbus_writel(tmp, cregs + CREG_TXWBUFPTR); | |
173 | ||
174 | /* Clear the channel collision counter. */ | |
175 | sbus_writel(0, cregs + CREG_CCNT); | |
176 | ||
177 | /* For 10baseT, inter frame space nor throttle seems to be necessary. */ | |
178 | sbus_writel(0, cregs + CREG_PIPG); | |
179 | ||
180 | /* Now dork with the AMD MACE. */ | |
181 | sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG); | |
182 | sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL); | |
183 | sbus_writeb(0, mregs + MREGS_RXFCNTL); | |
184 | ||
185 | /* The QEC dma's the rx'd packets from local memory out to main memory, | |
186 | * and therefore it interrupts when the packet reception is "complete". | |
187 | * So don't listen for the MACE talking about it. | |
188 | */ | |
189 | sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK); | |
190 | sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG); | |
191 | sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 | | |
192 | MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU), | |
193 | mregs + MREGS_FCONFIG); | |
194 | ||
195 | /* Only usable interface on QuadEther is twisted pair. */ | |
196 | sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG); | |
197 | ||
198 | /* Tell MACE we are changing the ether address. */ | |
199 | sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET, | |
200 | mregs + MREGS_IACONFIG); | |
201 | while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0) | |
202 | barrier(); | |
203 | sbus_writeb(e[0], mregs + MREGS_ETHADDR); | |
204 | sbus_writeb(e[1], mregs + MREGS_ETHADDR); | |
205 | sbus_writeb(e[2], mregs + MREGS_ETHADDR); | |
206 | sbus_writeb(e[3], mregs + MREGS_ETHADDR); | |
207 | sbus_writeb(e[4], mregs + MREGS_ETHADDR); | |
208 | sbus_writeb(e[5], mregs + MREGS_ETHADDR); | |
209 | ||
210 | /* Clear out the address filter. */ | |
211 | sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET, | |
212 | mregs + MREGS_IACONFIG); | |
213 | while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0) | |
214 | barrier(); | |
215 | for (i = 0; i < 8; i++) | |
216 | sbus_writeb(0, mregs + MREGS_FILTER); | |
217 | ||
218 | /* Address changes are now complete. */ | |
219 | sbus_writeb(0, mregs + MREGS_IACONFIG); | |
220 | ||
221 | qe_init_rings(qep); | |
222 | ||
223 | /* Wait a little bit for the link to come up... */ | |
224 | mdelay(5); | |
225 | if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) { | |
226 | int tries = 50; | |
227 | ||
228 | while (tries--) { | |
229 | u8 tmp; | |
230 | ||
231 | mdelay(5); | |
232 | barrier(); | |
233 | tmp = sbus_readb(mregs + MREGS_PHYCONFIG); | |
234 | if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0) | |
235 | break; | |
236 | } | |
237 | if (tries == 0) | |
238 | printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name); | |
239 | } | |
240 | ||
241 | /* Missed packet counter is cleared on a read. */ | |
242 | sbus_readb(mregs + MREGS_MPCNT); | |
243 | ||
244 | /* Reload multicast information, this will enable the receiver | |
245 | * and transmitter. | |
246 | */ | |
247 | qe_set_multicast(qep->dev); | |
248 | ||
249 | /* QEC should now start to show interrupts. */ | |
250 | return 0; | |
251 | } | |
252 | ||
253 | /* Grrr, certain error conditions completely lock up the AMD MACE, | |
254 | * so when we get these we _must_ reset the chip. | |
255 | */ | |
256 | static int qe_is_bolixed(struct sunqe *qep, u32 qe_status) | |
257 | { | |
258 | struct net_device *dev = qep->dev; | |
259 | int mace_hwbug_workaround = 0; | |
260 | ||
261 | if (qe_status & CREG_STAT_EDEFER) { | |
262 | printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name); | |
263 | qep->net_stats.tx_errors++; | |
264 | } | |
265 | ||
266 | if (qe_status & CREG_STAT_CLOSS) { | |
267 | printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name); | |
268 | qep->net_stats.tx_errors++; | |
269 | qep->net_stats.tx_carrier_errors++; | |
270 | } | |
271 | ||
272 | if (qe_status & CREG_STAT_ERETRIES) { | |
273 | printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name); | |
274 | qep->net_stats.tx_errors++; | |
275 | mace_hwbug_workaround = 1; | |
276 | } | |
277 | ||
278 | if (qe_status & CREG_STAT_LCOLL) { | |
279 | printk(KERN_ERR "%s: Late transmit collision.\n", dev->name); | |
280 | qep->net_stats.tx_errors++; | |
281 | qep->net_stats.collisions++; | |
282 | mace_hwbug_workaround = 1; | |
283 | } | |
284 | ||
285 | if (qe_status & CREG_STAT_FUFLOW) { | |
286 | printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name); | |
287 | qep->net_stats.tx_errors++; | |
288 | mace_hwbug_workaround = 1; | |
289 | } | |
290 | ||
291 | if (qe_status & CREG_STAT_JERROR) { | |
292 | printk(KERN_ERR "%s: Jabber error.\n", dev->name); | |
293 | } | |
294 | ||
295 | if (qe_status & CREG_STAT_BERROR) { | |
296 | printk(KERN_ERR "%s: Babble error.\n", dev->name); | |
297 | } | |
298 | ||
299 | if (qe_status & CREG_STAT_CCOFLOW) { | |
300 | qep->net_stats.tx_errors += 256; | |
301 | qep->net_stats.collisions += 256; | |
302 | } | |
303 | ||
304 | if (qe_status & CREG_STAT_TXDERROR) { | |
305 | printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name); | |
306 | qep->net_stats.tx_errors++; | |
307 | qep->net_stats.tx_aborted_errors++; | |
308 | mace_hwbug_workaround = 1; | |
309 | } | |
310 | ||
311 | if (qe_status & CREG_STAT_TXLERR) { | |
312 | printk(KERN_ERR "%s: Transmit late error.\n", dev->name); | |
313 | qep->net_stats.tx_errors++; | |
314 | mace_hwbug_workaround = 1; | |
315 | } | |
316 | ||
317 | if (qe_status & CREG_STAT_TXPERR) { | |
318 | printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name); | |
319 | qep->net_stats.tx_errors++; | |
320 | qep->net_stats.tx_aborted_errors++; | |
321 | mace_hwbug_workaround = 1; | |
322 | } | |
323 | ||
324 | if (qe_status & CREG_STAT_TXSERR) { | |
325 | printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name); | |
326 | qep->net_stats.tx_errors++; | |
327 | qep->net_stats.tx_aborted_errors++; | |
328 | mace_hwbug_workaround = 1; | |
329 | } | |
330 | ||
331 | if (qe_status & CREG_STAT_RCCOFLOW) { | |
332 | qep->net_stats.rx_errors += 256; | |
333 | qep->net_stats.collisions += 256; | |
334 | } | |
335 | ||
336 | if (qe_status & CREG_STAT_RUOFLOW) { | |
337 | qep->net_stats.rx_errors += 256; | |
338 | qep->net_stats.rx_over_errors += 256; | |
339 | } | |
340 | ||
341 | if (qe_status & CREG_STAT_MCOFLOW) { | |
342 | qep->net_stats.rx_errors += 256; | |
343 | qep->net_stats.rx_missed_errors += 256; | |
344 | } | |
345 | ||
346 | if (qe_status & CREG_STAT_RXFOFLOW) { | |
347 | printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name); | |
348 | qep->net_stats.rx_errors++; | |
349 | qep->net_stats.rx_over_errors++; | |
350 | } | |
351 | ||
352 | if (qe_status & CREG_STAT_RLCOLL) { | |
353 | printk(KERN_ERR "%s: Late receive collision.\n", dev->name); | |
354 | qep->net_stats.rx_errors++; | |
355 | qep->net_stats.collisions++; | |
356 | } | |
357 | ||
358 | if (qe_status & CREG_STAT_FCOFLOW) { | |
359 | qep->net_stats.rx_errors += 256; | |
360 | qep->net_stats.rx_frame_errors += 256; | |
361 | } | |
362 | ||
363 | if (qe_status & CREG_STAT_CECOFLOW) { | |
364 | qep->net_stats.rx_errors += 256; | |
365 | qep->net_stats.rx_crc_errors += 256; | |
366 | } | |
367 | ||
368 | if (qe_status & CREG_STAT_RXDROP) { | |
369 | printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name); | |
370 | qep->net_stats.rx_errors++; | |
371 | qep->net_stats.rx_dropped++; | |
372 | qep->net_stats.rx_missed_errors++; | |
373 | } | |
374 | ||
375 | if (qe_status & CREG_STAT_RXSMALL) { | |
376 | printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name); | |
377 | qep->net_stats.rx_errors++; | |
378 | qep->net_stats.rx_length_errors++; | |
379 | } | |
380 | ||
381 | if (qe_status & CREG_STAT_RXLERR) { | |
382 | printk(KERN_ERR "%s: Receive late error.\n", dev->name); | |
383 | qep->net_stats.rx_errors++; | |
384 | mace_hwbug_workaround = 1; | |
385 | } | |
386 | ||
387 | if (qe_status & CREG_STAT_RXPERR) { | |
388 | printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name); | |
389 | qep->net_stats.rx_errors++; | |
390 | qep->net_stats.rx_missed_errors++; | |
391 | mace_hwbug_workaround = 1; | |
392 | } | |
393 | ||
394 | if (qe_status & CREG_STAT_RXSERR) { | |
395 | printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name); | |
396 | qep->net_stats.rx_errors++; | |
397 | qep->net_stats.rx_missed_errors++; | |
398 | mace_hwbug_workaround = 1; | |
399 | } | |
400 | ||
401 | if (mace_hwbug_workaround) | |
402 | qe_init(qep, 1); | |
403 | return mace_hwbug_workaround; | |
404 | } | |
405 | ||
406 | /* Per-QE receive interrupt service routine. Just like on the happy meal | |
407 | * we receive directly into skb's with a small packet copy water mark. | |
408 | */ | |
409 | static void qe_rx(struct sunqe *qep) | |
410 | { | |
411 | struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0]; | |
412 | struct qe_rxd *this; | |
413 | struct sunqe_buffers *qbufs = qep->buffers; | |
414 | __u32 qbufs_dvma = qep->buffers_dvma; | |
415 | int elem = qep->rx_new, drops = 0; | |
416 | u32 flags; | |
417 | ||
418 | this = &rxbase[elem]; | |
419 | while (!((flags = this->rx_flags) & RXD_OWN)) { | |
420 | struct sk_buff *skb; | |
421 | unsigned char *this_qbuf = | |
422 | &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0]; | |
423 | __u32 this_qbuf_dvma = qbufs_dvma + | |
424 | qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1))); | |
425 | struct qe_rxd *end_rxd = | |
426 | &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)]; | |
427 | int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */ | |
428 | ||
429 | /* Check for errors. */ | |
430 | if (len < ETH_ZLEN) { | |
431 | qep->net_stats.rx_errors++; | |
432 | qep->net_stats.rx_length_errors++; | |
433 | qep->net_stats.rx_dropped++; | |
434 | } else { | |
435 | skb = dev_alloc_skb(len + 2); | |
436 | if (skb == NULL) { | |
437 | drops++; | |
438 | qep->net_stats.rx_dropped++; | |
439 | } else { | |
1da177e4 LT |
440 | skb_reserve(skb, 2); |
441 | skb_put(skb, len); | |
8c7b7faa DM |
442 | skb_copy_to_linear_data(skb, (unsigned char *) this_qbuf, |
443 | len); | |
1da177e4 LT |
444 | skb->protocol = eth_type_trans(skb, qep->dev); |
445 | netif_rx(skb); | |
446 | qep->dev->last_rx = jiffies; | |
447 | qep->net_stats.rx_packets++; | |
448 | qep->net_stats.rx_bytes += len; | |
449 | } | |
450 | } | |
451 | end_rxd->rx_addr = this_qbuf_dvma; | |
452 | end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH)); | |
6aa20a22 | 453 | |
1da177e4 LT |
454 | elem = NEXT_RX(elem); |
455 | this = &rxbase[elem]; | |
456 | } | |
457 | qep->rx_new = elem; | |
458 | if (drops) | |
459 | printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name); | |
460 | } | |
461 | ||
462 | static void qe_tx_reclaim(struct sunqe *qep); | |
463 | ||
464 | /* Interrupts for all QE's get filtered out via the QEC master controller, | |
465 | * so we just run through each qe and check to see who is signaling | |
466 | * and thus needs to be serviced. | |
467 | */ | |
7d12e780 | 468 | static irqreturn_t qec_interrupt(int irq, void *dev_id) |
1da177e4 | 469 | { |
c31f28e7 | 470 | struct sunqec *qecp = dev_id; |
1da177e4 LT |
471 | u32 qec_status; |
472 | int channel = 0; | |
473 | ||
474 | /* Latch the status now. */ | |
475 | qec_status = sbus_readl(qecp->gregs + GLOB_STAT); | |
476 | while (channel < 4) { | |
477 | if (qec_status & 0xf) { | |
478 | struct sunqe *qep = qecp->qes[channel]; | |
479 | u32 qe_status; | |
480 | ||
481 | qe_status = sbus_readl(qep->qcregs + CREG_STAT); | |
482 | if (qe_status & CREG_STAT_ERRORS) { | |
483 | if (qe_is_bolixed(qep, qe_status)) | |
484 | goto next; | |
485 | } | |
486 | if (qe_status & CREG_STAT_RXIRQ) | |
487 | qe_rx(qep); | |
488 | if (netif_queue_stopped(qep->dev) && | |
489 | (qe_status & CREG_STAT_TXIRQ)) { | |
490 | spin_lock(&qep->lock); | |
491 | qe_tx_reclaim(qep); | |
492 | if (TX_BUFFS_AVAIL(qep) > 0) { | |
493 | /* Wake net queue and return to | |
494 | * lazy tx reclaim. | |
495 | */ | |
496 | netif_wake_queue(qep->dev); | |
497 | sbus_writel(1, qep->qcregs + CREG_TIMASK); | |
498 | } | |
499 | spin_unlock(&qep->lock); | |
500 | } | |
501 | next: | |
502 | ; | |
503 | } | |
504 | qec_status >>= 4; | |
505 | channel++; | |
506 | } | |
507 | ||
508 | return IRQ_HANDLED; | |
509 | } | |
510 | ||
511 | static int qe_open(struct net_device *dev) | |
512 | { | |
513 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
514 | ||
515 | qep->mconfig = (MREGS_MCONFIG_TXENAB | | |
516 | MREGS_MCONFIG_RXENAB | | |
517 | MREGS_MCONFIG_MBAENAB); | |
518 | return qe_init(qep, 0); | |
519 | } | |
520 | ||
521 | static int qe_close(struct net_device *dev) | |
522 | { | |
523 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
524 | ||
525 | qe_stop(qep); | |
526 | return 0; | |
527 | } | |
528 | ||
529 | /* Reclaim TX'd frames from the ring. This must always run under | |
530 | * the IRQ protected qep->lock. | |
531 | */ | |
532 | static void qe_tx_reclaim(struct sunqe *qep) | |
533 | { | |
534 | struct qe_txd *txbase = &qep->qe_block->qe_txd[0]; | |
535 | int elem = qep->tx_old; | |
536 | ||
537 | while (elem != qep->tx_new) { | |
538 | u32 flags = txbase[elem].tx_flags; | |
539 | ||
540 | if (flags & TXD_OWN) | |
541 | break; | |
542 | elem = NEXT_TX(elem); | |
543 | } | |
544 | qep->tx_old = elem; | |
545 | } | |
546 | ||
547 | static void qe_tx_timeout(struct net_device *dev) | |
548 | { | |
549 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
550 | int tx_full; | |
551 | ||
552 | spin_lock_irq(&qep->lock); | |
553 | ||
554 | /* Try to reclaim, if that frees up some tx | |
555 | * entries, we're fine. | |
556 | */ | |
557 | qe_tx_reclaim(qep); | |
558 | tx_full = TX_BUFFS_AVAIL(qep) <= 0; | |
559 | ||
560 | spin_unlock_irq(&qep->lock); | |
561 | ||
562 | if (! tx_full) | |
563 | goto out; | |
564 | ||
565 | printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); | |
566 | qe_init(qep, 1); | |
567 | ||
568 | out: | |
569 | netif_wake_queue(dev); | |
570 | } | |
571 | ||
572 | /* Get a packet queued to go onto the wire. */ | |
573 | static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
574 | { | |
575 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
576 | struct sunqe_buffers *qbufs = qep->buffers; | |
577 | __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma; | |
578 | unsigned char *txbuf; | |
579 | int len, entry; | |
580 | ||
581 | spin_lock_irq(&qep->lock); | |
582 | ||
583 | qe_tx_reclaim(qep); | |
584 | ||
585 | len = skb->len; | |
586 | entry = qep->tx_new; | |
587 | ||
588 | txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0]; | |
589 | txbuf_dvma = qbufs_dvma + | |
590 | qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1))); | |
591 | ||
592 | /* Avoid a race... */ | |
593 | qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE; | |
594 | ||
d626f62b | 595 | skb_copy_from_linear_data(skb, txbuf, len); |
1da177e4 LT |
596 | |
597 | qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma; | |
598 | qep->qe_block->qe_txd[entry].tx_flags = | |
599 | (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH)); | |
600 | qep->tx_new = NEXT_TX(entry); | |
601 | ||
602 | /* Get it going. */ | |
603 | dev->trans_start = jiffies; | |
604 | sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL); | |
605 | ||
606 | qep->net_stats.tx_packets++; | |
607 | qep->net_stats.tx_bytes += len; | |
608 | ||
609 | if (TX_BUFFS_AVAIL(qep) <= 0) { | |
610 | /* Halt the net queue and enable tx interrupts. | |
611 | * When the tx queue empties the tx irq handler | |
612 | * will wake up the queue and return us back to | |
613 | * the lazy tx reclaim scheme. | |
614 | */ | |
615 | netif_stop_queue(dev); | |
616 | sbus_writel(0, qep->qcregs + CREG_TIMASK); | |
617 | } | |
618 | spin_unlock_irq(&qep->lock); | |
619 | ||
620 | dev_kfree_skb(skb); | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static struct net_device_stats *qe_get_stats(struct net_device *dev) | |
626 | { | |
627 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
628 | ||
629 | return &qep->net_stats; | |
630 | } | |
631 | ||
632 | static void qe_set_multicast(struct net_device *dev) | |
633 | { | |
634 | struct sunqe *qep = (struct sunqe *) dev->priv; | |
635 | struct dev_mc_list *dmi = dev->mc_list; | |
636 | u8 new_mconfig = qep->mconfig; | |
637 | char *addrs; | |
638 | int i; | |
639 | u32 crc; | |
640 | ||
641 | /* Lock out others. */ | |
642 | netif_stop_queue(dev); | |
643 | ||
644 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) { | |
645 | sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET, | |
646 | qep->mregs + MREGS_IACONFIG); | |
647 | while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0) | |
648 | barrier(); | |
649 | for (i = 0; i < 8; i++) | |
650 | sbus_writeb(0xff, qep->mregs + MREGS_FILTER); | |
651 | sbus_writeb(0, qep->mregs + MREGS_IACONFIG); | |
652 | } else if (dev->flags & IFF_PROMISC) { | |
653 | new_mconfig |= MREGS_MCONFIG_PROMISC; | |
654 | } else { | |
655 | u16 hash_table[4]; | |
656 | u8 *hbytes = (unsigned char *) &hash_table[0]; | |
657 | ||
658 | for (i = 0; i < 4; i++) | |
659 | hash_table[i] = 0; | |
660 | ||
661 | for (i = 0; i < dev->mc_count; i++) { | |
662 | addrs = dmi->dmi_addr; | |
663 | dmi = dmi->next; | |
664 | ||
665 | if (!(*addrs & 1)) | |
666 | continue; | |
667 | crc = ether_crc_le(6, addrs); | |
668 | crc >>= 26; | |
669 | hash_table[crc >> 4] |= 1 << (crc & 0xf); | |
670 | } | |
671 | /* Program the qe with the new filter value. */ | |
672 | sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET, | |
673 | qep->mregs + MREGS_IACONFIG); | |
674 | while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0) | |
675 | barrier(); | |
676 | for (i = 0; i < 8; i++) { | |
677 | u8 tmp = *hbytes++; | |
678 | sbus_writeb(tmp, qep->mregs + MREGS_FILTER); | |
679 | } | |
680 | sbus_writeb(0, qep->mregs + MREGS_IACONFIG); | |
681 | } | |
682 | ||
683 | /* Any change of the logical address filter, the physical address, | |
684 | * or enabling/disabling promiscuous mode causes the MACE to disable | |
685 | * the receiver. So we must re-enable them here or else the MACE | |
686 | * refuses to listen to anything on the network. Sheesh, took | |
687 | * me a day or two to find this bug. | |
688 | */ | |
689 | qep->mconfig = new_mconfig; | |
690 | sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG); | |
691 | ||
692 | /* Let us get going again. */ | |
693 | netif_wake_queue(dev); | |
694 | } | |
695 | ||
696 | /* Ethtool support... */ | |
697 | static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
698 | { | |
699 | struct sunqe *qep = dev->priv; | |
700 | ||
701 | strcpy(info->driver, "sunqe"); | |
702 | strcpy(info->version, "3.0"); | |
703 | sprintf(info->bus_info, "SBUS:%d", | |
704 | qep->qe_sdev->slot); | |
705 | } | |
706 | ||
707 | static u32 qe_get_link(struct net_device *dev) | |
708 | { | |
709 | struct sunqe *qep = dev->priv; | |
710 | void __iomem *mregs = qep->mregs; | |
711 | u8 phyconfig; | |
712 | ||
713 | spin_lock_irq(&qep->lock); | |
714 | phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG); | |
715 | spin_unlock_irq(&qep->lock); | |
716 | ||
717 | return (phyconfig & MREGS_PHYCONFIG_LSTAT); | |
718 | } | |
719 | ||
7282d491 | 720 | static const struct ethtool_ops qe_ethtool_ops = { |
1da177e4 LT |
721 | .get_drvinfo = qe_get_drvinfo, |
722 | .get_link = qe_get_link, | |
723 | }; | |
724 | ||
725 | /* This is only called once at boot time for each card probed. */ | |
726 | static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev) | |
727 | { | |
728 | u8 bsizes = qecp->qec_bursts; | |
729 | ||
730 | if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) { | |
731 | sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL); | |
732 | } else if (bsizes & DMA_BURST32) { | |
733 | sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL); | |
734 | } else { | |
735 | sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL); | |
736 | } | |
737 | ||
738 | /* Packetsize only used in 100baseT BigMAC configurations, | |
739 | * set it to zero just to be on the safe side. | |
740 | */ | |
741 | sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE); | |
742 | ||
743 | /* Set the local memsize register, divided up to one piece per QE channel. */ | |
744 | sbus_writel((qsdev->reg_addrs[1].reg_size >> 2), | |
745 | qecp->gregs + GLOB_MSIZE); | |
746 | ||
747 | /* Divide up the local QEC memory amongst the 4 QE receiver and | |
748 | * transmitter FIFOs. Basically it is (total / 2 / num_channels). | |
749 | */ | |
750 | sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1, | |
751 | qecp->gregs + GLOB_TSIZE); | |
752 | sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1, | |
753 | qecp->gregs + GLOB_RSIZE); | |
754 | } | |
755 | ||
ecba38ab | 756 | static u8 __init qec_get_burst(struct device_node *dp) |
1da177e4 | 757 | { |
1da177e4 | 758 | u8 bsizes, bsizes_more; |
1da177e4 | 759 | |
ecba38ab DM |
760 | /* Find and set the burst sizes for the QEC, since it |
761 | * does the actual dma for all 4 channels. | |
762 | */ | |
763 | bsizes = of_getintprop_default(dp, "burst-sizes", 0xff); | |
764 | bsizes &= 0xff; | |
765 | bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff); | |
1da177e4 | 766 | |
ecba38ab DM |
767 | if (bsizes_more != 0xff) |
768 | bsizes &= bsizes_more; | |
769 | if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 || | |
770 | (bsizes & DMA_BURST32)==0) | |
771 | bsizes = (DMA_BURST32 - 1); | |
1da177e4 | 772 | |
ecba38ab DM |
773 | return bsizes; |
774 | } | |
1da177e4 | 775 | |
ecba38ab DM |
776 | static struct sunqec * __init get_qec(struct sbus_dev *child_sdev) |
777 | { | |
778 | struct sbus_dev *qec_sdev = child_sdev->parent; | |
779 | struct sunqec *qecp; | |
1da177e4 | 780 | |
ecba38ab DM |
781 | for (qecp = root_qec_dev; qecp; qecp = qecp->next_module) { |
782 | if (qecp->qec_sdev == qec_sdev) | |
783 | break; | |
1da177e4 | 784 | } |
ecba38ab DM |
785 | if (!qecp) { |
786 | qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL); | |
787 | if (qecp) { | |
788 | u32 ctrl; | |
789 | ||
790 | qecp->qec_sdev = qec_sdev; | |
791 | qecp->gregs = sbus_ioremap(&qec_sdev->resource[0], 0, | |
792 | GLOB_REG_SIZE, | |
793 | "QEC Global Registers"); | |
794 | if (!qecp->gregs) | |
795 | goto fail; | |
796 | ||
797 | /* Make sure the QEC is in MACE mode. */ | |
798 | ctrl = sbus_readl(qecp->gregs + GLOB_CTRL); | |
799 | ctrl &= 0xf0000000; | |
800 | if (ctrl != GLOB_CTRL_MMODE) { | |
801 | printk(KERN_ERR "qec: Not in MACE mode!\n"); | |
802 | goto fail; | |
803 | } | |
1da177e4 | 804 | |
ecba38ab DM |
805 | if (qec_global_reset(qecp->gregs)) |
806 | goto fail; | |
1da177e4 | 807 | |
ecba38ab | 808 | qecp->qec_bursts = qec_get_burst(qec_sdev->ofdev.node); |
1da177e4 | 809 | |
ecba38ab | 810 | qec_init_once(qecp, qec_sdev); |
1da177e4 | 811 | |
ecba38ab | 812 | if (request_irq(qec_sdev->irqs[0], &qec_interrupt, |
1fb9df5d | 813 | IRQF_SHARED, "qec", (void *) qecp)) { |
ecba38ab DM |
814 | printk(KERN_ERR "qec: Can't register irq.\n"); |
815 | goto fail; | |
816 | } | |
1da177e4 | 817 | |
ecba38ab DM |
818 | qecp->next_module = root_qec_dev; |
819 | root_qec_dev = qecp; | |
820 | } | |
1da177e4 LT |
821 | } |
822 | ||
ecba38ab | 823 | return qecp; |
1da177e4 | 824 | |
ecba38ab DM |
825 | fail: |
826 | if (qecp->gregs) | |
827 | sbus_iounmap(qecp->gregs, GLOB_REG_SIZE); | |
828 | kfree(qecp); | |
829 | return NULL; | |
830 | } | |
1da177e4 | 831 | |
ecba38ab DM |
832 | static int __init qec_ether_init(struct sbus_dev *sdev) |
833 | { | |
834 | static unsigned version_printed; | |
835 | struct net_device *dev; | |
836 | struct sunqe *qe; | |
837 | struct sunqec *qecp; | |
838 | int i, res; | |
1da177e4 | 839 | |
ecba38ab DM |
840 | if (version_printed++ == 0) |
841 | printk(KERN_INFO "%s", version); | |
1da177e4 | 842 | |
ecba38ab DM |
843 | dev = alloc_etherdev(sizeof(struct sunqe)); |
844 | if (!dev) | |
845 | return -ENOMEM; | |
1da177e4 | 846 | |
d0dc1129 MN |
847 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); |
848 | ||
ecba38ab | 849 | qe = netdev_priv(dev); |
1da177e4 | 850 | |
ecba38ab DM |
851 | i = of_getintprop_default(sdev->ofdev.node, "channel#", -1); |
852 | if (i == -1) { | |
853 | struct sbus_dev *td = sdev->parent->child; | |
854 | i = 0; | |
855 | while (td != sdev) { | |
856 | td = td->next; | |
857 | i++; | |
1da177e4 | 858 | } |
1da177e4 | 859 | } |
ecba38ab DM |
860 | qe->channel = i; |
861 | spin_lock_init(&qe->lock); | |
6aa20a22 | 862 | |
ecba38ab DM |
863 | res = -ENODEV; |
864 | qecp = get_qec(sdev); | |
865 | if (!qecp) | |
866 | goto fail; | |
1da177e4 | 867 | |
ecba38ab DM |
868 | qecp->qes[qe->channel] = qe; |
869 | qe->dev = dev; | |
870 | qe->parent = qecp; | |
871 | qe->qe_sdev = sdev; | |
1da177e4 | 872 | |
ecba38ab DM |
873 | res = -ENOMEM; |
874 | qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0, | |
875 | CREG_REG_SIZE, "QEC Channel Registers"); | |
876 | if (!qe->qcregs) { | |
877 | printk(KERN_ERR "qe: Cannot map channel registers.\n"); | |
878 | goto fail; | |
1da177e4 LT |
879 | } |
880 | ||
ecba38ab DM |
881 | qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0, |
882 | MREGS_REG_SIZE, "QE MACE Registers"); | |
883 | if (!qe->mregs) { | |
884 | printk(KERN_ERR "qe: Cannot map MACE registers.\n"); | |
885 | goto fail; | |
1da177e4 LT |
886 | } |
887 | ||
ecba38ab DM |
888 | qe->qe_block = sbus_alloc_consistent(qe->qe_sdev, |
889 | PAGE_SIZE, | |
890 | &qe->qblock_dvma); | |
891 | qe->buffers = sbus_alloc_consistent(qe->qe_sdev, | |
892 | sizeof(struct sunqe_buffers), | |
893 | &qe->buffers_dvma); | |
894 | if (qe->qe_block == NULL || qe->qblock_dvma == 0 || | |
895 | qe->buffers == NULL || qe->buffers_dvma == 0) | |
896 | goto fail; | |
897 | ||
898 | /* Stop this QE. */ | |
899 | qe_stop(qe); | |
900 | ||
901 | SET_MODULE_OWNER(dev); | |
902 | SET_NETDEV_DEV(dev, &sdev->ofdev.dev); | |
903 | ||
904 | dev->open = qe_open; | |
905 | dev->stop = qe_close; | |
906 | dev->hard_start_xmit = qe_start_xmit; | |
907 | dev->get_stats = qe_get_stats; | |
908 | dev->set_multicast_list = qe_set_multicast; | |
909 | dev->tx_timeout = qe_tx_timeout; | |
910 | dev->watchdog_timeo = 5*HZ; | |
911 | dev->irq = sdev->irqs[0]; | |
912 | dev->dma = 0; | |
913 | dev->ethtool_ops = &qe_ethtool_ops; | |
914 | ||
915 | res = register_netdev(dev); | |
916 | if (res) | |
917 | goto fail; | |
918 | ||
919 | dev_set_drvdata(&sdev->ofdev.dev, qe); | |
920 | ||
921 | printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel); | |
922 | for (i = 0; i < 6; i++) | |
923 | printk ("%2.2x%c", | |
924 | dev->dev_addr[i], | |
925 | i == 5 ? ' ': ':'); | |
926 | printk("\n"); | |
1da177e4 | 927 | |
1da177e4 LT |
928 | |
929 | return 0; | |
930 | ||
ecba38ab DM |
931 | fail: |
932 | if (qe->qcregs) | |
933 | sbus_iounmap(qe->qcregs, CREG_REG_SIZE); | |
934 | if (qe->mregs) | |
935 | sbus_iounmap(qe->mregs, MREGS_REG_SIZE); | |
936 | if (qe->qe_block) | |
937 | sbus_free_consistent(qe->qe_sdev, | |
938 | PAGE_SIZE, | |
939 | qe->qe_block, | |
940 | qe->qblock_dvma); | |
941 | if (qe->buffers) | |
942 | sbus_free_consistent(qe->qe_sdev, | |
943 | sizeof(struct sunqe_buffers), | |
944 | qe->buffers, | |
945 | qe->buffers_dvma); | |
946 | ||
947 | free_netdev(dev); | |
948 | ||
1da177e4 LT |
949 | return res; |
950 | } | |
951 | ||
ecba38ab | 952 | static int __devinit qec_sbus_probe(struct of_device *dev, const struct of_device_id *match) |
1da177e4 | 953 | { |
ecba38ab | 954 | struct sbus_dev *sdev = to_sbus_device(&dev->dev); |
1da177e4 | 955 | |
ecba38ab | 956 | return qec_ether_init(sdev); |
1da177e4 LT |
957 | } |
958 | ||
ecba38ab | 959 | static int __devexit qec_sbus_remove(struct of_device *dev) |
1da177e4 | 960 | { |
ecba38ab DM |
961 | struct sunqe *qp = dev_get_drvdata(&dev->dev); |
962 | struct net_device *net_dev = qp->dev; | |
963 | ||
d0dc1129 | 964 | unregister_netdev(net_dev); |
ecba38ab DM |
965 | |
966 | sbus_iounmap(qp->qcregs, CREG_REG_SIZE); | |
967 | sbus_iounmap(qp->mregs, MREGS_REG_SIZE); | |
968 | sbus_free_consistent(qp->qe_sdev, | |
969 | PAGE_SIZE, | |
970 | qp->qe_block, | |
971 | qp->qblock_dvma); | |
972 | sbus_free_consistent(qp->qe_sdev, | |
973 | sizeof(struct sunqe_buffers), | |
974 | qp->buffers, | |
975 | qp->buffers_dvma); | |
976 | ||
977 | free_netdev(net_dev); | |
978 | ||
979 | dev_set_drvdata(&dev->dev, NULL); | |
980 | ||
1da177e4 LT |
981 | return 0; |
982 | } | |
983 | ||
ecba38ab DM |
984 | static struct of_device_id qec_sbus_match[] = { |
985 | { | |
986 | .name = "qe", | |
987 | }, | |
988 | {}, | |
989 | }; | |
990 | ||
991 | MODULE_DEVICE_TABLE(of, qec_sbus_match); | |
992 | ||
993 | static struct of_platform_driver qec_sbus_driver = { | |
994 | .name = "qec", | |
995 | .match_table = qec_sbus_match, | |
996 | .probe = qec_sbus_probe, | |
997 | .remove = __devexit_p(qec_sbus_remove), | |
998 | }; | |
999 | ||
1000 | static int __init qec_init(void) | |
1001 | { | |
1002 | return of_register_driver(&qec_sbus_driver, &sbus_bus_type); | |
1003 | } | |
1004 | ||
1005 | static void __exit qec_exit(void) | |
1da177e4 | 1006 | { |
ecba38ab | 1007 | of_unregister_driver(&qec_sbus_driver); |
1da177e4 LT |
1008 | |
1009 | while (root_qec_dev) { | |
ecba38ab DM |
1010 | struct sunqec *next = root_qec_dev->next_module; |
1011 | ||
1012 | free_irq(root_qec_dev->qec_sdev->irqs[0], | |
1013 | (void *) root_qec_dev); | |
1da177e4 | 1014 | sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE); |
ecba38ab | 1015 | |
1da177e4 | 1016 | kfree(root_qec_dev); |
ecba38ab DM |
1017 | |
1018 | root_qec_dev = next; | |
1da177e4 LT |
1019 | } |
1020 | } | |
1021 | ||
ecba38ab DM |
1022 | module_init(qec_init); |
1023 | module_exit(qec_exit); |