projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: Change all drivers to use pci_device->revision
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / sunhme.c
CommitLineData
050bbb19 1/* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
1da177e4
LT		 2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
4 *
050bbb19
DM		 5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/in.h>
23#include <linux/slab.h>
24#include <linux/string.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/ethtool.h>
28#include <linux/mii.h>
29#include <linux/crc32.h>
30#include <linux/random.h>
31#include <linux/errno.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
d7fe0f24 35#include <linux/mm.h>
1da177e4
LT		 36#include <linux/bitops.h>
37
38#include <asm/system.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
9e326acf 43#ifdef CONFIG_SPARC
1da177e4
LT		 44#include <asm/idprom.h>
45#include <asm/sbus.h>
46#include <asm/openprom.h>
47#include <asm/oplib.h>
942a6bdd 48#include <asm/prom.h>
1da177e4 49#include <asm/auxio.h>
1da177e4
LT		 50#endif
51#include <asm/uaccess.h>
52
53#include <asm/pgtable.h>
54#include <asm/irq.h>
55
56#ifdef CONFIG_PCI
57#include <linux/pci.h>
1da177e4
LT		 58#endif
59
60#include "sunhme.h"
61
10158286 62#define DRV_NAME "sunhme"
050bbb19
DM		 63#define DRV_VERSION "3.00"
64#define DRV_RELDATE "June 23, 2006"
65#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
10158286
TC		 66
67static char version[] =
68 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
1da177e4 69
10158286
TC		 70MODULE_VERSION(DRV_VERSION);
71MODULE_AUTHOR(DRV_AUTHOR);
72MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
73MODULE_LICENSE("GPL");
1da177e4
LT		 74
75static int macaddr[6];
76
77/* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
78module_param_array(macaddr, int, NULL, 0);
79MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
1da177e4 80
1da177e4
LT		 81#ifdef CONFIG_SBUS
82static struct quattro *qfe_sbus_list;
83#endif
84
85#ifdef CONFIG_PCI
86static struct quattro *qfe_pci_list;
87#endif
88
89#undef HMEDEBUG
90#undef SXDEBUG
91#undef RXDEBUG
92#undef TXDEBUG
93#undef TXLOGGING
94
95#ifdef TXLOGGING
96struct hme_tx_logent {
97 unsigned int tstamp;
98 int tx_new, tx_old;
99 unsigned int action;
100#define TXLOG_ACTION_IRQ 0x01
101#define TXLOG_ACTION_TXMIT 0x02
102#define TXLOG_ACTION_TBUSY 0x04
103#define TXLOG_ACTION_NBUFS 0x08
104 unsigned int status;
105};
106#define TX_LOG_LEN 128
107static struct hme_tx_logent tx_log[TX_LOG_LEN];
108static int txlog_cur_entry;
109static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
110{
111 struct hme_tx_logent *tlp;
112 unsigned long flags;
113
114 save_and_cli(flags);
115 tlp = &tx_log[txlog_cur_entry];
116 tlp->tstamp = (unsigned int)jiffies;
117 tlp->tx_new = hp->tx_new;
118 tlp->tx_old = hp->tx_old;
119 tlp->action = a;
120 tlp->status = s;
121 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
122 restore_flags(flags);
123}
124static __inline__ void tx_dump_log(void)
125{
126 int i, this;
127
128 this = txlog_cur_entry;
129 for (i = 0; i < TX_LOG_LEN; i++) {
130 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
131 tx_log[this].tstamp,
132 tx_log[this].tx_new, tx_log[this].tx_old,
133 tx_log[this].action, tx_log[this].status);
134 this = (this + 1) & (TX_LOG_LEN - 1);
135 }
136}
137static __inline__ void tx_dump_ring(struct happy_meal *hp)
138{
139 struct hmeal_init_block *hb = hp->happy_block;
140 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
141 int i;
142
143 for (i = 0; i < TX_RING_SIZE; i+=4) {
144 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
145 i, i + 4,
146 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
147 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
148 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
149 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
150 }
151}
152#else
153#define tx_add_log(hp, a, s) do { } while(0)
154#define tx_dump_log() do { } while(0)
155#define tx_dump_ring(hp) do { } while(0)
156#endif
157
158#ifdef HMEDEBUG
159#define HMD(x) printk x
160#else
161#define HMD(x)
162#endif
163
164/* #define AUTO_SWITCH_DEBUG */
165
166#ifdef AUTO_SWITCH_DEBUG
167#define ASD(x) printk x
168#else
169#define ASD(x)
170#endif
171
172#define DEFAULT_IPG0 16 /* For lance-mode only */
173#define DEFAULT_IPG1 8 /* For all modes */
174#define DEFAULT_IPG2 4 /* For all modes */
175#define DEFAULT_JAMSIZE 4 /* Toe jam */
176
1da177e4
LT		 177/* NOTE: In the descriptor writes one _must_ write the address
178 * member _first_. The card must not be allowed to see
179 * the updated descriptor flags until the address is
180 * correct. I've added a write memory barrier between
181 * the two stores so that I can sleep well at night... -DaveM
182 */
183
184#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
185static void sbus_hme_write32(void __iomem *reg, u32 val)
186{
187 sbus_writel(val, reg);
188}
189
190static u32 sbus_hme_read32(void __iomem *reg)
191{
192 return sbus_readl(reg);
193}
194
195static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
196{
197 rxd->rx_addr = addr;
198 wmb();
199 rxd->rx_flags = flags;
200}
201
202static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
203{
204 txd->tx_addr = addr;
205 wmb();
206 txd->tx_flags = flags;
207}
208
209static u32 sbus_hme_read_desc32(u32 *p)
210{
211 return *p;
212}
213
214static void pci_hme_write32(void __iomem *reg, u32 val)
215{
216 writel(val, reg);
217}
218
219static u32 pci_hme_read32(void __iomem *reg)
220{
221 return readl(reg);
222}
223
224static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
225{
226 rxd->rx_addr = cpu_to_le32(addr);
227 wmb();
228 rxd->rx_flags = cpu_to_le32(flags);
229}
230
231static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
232{
233 txd->tx_addr = cpu_to_le32(addr);
234 wmb();
235 txd->tx_flags = cpu_to_le32(flags);
236}
237
238static u32 pci_hme_read_desc32(u32 *p)
239{
240 return cpu_to_le32p(p);
241}
242
243#define hme_write32(__hp, __reg, __val) \
244 ((__hp)->write32((__reg), (__val)))
245#define hme_read32(__hp, __reg) \
246 ((__hp)->read32(__reg))
247#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
248 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
249#define hme_write_txd(__hp, __txd, __flags, __addr) \
250 ((__hp)->write_txd((__txd), (__flags), (__addr)))
251#define hme_read_desc32(__hp, __p) \
252 ((__hp)->read_desc32(__p))
253#define hme_dma_map(__hp, __ptr, __size, __dir) \
254 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
255#define hme_dma_unmap(__hp, __addr, __size, __dir) \
256 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
257#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
259#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
261#else
262#ifdef CONFIG_SBUS
263/* SBUS only compilation */
264#define hme_write32(__hp, __reg, __val) \
265 sbus_writel((__val), (__reg))
266#define hme_read32(__hp, __reg) \
267 sbus_readl(__reg)
268#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
269do { (__rxd)->rx_addr = (__addr); \
270 wmb(); \
271 (__rxd)->rx_flags = (__flags); \
272} while(0)
273#define hme_write_txd(__hp, __txd, __flags, __addr) \
274do { (__txd)->tx_addr = (__addr); \
275 wmb(); \
276 (__txd)->tx_flags = (__flags); \
277} while(0)
278#define hme_read_desc32(__hp, __p) (*(__p))
279#define hme_dma_map(__hp, __ptr, __size, __dir) \
280 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
281#define hme_dma_unmap(__hp, __addr, __size, __dir) \
282 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
283#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
284 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
285#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
286 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
287#else
288/* PCI only compilation */
289#define hme_write32(__hp, __reg, __val) \
290 writel((__val), (__reg))
291#define hme_read32(__hp, __reg) \
292 readl(__reg)
293#define hme_write_rxd(__hp, __rxd, __flags, __addr) \
294do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
295 wmb(); \
296 (__rxd)->rx_flags = cpu_to_le32(__flags); \
297} while(0)
298#define hme_write_txd(__hp, __txd, __flags, __addr) \
299do { (__txd)->tx_addr = cpu_to_le32(__addr); \
300 wmb(); \
301 (__txd)->tx_flags = cpu_to_le32(__flags); \
302} while(0)
303#define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
304#define hme_dma_map(__hp, __ptr, __size, __dir) \
305 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
306#define hme_dma_unmap(__hp, __addr, __size, __dir) \
307 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
308#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
309 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
310#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
311 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
312#endif
313#endif
314
315
316#ifdef SBUS_DMA_BIDIRECTIONAL
317# define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
318#else
319# define DMA_BIDIRECTIONAL 0
320#endif
321
322#ifdef SBUS_DMA_FROMDEVICE
323# define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
324#else
325# define DMA_TODEVICE 1
326#endif
327
328#ifdef SBUS_DMA_TODEVICE
329# define DMA_TODEVICE SBUS_DMA_TODEVICE
330#else
331# define DMA_FROMDEVICE 2
332#endif
333
334
335/* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
336static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
337{
338 hme_write32(hp, tregs + TCVR_BBDATA, bit);
339 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
340 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
341}
342
343#if 0
344static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
345{
346 u32 ret;
347
348 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
350 ret = hme_read32(hp, tregs + TCVR_CFG);
351 if (internal)
352 ret &= TCV_CFG_MDIO0;
353 else
354 ret &= TCV_CFG_MDIO1;
355
356 return ret;
357}
358#endif
359
360static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
361{
362 u32 retval;
363
364 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
365 udelay(1);
366 retval = hme_read32(hp, tregs + TCVR_CFG);
367 if (internal)
368 retval &= TCV_CFG_MDIO0;
369 else
370 retval &= TCV_CFG_MDIO1;
371 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
372
373 return retval;
374}
375
376#define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
377
378static int happy_meal_bb_read(struct happy_meal *hp,
379 void __iomem *tregs, int reg)
380{
381 u32 tmp;
382 int retval = 0;
383 int i;
384
385 ASD(("happy_meal_bb_read: reg=%d ", reg));
386
387 /* Enable the MIF BitBang outputs. */
388 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
389
390 /* Force BitBang into the idle state. */
391 for (i = 0; i < 32; i++)
392 BB_PUT_BIT(hp, tregs, 1);
393
394 /* Give it the read sequence. */
395 BB_PUT_BIT(hp, tregs, 0);
396 BB_PUT_BIT(hp, tregs, 1);
397 BB_PUT_BIT(hp, tregs, 1);
398 BB_PUT_BIT(hp, tregs, 0);
399
400 /* Give it the PHY address. */
401 tmp = hp->paddr & 0xff;
402 for (i = 4; i >= 0; i--)
403 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
404
405 /* Tell it what register we want to read. */
406 tmp = (reg & 0xff);
407 for (i = 4; i >= 0; i--)
408 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
409
410 /* Close down the MIF BitBang outputs. */
411 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
412
413 /* Now read in the value. */
414 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
415 for (i = 15; i >= 0; i--)
416 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
417 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
418 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
419 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
420 ASD(("value=%x\n", retval));
421 return retval;
422}
423
424static void happy_meal_bb_write(struct happy_meal *hp,
425 void __iomem *tregs, int reg,
426 unsigned short value)
427{
428 u32 tmp;
429 int i;
430
431 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
432
433 /* Enable the MIF BitBang outputs. */
434 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
435
436 /* Force BitBang into the idle state. */
437 for (i = 0; i < 32; i++)
438 BB_PUT_BIT(hp, tregs, 1);
439
440 /* Give it write sequence. */
441 BB_PUT_BIT(hp, tregs, 0);
442 BB_PUT_BIT(hp, tregs, 1);
443 BB_PUT_BIT(hp, tregs, 0);
444 BB_PUT_BIT(hp, tregs, 1);
445
446 /* Give it the PHY address. */
447 tmp = (hp->paddr & 0xff);
448 for (i = 4; i >= 0; i--)
449 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
450
451 /* Tell it what register we will be writing. */
452 tmp = (reg & 0xff);
453 for (i = 4; i >= 0; i--)
454 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
455
456 /* Tell it to become ready for the bits. */
457 BB_PUT_BIT(hp, tregs, 1);
458 BB_PUT_BIT(hp, tregs, 0);
459
460 for (i = 15; i >= 0; i--)
461 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
462
463 /* Close down the MIF BitBang outputs. */
464 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
465}
466
467#define TCVR_READ_TRIES 16
468
469static int happy_meal_tcvr_read(struct happy_meal *hp,
470 void __iomem *tregs, int reg)
471{
472 int tries = TCVR_READ_TRIES;
473 int retval;
474
475 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
476 if (hp->tcvr_type == none) {
477 ASD(("no transceiver, value=TCVR_FAILURE\n"));
478 return TCVR_FAILURE;
479 }
480
481 if (!(hp->happy_flags & HFLAG_FENABLE)) {
482 ASD(("doing bit bang\n"));
483 return happy_meal_bb_read(hp, tregs, reg);
484 }
485
486 hme_write32(hp, tregs + TCVR_FRAME,
487 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
488 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
489 udelay(20);
490 if (!tries) {
491 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
492 return TCVR_FAILURE;
493 }
494 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
495 ASD(("value=%04x\n", retval));
496 return retval;
497}
498
499#define TCVR_WRITE_TRIES 16
500
501static void happy_meal_tcvr_write(struct happy_meal *hp,
502 void __iomem *tregs, int reg,
503 unsigned short value)
504{
505 int tries = TCVR_WRITE_TRIES;
6aa20a22 506
1da177e4
LT		 507 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
508
509 /* Welcome to Sun Microsystems, can I take your order please? */
510 if (!(hp->happy_flags & HFLAG_FENABLE)) {
511 happy_meal_bb_write(hp, tregs, reg, value);
512 return;
513 }
514
515 /* Would you like fries with that? */
516 hme_write32(hp, tregs + TCVR_FRAME,
517 (FRAME_WRITE | (hp->paddr << 23) |
518 ((reg & 0xff) << 18) | (value & 0xffff)));
519 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
520 udelay(20);
521
522 /* Anything else? */
523 if (!tries)
524 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
525
526 /* Fifty-two cents is your change, have a nice day. */
527}
528
529/* Auto negotiation. The scheme is very simple. We have a timer routine
530 * that keeps watching the auto negotiation process as it progresses.
531 * The DP83840 is first told to start doing it's thing, we set up the time
532 * and place the timer state machine in it's initial state.
533 *
534 * Here the timer peeks at the DP83840 status registers at each click to see
535 * if the auto negotiation has completed, we assume here that the DP83840 PHY
536 * will time out at some point and just tell us what (didn't) happen. For
537 * complete coverage we only allow so many of the ticks at this level to run,
538 * when this has expired we print a warning message and try another strategy.
539 * This "other" strategy is to force the interface into various speed/duplex
540 * configurations and we stop when we see a link-up condition before the
541 * maximum number of "peek" ticks have occurred.
542 *
543 * Once a valid link status has been detected we configure the BigMAC and
544 * the rest of the Happy Meal to speak the most efficient protocol we could
545 * get a clean link for. The priority for link configurations, highest first
546 * is:
547 * 100 Base-T Full Duplex
548 * 100 Base-T Half Duplex
549 * 10 Base-T Full Duplex
550 * 10 Base-T Half Duplex
551 *
552 * We start a new timer now, after a successful auto negotiation status has
553 * been detected. This timer just waits for the link-up bit to get set in
554 * the BMCR of the DP83840. When this occurs we print a kernel log message
555 * describing the link type in use and the fact that it is up.
556 *
557 * If a fatal error of some sort is signalled and detected in the interrupt
558 * service routine, and the chip is reset, or the link is ifconfig'd down
559 * and then back up, this entire process repeats itself all over again.
560 */
561static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
562{
563 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
564
565 /* Downgrade from full to half duplex. Only possible
566 * via ethtool.
567 */
568 if (hp->sw_bmcr & BMCR_FULLDPLX) {
569 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
570 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
571 return 0;
572 }
573
574 /* Downgrade from 100 to 10. */
575 if (hp->sw_bmcr & BMCR_SPEED100) {
576 hp->sw_bmcr &= ~(BMCR_SPEED100);
577 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
578 return 0;
579 }
580
581 /* We've tried everything. */
582 return -1;
583}
584
585static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
586{
587 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
588 if (hp->tcvr_type == external)
589 printk("external ");
590 else
591 printk("internal ");
592 printk("transceiver at ");
593 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
594 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
595 if (hp->sw_lpa & LPA_100FULL)
596 printk("100Mb/s, Full Duplex.\n");
597 else
598 printk("100Mb/s, Half Duplex.\n");
599 } else {
600 if (hp->sw_lpa & LPA_10FULL)
601 printk("10Mb/s, Full Duplex.\n");
602 else
603 printk("10Mb/s, Half Duplex.\n");
604 }
605}
606
607static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
608{
609 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
610 if (hp->tcvr_type == external)
611 printk("external ");
612 else
613 printk("internal ");
614 printk("transceiver at ");
615 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
616 if (hp->sw_bmcr & BMCR_SPEED100)
617 printk("100Mb/s, ");
618 else
619 printk("10Mb/s, ");
620 if (hp->sw_bmcr & BMCR_FULLDPLX)
621 printk("Full Duplex.\n");
622 else
623 printk("Half Duplex.\n");
624}
625
626static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
627{
628 int full;
629
630 /* All we care about is making sure the bigmac tx_cfg has a
631 * proper duplex setting.
632 */
633 if (hp->timer_state == arbwait) {
634 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
635 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
636 goto no_response;
637 if (hp->sw_lpa & LPA_100FULL)
638 full = 1;
639 else if (hp->sw_lpa & LPA_100HALF)
640 full = 0;
641 else if (hp->sw_lpa & LPA_10FULL)
642 full = 1;
643 else
644 full = 0;
645 } else {
646 /* Forcing a link mode. */
647 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
648 if (hp->sw_bmcr & BMCR_FULLDPLX)
649 full = 1;
650 else
651 full = 0;
652 }
653
654 /* Before changing other bits in the tx_cfg register, and in
655 * general any of other the TX config registers too, you
656 * must:
657 * 1) Clear Enable
658 * 2) Poll with reads until that bit reads back as zero
659 * 3) Make TX configuration changes
660 * 4) Set Enable once more
661 */
662 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
663 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
664 ~(BIGMAC_TXCFG_ENABLE));
665 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
666 barrier();
667 if (full) {
668 hp->happy_flags |= HFLAG_FULL;
669 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
670 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
671 BIGMAC_TXCFG_FULLDPLX);
672 } else {
673 hp->happy_flags &= ~(HFLAG_FULL);
674 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
675 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
676 ~(BIGMAC_TXCFG_FULLDPLX));
677 }
678 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
679 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
680 BIGMAC_TXCFG_ENABLE);
681 return 0;
682no_response:
683 return 1;
684}
685
686static int happy_meal_init(struct happy_meal *hp);
687
688static int is_lucent_phy(struct happy_meal *hp)
689{
690 void __iomem *tregs = hp->tcvregs;
691 unsigned short mr2, mr3;
692 int ret = 0;
693
694 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
695 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
696 if ((mr2 & 0xffff) == 0x0180 &&
697 ((mr3 & 0xffff) >> 10) == 0x1d)
698 ret = 1;
699
700 return ret;
701}
702
703static void happy_meal_timer(unsigned long data)
704{
705 struct happy_meal *hp = (struct happy_meal *) data;
706 void __iomem *tregs = hp->tcvregs;
707 int restart_timer = 0;
708
709 spin_lock_irq(&hp->happy_lock);
710
711 hp->timer_ticks++;
712 switch(hp->timer_state) {
713 case arbwait:
714 /* Only allow for 5 ticks, thats 10 seconds and much too
715 * long to wait for arbitration to complete.
716 */
717 if (hp->timer_ticks >= 10) {
718 /* Enter force mode. */
719 do_force_mode:
720 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
721 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
722 hp->dev->name);
723 hp->sw_bmcr = BMCR_SPEED100;
724 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
725
726 if (!is_lucent_phy(hp)) {
727 /* OK, seems we need do disable the transceiver for the first
728 * tick to make sure we get an accurate link state at the
729 * second tick.
730 */
731 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
732 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
733 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
734 }
735 hp->timer_state = ltrywait;
736 hp->timer_ticks = 0;
737 restart_timer = 1;
738 } else {
739 /* Anything interesting happen? */
740 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
741 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
742 int ret;
743
744 /* Just what we've been waiting for... */
745 ret = set_happy_link_modes(hp, tregs);
746 if (ret) {
747 /* Ooops, something bad happened, go to force
748 * mode.
749 *
750 * XXX Broken hubs which don't support 802.3u
751 * XXX auto-negotiation make this happen as well.
752 */
753 goto do_force_mode;
754 }
755
756 /* Success, at least so far, advance our state engine. */
757 hp->timer_state = lupwait;
758 restart_timer = 1;
759 } else {
760 restart_timer = 1;
761 }
762 }
763 break;
764
765 case lupwait:
766 /* Auto negotiation was successful and we are awaiting a
767 * link up status. I have decided to let this timer run
768 * forever until some sort of error is signalled, reporting
769 * a message to the user at 10 second intervals.
770 */
771 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
772 if (hp->sw_bmsr & BMSR_LSTATUS) {
773 /* Wheee, it's up, display the link mode in use and put
774 * the timer to sleep.
775 */
776 display_link_mode(hp, tregs);
777 hp->timer_state = asleep;
778 restart_timer = 0;
779 } else {
780 if (hp->timer_ticks >= 10) {
781 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
782 "not completely up.\n", hp->dev->name);
783 hp->timer_ticks = 0;
784 restart_timer = 1;
785 } else {
786 restart_timer = 1;
787 }
788 }
789 break;
790
791 case ltrywait:
792 /* Making the timeout here too long can make it take
793 * annoyingly long to attempt all of the link mode
794 * permutations, but then again this is essentially
795 * error recovery code for the most part.
796 */
797 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
798 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
799 if (hp->timer_ticks == 1) {
800 if (!is_lucent_phy(hp)) {
801 /* Re-enable transceiver, we'll re-enable the transceiver next
802 * tick, then check link state on the following tick.
803 */
804 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
805 happy_meal_tcvr_write(hp, tregs,
806 DP83840_CSCONFIG, hp->sw_csconfig);
807 }
808 restart_timer = 1;
809 break;
810 }
811 if (hp->timer_ticks == 2) {
812 if (!is_lucent_phy(hp)) {
813 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
814 happy_meal_tcvr_write(hp, tregs,
815 DP83840_CSCONFIG, hp->sw_csconfig);
816 }
817 restart_timer = 1;
818 break;
819 }
820 if (hp->sw_bmsr & BMSR_LSTATUS) {
821 /* Force mode selection success. */
822 display_forced_link_mode(hp, tregs);
823 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
824 hp->timer_state = asleep;
825 restart_timer = 0;
826 } else {
827 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
828 int ret;
829
830 ret = try_next_permutation(hp, tregs);
831 if (ret == -1) {
832 /* Aieee, tried them all, reset the
833 * chip and try all over again.
834 */
835
836 /* Let the user know... */
837 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
838 hp->dev->name);
839
840 ret = happy_meal_init(hp);
841 if (ret) {
842 /* ho hum... */
843 printk(KERN_ERR "%s: Error, cannot re-init the "
844 "Happy Meal.\n", hp->dev->name);
845 }
846 goto out;
847 }
848 if (!is_lucent_phy(hp)) {
849 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
850 DP83840_CSCONFIG);
851 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
852 happy_meal_tcvr_write(hp, tregs,
853 DP83840_CSCONFIG, hp->sw_csconfig);
854 }
855 hp->timer_ticks = 0;
856 restart_timer = 1;
857 } else {
858 restart_timer = 1;
859 }
860 }
861 break;
862
863 case asleep:
864 default:
865 /* Can't happens.... */
866 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
867 hp->dev->name);
868 restart_timer = 0;
869 hp->timer_ticks = 0;
870 hp->timer_state = asleep; /* foo on you */
871 break;
872 };
873
874 if (restart_timer) {
875 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
876 add_timer(&hp->happy_timer);
877 }
878
879out:
880 spin_unlock_irq(&hp->happy_lock);
881}
882
883#define TX_RESET_TRIES 32
884#define RX_RESET_TRIES 32
885
886/* hp->happy_lock must be held */
887static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
888{
889 int tries = TX_RESET_TRIES;
890
891 HMD(("happy_meal_tx_reset: reset, "));
892
893 /* Would you like to try our SMCC Delux? */
894 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
895 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
896 udelay(20);
897
898 /* Lettuce, tomato, buggy hardware (no extra charge)? */
899 if (!tries)
900 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
901
902 /* Take care. */
903 HMD(("done\n"));
904}
905
906/* hp->happy_lock must be held */
907static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
908{
909 int tries = RX_RESET_TRIES;
910
911 HMD(("happy_meal_rx_reset: reset, "));
912
913 /* We have a special on GNU/Viking hardware bugs today. */
914 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
915 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
916 udelay(20);
917
918 /* Will that be all? */
919 if (!tries)
920 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
921
922 /* Don't forget your vik_1137125_wa. Have a nice day. */
923 HMD(("done\n"));
924}
925
926#define STOP_TRIES 16
927
928/* hp->happy_lock must be held */
929static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
930{
931 int tries = STOP_TRIES;
932
933 HMD(("happy_meal_stop: reset, "));
934
935 /* We're consolidating our STB products, it's your lucky day. */
936 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
937 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
938 udelay(20);
939
940 /* Come back next week when we are "Sun Microelectronics". */
941 if (!tries)
942 printk(KERN_ERR "happy meal: Fry guys.");
943
944 /* Remember: "Different name, same old buggy as shit hardware." */
945 HMD(("done\n"));
946}
947
948/* hp->happy_lock must be held */
949static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
950{
951 struct net_device_stats *stats = &hp->net_stats;
952
953 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
954 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
955
956 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
957 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
958
959 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
960 hme_write32(hp, bregs + BMAC_GLECTR, 0);
961
962 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
963
964 stats->collisions +=
965 (hme_read32(hp, bregs + BMAC_EXCTR) +
966 hme_read32(hp, bregs + BMAC_LTCTR));
967 hme_write32(hp, bregs + BMAC_EXCTR, 0);
968 hme_write32(hp, bregs + BMAC_LTCTR, 0);
969}
970
971/* hp->happy_lock must be held */
972static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
973{
974 ASD(("happy_meal_poll_stop: "));
975
976 /* If polling disabled or not polling already, nothing to do. */
977 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
978 (HFLAG_POLLENABLE | HFLAG_POLL)) {
979 HMD(("not polling, return\n"));
980 return;
981 }
982
983 /* Shut up the MIF. */
984 ASD(("were polling, mif ints off, "));
985 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
986
987 /* Turn off polling. */
988 ASD(("polling off, "));
989 hme_write32(hp, tregs + TCVR_CFG,
990 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
991
992 /* We are no longer polling. */
993 hp->happy_flags &= ~(HFLAG_POLL);
994
995 /* Let the bits set. */
996 udelay(200);
997 ASD(("done\n"));
998}
999
1000/* Only Sun can take such nice parts and fuck up the programming interface
1001 * like this. Good job guys...
1002 */
1003#define TCVR_RESET_TRIES 16 /* It should reset quickly */
1004#define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1005
1006/* hp->happy_lock must be held */
1007static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1008{
1009 u32 tconfig;
1010 int result, tries = TCVR_RESET_TRIES;
1011
1012 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1013 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1014 if (hp->tcvr_type == external) {
1015 ASD(("external<"));
1016 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1017 hp->tcvr_type = internal;
1018 hp->paddr = TCV_PADDR_ITX;
1019 ASD(("ISOLATE,"));
1020 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1021 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1022 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1023 if (result == TCVR_FAILURE) {
1024 ASD(("phyread_fail>\n"));
1025 return -1;
1026 }
1027 ASD(("phyread_ok,PSELECT>"));
1028 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1029 hp->tcvr_type = external;
1030 hp->paddr = TCV_PADDR_ETX;
1031 } else {
1032 if (tconfig & TCV_CFG_MDIO1) {
1033 ASD(("internal<PSELECT,"));
1034 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1035 ASD(("ISOLATE,"));
1036 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1037 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1038 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1039 if (result == TCVR_FAILURE) {
1040 ASD(("phyread_fail>\n"));
1041 return -1;
1042 }
1043 ASD(("phyread_ok,~PSELECT>"));
1044 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1045 hp->tcvr_type = internal;
1046 hp->paddr = TCV_PADDR_ITX;
1047 }
1048 }
1049
1050 ASD(("BMCR_RESET "));
1051 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1052
1053 while (--tries) {
1054 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1055 if (result == TCVR_FAILURE)
1056 return -1;
1057 hp->sw_bmcr = result;
1058 if (!(result & BMCR_RESET))
1059 break;
1060 udelay(20);
1061 }
1062 if (!tries) {
1063 ASD(("BMCR RESET FAILED!\n"));
1064 return -1;
1065 }
1066 ASD(("RESET_OK\n"));
1067
1068 /* Get fresh copies of the PHY registers. */
1069 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1070 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1071 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1072 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1073
1074 ASD(("UNISOLATE"));
1075 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1076 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1077
1078 tries = TCVR_UNISOLATE_TRIES;
1079 while (--tries) {
1080 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1081 if (result == TCVR_FAILURE)
1082 return -1;
1083 if (!(result & BMCR_ISOLATE))
1084 break;
1085 udelay(20);
1086 }
1087 if (!tries) {
1088 ASD((" FAILED!\n"));
1089 return -1;
1090 }
1091 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1092 if (!is_lucent_phy(hp)) {
1093 result = happy_meal_tcvr_read(hp, tregs,
1094 DP83840_CSCONFIG);
1095 happy_meal_tcvr_write(hp, tregs,
1096 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1097 }
1098 return 0;
1099}
1100
1101/* Figure out whether we have an internal or external transceiver.
1102 *
1103 * hp->happy_lock must be held
1104 */
1105static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1106{
1107 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1108
1109 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1110 if (hp->happy_flags & HFLAG_POLL) {
1111 /* If we are polling, we must stop to get the transceiver type. */
1112 ASD(("<polling> "));
1113 if (hp->tcvr_type == internal) {
1114 if (tconfig & TCV_CFG_MDIO1) {
1115 ASD(("<internal> <poll stop> "));
1116 happy_meal_poll_stop(hp, tregs);
1117 hp->paddr = TCV_PADDR_ETX;
1118 hp->tcvr_type = external;
1119 ASD(("<external>\n"));
1120 tconfig &= ~(TCV_CFG_PENABLE);
1121 tconfig |= TCV_CFG_PSELECT;
1122 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1123 }
1124 } else {
1125 if (hp->tcvr_type == external) {
1126 ASD(("<external> "));
1127 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1128 ASD(("<poll stop> "));
1129 happy_meal_poll_stop(hp, tregs);
1130 hp->paddr = TCV_PADDR_ITX;
1131 hp->tcvr_type = internal;
1132 ASD(("<internal>\n"));
1133 hme_write32(hp, tregs + TCVR_CFG,
1134 hme_read32(hp, tregs + TCVR_CFG) &
1135 ~(TCV_CFG_PSELECT));
1136 }
1137 ASD(("\n"));
1138 } else {
1139 ASD(("<none>\n"));
1140 }
1141 }
1142 } else {
1143 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1144
1145 /* Else we can just work off of the MDIO bits. */
1146 ASD(("<not polling> "));
1147 if (reread & TCV_CFG_MDIO1) {
1148 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1149 hp->paddr = TCV_PADDR_ETX;
1150 hp->tcvr_type = external;
1151 ASD(("<external>\n"));
1152 } else {
1153 if (reread & TCV_CFG_MDIO0) {
1154 hme_write32(hp, tregs + TCVR_CFG,
1155 tconfig & ~(TCV_CFG_PSELECT));
1156 hp->paddr = TCV_PADDR_ITX;
1157 hp->tcvr_type = internal;
1158 ASD(("<internal>\n"));
1159 } else {
1160 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1161 hp->tcvr_type = none; /* Grrr... */
1162 ASD(("<none>\n"));
1163 }
1164 }
1165 }
1166}
1167
1168/* The receive ring buffers are a bit tricky to get right. Here goes...
1169 *
1170 * The buffers we dma into must be 64 byte aligned. So we use a special
1171 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1172 * we really need.
1173 *
1174 * We use skb_reserve() to align the data block we get in the skb. We
1175 * also program the etxregs->cfg register to use an offset of 2. This
1176 * imperical constant plus the ethernet header size will always leave
1177 * us with a nicely aligned ip header once we pass things up to the
1178 * protocol layers.
1179 *
1180 * The numbers work out to:
1181 *
1182 * Max ethernet frame size 1518
1183 * Ethernet header size 14
1184 * Happy Meal base offset 2
1185 *
1186 * Say a skb data area is at 0xf001b010, and its size alloced is
1187 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1188 *
1189 * First our alloc_skb() routine aligns the data base to a 64 byte
1190 * boundary. We now have 0xf001b040 as our skb data address. We
1191 * plug this into the receive descriptor address.
1192 *
1193 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1194 * So now the data we will end up looking at starts at 0xf001b042. When
1195 * the packet arrives, we will check out the size received and subtract
1196 * this from the skb->length. Then we just pass the packet up to the
1197 * protocols as is, and allocate a new skb to replace this slot we have
1198 * just received from.
1199 *
1200 * The ethernet layer will strip the ether header from the front of the
1201 * skb we just sent to it, this leaves us with the ip header sitting
1202 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1203 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1204 * bit checksum is obtained from the low bits of the receive descriptor
1205 * flags, thus:
1206 *
1207 * skb->csum = rxd->rx_flags & 0xffff;
84fa7933 1208 * skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 1209 *
1210 * before sending off the skb to the protocols, and we are good as gold.
1211 */
1212static void happy_meal_clean_rings(struct happy_meal *hp)
1213{
1214 int i;
1215
1216 for (i = 0; i < RX_RING_SIZE; i++) {
1217 if (hp->rx_skbs[i] != NULL) {
1218 struct sk_buff *skb = hp->rx_skbs[i];
1219 struct happy_meal_rxd *rxd;
1220 u32 dma_addr;
1221
1222 rxd = &hp->happy_block->happy_meal_rxd[i];
1223 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1224 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1225 dev_kfree_skb_any(skb);
1226 hp->rx_skbs[i] = NULL;
1227 }
1228 }
1229
1230 for (i = 0; i < TX_RING_SIZE; i++) {
1231 if (hp->tx_skbs[i] != NULL) {
1232 struct sk_buff *skb = hp->tx_skbs[i];
1233 struct happy_meal_txd *txd;
1234 u32 dma_addr;
1235 int frag;
1236
1237 hp->tx_skbs[i] = NULL;
1238
1239 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1240 txd = &hp->happy_block->happy_meal_txd[i];
1241 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1242 hme_dma_unmap(hp, dma_addr,
1243 (hme_read_desc32(hp, &txd->tx_flags)
1244 & TXFLAG_SIZE),
1245 DMA_TODEVICE);
1246
1247 if (frag != skb_shinfo(skb)->nr_frags)
1248 i++;
1249 }
1250
1251 dev_kfree_skb_any(skb);
1252 }
1253 }
1254}
1255
1256/* hp->happy_lock must be held */
1257static void happy_meal_init_rings(struct happy_meal *hp)
1258{
1259 struct hmeal_init_block *hb = hp->happy_block;
1260 struct net_device *dev = hp->dev;
1261 int i;
1262
1263 HMD(("happy_meal_init_rings: counters to zero, "));
1264 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1265
1266 /* Free any skippy bufs left around in the rings. */
1267 HMD(("clean, "));
1268 happy_meal_clean_rings(hp);
1269
1270 /* Now get new skippy bufs for the receive ring. */
1271 HMD(("init rxring, "));
1272 for (i = 0; i < RX_RING_SIZE; i++) {
1273 struct sk_buff *skb;
1274
1275 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1276 if (!skb) {
1277 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1278 continue;
1279 }
1280 hp->rx_skbs[i] = skb;
1281 skb->dev = dev;
1282
1283 /* Because we reserve afterwards. */
1284 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1285 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1286 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1287 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1288 skb_reserve(skb, RX_OFFSET);
1289 }
1290
1291 HMD(("init txring, "));
1292 for (i = 0; i < TX_RING_SIZE; i++)
1293 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1294
1295 HMD(("done\n"));
1296}
1297
1298/* hp->happy_lock must be held */
1299static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1300 void __iomem *tregs,
1301 struct ethtool_cmd *ep)
1302{
1303 int timeout;
1304
1305 /* Read all of the registers we are interested in now. */
1306 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1307 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1308 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1309 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1310
1311 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1312
1313 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1314 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1315 /* Advertise everything we can support. */
1316 if (hp->sw_bmsr & BMSR_10HALF)
1317 hp->sw_advertise |= (ADVERTISE_10HALF);
1318 else
1319 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1320
1321 if (hp->sw_bmsr & BMSR_10FULL)
1322 hp->sw_advertise |= (ADVERTISE_10FULL);
1323 else
1324 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1325 if (hp->sw_bmsr & BMSR_100HALF)
1326 hp->sw_advertise |= (ADVERTISE_100HALF);
1327 else
1328 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1329 if (hp->sw_bmsr & BMSR_100FULL)
1330 hp->sw_advertise |= (ADVERTISE_100FULL);
1331 else
1332 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1333 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1334
1335 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1336 * XXX and this is because the DP83840 does not support it, changes
1337 * XXX would need to be made to the tx/rx logic in the driver as well
1338 * XXX so I completely skip checking for it in the BMSR for now.
1339 */
1340
1341#ifdef AUTO_SWITCH_DEBUG
1342 ASD(("%s: Advertising [ ", hp->dev->name));
1343 if (hp->sw_advertise & ADVERTISE_10HALF)
1344 ASD(("10H "));
1345 if (hp->sw_advertise & ADVERTISE_10FULL)
1346 ASD(("10F "));
1347 if (hp->sw_advertise & ADVERTISE_100HALF)
1348 ASD(("100H "));
1349 if (hp->sw_advertise & ADVERTISE_100FULL)
1350 ASD(("100F "));
1351#endif
1352
1353 /* Enable Auto-Negotiation, this is usually on already... */
1354 hp->sw_bmcr |= BMCR_ANENABLE;
1355 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1356
1357 /* Restart it to make sure it is going. */
1358 hp->sw_bmcr |= BMCR_ANRESTART;
1359 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1360
1361 /* BMCR_ANRESTART self clears when the process has begun. */
1362
1363 timeout = 64; /* More than enough. */
1364 while (--timeout) {
1365 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1366 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1367 break; /* got it. */
1368 udelay(10);
1369 }
1370 if (!timeout) {
1371 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1372 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1373 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1374 hp->dev->name);
1375 goto force_link;
1376 } else {
1377 hp->timer_state = arbwait;
1378 }
1379 } else {
1380force_link:
1381 /* Force the link up, trying first a particular mode.
1382 * Either we are here at the request of ethtool or
1383 * because the Happy Meal would not start to autoneg.
1384 */
1385
1386 /* Disable auto-negotiation in BMCR, enable the duplex and
1387 * speed setting, init the timer state machine, and fire it off.
1388 */
1389 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1390 hp->sw_bmcr = BMCR_SPEED100;
1391 } else {
1392 if (ep->speed == SPEED_100)
1393 hp->sw_bmcr = BMCR_SPEED100;
1394 else
1395 hp->sw_bmcr = 0;
1396 if (ep->duplex == DUPLEX_FULL)
1397 hp->sw_bmcr |= BMCR_FULLDPLX;
1398 }
1399 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1400
1401 if (!is_lucent_phy(hp)) {
1402 /* OK, seems we need do disable the transceiver for the first
1403 * tick to make sure we get an accurate link state at the
1404 * second tick.
1405 */
1406 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1407 DP83840_CSCONFIG);
1408 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1409 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1410 hp->sw_csconfig);
1411 }
1412 hp->timer_state = ltrywait;
1413 }
1414
1415 hp->timer_ticks = 0;
1416 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1417 hp->happy_timer.data = (unsigned long) hp;
1418 hp->happy_timer.function = &happy_meal_timer;
1419 add_timer(&hp->happy_timer);
1420}
1421
1422/* hp->happy_lock must be held */
1423static int happy_meal_init(struct happy_meal *hp)
1424{
1425 void __iomem *gregs = hp->gregs;
1426 void __iomem *etxregs = hp->etxregs;
1427 void __iomem *erxregs = hp->erxregs;
1428 void __iomem *bregs = hp->bigmacregs;
1429 void __iomem *tregs = hp->tcvregs;
1430 u32 regtmp, rxcfg;
1431 unsigned char *e = &hp->dev->dev_addr[0];
1432
1433 /* If auto-negotiation timer is running, kill it. */
1434 del_timer(&hp->happy_timer);
1435
1436 HMD(("happy_meal_init: happy_flags[%08x] ",
1437 hp->happy_flags));
1438 if (!(hp->happy_flags & HFLAG_INIT)) {
1439 HMD(("set HFLAG_INIT, "));
1440 hp->happy_flags |= HFLAG_INIT;
1441 happy_meal_get_counters(hp, bregs);
1442 }
1443
1444 /* Stop polling. */
1445 HMD(("to happy_meal_poll_stop\n"));
1446 happy_meal_poll_stop(hp, tregs);
1447
1448 /* Stop transmitter and receiver. */
1449 HMD(("happy_meal_init: to happy_meal_stop\n"));
1450 happy_meal_stop(hp, gregs);
1451
1452 /* Alloc and reset the tx/rx descriptor chains. */
1453 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1454 happy_meal_init_rings(hp);
1455
1456 /* Shut up the MIF. */
1457 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1458 hme_read32(hp, tregs + TCVR_IMASK)));
1459 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1460
1461 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1462 if (hp->happy_flags & HFLAG_FENABLE) {
1463 HMD(("use frame old[%08x], ",
1464 hme_read32(hp, tregs + TCVR_CFG)));
1465 hme_write32(hp, tregs + TCVR_CFG,
1466 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1467 } else {
1468 HMD(("use bitbang old[%08x], ",
1469 hme_read32(hp, tregs + TCVR_CFG)));
1470 hme_write32(hp, tregs + TCVR_CFG,
1471 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1472 }
1473
1474 /* Check the state of the transceiver. */
1475 HMD(("to happy_meal_transceiver_check\n"));
1476 happy_meal_transceiver_check(hp, tregs);
1477
1478 /* Put the Big Mac into a sane state. */
1479 HMD(("happy_meal_init: "));
1480 switch(hp->tcvr_type) {
1481 case none:
1482 /* Cannot operate if we don't know the transceiver type! */
1483 HMD(("AAIEEE no transceiver type, EAGAIN"));
1484 return -EAGAIN;
1485
1486 case internal:
1487 /* Using the MII buffers. */
1488 HMD(("internal, using MII, "));
1489 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1490 break;
1491
1492 case external:
1493 /* Not using the MII, disable it. */
1494 HMD(("external, disable MII, "));
1495 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1496 break;
1497 };
1498
1499 if (happy_meal_tcvr_reset(hp, tregs))
1500 return -EAGAIN;
1501
1502 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1503 HMD(("tx/rx reset, "));
1504 happy_meal_tx_reset(hp, bregs);
1505 happy_meal_rx_reset(hp, bregs);
1506
1507 /* Set jam size and inter-packet gaps to reasonable defaults. */
1508 HMD(("jsize/ipg1/ipg2, "));
1509 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1510 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1511 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1512
1513 /* Load up the MAC address and random seed. */
1514 HMD(("rseed/macaddr, "));
1515
1516 /* The docs recommend to use the 10LSB of our MAC here. */
1517 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1518
1519 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1520 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1521 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1522
1523 HMD(("htable, "));
1524 if ((hp->dev->flags & IFF_ALLMULTI) ||
1525 (hp->dev->mc_count > 64)) {
1526 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1527 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1528 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1529 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1530 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1531 u16 hash_table[4];
1532 struct dev_mc_list *dmi = hp->dev->mc_list;
1533 char *addrs;
1534 int i;
1535 u32 crc;
1536
1537 for (i = 0; i < 4; i++)
1538 hash_table[i] = 0;
1539
1540 for (i = 0; i < hp->dev->mc_count; i++) {
1541 addrs = dmi->dmi_addr;
1542 dmi = dmi->next;
1543
1544 if (!(*addrs & 1))
1545 continue;
1546
1547 crc = ether_crc_le(6, addrs);
1548 crc >>= 26;
1549 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1550 }
1551 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1552 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1553 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1554 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1555 } else {
1556 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1557 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1558 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1559 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1560 }
1561
1562 /* Set the RX and TX ring ptrs. */
1563 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1564 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1565 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1566 hme_write32(hp, erxregs + ERX_RING,
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1568 hme_write32(hp, etxregs + ETX_RING,
1569 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1570
1571 /* Parity issues in the ERX unit of some HME revisions can cause some
1572 * registers to not be written unless their parity is even. Detect such
1573 * lost writes and simply rewrite with a low bit set (which will be ignored
1574 * since the rxring needs to be 2K aligned).
1575 */
1576 if (hme_read32(hp, erxregs + ERX_RING) !=
1577 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1578 hme_write32(hp, erxregs + ERX_RING,
1579 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1580 | 0x4);
1581
1582 /* Set the supported burst sizes. */
1583 HMD(("happy_meal_init: old[%08x] bursts<",
1584 hme_read32(hp, gregs + GREG_CFG)));
1585
9e326acf 1586#ifndef CONFIG_SPARC
1da177e4
LT		 1587 /* It is always PCI and can handle 64byte bursts. */
1588 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1589#else
1590 if ((hp->happy_bursts & DMA_BURST64) &&
1591 ((hp->happy_flags & HFLAG_PCI) != 0
1592#ifdef CONFIG_SBUS
1593 || sbus_can_burst64(hp->happy_dev)
1594#endif
1595 || 0)) {
1596 u32 gcfg = GREG_CFG_BURST64;
1597
1598 /* I have no idea if I should set the extended
1599 * transfer mode bit for Cheerio, so for now I
1600 * do not. -DaveM
1601 */
1602#ifdef CONFIG_SBUS
1603 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1604 sbus_can_dma_64bit(hp->happy_dev)) {
1605 sbus_set_sbus64(hp->happy_dev,
1606 hp->happy_bursts);
1607 gcfg |= GREG_CFG_64BIT;
1608 }
1609#endif
1610
1611 HMD(("64>"));
1612 hme_write32(hp, gregs + GREG_CFG, gcfg);
1613 } else if (hp->happy_bursts & DMA_BURST32) {
1614 HMD(("32>"));
1615 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1616 } else if (hp->happy_bursts & DMA_BURST16) {
1617 HMD(("16>"));
1618 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1619 } else {
1620 HMD(("XXX>"));
1621 hme_write32(hp, gregs + GREG_CFG, 0);
1622 }
9e326acf 1623#endif /* CONFIG_SPARC */
1da177e4
LT		 1624
1625 /* Turn off interrupts we do not want to hear. */
1626 HMD((", enable global interrupts, "));
1627 hme_write32(hp, gregs + GREG_IMASK,
1628 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1629 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1630
1631 /* Set the transmit ring buffer size. */
1632 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1633 hme_read32(hp, etxregs + ETX_RSIZE)));
1634 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1635
1636 /* Enable transmitter DVMA. */
1637 HMD(("tx dma enable old[%08x], ",
1638 hme_read32(hp, etxregs + ETX_CFG)));
1639 hme_write32(hp, etxregs + ETX_CFG,
1640 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1641
1642 /* This chip really rots, for the receiver sometimes when you
1643 * write to its control registers not all the bits get there
1644 * properly. I cannot think of a sane way to provide complete
1645 * coverage for this hardware bug yet.
1646 */
1647 HMD(("erx regs bug old[%08x]\n",
1648 hme_read32(hp, erxregs + ERX_CFG)));
1649 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1650 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1651 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1652 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1653 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1654 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1655 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1656 /* XXX Should return failure here... */
1657 }
1658
1659 /* Enable Big Mac hash table filter. */
1660 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1661 hme_read32(hp, bregs + BMAC_RXCFG)));
1662 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1663 if (hp->dev->flags & IFF_PROMISC)
1664 rxcfg |= BIGMAC_RXCFG_PMISC;
1665 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1666
1667 /* Let the bits settle in the chip. */
1668 udelay(10);
1669
1670 /* Ok, configure the Big Mac transmitter. */
1671 HMD(("BIGMAC init, "));
1672 regtmp = 0;
1673 if (hp->happy_flags & HFLAG_FULL)
1674 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1675
1676 /* Don't turn on the "don't give up" bit for now. It could cause hme
1677 * to deadlock with the PHY if a Jabber occurs.
1678 */
1679 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1680
1681 /* Give up after 16 TX attempts. */
1682 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1683
1684 /* Enable the output drivers no matter what. */
1685 regtmp = BIGMAC_XCFG_ODENABLE;
1686
1687 /* If card can do lance mode, enable it. */
1688 if (hp->happy_flags & HFLAG_LANCE)
1689 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1690
1691 /* Disable the MII buffers if using external transceiver. */
1692 if (hp->tcvr_type == external)
1693 regtmp |= BIGMAC_XCFG_MIIDISAB;
1694
1695 HMD(("XIF config old[%08x], ",
1696 hme_read32(hp, bregs + BMAC_XIFCFG)));
1697 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1698
1699 /* Start things up. */
1700 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1701 hme_read32(hp, bregs + BMAC_TXCFG),
1702 hme_read32(hp, bregs + BMAC_RXCFG)));
1703 hme_write32(hp, bregs + BMAC_TXCFG,
1704 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1705 hme_write32(hp, bregs + BMAC_RXCFG,
1706 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1707
1708 /* Get the autonegotiation started, and the watch timer ticking. */
1709 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1710
1711 /* Success. */
1712 return 0;
1713}
1714
1715/* hp->happy_lock must be held */
1716static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1717{
1718 void __iomem *tregs = hp->tcvregs;
1719 void __iomem *bregs = hp->bigmacregs;
1720 void __iomem *gregs = hp->gregs;
1721
1722 happy_meal_stop(hp, gregs);
1723 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1724 if (hp->happy_flags & HFLAG_FENABLE)
1725 hme_write32(hp, tregs + TCVR_CFG,
1726 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1727 else
1728 hme_write32(hp, tregs + TCVR_CFG,
1729 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1730 happy_meal_transceiver_check(hp, tregs);
1731 switch(hp->tcvr_type) {
1732 case none:
1733 return;
1734 case internal:
1735 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1736 break;
1737 case external:
1738 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1739 break;
1740 };
1741 if (happy_meal_tcvr_reset(hp, tregs))
1742 return;
1743
1744 /* Latch PHY registers as of now. */
1745 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1746 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1747
1748 /* Advertise everything we can support. */
1749 if (hp->sw_bmsr & BMSR_10HALF)
1750 hp->sw_advertise |= (ADVERTISE_10HALF);
1751 else
1752 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1753
1754 if (hp->sw_bmsr & BMSR_10FULL)
1755 hp->sw_advertise |= (ADVERTISE_10FULL);
1756 else
1757 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1758 if (hp->sw_bmsr & BMSR_100HALF)
1759 hp->sw_advertise |= (ADVERTISE_100HALF);
1760 else
1761 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1762 if (hp->sw_bmsr & BMSR_100FULL)
1763 hp->sw_advertise |= (ADVERTISE_100FULL);
1764 else
1765 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1766
1767 /* Update the PHY advertisement register. */
1768 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1769}
1770
1771/* Once status is latched (by happy_meal_interrupt) it is cleared by
1772 * the hardware, so we cannot re-read it and get a correct value.
1773 *
1774 * hp->happy_lock must be held
1775 */
1776static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1777{
1778 int reset = 0;
6aa20a22 1779
1da177e4
LT		 1780 /* Only print messages for non-counter related interrupts. */
1781 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1782 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1783 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1784 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1785 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1786 GREG_STAT_SLVPERR))
1787 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1788 hp->dev->name, status);
1789
1790 if (status & GREG_STAT_RFIFOVF) {
1791 /* Receive FIFO overflow is harmless and the hardware will take
1792 care of it, just some packets are lost. Who cares. */
1793 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1794 }
1795
1796 if (status & GREG_STAT_STSTERR) {
1797 /* BigMAC SQE link test failed. */
1798 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1799 reset = 1;
1800 }
1801
1802 if (status & GREG_STAT_TFIFO_UND) {
1803 /* Transmit FIFO underrun, again DMA error likely. */
1804 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1805 hp->dev->name);
1806 reset = 1;
1807 }
1808
1809 if (status & GREG_STAT_MAXPKTERR) {
1810 /* Driver error, tried to transmit something larger
1811 * than ethernet max mtu.
1812 */
1813 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1814 reset = 1;
1815 }
1816
1817 if (status & GREG_STAT_NORXD) {
1818 /* This is harmless, it just means the system is
1819 * quite loaded and the incoming packet rate was
1820 * faster than the interrupt handler could keep up
1821 * with.
1822 */
1823 printk(KERN_INFO "%s: Happy Meal out of receive "
1824 "descriptors, packet dropped.\n",
1825 hp->dev->name);
1826 }
1827
1828 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1829 /* All sorts of DMA receive errors. */
1830 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1831 if (status & GREG_STAT_RXERR)
1832 printk("GenericError ");
1833 if (status & GREG_STAT_RXPERR)
1834 printk("ParityError ");
1835 if (status & GREG_STAT_RXTERR)
1836 printk("RxTagBotch ");
1837 printk("]\n");
1838 reset = 1;
1839 }
1840
1841 if (status & GREG_STAT_EOPERR) {
1842 /* Driver bug, didn't set EOP bit in tx descriptor given
1843 * to the happy meal.
1844 */
1845 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1846 hp->dev->name);
1847 reset = 1;
1848 }
1849
1850 if (status & GREG_STAT_MIFIRQ) {
1851 /* MIF signalled an interrupt, were we polling it? */
1852 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1853 }
1854
1855 if (status &
1856 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1857 /* All sorts of transmit DMA errors. */
1858 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1859 if (status & GREG_STAT_TXEACK)
1860 printk("GenericError ");
1861 if (status & GREG_STAT_TXLERR)
1862 printk("LateError ");
1863 if (status & GREG_STAT_TXPERR)
1864 printk("ParityErro ");
1865 if (status & GREG_STAT_TXTERR)
1866 printk("TagBotch ");
1867 printk("]\n");
1868 reset = 1;
1869 }
1870
1871 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1872 /* Bus or parity error when cpu accessed happy meal registers
1873 * or it's internal FIFO's. Should never see this.
1874 */
1875 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1876 hp->dev->name,
1877 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1878 reset = 1;
1879 }
1880
1881 if (reset) {
1882 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1883 happy_meal_init(hp);
1884 return 1;
1885 }
1886 return 0;
1887}
1888
1889/* hp->happy_lock must be held */
1890static void happy_meal_mif_interrupt(struct happy_meal *hp)
1891{
1892 void __iomem *tregs = hp->tcvregs;
1893
1894 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1895 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1896 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1897
1898 /* Use the fastest transmission protocol possible. */
1899 if (hp->sw_lpa & LPA_100FULL) {
1900 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1901 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1902 } else if (hp->sw_lpa & LPA_100HALF) {
1903 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1904 hp->sw_bmcr |= BMCR_SPEED100;
1905 } else if (hp->sw_lpa & LPA_10FULL) {
1906 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1907 hp->sw_bmcr |= BMCR_FULLDPLX;
1908 } else {
1909 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1910 }
1911 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1912
1913 /* Finally stop polling and shut up the MIF. */
1914 happy_meal_poll_stop(hp, tregs);
1915}
1916
1917#ifdef TXDEBUG
1918#define TXD(x) printk x
1919#else
1920#define TXD(x)
1921#endif
1922
1923/* hp->happy_lock must be held */
1924static void happy_meal_tx(struct happy_meal *hp)
1925{
1926 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1927 struct happy_meal_txd *this;
1928 struct net_device *dev = hp->dev;
1929 int elem;
1930
1931 elem = hp->tx_old;
1932 TXD(("TX<"));
1933 while (elem != hp->tx_new) {
1934 struct sk_buff *skb;
1935 u32 flags, dma_addr, dma_len;
1936 int frag;
1937
1938 TXD(("[%d]", elem));
1939 this = &txbase[elem];
1940 flags = hme_read_desc32(hp, &this->tx_flags);
1941 if (flags & TXFLAG_OWN)
1942 break;
1943 skb = hp->tx_skbs[elem];
1944 if (skb_shinfo(skb)->nr_frags) {
1945 int last;
1946
1947 last = elem + skb_shinfo(skb)->nr_frags;
1948 last &= (TX_RING_SIZE - 1);
1949 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1950 if (flags & TXFLAG_OWN)
1951 break;
1952 }
1953 hp->tx_skbs[elem] = NULL;
1954 hp->net_stats.tx_bytes += skb->len;
1955
1956 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1957 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1958 dma_len = hme_read_desc32(hp, &this->tx_flags);
1959
1960 dma_len &= TXFLAG_SIZE;
1961 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1962
1963 elem = NEXT_TX(elem);
1964 this = &txbase[elem];
1965 }
1966
1967 dev_kfree_skb_irq(skb);
1968 hp->net_stats.tx_packets++;
1969 }
1970 hp->tx_old = elem;
1971 TXD((">"));
1972
1973 if (netif_queue_stopped(dev) &&
1974 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1975 netif_wake_queue(dev);
1976}
1977
1978#ifdef RXDEBUG
1979#define RXD(x) printk x
1980#else
1981#define RXD(x)
1982#endif
1983
1984/* Originally I used to handle the allocation failure by just giving back just
1985 * that one ring buffer to the happy meal. Problem is that usually when that
1986 * condition is triggered, the happy meal expects you to do something reasonable
1987 * with all of the packets it has DMA'd in. So now I just drop the entire
1988 * ring when we cannot get a new skb and give them all back to the happy meal,
1989 * maybe things will be "happier" now.
1990 *
1991 * hp->happy_lock must be held
1992 */
1993static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1994{
1995 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1996 struct happy_meal_rxd *this;
1997 int elem = hp->rx_new, drops = 0;
1998 u32 flags;
1999
2000 RXD(("RX<"));
2001 this = &rxbase[elem];
2002 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2003 struct sk_buff *skb;
2004 int len = flags >> 16;
2005 u16 csum = flags & RXFLAG_CSUM;
2006 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2007
2008 RXD(("[%d ", elem));
2009
2010 /* Check for errors. */
2011 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2012 RXD(("ERR(%08x)]", flags));
2013 hp->net_stats.rx_errors++;
2014 if (len < ETH_ZLEN)
2015 hp->net_stats.rx_length_errors++;
2016 if (len & (RXFLAG_OVERFLOW >> 16)) {
2017 hp->net_stats.rx_over_errors++;
2018 hp->net_stats.rx_fifo_errors++;
2019 }
2020
2021 /* Return it to the Happy meal. */
2022 drop_it:
2023 hp->net_stats.rx_dropped++;
2024 hme_write_rxd(hp, this,
2025 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2026 dma_addr);
2027 goto next;
2028 }
2029 skb = hp->rx_skbs[elem];
2030 if (len > RX_COPY_THRESHOLD) {
2031 struct sk_buff *new_skb;
2032
2033 /* Now refill the entry, if we can. */
2034 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2035 if (new_skb == NULL) {
2036 drops++;
2037 goto drop_it;
2038 }
2039 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2040 hp->rx_skbs[elem] = new_skb;
2041 new_skb->dev = dev;
2042 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2043 hme_write_rxd(hp, this,
2044 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2045 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2046 skb_reserve(new_skb, RX_OFFSET);
2047
2048 /* Trim the original skb for the netif. */
2049 skb_trim(skb, len);
2050 } else {
2051 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2052
2053 if (copy_skb == NULL) {
2054 drops++;
2055 goto drop_it;
2056 }
2057
1da177e4
LT		 2058 skb_reserve(copy_skb, 2);
2059 skb_put(copy_skb, len);
2060 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
d626f62b 2061 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 2062 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2063
2064 /* Reuse original ring buffer. */
2065 hme_write_rxd(hp, this,
2066 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2067 dma_addr);
2068
2069 skb = copy_skb;
2070 }
2071
2072 /* This card is _fucking_ hot... */
2073 skb->csum = ntohs(csum ^ 0xffff);
84fa7933 2074 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2075
2076 RXD(("len=%d csum=%4x]", len, csum));
2077 skb->protocol = eth_type_trans(skb, dev);
2078 netif_rx(skb);
2079
2080 dev->last_rx = jiffies;
2081 hp->net_stats.rx_packets++;
2082 hp->net_stats.rx_bytes += len;
2083 next:
2084 elem = NEXT_RX(elem);
2085 this = &rxbase[elem];
2086 }
2087 hp->rx_new = elem;
2088 if (drops)
2089 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2090 RXD((">"));
2091}
2092
7d12e780 2093static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
1da177e4 2094{
c31f28e7
JG		 2095 struct net_device *dev = dev_id;
2096 struct happy_meal *hp = netdev_priv(dev);
1da177e4
LT		 2097 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2098
2099 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2100
2101 spin_lock(&hp->happy_lock);
2102
2103 if (happy_status & GREG_STAT_ERRORS) {
2104 HMD(("ERRORS "));
2105 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2106 goto out;
2107 }
2108
2109 if (happy_status & GREG_STAT_MIFIRQ) {
2110 HMD(("MIFIRQ "));
2111 happy_meal_mif_interrupt(hp);
2112 }
2113
2114 if (happy_status & GREG_STAT_TXALL) {
2115 HMD(("TXALL "));
2116 happy_meal_tx(hp);
2117 }
2118
2119 if (happy_status & GREG_STAT_RXTOHOST) {
2120 HMD(("RXTOHOST "));
2121 happy_meal_rx(hp, dev);
2122 }
2123
2124 HMD(("done\n"));
2125out:
2126 spin_unlock(&hp->happy_lock);
2127
2128 return IRQ_HANDLED;
2129}
2130
2131#ifdef CONFIG_SBUS
7d12e780 2132static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
1da177e4
LT		 2133{
2134 struct quattro *qp = (struct quattro *) cookie;
2135 int i;
2136
2137 for (i = 0; i < 4; i++) {
2138 struct net_device *dev = qp->happy_meals[i];
2139 struct happy_meal *hp = dev->priv;
2140 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2141
2142 HMD(("quattro_interrupt: status=%08x ", happy_status));
2143
2144 if (!(happy_status & (GREG_STAT_ERRORS |
2145 GREG_STAT_MIFIRQ |
2146 GREG_STAT_TXALL |
2147 GREG_STAT_RXTOHOST)))
2148 continue;
2149
2150 spin_lock(&hp->happy_lock);
2151
2152 if (happy_status & GREG_STAT_ERRORS) {
2153 HMD(("ERRORS "));
2154 if (happy_meal_is_not_so_happy(hp, happy_status))
2155 goto next;
2156 }
2157
2158 if (happy_status & GREG_STAT_MIFIRQ) {
2159 HMD(("MIFIRQ "));
2160 happy_meal_mif_interrupt(hp);
2161 }
2162
2163 if (happy_status & GREG_STAT_TXALL) {
2164 HMD(("TXALL "));
2165 happy_meal_tx(hp);
2166 }
2167
2168 if (happy_status & GREG_STAT_RXTOHOST) {
2169 HMD(("RXTOHOST "));
2170 happy_meal_rx(hp, dev);
2171 }
2172
2173 next:
2174 spin_unlock(&hp->happy_lock);
2175 }
2176 HMD(("done\n"));
2177
2178 return IRQ_HANDLED;
2179}
2180#endif
2181
2182static int happy_meal_open(struct net_device *dev)
2183{
2184 struct happy_meal *hp = dev->priv;
2185 int res;
2186
2187 HMD(("happy_meal_open: "));
2188
2189 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2190 * into a single source which we register handling at probe time.
2191 */
2192 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2193 if (request_irq(dev->irq, &happy_meal_interrupt,
1fb9df5d 2194 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4 2195 HMD(("EAGAIN\n"));
1da177e4
LT		 2196 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2197 dev->irq);
1da177e4
LT		 2198
2199 return -EAGAIN;
2200 }
2201 }
2202
2203 HMD(("to happy_meal_init\n"));
2204
2205 spin_lock_irq(&hp->happy_lock);
2206 res = happy_meal_init(hp);
2207 spin_unlock_irq(&hp->happy_lock);
2208
2209 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2210 free_irq(dev->irq, dev);
2211 return res;
2212}
2213
2214static int happy_meal_close(struct net_device *dev)
2215{
2216 struct happy_meal *hp = dev->priv;
2217
2218 spin_lock_irq(&hp->happy_lock);
2219 happy_meal_stop(hp, hp->gregs);
2220 happy_meal_clean_rings(hp);
2221
2222 /* If auto-negotiation timer is running, kill it. */
2223 del_timer(&hp->happy_timer);
2224
2225 spin_unlock_irq(&hp->happy_lock);
2226
2227 /* On Quattro QFE cards, all hme interrupts are concentrated
2228 * into a single source which we register handling at probe
2229 * time and never unregister.
2230 */
2231 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2232 free_irq(dev->irq, dev);
2233
2234 return 0;
2235}
2236
2237#ifdef SXDEBUG
2238#define SXD(x) printk x
2239#else
2240#define SXD(x)
2241#endif
2242
2243static void happy_meal_tx_timeout(struct net_device *dev)
2244{
2245 struct happy_meal *hp = dev->priv;
2246
2247 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2248 tx_dump_log();
2249 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2250 hme_read32(hp, hp->gregs + GREG_STAT),
2251 hme_read32(hp, hp->etxregs + ETX_CFG),
2252 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2253
2254 spin_lock_irq(&hp->happy_lock);
2255 happy_meal_init(hp);
2256 spin_unlock_irq(&hp->happy_lock);
2257
2258 netif_wake_queue(dev);
2259}
2260
2261static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2262{
2263 struct happy_meal *hp = dev->priv;
2264 int entry;
2265 u32 tx_flags;
2266
2267 tx_flags = TXFLAG_OWN;
84fa7933 2268 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 2269 const u32 csum_start_off = skb_transport_offset(skb);
2270 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 2271
2272 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2273 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2274 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2275 }
2276
2277 spin_lock_irq(&hp->happy_lock);
2278
2279 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2280 netif_stop_queue(dev);
2281 spin_unlock_irq(&hp->happy_lock);
2282 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2283 dev->name);
2284 return 1;
2285 }
2286
2287 entry = hp->tx_new;
2288 SXD(("SX<l[%d]e[%d]>", len, entry));
2289 hp->tx_skbs[entry] = skb;
2290
2291 if (skb_shinfo(skb)->nr_frags == 0) {
2292 u32 mapping, len;
2293
2294 len = skb->len;
2295 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2296 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2297 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2298 (tx_flags | (len & TXFLAG_SIZE)),
2299 mapping);
2300 entry = NEXT_TX(entry);
2301 } else {
2302 u32 first_len, first_mapping;
2303 int frag, first_entry = entry;
2304
2305 /* We must give this initial chunk to the device last.
2306 * Otherwise we could race with the device.
2307 */
2308 first_len = skb_headlen(skb);
2309 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2310 entry = NEXT_TX(entry);
2311
2312 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2313 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2314 u32 len, mapping, this_txflags;
2315
2316 len = this_frag->size;
2317 mapping = hme_dma_map(hp,
2318 ((void *) page_address(this_frag->page) +
2319 this_frag->page_offset),
2320 len, DMA_TODEVICE);
2321 this_txflags = tx_flags;
2322 if (frag == skb_shinfo(skb)->nr_frags - 1)
2323 this_txflags |= TXFLAG_EOP;
2324 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2325 (this_txflags | (len & TXFLAG_SIZE)),
2326 mapping);
2327 entry = NEXT_TX(entry);
2328 }
2329 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2330 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2331 first_mapping);
2332 }
2333
2334 hp->tx_new = entry;
2335
2336 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2337 netif_stop_queue(dev);
2338
2339 /* Get it going. */
2340 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2341
2342 spin_unlock_irq(&hp->happy_lock);
2343
2344 dev->trans_start = jiffies;
2345
2346 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2347 return 0;
2348}
2349
2350static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2351{
2352 struct happy_meal *hp = dev->priv;
2353
2354 spin_lock_irq(&hp->happy_lock);
2355 happy_meal_get_counters(hp, hp->bigmacregs);
2356 spin_unlock_irq(&hp->happy_lock);
2357
2358 return &hp->net_stats;
2359}
2360
2361static void happy_meal_set_multicast(struct net_device *dev)
2362{
2363 struct happy_meal *hp = dev->priv;
2364 void __iomem *bregs = hp->bigmacregs;
2365 struct dev_mc_list *dmi = dev->mc_list;
2366 char *addrs;
2367 int i;
2368 u32 crc;
2369
2370 spin_lock_irq(&hp->happy_lock);
2371
2372 netif_stop_queue(dev);
2373
2374 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2375 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2376 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2377 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2378 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2379 } else if (dev->flags & IFF_PROMISC) {
2380 hme_write32(hp, bregs + BMAC_RXCFG,
2381 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2382 } else {
2383 u16 hash_table[4];
2384
2385 for (i = 0; i < 4; i++)
2386 hash_table[i] = 0;
2387
2388 for (i = 0; i < dev->mc_count; i++) {
2389 addrs = dmi->dmi_addr;
2390 dmi = dmi->next;
2391
2392 if (!(*addrs & 1))
2393 continue;
2394
2395 crc = ether_crc_le(6, addrs);
2396 crc >>= 26;
2397 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2398 }
2399 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2400 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2401 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2402 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2403 }
2404
2405 netif_wake_queue(dev);
2406
2407 spin_unlock_irq(&hp->happy_lock);
2408}
2409
2410/* Ethtool support... */
2411static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2412{
2413 struct happy_meal *hp = dev->priv;
2414
2415 cmd->supported =
2416 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2417 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2418 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2419
2420 /* XXX hardcoded stuff for now */
2421 cmd->port = PORT_TP; /* XXX no MII support */
2422 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2423 cmd->phy_address = 0; /* XXX fixed PHYAD */
2424
2425 /* Record PHY settings. */
2426 spin_lock_irq(&hp->happy_lock);
2427 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2428 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2429 spin_unlock_irq(&hp->happy_lock);
2430
2431 if (hp->sw_bmcr & BMCR_ANENABLE) {
2432 cmd->autoneg = AUTONEG_ENABLE;
2433 cmd->speed =
2434 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2435 SPEED_100 : SPEED_10;
2436 if (cmd->speed == SPEED_100)
2437 cmd->duplex =
2438 (hp->sw_lpa & (LPA_100FULL)) ?
2439 DUPLEX_FULL : DUPLEX_HALF;
2440 else
2441 cmd->duplex =
2442 (hp->sw_lpa & (LPA_10FULL)) ?
2443 DUPLEX_FULL : DUPLEX_HALF;
2444 } else {
2445 cmd->autoneg = AUTONEG_DISABLE;
2446 cmd->speed =
2447 (hp->sw_bmcr & BMCR_SPEED100) ?
2448 SPEED_100 : SPEED_10;
2449 cmd->duplex =
2450 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2451 DUPLEX_FULL : DUPLEX_HALF;
2452 }
2453 return 0;
2454}
2455
2456static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2457{
2458 struct happy_meal *hp = dev->priv;
2459
2460 /* Verify the settings we care about. */
2461 if (cmd->autoneg != AUTONEG_ENABLE &&
2462 cmd->autoneg != AUTONEG_DISABLE)
2463 return -EINVAL;
2464 if (cmd->autoneg == AUTONEG_DISABLE &&
2465 ((cmd->speed != SPEED_100 &&
2466 cmd->speed != SPEED_10) ||
2467 (cmd->duplex != DUPLEX_HALF &&
2468 cmd->duplex != DUPLEX_FULL)))
2469 return -EINVAL;
2470
2471 /* Ok, do it to it. */
2472 spin_lock_irq(&hp->happy_lock);
2473 del_timer(&hp->happy_timer);
2474 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2475 spin_unlock_irq(&hp->happy_lock);
2476
2477 return 0;
2478}
2479
2480static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2481{
2482 struct happy_meal *hp = dev->priv;
2483
2484 strcpy(info->driver, "sunhme");
2485 strcpy(info->version, "2.02");
2486 if (hp->happy_flags & HFLAG_PCI) {
2487 struct pci_dev *pdev = hp->happy_dev;
2488 strcpy(info->bus_info, pci_name(pdev));
2489 }
2490#ifdef CONFIG_SBUS
2491 else {
2492 struct sbus_dev *sdev = hp->happy_dev;
2493 sprintf(info->bus_info, "SBUS:%d",
2494 sdev->slot);
2495 }
2496#endif
2497}
2498
2499static u32 hme_get_link(struct net_device *dev)
2500{
2501 struct happy_meal *hp = dev->priv;
2502
2503 spin_lock_irq(&hp->happy_lock);
2504 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2505 spin_unlock_irq(&hp->happy_lock);
2506
2507 return (hp->sw_bmsr & BMSR_LSTATUS);
2508}
2509
7282d491 2510static const struct ethtool_ops hme_ethtool_ops = {
1da177e4
LT		 2511 .get_settings = hme_get_settings,
2512 .set_settings = hme_set_settings,
2513 .get_drvinfo = hme_get_drvinfo,
2514 .get_link = hme_get_link,
2515};
2516
2517static int hme_version_printed;
2518
2519#ifdef CONFIG_SBUS
6002e450 2520void __devinit quattro_get_ranges(struct quattro *qp)
1da177e4
LT		 2521{
2522 struct sbus_dev *sdev = qp->quattro_dev;
2523 int err;
2524
2525 err = prom_getproperty(sdev->prom_node,
2526 "ranges",
2527 (char *)&qp->ranges[0],
2528 sizeof(qp->ranges));
2529 if (err == 0 || err == -1) {
2530 qp->nranges = 0;
2531 return;
2532 }
2533 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2534}
2535
6002e450 2536static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
1da177e4
LT		 2537{
2538 struct sbus_dev *sdev = hp->happy_dev;
2539 int rng;
2540
2541 for (rng = 0; rng < qp->nranges; rng++) {
2542 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2543 int reg;
2544
2545 for (reg = 0; reg < 5; reg++) {
2546 if (sdev->reg_addrs[reg].which_io ==
2547 rngp->ot_child_space)
2548 break;
2549 }
2550 if (reg == 5)
2551 continue;
2552
2553 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2554 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2555 }
2556}
2557
2558/* Given a happy meal sbus device, find it's quattro parent.
2559 * If none exist, allocate and return a new one.
2560 *
2561 * Return NULL on failure.
2562 */
6002e450 2563static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
1da177e4 2564{
1da177e4
LT		 2565 struct sbus_dev *sdev;
2566 struct quattro *qp;
2567 int i;
2568
1da177e4
LT		 2569 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2570 for (i = 0, sdev = qp->quattro_dev;
2571 (sdev != NULL) && (i < 4);
2572 sdev = sdev->next, i++) {
2573 if (sdev == goal_sdev)
2574 return qp;
2575 }
2576 }
1da177e4 2577
1da177e4
LT		 2578 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2579 if (qp != NULL) {
2580 int i;
2581
2582 for (i = 0; i < 4; i++)
2583 qp->happy_meals[i] = NULL;
2584
2585 qp->quattro_dev = goal_sdev;
2586 qp->next = qfe_sbus_list;
2587 qfe_sbus_list = qp;
2588 quattro_get_ranges(qp);
2589 }
2590 return qp;
2591}
2592
2593/* After all quattro cards have been probed, we call these functions
2594 * to register the IRQ handlers.
2595 */
2596static void __init quattro_sbus_register_irqs(void)
2597{
2598 struct quattro *qp;
2599
2600 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2601 struct sbus_dev *sdev = qp->quattro_dev;
2602 int err;
2603
2604 err = request_irq(sdev->irqs[0],
2605 quattro_sbus_interrupt,
1fb9df5d 2606 IRQF_SHARED, "Quattro",
1da177e4
LT		 2607 qp);
2608 if (err != 0) {
2609 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2610 panic("QFE request irq");
2611 }
2612 }
2613}
050bbb19 2614
6002e450 2615static void quattro_sbus_free_irqs(void)
050bbb19
DM		 2616{
2617 struct quattro *qp;
2618
2619 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2620 struct sbus_dev *sdev = qp->quattro_dev;
2621
2622 free_irq(sdev->irqs[0], qp);
2623 }
2624}
1da177e4
LT		 2625#endif /* CONFIG_SBUS */
2626
2627#ifdef CONFIG_PCI
cd6f5b80 2628static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
1da177e4
LT		 2629{
2630 struct pci_dev *bdev = pdev->bus->self;
2631 struct quattro *qp;
2632
2633 if (!bdev) return NULL;
2634 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2635 struct pci_dev *qpdev = qp->quattro_dev;
2636
2637 if (qpdev == bdev)
2638 return qp;
2639 }
2640 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2641 if (qp != NULL) {
2642 int i;
2643
2644 for (i = 0; i < 4; i++)
2645 qp->happy_meals[i] = NULL;
2646
2647 qp->quattro_dev = bdev;
2648 qp->next = qfe_pci_list;
2649 qfe_pci_list = qp;
2650
2651 /* No range tricks necessary on PCI. */
2652 qp->nranges = 0;
2653 }
2654 return qp;
2655}
2656#endif /* CONFIG_PCI */
2657
2658#ifdef CONFIG_SBUS
6002e450 2659static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
1da177e4 2660{
050bbb19 2661 struct device_node *dp = sdev->ofdev.node;
1da177e4
LT		 2662 struct quattro *qp = NULL;
2663 struct happy_meal *hp;
2664 struct net_device *dev;
2665 int i, qfe_slot = -1;
2666 int err = -ENODEV;
2667
2668 if (is_qfe) {
2669 qp = quattro_sbus_find(sdev);
2670 if (qp == NULL)
2671 goto err_out;
2672 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2673 if (qp->happy_meals[qfe_slot] == NULL)
2674 break;
2675 if (qfe_slot == 4)
2676 goto err_out;
2677 }
2678
2679 err = -ENOMEM;
2680 dev = alloc_etherdev(sizeof(struct happy_meal));
2681 if (!dev)
2682 goto err_out;
2683 SET_MODULE_OWNER(dev);
050bbb19 2684 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
1da177e4
LT		 2685
2686 if (hme_version_printed++ == 0)
2687 printk(KERN_INFO "%s", version);
2688
2689 /* If user did not specify a MAC address specifically, use
2690 * the Quattro local-mac-address property...
2691 */
2692 for (i = 0; i < 6; i++) {
2693 if (macaddr[i] != 0)
2694 break;
2695 }
2696 if (i < 6) { /* a mac address was given */
2697 for (i = 0; i < 6; i++)
2698 dev->dev_addr[i] = macaddr[i];
2699 macaddr[5]++;
1da177e4 2700 } else {
ccf0dec6 2701 const unsigned char *addr;
050bbb19
DM		 2702 int len;
2703
2704 addr = of_get_property(dp, "local-mac-address", &len);
2705
2706 if (qfe_slot != -1 && addr && len == 6)
2707 memcpy(dev->dev_addr, addr, 6);
2708 else
2709 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
1da177e4
LT		 2710 }
2711
2712 hp = dev->priv;
2713
2714 hp->happy_dev = sdev;
2715
2716 spin_lock_init(&hp->happy_lock);
2717
2718 err = -ENODEV;
2719 if (sdev->num_registers != 5) {
050bbb19 2720 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
1da177e4 2721 sdev->num_registers);
1da177e4
LT		 2722 goto err_out_free_netdev;
2723 }
2724
2725 if (qp != NULL) {
2726 hp->qfe_parent = qp;
2727 hp->qfe_ent = qfe_slot;
2728 qp->happy_meals[qfe_slot] = dev;
2729 quattro_apply_ranges(qp, hp);
2730 }
2731
2732 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2733 GREG_REG_SIZE, "HME Global Regs");
2734 if (!hp->gregs) {
050bbb19 2735 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
1da177e4
LT		 2736 goto err_out_free_netdev;
2737 }
2738
2739 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2740 ETX_REG_SIZE, "HME TX Regs");
2741 if (!hp->etxregs) {
050bbb19 2742 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
1da177e4
LT		 2743 goto err_out_iounmap;
2744 }
2745
2746 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2747 ERX_REG_SIZE, "HME RX Regs");
2748 if (!hp->erxregs) {
050bbb19 2749 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
1da177e4
LT		 2750 goto err_out_iounmap;
2751 }
2752
2753 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2754 BMAC_REG_SIZE, "HME BIGMAC Regs");
2755 if (!hp->bigmacregs) {
050bbb19 2756 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
1da177e4
LT		 2757 goto err_out_iounmap;
2758 }
2759
2760 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2761 TCVR_REG_SIZE, "HME Tranceiver Regs");
2762 if (!hp->tcvregs) {
050bbb19 2763 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
1da177e4
LT		 2764 goto err_out_iounmap;
2765 }
2766
050bbb19 2767 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
1da177e4
LT		 2768 if (hp->hm_revision == 0xff)
2769 hp->hm_revision = 0xa0;
2770
2771 /* Now enable the feature flags we can. */
2772 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2773 hp->happy_flags = HFLAG_20_21;
2774 else if (hp->hm_revision != 0xa0)
2775 hp->happy_flags = HFLAG_NOT_A0;
2776
2777 if (qp != NULL)
2778 hp->happy_flags |= HFLAG_QUATTRO;
2779
2780 /* Get the supported DVMA burst sizes from our Happy SBUS. */
050bbb19
DM		 2781 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
2782 "burst-sizes", 0x00);
1da177e4
LT		 2783
2784 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2785 PAGE_SIZE,
2786 &hp->hblock_dvma);
2787 err = -ENOMEM;
2788 if (!hp->happy_block) {
2789 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2790 goto err_out_iounmap;
2791 }
2792
2793 /* Force check of the link first time we are brought up. */
2794 hp->linkcheck = 0;
2795
2796 /* Force timer state to 'asleep' with count of zero. */
2797 hp->timer_state = asleep;
2798 hp->timer_ticks = 0;
2799
2800 init_timer(&hp->happy_timer);
2801
2802 hp->dev = dev;
2803 dev->open = &happy_meal_open;
2804 dev->stop = &happy_meal_close;
2805 dev->hard_start_xmit = &happy_meal_start_xmit;
2806 dev->get_stats = &happy_meal_get_stats;
2807 dev->set_multicast_list = &happy_meal_set_multicast;
2808 dev->tx_timeout = &happy_meal_tx_timeout;
2809 dev->watchdog_timeo = 5*HZ;
2810 dev->ethtool_ops = &hme_ethtool_ops;
2811
2812 /* Happy Meal can do it all... except VLAN. */
2813 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2814
2815 dev->irq = sdev->irqs[0];
2816
2817#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2818 /* Hook up PCI register/dma accessors. */
2819 hp->read_desc32 = sbus_hme_read_desc32;
2820 hp->write_txd = sbus_hme_write_txd;
2821 hp->write_rxd = sbus_hme_write_rxd;
2822 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2823 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2824 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2825 sbus_dma_sync_single_for_cpu;
2826 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2827 sbus_dma_sync_single_for_device;
2828 hp->read32 = sbus_hme_read32;
2829 hp->write32 = sbus_hme_write32;
2830#endif
2831
2832 /* Grrr, Happy Meal comes up by default not advertising
2833 * full duplex 100baseT capabilities, fix this.
2834 */
2835 spin_lock_irq(&hp->happy_lock);
2836 happy_meal_set_initial_advertisement(hp);
2837 spin_unlock_irq(&hp->happy_lock);
2838
2839 if (register_netdev(hp->dev)) {
2840 printk(KERN_ERR "happymeal: Cannot register net device, "
2841 "aborting.\n");
2842 goto err_out_free_consistent;
2843 }
2844
050bbb19
DM		 2845 dev_set_drvdata(&sdev->ofdev.dev, hp);
2846
1da177e4
LT		 2847 if (qfe_slot != -1)
2848 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2849 dev->name, qfe_slot);
2850 else
2851 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2852 dev->name);
2853
2854 for (i = 0; i < 6; i++)
2855 printk("%2.2x%c",
2856 dev->dev_addr[i], i == 5 ? ' ' : ':');
2857 printk("\n");
2858
1da177e4
LT		 2859 return 0;
2860
2861err_out_free_consistent:
2862 sbus_free_consistent(hp->happy_dev,
2863 PAGE_SIZE,
2864 hp->happy_block,
2865 hp->hblock_dvma);
2866
2867err_out_iounmap:
2868 if (hp->gregs)
2869 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2870 if (hp->etxregs)
2871 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2872 if (hp->erxregs)
2873 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2874 if (hp->bigmacregs)
2875 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2876 if (hp->tcvregs)
2877 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2878
2879err_out_free_netdev:
2880 free_netdev(dev);
2881
2882err_out:
2883 return err;
2884}
2885#endif
2886
2887#ifdef CONFIG_PCI
9e326acf 2888#ifndef CONFIG_SPARC
1da177e4
LT		 2889static int is_quattro_p(struct pci_dev *pdev)
2890{
2891 struct pci_dev *busdev = pdev->bus->self;
2892 struct list_head *tmp;
2893 int n_hmes;
2894
2895 if (busdev == NULL ||
2896 busdev->vendor != PCI_VENDOR_ID_DEC ||
2897 busdev->device != PCI_DEVICE_ID_DEC_21153)
2898 return 0;
2899
2900 n_hmes = 0;
2901 tmp = pdev->bus->devices.next;
2902 while (tmp != &pdev->bus->devices) {
2903 struct pci_dev *this_pdev = pci_dev_b(tmp);
2904
2905 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2906 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2907 n_hmes++;
2908
2909 tmp = tmp->next;
2910 }
2911
2912 if (n_hmes != 4)
2913 return 0;
2914
2915 return 1;
2916}
2917
2918/* Fetch MAC address from vital product data of PCI ROM. */
ce1289ad 2919static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
1da177e4
LT		 2920{
2921 int this_offset;
2922
2923 for (this_offset = 0x20; this_offset < len; this_offset++) {
2924 void __iomem *p = rom_base + this_offset;
2925
2926 if (readb(p + 0) != 0x90 ||
2927 readb(p + 1) != 0x00 ||
2928 readb(p + 2) != 0x09 ||
2929 readb(p + 3) != 0x4e ||
2930 readb(p + 4) != 0x41 ||
2931 readb(p + 5) != 0x06)
2932 continue;
2933
2934 this_offset += 6;
2935 p += 6;
2936
2937 if (index == 0) {
2938 int i;
2939
2940 for (i = 0; i < 6; i++)
2941 dev_addr[i] = readb(p + i);
ce1289ad 2942 return 1;
1da177e4
LT		 2943 }
2944 index--;
2945 }
ce1289ad 2946 return 0;
1da177e4
LT		 2947}
2948
2949static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2950{
ce1289ad
WT		 2951 size_t size;
2952 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2953
ce1289ad
WT		 2954 if (p) {
2955 int index = 0;
2956 int found;
1da177e4 2957
ce1289ad
WT		 2958 if (is_quattro_p(pdev))
2959 index = PCI_SLOT(pdev->devfn);
1da177e4 2960
ce1289ad
WT		 2961 found = readb(p) == 0x55 &&
2962 readb(p + 1) == 0xaa &&
2963 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2964 pci_unmap_rom(pdev, p);
2965 if (found)
2966 return;
2967 }
1da177e4 2968
1da177e4
LT		 2969 /* Sun MAC prefix then 3 random bytes. */
2970 dev_addr[0] = 0x08;
2971 dev_addr[1] = 0x00;
2972 dev_addr[2] = 0x20;
2973 get_random_bytes(&dev_addr[3], 3);
2974 return;
2975}
9e326acf 2976#endif /* !(CONFIG_SPARC) */
1da177e4 2977
050bbb19
DM		 2978static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2979 const struct pci_device_id *ent)
1da177e4
LT		 2980{
2981 struct quattro *qp = NULL;
9e326acf 2982#ifdef CONFIG_SPARC
6f85a859 2983 struct device_node *dp;
1da177e4
LT		 2984#endif
2985 struct happy_meal *hp;
2986 struct net_device *dev;
2987 void __iomem *hpreg_base;
2988 unsigned long hpreg_res;
2989 int i, qfe_slot = -1;
2990 char prom_name[64];
2991 int err;
2992
2993 /* Now make sure pci_dev cookie is there. */
9e326acf 2994#ifdef CONFIG_SPARC
6f85a859
DM		 2995 dp = pci_device_to_OF_node(pdev);
2996 strcpy(prom_name, dp->name);
1da177e4
LT		 2997#else
2998 if (is_quattro_p(pdev))
2999 strcpy(prom_name, "SUNW,qfe");
3000 else
3001 strcpy(prom_name, "SUNW,hme");
3002#endif
3003
3004 err = -ENODEV;
ef9467f8
JS		 3005
3006 if (pci_enable_device(pdev))
3007 goto err_out;
3008 pci_set_master(pdev);
3009
1da177e4
LT		 3010 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3011 qp = quattro_pci_find(pdev);
3012 if (qp == NULL)
3013 goto err_out;
3014 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3015 if (qp->happy_meals[qfe_slot] == NULL)
3016 break;
3017 if (qfe_slot == 4)
3018 goto err_out;
3019 }
3020
3021 dev = alloc_etherdev(sizeof(struct happy_meal));
3022 err = -ENOMEM;
3023 if (!dev)
3024 goto err_out;
3025 SET_MODULE_OWNER(dev);
3026 SET_NETDEV_DEV(dev, &pdev->dev);
3027
3028 if (hme_version_printed++ == 0)
3029 printk(KERN_INFO "%s", version);
3030
3031 dev->base_addr = (long) pdev;
3032
3033 hp = (struct happy_meal *)dev->priv;
3034 memset(hp, 0, sizeof(*hp));
3035
3036 hp->happy_dev = pdev;
3037
3038 spin_lock_init(&hp->happy_lock);
3039
3040 if (qp != NULL) {
3041 hp->qfe_parent = qp;
3042 hp->qfe_ent = qfe_slot;
3043 qp->happy_meals[qfe_slot] = dev;
6aa20a22 3044 }
1da177e4
LT		 3045
3046 hpreg_res = pci_resource_start(pdev, 0);
3047 err = -ENODEV;
3048 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3049 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3050 goto err_out_clear_quattro;
3051 }
3052 if (pci_request_regions(pdev, DRV_NAME)) {
3053 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3054 "aborting.\n");
3055 goto err_out_clear_quattro;
3056 }
3057
3058 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3059 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3060 goto err_out_free_res;
3061 }
3062
3063 for (i = 0; i < 6; i++) {
3064 if (macaddr[i] != 0)
3065 break;
3066 }
3067 if (i < 6) { /* a mac address was given */
3068 for (i = 0; i < 6; i++)
3069 dev->dev_addr[i] = macaddr[i];
3070 macaddr[5]++;
3071 } else {
9e326acf 3072#ifdef CONFIG_SPARC
ccf0dec6 3073 const unsigned char *addr;
de8d28b1
DM		 3074 int len;
3075
1da177e4 3076 if (qfe_slot != -1 &&
6f85a859 3077 (addr = of_get_property(dp,
de8d28b1
DM		 3078 "local-mac-address", &len)) != NULL
3079 && len == 6) {
3080 memcpy(dev->dev_addr, addr, 6);
1da177e4
LT		 3081 } else {
3082 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3083 }
3084#else
3085 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3086#endif
3087 }
6aa20a22 3088
1da177e4
LT		 3089 /* Layout registers. */
3090 hp->gregs = (hpreg_base + 0x0000UL);
3091 hp->etxregs = (hpreg_base + 0x2000UL);
3092 hp->erxregs = (hpreg_base + 0x4000UL);
3093 hp->bigmacregs = (hpreg_base + 0x6000UL);
3094 hp->tcvregs = (hpreg_base + 0x7000UL);
3095
9e326acf 3096#ifdef CONFIG_SPARC
6f85a859 3097 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
44c10138
AK		 3098 if (hp->hm_revision == 0xff)
3099 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
1da177e4
LT		 3100#else
3101 /* works with this on non-sparc hosts */
3102 hp->hm_revision = 0x20;
3103#endif
3104
3105 /* Now enable the feature flags we can. */
3106 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3107 hp->happy_flags = HFLAG_20_21;
3108 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3109 hp->happy_flags = HFLAG_NOT_A0;
3110
3111 if (qp != NULL)
3112 hp->happy_flags |= HFLAG_QUATTRO;
3113
3114 /* And of course, indicate this is PCI. */
3115 hp->happy_flags |= HFLAG_PCI;
3116
9e326acf 3117#ifdef CONFIG_SPARC
1da177e4
LT		 3118 /* Assume PCI happy meals can handle all burst sizes. */
3119 hp->happy_bursts = DMA_BURSTBITS;
3120#endif
3121
3122 hp->happy_block = (struct hmeal_init_block *)
3123 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3124
3125 err = -ENODEV;
3126 if (!hp->happy_block) {
3127 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3128 goto err_out_iounmap;
3129 }
3130
3131 hp->linkcheck = 0;
3132 hp->timer_state = asleep;
3133 hp->timer_ticks = 0;
3134
3135 init_timer(&hp->happy_timer);
3136
3137 hp->dev = dev;
3138 dev->open = &happy_meal_open;
3139 dev->stop = &happy_meal_close;
3140 dev->hard_start_xmit = &happy_meal_start_xmit;
3141 dev->get_stats = &happy_meal_get_stats;
3142 dev->set_multicast_list = &happy_meal_set_multicast;
3143 dev->tx_timeout = &happy_meal_tx_timeout;
3144 dev->watchdog_timeo = 5*HZ;
3145 dev->ethtool_ops = &hme_ethtool_ops;
3146 dev->irq = pdev->irq;
3147 dev->dma = 0;
3148
3149 /* Happy Meal can do it all... */
3150 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3151
3152#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3153 /* Hook up PCI register/dma accessors. */
3154 hp->read_desc32 = pci_hme_read_desc32;
3155 hp->write_txd = pci_hme_write_txd;
3156 hp->write_rxd = pci_hme_write_rxd;
3157 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3158 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3159 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3160 pci_dma_sync_single_for_cpu;
3161 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3162 pci_dma_sync_single_for_device;
3163 hp->read32 = pci_hme_read32;
3164 hp->write32 = pci_hme_write32;
3165#endif
3166
3167 /* Grrr, Happy Meal comes up by default not advertising
3168 * full duplex 100baseT capabilities, fix this.
3169 */
3170 spin_lock_irq(&hp->happy_lock);
3171 happy_meal_set_initial_advertisement(hp);
3172 spin_unlock_irq(&hp->happy_lock);
3173
3174 if (register_netdev(hp->dev)) {
3175 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3176 "aborting.\n");
3177 goto err_out_iounmap;
3178 }
3179
050bbb19
DM		 3180 dev_set_drvdata(&pdev->dev, hp);
3181
1da177e4
LT		 3182 if (!qfe_slot) {
3183 struct pci_dev *qpdev = qp->quattro_dev;
3184
3185 prom_name[0] = 0;
3186 if (!strncmp(dev->name, "eth", 3)) {
3187 int i = simple_strtoul(dev->name + 3, NULL, 10);
3188 sprintf(prom_name, "-%d", i + 3);
3189 }
3190 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3191 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3192 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3193 printk("DEC 21153 PCI Bridge\n");
3194 else
6aa20a22 3195 printk("unknown bridge %04x.%04x\n",
1da177e4
LT		 3196 qpdev->vendor, qpdev->device);
3197 }
3198
3199 if (qfe_slot != -1)
3200 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3201 dev->name, qfe_slot);
3202 else
3203 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3204 dev->name);
3205
3206 for (i = 0; i < 6; i++)
3207 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3208
3209 printk("\n");
3210
1da177e4
LT		 3211 return 0;
3212
3213err_out_iounmap:
3214 iounmap(hp->gregs);
3215
3216err_out_free_res:
3217 pci_release_regions(pdev);
3218
3219err_out_clear_quattro:
3220 if (qp != NULL)
3221 qp->happy_meals[qfe_slot] = NULL;
3222
3223 free_netdev(dev);
3224
3225err_out:
3226 return err;
3227}
1da177e4 3228
050bbb19 3229static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
1da177e4 3230{
050bbb19
DM		 3231 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3232 struct net_device *net_dev = hp->dev;
1da177e4 3233
050bbb19
DM		 3234 unregister_netdev(net_dev);
3235
3236 pci_free_consistent(hp->happy_dev,
3237 PAGE_SIZE,
3238 hp->happy_block,
3239 hp->hblock_dvma);
3240 iounmap(hp->gregs);
3241 pci_release_regions(hp->happy_dev);
3242
3243 free_netdev(net_dev);
3244
3245 dev_set_drvdata(&pdev->dev, NULL);
1da177e4 3246}
1da177e4 3247
050bbb19 3248static struct pci_device_id happymeal_pci_ids[] = {
a0ee7c70 3249 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
050bbb19
DM		 3250 { } /* Terminating entry */
3251};
3252
3253MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3254
3255static struct pci_driver hme_pci_driver = {
3256 .name = "hme",
3257 .id_table = happymeal_pci_ids,
3258 .probe = happy_meal_pci_probe,
3259 .remove = __devexit_p(happy_meal_pci_remove),
3260};
3261
3262static int __init happy_meal_pci_init(void)
1da177e4 3263{
a0ee7c70 3264 return pci_register_driver(&hme_pci_driver);
050bbb19 3265}
1da177e4 3266
050bbb19
DM		 3267static void happy_meal_pci_exit(void)
3268{
3269 pci_unregister_driver(&hme_pci_driver);
3270
3271 while (qfe_pci_list) {
3272 struct quattro *qfe = qfe_pci_list;
3273 struct quattro *next = qfe->next;
3274
3275 kfree(qfe);
3276
3277 qfe_pci_list = next;
1da177e4 3278 }
1da177e4 3279}
050bbb19 3280
1da177e4
LT		 3281#endif
3282
050bbb19
DM		 3283#ifdef CONFIG_SBUS
3284static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1da177e4 3285{
050bbb19
DM		 3286 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
3287 struct device_node *dp = dev->node;
ccf0dec6 3288 const char *model = of_get_property(dp, "model", NULL);
050bbb19 3289 int is_qfe = (match->data != NULL);
1da177e4 3290
050bbb19
DM		 3291 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3292 is_qfe = 1;
1da177e4 3293
050bbb19
DM		 3294 return happy_meal_sbus_probe_one(sdev, is_qfe);
3295}
3296
3297static int __devexit hme_sbus_remove(struct of_device *dev)
3298{
3299 struct happy_meal *hp = dev_get_drvdata(&dev->dev);
3300 struct net_device *net_dev = hp->dev;
3301
c3b99f0d 3302 unregister_netdev(net_dev);
050bbb19
DM		 3303
3304 /* XXX qfe parent interrupt... */
3305
3306 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3307 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3308 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3309 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3310 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3311 sbus_free_consistent(hp->happy_dev,
3312 PAGE_SIZE,
3313 hp->happy_block,
3314 hp->hblock_dvma);
3315
3316 free_netdev(net_dev);
3317
3318 dev_set_drvdata(&dev->dev, NULL);
1da177e4 3319
1da177e4
LT		 3320 return 0;
3321}
3322
050bbb19
DM		 3323static struct of_device_id hme_sbus_match[] = {
3324 {
3325 .name = "SUNW,hme",
3326 },
3327 {
3328 .name = "SUNW,qfe",
3329 .data = (void *) 1,
3330 },
3331 {
3332 .name = "qfe",
3333 .data = (void *) 1,
3334 },
3335 {},
3336};
1da177e4 3337
050bbb19 3338MODULE_DEVICE_TABLE(of, hme_sbus_match);
1da177e4 3339
050bbb19
DM		 3340static struct of_platform_driver hme_sbus_driver = {
3341 .name = "hme",
3342 .match_table = hme_sbus_match,
3343 .probe = hme_sbus_probe,
3344 .remove = __devexit_p(hme_sbus_remove),
3345};
1da177e4 3346
050bbb19
DM		 3347static int __init happy_meal_sbus_init(void)
3348{
3349 int err;
1da177e4 3350
050bbb19
DM		 3351 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
3352 if (!err)
3353 quattro_sbus_register_irqs();
1da177e4 3354
050bbb19
DM		 3355 return err;
3356}
1da177e4 3357
050bbb19
DM		 3358static void happy_meal_sbus_exit(void)
3359{
3360 of_unregister_driver(&hme_sbus_driver);
3361 quattro_sbus_free_irqs();
1da177e4 3362
1da177e4
LT		 3363 while (qfe_sbus_list) {
3364 struct quattro *qfe = qfe_sbus_list;
3365 struct quattro *next = qfe->next;
3366
3367 kfree(qfe);
3368
3369 qfe_sbus_list = next;
3370 }
050bbb19 3371}
1da177e4 3372#endif
1da177e4 3373
050bbb19
DM		 3374static int __init happy_meal_probe(void)
3375{
3376 int err = 0;
1da177e4 3377
050bbb19
DM		 3378#ifdef CONFIG_SBUS
3379 err = happy_meal_sbus_init();
3380#endif
3381#ifdef CONFIG_PCI
3382 if (!err) {
3383 err = happy_meal_pci_init();
3384#ifdef CONFIG_SBUS
3385 if (err)
3386 happy_meal_sbus_exit();
3387#endif
1da177e4
LT		 3388 }
3389#endif
050bbb19
DM		 3390
3391 return err;
3392}
3393
3394
3395static void __exit happy_meal_exit(void)
3396{
3397#ifdef CONFIG_SBUS
3398 happy_meal_sbus_exit();
3399#endif
3400#ifdef CONFIG_PCI
3401 happy_meal_pci_exit();
3402#endif
1da177e4
LT		 3403}
3404
3405module_init(happy_meal_probe);
050bbb19 3406module_exit(happy_meal_exit);