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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sungem.c
CommitLineData
1da177e4
LT		 1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6aa20a22 5 *
1da177e4
LT		 6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
6aa20a22
JG		 12 *
13 * TODO:
1da177e4
LT		 14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
6aa20a22 19 *
1da177e4
LT		 20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/in.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/errno.h>
46#include <linux/pci.h>
1e7f0bd8 47#include <linux/dma-mapping.h>
1da177e4
LT		 48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/mii.h>
52#include <linux/ethtool.h>
53#include <linux/crc32.h>
54#include <linux/random.h>
55#include <linux/workqueue.h>
56#include <linux/if_vlan.h>
57#include <linux/bitops.h>
e3968fc0 58#include <linux/mutex.h>
1da177e4
LT		 59
60#include <asm/system.h>
61#include <asm/io.h>
62#include <asm/byteorder.h>
63#include <asm/uaccess.h>
64#include <asm/irq.h>
65
66#ifdef __sparc__
67#include <asm/idprom.h>
68#include <asm/openprom.h>
69#include <asm/oplib.h>
70#include <asm/pbm.h>
71#endif
72
73#ifdef CONFIG_PPC_PMAC
74#include <asm/pci-bridge.h>
75#include <asm/prom.h>
76#include <asm/machdep.h>
77#include <asm/pmac_feature.h>
78#endif
79
80#include "sungem_phy.h"
81#include "sungem.h"
82
83/* Stripping FCS is causing problems, disabled for now */
84#undef STRIP_FCS
85
86#define DEFAULT_MSG (NETIF_MSG_DRV | \
87 NETIF_MSG_PROBE | \
88 NETIF_MSG_LINK)
89
90#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
91 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
92 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
93
94#define DRV_NAME "sungem"
95#define DRV_VERSION "0.98"
96#define DRV_RELDATE "8/24/03"
97#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102MODULE_AUTHOR(DRV_AUTHOR);
103MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104MODULE_LICENSE("GPL");
105
106#define GEM_MODULE_NAME "gem"
107#define PFX GEM_MODULE_NAME ": "
108
109static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
6aa20a22 116 *
1da177e4
LT		 117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7fce260a
OJ		 132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 134 {0, }
135};
136
137MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140{
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
151 while (limit--) {
152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163}
164
165static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166{
167 struct gem *gp = dev->priv;
168 return __phy_read(gp, mii_id, reg);
169}
170
171static inline u16 phy_read(struct gem *gp, int reg)
172{
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174}
175
176static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177{
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196}
197
198static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199{
200 struct gem *gp = dev->priv;
201 __phy_write(gp, mii_id, reg, val & 0xffff);
202}
203
204static inline void phy_write(struct gem *gp, int reg, u16 val)
205{
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207}
208
209static inline void gem_enable_ints(struct gem *gp)
210{
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213}
214
215static inline void gem_disable_ints(struct gem *gp)
216{
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219}
220
221static void gem_get_cell(struct gem *gp)
222{
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225#ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231#endif /* CONFIG_PPC_PMAC */
232}
233
234/* Turn off the chip's clock */
235static void gem_put_cell(struct gem *gp)
236{
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239#ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245#endif /* CONFIG_PPC_PMAC */
246}
247
248static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249{
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252}
253
254static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255{
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307}
308
309static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310{
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356}
357
358/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364static int gem_rxmac_reset(struct gem *gp)
365{
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467}
468
469static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470{
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502}
503
504static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505{
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523}
524
525static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526{
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536}
537
538static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539{
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601}
602
603/* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609{
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665}
666
667static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668{
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725}
726
727static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728{
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755}
756
757static int gem_rx(struct gem *gp, int work_to_do)
758{
759 int entry, drops, work_done = 0;
760 u32 done;
761
762 if (netif_msg_rx_status(gp))
763 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
764 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
765
766 entry = gp->rx_new;
767 drops = 0;
768 done = readl(gp->regs + RXDMA_DONE);
769 for (;;) {
770 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
771 struct sk_buff *skb;
772 u64 status = cpu_to_le64(rxd->status_word);
773 dma_addr_t dma_addr;
774 int len;
775
776 if ((status & RXDCTRL_OWN) != 0)
777 break;
778
779 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
780 break;
781
782 /* When writing back RX descriptor, GEM writes status
783 * then buffer address, possibly in seperate transactions.
784 * If we don't wait for the chip to write both, we could
785 * post a new buffer to this descriptor then have GEM spam
786 * on the buffer address. We sync on the RX completion
787 * register to prevent this from happening.
788 */
789 if (entry == done) {
790 done = readl(gp->regs + RXDMA_DONE);
791 if (entry == done)
792 break;
793 }
794
795 /* We can now account for the work we're about to do */
796 work_done++;
797
798 skb = gp->rx_skbs[entry];
799
800 len = (status & RXDCTRL_BUFSZ) >> 16;
801 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
802 gp->net_stats.rx_errors++;
803 if (len < ETH_ZLEN)
804 gp->net_stats.rx_length_errors++;
805 if (len & RXDCTRL_BAD)
806 gp->net_stats.rx_crc_errors++;
807
808 /* We'll just return it to GEM. */
809 drop_it:
810 gp->net_stats.rx_dropped++;
811 goto next;
812 }
813
814 dma_addr = cpu_to_le64(rxd->buffer);
815 if (len > RX_COPY_THRESHOLD) {
816 struct sk_buff *new_skb;
817
818 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
819 if (new_skb == NULL) {
820 drops++;
821 goto drop_it;
822 }
823 pci_unmap_page(gp->pdev, dma_addr,
824 RX_BUF_ALLOC_SIZE(gp),
825 PCI_DMA_FROMDEVICE);
826 gp->rx_skbs[entry] = new_skb;
827 new_skb->dev = gp->dev;
828 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
829 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
830 virt_to_page(new_skb->data),
831 offset_in_page(new_skb->data),
832 RX_BUF_ALLOC_SIZE(gp),
833 PCI_DMA_FROMDEVICE));
834 skb_reserve(new_skb, RX_OFFSET);
835
836 /* Trim the original skb for the netif. */
837 skb_trim(skb, len);
838 } else {
839 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
840
841 if (copy_skb == NULL) {
842 drops++;
843 goto drop_it;
844 }
845
846 copy_skb->dev = gp->dev;
847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
850 memcpy(copy_skb->data, skb->data, len);
851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
857 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
84fa7933 858 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 859 skb->protocol = eth_type_trans(skb, gp->dev);
860
861 netif_receive_skb(skb);
862
863 gp->net_stats.rx_packets++;
864 gp->net_stats.rx_bytes += len;
865 gp->dev->last_rx = jiffies;
866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
877 gp->dev->name);
878
879 return work_done;
880}
881
882static int gem_poll(struct net_device *dev, int *budget)
883{
884 struct gem *gp = dev->priv;
885 unsigned long flags;
886
887 /*
6aa20a22 888 * NAPI locking nightmare: See comment at head of driver
1da177e4
LT		 889 */
890 spin_lock_irqsave(&gp->lock, flags);
891
892 do {
893 int work_to_do, work_done;
894
895 /* Handle anomalies */
896 if (gp->status & GREG_STAT_ABNORMAL) {
897 if (gem_abnormal_irq(dev, gp, gp->status))
898 break;
899 }
900
901 /* Run TX completion thread */
902 spin_lock(&gp->tx_lock);
903 gem_tx(dev, gp, gp->status);
904 spin_unlock(&gp->tx_lock);
905
906 spin_unlock_irqrestore(&gp->lock, flags);
907
6aa20a22
JG		 908 /* Run RX thread. We don't use any locking here,
909 * code willing to do bad things - like cleaning the
1da177e4
LT		 910 * rx ring - must call netif_poll_disable(), which
911 * schedule_timeout()'s if polling is already disabled.
912 */
913 work_to_do = min(*budget, dev->quota);
914
915 work_done = gem_rx(gp, work_to_do);
916
917 *budget -= work_done;
918 dev->quota -= work_done;
919
920 if (work_done >= work_to_do)
921 return 1;
922
923 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 924
1da177e4
LT		 925 gp->status = readl(gp->regs + GREG_STAT);
926 } while (gp->status & GREG_STAT_NAPI);
927
928 __netif_rx_complete(dev);
929 gem_enable_ints(gp);
930
931 spin_unlock_irqrestore(&gp->lock, flags);
932 return 0;
933}
934
7d12e780 935static irqreturn_t gem_interrupt(int irq, void *dev_id)
1da177e4
LT		 936{
937 struct net_device *dev = dev_id;
938 struct gem *gp = dev->priv;
939 unsigned long flags;
940
941 /* Swallow interrupts when shutting the chip down, though
942 * that shouldn't happen, we should have done free_irq() at
943 * this point...
944 */
945 if (!gp->running)
946 return IRQ_HANDLED;
947
948 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 949
1da177e4
LT		 950 if (netif_rx_schedule_prep(dev)) {
951 u32 gem_status = readl(gp->regs + GREG_STAT);
952
953 if (gem_status == 0) {
86d9f7f0 954 netif_poll_enable(dev);
1da177e4
LT		 955 spin_unlock_irqrestore(&gp->lock, flags);
956 return IRQ_NONE;
957 }
958 gp->status = gem_status;
959 gem_disable_ints(gp);
960 __netif_rx_schedule(dev);
961 }
962
963 spin_unlock_irqrestore(&gp->lock, flags);
6aa20a22 964
1da177e4 965 /* If polling was disabled at the time we received that
6aa20a22 966 * interrupt, we may return IRQ_HANDLED here while we
1da177e4
LT		 967 * should return IRQ_NONE. No big deal...
968 */
969 return IRQ_HANDLED;
970}
971
972#ifdef CONFIG_NET_POLL_CONTROLLER
973static void gem_poll_controller(struct net_device *dev)
974{
975 /* gem_interrupt is safe to reentrance so no need
976 * to disable_irq here.
977 */
7d12e780 978 gem_interrupt(dev->irq, dev);
1da177e4
LT		 979}
980#endif
981
982static void gem_tx_timeout(struct net_device *dev)
983{
984 struct gem *gp = dev->priv;
985
986 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
987 if (!gp->running) {
988 printk("%s: hrm.. hw not running !\n", dev->name);
989 return;
990 }
991 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
992 dev->name,
993 readl(gp->regs + TXDMA_CFG),
994 readl(gp->regs + MAC_TXSTAT),
995 readl(gp->regs + MAC_TXCFG));
996 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
997 dev->name,
998 readl(gp->regs + RXDMA_CFG),
999 readl(gp->regs + MAC_RXSTAT),
1000 readl(gp->regs + MAC_RXCFG));
1001
1002 spin_lock_irq(&gp->lock);
1003 spin_lock(&gp->tx_lock);
1004
1005 gp->reset_task_pending = 1;
1006 schedule_work(&gp->reset_task);
1007
1008 spin_unlock(&gp->tx_lock);
1009 spin_unlock_irq(&gp->lock);
1010}
1011
1012static __inline__ int gem_intme(int entry)
1013{
1014 /* Algorithm: IRQ every 1/2 of descriptors. */
1015 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1016 return 1;
1017
1018 return 0;
1019}
1020
1021static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1022{
1023 struct gem *gp = dev->priv;
1024 int entry;
1025 u64 ctrl;
1026 unsigned long flags;
1027
1028 ctrl = 0;
84fa7933 1029 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 1030 u64 csum_start_off, csum_stuff_off;
1031
1032 csum_start_off = (u64) (skb->h.raw - skb->data);
1033 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
1034
1035 ctrl = (TXDCTRL_CENAB |
1036 (csum_start_off << 15) |
1037 (csum_stuff_off << 21));
1038 }
1039
1040 local_irq_save(flags);
1041 if (!spin_trylock(&gp->tx_lock)) {
1042 /* Tell upper layer to requeue */
1043 local_irq_restore(flags);
1044 return NETDEV_TX_LOCKED;
1045 }
1046 /* We raced with gem_do_stop() */
1047 if (!gp->running) {
1048 spin_unlock_irqrestore(&gp->tx_lock, flags);
1049 return NETDEV_TX_BUSY;
1050 }
1051
1052 /* This is a hard error, log it. */
1053 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1054 netif_stop_queue(dev);
1055 spin_unlock_irqrestore(&gp->tx_lock, flags);
1056 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1057 dev->name);
1058 return NETDEV_TX_BUSY;
1059 }
1060
1061 entry = gp->tx_new;
1062 gp->tx_skbs[entry] = skb;
1063
1064 if (skb_shinfo(skb)->nr_frags == 0) {
1065 struct gem_txd *txd = &gp->init_block->txd[entry];
1066 dma_addr_t mapping;
1067 u32 len;
1068
1069 len = skb->len;
1070 mapping = pci_map_page(gp->pdev,
1071 virt_to_page(skb->data),
1072 offset_in_page(skb->data),
1073 len, PCI_DMA_TODEVICE);
1074 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1075 if (gem_intme(entry))
1076 ctrl |= TXDCTRL_INTME;
1077 txd->buffer = cpu_to_le64(mapping);
1078 wmb();
1079 txd->control_word = cpu_to_le64(ctrl);
1080 entry = NEXT_TX(entry);
1081 } else {
1082 struct gem_txd *txd;
1083 u32 first_len;
1084 u64 intme;
1085 dma_addr_t first_mapping;
1086 int frag, first_entry = entry;
1087
1088 intme = 0;
1089 if (gem_intme(entry))
1090 intme |= TXDCTRL_INTME;
1091
1092 /* We must give this initial chunk to the device last.
1093 * Otherwise we could race with the device.
1094 */
1095 first_len = skb_headlen(skb);
1096 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1097 offset_in_page(skb->data),
1098 first_len, PCI_DMA_TODEVICE);
1099 entry = NEXT_TX(entry);
1100
1101 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1102 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1103 u32 len;
1104 dma_addr_t mapping;
1105 u64 this_ctrl;
1106
1107 len = this_frag->size;
1108 mapping = pci_map_page(gp->pdev,
1109 this_frag->page,
1110 this_frag->page_offset,
1111 len, PCI_DMA_TODEVICE);
1112 this_ctrl = ctrl;
1113 if (frag == skb_shinfo(skb)->nr_frags - 1)
1114 this_ctrl |= TXDCTRL_EOF;
6aa20a22 1115
1da177e4
LT		 1116 txd = &gp->init_block->txd[entry];
1117 txd->buffer = cpu_to_le64(mapping);
1118 wmb();
1119 txd->control_word = cpu_to_le64(this_ctrl | len);
1120
1121 if (gem_intme(entry))
1122 intme |= TXDCTRL_INTME;
1123
1124 entry = NEXT_TX(entry);
1125 }
1126 txd = &gp->init_block->txd[first_entry];
1127 txd->buffer = cpu_to_le64(first_mapping);
1128 wmb();
1129 txd->control_word =
1130 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1131 }
1132
1133 gp->tx_new = entry;
1134 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1135 netif_stop_queue(dev);
1136
1137 if (netif_msg_tx_queued(gp))
1138 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1139 dev->name, entry, skb->len);
1140 mb();
1141 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1142 spin_unlock_irqrestore(&gp->tx_lock, flags);
1143
1144 dev->trans_start = jiffies;
1145
1146 return NETDEV_TX_OK;
1147}
1148
1149#define STOP_TRIES 32
1150
1151/* Must be invoked under gp->lock and gp->tx_lock. */
1152static void gem_reset(struct gem *gp)
1153{
1154 int limit;
1155 u32 val;
1156
1157 /* Make sure we won't get any more interrupts */
1158 writel(0xffffffff, gp->regs + GREG_IMASK);
1159
1160 /* Reset the chip */
1161 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1162 gp->regs + GREG_SWRST);
1163
1164 limit = STOP_TRIES;
1165
1166 do {
1167 udelay(20);
1168 val = readl(gp->regs + GREG_SWRST);
1169 if (limit-- <= 0)
1170 break;
1171 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1172
1173 if (limit <= 0)
1174 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1175}
1176
1177/* Must be invoked under gp->lock and gp->tx_lock. */
1178static void gem_start_dma(struct gem *gp)
1179{
1180 u32 val;
6aa20a22 1181
1da177e4
LT		 1182 /* We are ready to rock, turn everything on. */
1183 val = readl(gp->regs + TXDMA_CFG);
1184 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1185 val = readl(gp->regs + RXDMA_CFG);
1186 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1187 val = readl(gp->regs + MAC_TXCFG);
1188 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1189 val = readl(gp->regs + MAC_RXCFG);
1190 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1191
1192 (void) readl(gp->regs + MAC_RXCFG);
1193 udelay(100);
1194
1195 gem_enable_ints(gp);
1196
1197 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1198}
1199
1200/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1201 * actually stopped before about 4ms tho ...
1202 */
1203static void gem_stop_dma(struct gem *gp)
1204{
1205 u32 val;
1206
1207 /* We are done rocking, turn everything off. */
1208 val = readl(gp->regs + TXDMA_CFG);
1209 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1210 val = readl(gp->regs + RXDMA_CFG);
1211 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1212 val = readl(gp->regs + MAC_TXCFG);
1213 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1214 val = readl(gp->regs + MAC_RXCFG);
1215 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1216
1217 (void) readl(gp->regs + MAC_RXCFG);
1218
1219 /* Need to wait a bit ... done by the caller */
1220}
1221
1222
1223/* Must be invoked under gp->lock and gp->tx_lock. */
1224// XXX dbl check what that function should do when called on PCS PHY
1225static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1226{
1227 u32 advertise, features;
1228 int autoneg;
1229 int speed;
1230 int duplex;
1231
1232 if (gp->phy_type != phy_mii_mdio0 &&
1233 gp->phy_type != phy_mii_mdio1)
1234 goto non_mii;
1235
1236 /* Setup advertise */
1237 if (found_mii_phy(gp))
1238 features = gp->phy_mii.def->features;
1239 else
1240 features = 0;
1241
1242 advertise = features & ADVERTISE_MASK;
1243 if (gp->phy_mii.advertising != 0)
1244 advertise &= gp->phy_mii.advertising;
1245
1246 autoneg = gp->want_autoneg;
1247 speed = gp->phy_mii.speed;
1248 duplex = gp->phy_mii.duplex;
6aa20a22 1249
1da177e4
LT		 1250 /* Setup link parameters */
1251 if (!ep)
1252 goto start_aneg;
1253 if (ep->autoneg == AUTONEG_ENABLE) {
1254 advertise = ep->advertising;
1255 autoneg = 1;
1256 } else {
1257 autoneg = 0;
1258 speed = ep->speed;
1259 duplex = ep->duplex;
1260 }
1261
1262start_aneg:
1263 /* Sanitize settings based on PHY capabilities */
1264 if ((features & SUPPORTED_Autoneg) == 0)
1265 autoneg = 0;
1266 if (speed == SPEED_1000 &&
1267 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1268 speed = SPEED_100;
1269 if (speed == SPEED_100 &&
1270 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1271 speed = SPEED_10;
1272 if (duplex == DUPLEX_FULL &&
1273 !(features & (SUPPORTED_1000baseT_Full |
1274 SUPPORTED_100baseT_Full |
1275 SUPPORTED_10baseT_Full)))
1276 duplex = DUPLEX_HALF;
1277 if (speed == 0)
1278 speed = SPEED_10;
6aa20a22 1279
1da177e4
LT		 1280 /* If we are asleep, we don't try to actually setup the PHY, we
1281 * just store the settings
1282 */
1283 if (gp->asleep) {
1284 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1285 gp->phy_mii.speed = speed;
1286 gp->phy_mii.duplex = duplex;
1287 return;
1288 }
1289
1290 /* Configure PHY & start aneg */
1291 gp->want_autoneg = autoneg;
1292 if (autoneg) {
1293 if (found_mii_phy(gp))
1294 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1295 gp->lstate = link_aneg;
1296 } else {
1297 if (found_mii_phy(gp))
1298 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1299 gp->lstate = link_force_ok;
1300 }
1301
1302non_mii:
1303 gp->timer_ticks = 0;
1304 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1305}
1306
1307/* A link-up condition has occurred, initialize and enable the
1308 * rest of the chip.
1309 *
1310 * Must be invoked under gp->lock and gp->tx_lock.
1311 */
1312static int gem_set_link_modes(struct gem *gp)
1313{
1314 u32 val;
1315 int full_duplex, speed, pause;
1316
1317 full_duplex = 0;
1318 speed = SPEED_10;
1319 pause = 0;
1320
1321 if (found_mii_phy(gp)) {
1322 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1323 return 1;
1324 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1325 speed = gp->phy_mii.speed;
1326 pause = gp->phy_mii.pause;
1327 } else if (gp->phy_type == phy_serialink ||
1328 gp->phy_type == phy_serdes) {
1329 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1330
1331 if (pcs_lpa & PCS_MIIADV_FD)
1332 full_duplex = 1;
1333 speed = SPEED_1000;
1334 }
1335
1336 if (netif_msg_link(gp))
1337 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1338 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1339
1340 if (!gp->running)
1341 return 0;
1342
1343 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1344 if (full_duplex) {
1345 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1346 } else {
1347 /* MAC_TXCFG_NBO must be zero. */
6aa20a22 1348 }
1da177e4
LT		 1349 writel(val, gp->regs + MAC_TXCFG);
1350
1351 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1352 if (!full_duplex &&
1353 (gp->phy_type == phy_mii_mdio0 ||
1354 gp->phy_type == phy_mii_mdio1)) {
1355 val |= MAC_XIFCFG_DISE;
1356 } else if (full_duplex) {
1357 val |= MAC_XIFCFG_FLED;
1358 }
1359
1360 if (speed == SPEED_1000)
1361 val |= (MAC_XIFCFG_GMII);
1362
1363 writel(val, gp->regs + MAC_XIFCFG);
1364
1365 /* If gigabit and half-duplex, enable carrier extension
1366 * mode. Else, disable it.
1367 */
1368 if (speed == SPEED_1000 && !full_duplex) {
1369 val = readl(gp->regs + MAC_TXCFG);
1370 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1371
1372 val = readl(gp->regs + MAC_RXCFG);
1373 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1374 } else {
1375 val = readl(gp->regs + MAC_TXCFG);
1376 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1377
1378 val = readl(gp->regs + MAC_RXCFG);
1379 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1380 }
1381
1382 if (gp->phy_type == phy_serialink ||
1383 gp->phy_type == phy_serdes) {
1384 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1385
1386 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1387 pause = 1;
1388 }
1389
1390 if (netif_msg_link(gp)) {
1391 if (pause) {
1392 printk(KERN_INFO "%s: Pause is enabled "
1393 "(rxfifo: %d off: %d on: %d)\n",
1394 gp->dev->name,
1395 gp->rx_fifo_sz,
1396 gp->rx_pause_off,
1397 gp->rx_pause_on);
1398 } else {
1399 printk(KERN_INFO "%s: Pause is disabled\n",
1400 gp->dev->name);
1401 }
1402 }
1403
1404 if (!full_duplex)
1405 writel(512, gp->regs + MAC_STIME);
1406 else
1407 writel(64, gp->regs + MAC_STIME);
1408 val = readl(gp->regs + MAC_MCCFG);
1409 if (pause)
1410 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1411 else
1412 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1413 writel(val, gp->regs + MAC_MCCFG);
1414
1415 gem_start_dma(gp);
1416
1417 return 0;
1418}
1419
1420/* Must be invoked under gp->lock and gp->tx_lock. */
1421static int gem_mdio_link_not_up(struct gem *gp)
1422{
1423 switch (gp->lstate) {
1424 case link_force_ret:
1425 if (netif_msg_link(gp))
1426 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1427 " forced mode\n", gp->dev->name);
1428 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1429 gp->last_forced_speed, DUPLEX_HALF);
1430 gp->timer_ticks = 5;
1431 gp->lstate = link_force_ok;
1432 return 0;
1433 case link_aneg:
1434 /* We try forced modes after a failed aneg only on PHYs that don't
1435 * have "magic_aneg" bit set, which means they internally do the
1436 * while forced-mode thingy. On these, we just restart aneg
1437 */
1438 if (gp->phy_mii.def->magic_aneg)
1439 return 1;
1440 if (netif_msg_link(gp))
1441 printk(KERN_INFO "%s: switching to forced 100bt\n",
1442 gp->dev->name);
1443 /* Try forced modes. */
1444 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1445 DUPLEX_HALF);
1446 gp->timer_ticks = 5;
1447 gp->lstate = link_force_try;
1448 return 0;
1449 case link_force_try:
1450 /* Downgrade from 100 to 10 Mbps if necessary.
1451 * If already at 10Mbps, warn user about the
1452 * situation every 10 ticks.
1453 */
1454 if (gp->phy_mii.speed == SPEED_100) {
1455 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1456 DUPLEX_HALF);
1457 gp->timer_ticks = 5;
1458 if (netif_msg_link(gp))
1459 printk(KERN_INFO "%s: switching to forced 10bt\n",
1460 gp->dev->name);
1461 return 0;
1462 } else
1463 return 1;
1464 default:
1465 return 0;
1466 }
1467}
1468
1469static void gem_link_timer(unsigned long data)
1470{
1471 struct gem *gp = (struct gem *) data;
1472 int restart_aneg = 0;
6aa20a22 1473
1da177e4
LT		 1474 if (gp->asleep)
1475 return;
1476
1477 spin_lock_irq(&gp->lock);
1478 spin_lock(&gp->tx_lock);
1479 gem_get_cell(gp);
1480
1481 /* If the reset task is still pending, we just
1482 * reschedule the link timer
1483 */
1484 if (gp->reset_task_pending)
1485 goto restart;
6aa20a22 1486
1da177e4
LT		 1487 if (gp->phy_type == phy_serialink ||
1488 gp->phy_type == phy_serdes) {
1489 u32 val = readl(gp->regs + PCS_MIISTAT);
1490
1491 if (!(val & PCS_MIISTAT_LS))
1492 val = readl(gp->regs + PCS_MIISTAT);
1493
1494 if ((val & PCS_MIISTAT_LS) != 0) {
1495 gp->lstate = link_up;
1496 netif_carrier_on(gp->dev);
1497 (void)gem_set_link_modes(gp);
1498 }
1499 goto restart;
1500 }
1501 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1502 /* Ok, here we got a link. If we had it due to a forced
1503 * fallback, and we were configured for autoneg, we do
1504 * retry a short autoneg pass. If you know your hub is
1505 * broken, use ethtool ;)
1506 */
1507 if (gp->lstate == link_force_try && gp->want_autoneg) {
1508 gp->lstate = link_force_ret;
1509 gp->last_forced_speed = gp->phy_mii.speed;
1510 gp->timer_ticks = 5;
1511 if (netif_msg_link(gp))
1512 printk(KERN_INFO "%s: Got link after fallback, retrying"
1513 " autoneg once...\n", gp->dev->name);
1514 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1515 } else if (gp->lstate != link_up) {
1516 gp->lstate = link_up;
1517 netif_carrier_on(gp->dev);
1518 if (gem_set_link_modes(gp))
1519 restart_aneg = 1;
1520 }
1521 } else {
1522 /* If the link was previously up, we restart the
1523 * whole process
1524 */
1525 if (gp->lstate == link_up) {
1526 gp->lstate = link_down;
1527 if (netif_msg_link(gp))
1528 printk(KERN_INFO "%s: Link down\n",
1529 gp->dev->name);
1530 netif_carrier_off(gp->dev);
1531 gp->reset_task_pending = 1;
1532 schedule_work(&gp->reset_task);
1533 restart_aneg = 1;
1534 } else if (++gp->timer_ticks > 10) {
1535 if (found_mii_phy(gp))
1536 restart_aneg = gem_mdio_link_not_up(gp);
1537 else
1538 restart_aneg = 1;
1539 }
1540 }
1541 if (restart_aneg) {
1542 gem_begin_auto_negotiation(gp, NULL);
1543 goto out_unlock;
1544 }
1545restart:
1546 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1547out_unlock:
1548 gem_put_cell(gp);
1549 spin_unlock(&gp->tx_lock);
1550 spin_unlock_irq(&gp->lock);
1551}
1552
1553/* Must be invoked under gp->lock and gp->tx_lock. */
1554static void gem_clean_rings(struct gem *gp)
1555{
1556 struct gem_init_block *gb = gp->init_block;
1557 struct sk_buff *skb;
1558 int i;
1559 dma_addr_t dma_addr;
1560
1561 for (i = 0; i < RX_RING_SIZE; i++) {
1562 struct gem_rxd *rxd;
1563
1564 rxd = &gb->rxd[i];
1565 if (gp->rx_skbs[i] != NULL) {
1566 skb = gp->rx_skbs[i];
1567 dma_addr = le64_to_cpu(rxd->buffer);
1568 pci_unmap_page(gp->pdev, dma_addr,
1569 RX_BUF_ALLOC_SIZE(gp),
1570 PCI_DMA_FROMDEVICE);
1571 dev_kfree_skb_any(skb);
1572 gp->rx_skbs[i] = NULL;
1573 }
1574 rxd->status_word = 0;
1575 wmb();
1576 rxd->buffer = 0;
1577 }
1578
1579 for (i = 0; i < TX_RING_SIZE; i++) {
1580 if (gp->tx_skbs[i] != NULL) {
1581 struct gem_txd *txd;
1582 int frag;
1583
1584 skb = gp->tx_skbs[i];
1585 gp->tx_skbs[i] = NULL;
1586
1587 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1588 int ent = i & (TX_RING_SIZE - 1);
1589
1590 txd = &gb->txd[ent];
1591 dma_addr = le64_to_cpu(txd->buffer);
1592 pci_unmap_page(gp->pdev, dma_addr,
1593 le64_to_cpu(txd->control_word) &
1594 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1595
1596 if (frag != skb_shinfo(skb)->nr_frags)
1597 i++;
1598 }
1599 dev_kfree_skb_any(skb);
1600 }
1601 }
1602}
1603
1604/* Must be invoked under gp->lock and gp->tx_lock. */
1605static void gem_init_rings(struct gem *gp)
1606{
1607 struct gem_init_block *gb = gp->init_block;
1608 struct net_device *dev = gp->dev;
1609 int i;
1610 dma_addr_t dma_addr;
1611
1612 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1613
1614 gem_clean_rings(gp);
1615
1616 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1617 (unsigned)VLAN_ETH_FRAME_LEN);
1618
1619 for (i = 0; i < RX_RING_SIZE; i++) {
1620 struct sk_buff *skb;
1621 struct gem_rxd *rxd = &gb->rxd[i];
1622
1623 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1624 if (!skb) {
1625 rxd->buffer = 0;
1626 rxd->status_word = 0;
1627 continue;
1628 }
1629
1630 gp->rx_skbs[i] = skb;
1631 skb->dev = dev;
1632 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1633 dma_addr = pci_map_page(gp->pdev,
1634 virt_to_page(skb->data),
1635 offset_in_page(skb->data),
1636 RX_BUF_ALLOC_SIZE(gp),
1637 PCI_DMA_FROMDEVICE);
1638 rxd->buffer = cpu_to_le64(dma_addr);
1639 wmb();
1640 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1641 skb_reserve(skb, RX_OFFSET);
1642 }
1643
1644 for (i = 0; i < TX_RING_SIZE; i++) {
1645 struct gem_txd *txd = &gb->txd[i];
1646
1647 txd->control_word = 0;
1648 wmb();
1649 txd->buffer = 0;
1650 }
1651 wmb();
1652}
1653
1654/* Init PHY interface and start link poll state machine */
1655static void gem_init_phy(struct gem *gp)
1656{
7fb76aa0 1657 u32 mifcfg;
1da177e4
LT		 1658
1659 /* Revert MIF CFG setting done on stop_phy */
7fb76aa0
DM		 1660 mifcfg = readl(gp->regs + MIF_CFG);
1661 mifcfg &= ~MIF_CFG_BBMODE;
1662 writel(mifcfg, gp->regs + MIF_CFG);
6aa20a22 1663
1da177e4
LT		 1664 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1665 int i;
1666
7fb76aa0
DM		 1667 /* Those delay sucks, the HW seem to love them though, I'll
1668 * serisouly consider breaking some locks here to be able
1669 * to schedule instead
1670 */
1671 for (i = 0; i < 3; i++) {
1da177e4 1672#ifdef CONFIG_PPC_PMAC
7fb76aa0
DM		 1673 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1674 msleep(20);
1da177e4 1675#endif
7fb76aa0
DM		 1676 /* Some PHYs used by apple have problem getting back to us,
1677 * we do an additional reset here
1678 */
1679 phy_write(gp, MII_BMCR, BMCR_RESET);
1680 msleep(20);
1681 if (phy_read(gp, MII_BMCR) != 0xffff)
1da177e4 1682 break;
7fb76aa0
DM		 1683 if (i == 2)
1684 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1685 gp->dev->name);
1da177e4
LT		 1686 }
1687 }
1688
1689 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1690 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1691 u32 val;
1692
1693 /* Init datapath mode register. */
1694 if (gp->phy_type == phy_mii_mdio0 ||
1695 gp->phy_type == phy_mii_mdio1) {
1696 val = PCS_DMODE_MGM;
1697 } else if (gp->phy_type == phy_serialink) {
1698 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1699 } else {
1700 val = PCS_DMODE_ESM;
1701 }
1702
1703 writel(val, gp->regs + PCS_DMODE);
1704 }
1705
1706 if (gp->phy_type == phy_mii_mdio0 ||
1707 gp->phy_type == phy_mii_mdio1) {
1708 // XXX check for errors
1709 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1710
1711 /* Init PHY */
1712 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1713 gp->phy_mii.def->ops->init(&gp->phy_mii);
1714 } else {
1715 u32 val;
1716 int limit;
1717
1718 /* Reset PCS unit. */
1719 val = readl(gp->regs + PCS_MIICTRL);
1720 val |= PCS_MIICTRL_RST;
1721 writeb(val, gp->regs + PCS_MIICTRL);
1722
1723 limit = 32;
1724 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1725 udelay(100);
1726 if (limit-- <= 0)
1727 break;
1728 }
1729 if (limit <= 0)
1730 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1731 gp->dev->name);
1732
1733 /* Make sure PCS is disabled while changing advertisement
1734 * configuration.
1735 */
1736 val = readl(gp->regs + PCS_CFG);
1737 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1738 writel(val, gp->regs + PCS_CFG);
1739
1740 /* Advertise all capabilities except assymetric
1741 * pause.
1742 */
1743 val = readl(gp->regs + PCS_MIIADV);
1744 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1745 PCS_MIIADV_SP | PCS_MIIADV_AP);
1746 writel(val, gp->regs + PCS_MIIADV);
1747
1748 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1749 * and re-enable PCS.
1750 */
1751 val = readl(gp->regs + PCS_MIICTRL);
1752 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1753 val &= ~PCS_MIICTRL_WB;
1754 writel(val, gp->regs + PCS_MIICTRL);
1755
1756 val = readl(gp->regs + PCS_CFG);
1757 val |= PCS_CFG_ENABLE;
1758 writel(val, gp->regs + PCS_CFG);
1759
1760 /* Make sure serialink loopback is off. The meaning
1761 * of this bit is logically inverted based upon whether
1762 * you are in Serialink or SERDES mode.
1763 */
1764 val = readl(gp->regs + PCS_SCTRL);
1765 if (gp->phy_type == phy_serialink)
1766 val &= ~PCS_SCTRL_LOOP;
1767 else
1768 val |= PCS_SCTRL_LOOP;
1769 writel(val, gp->regs + PCS_SCTRL);
1770 }
1771
1772 /* Default aneg parameters */
1773 gp->timer_ticks = 0;
1774 gp->lstate = link_down;
1775 netif_carrier_off(gp->dev);
1776
1777 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1778 spin_lock_irq(&gp->lock);
1779 gem_begin_auto_negotiation(gp, NULL);
1780 spin_unlock_irq(&gp->lock);
1781}
1782
1783/* Must be invoked under gp->lock and gp->tx_lock. */
1784static void gem_init_dma(struct gem *gp)
1785{
1786 u64 desc_dma = (u64) gp->gblock_dvma;
1787 u32 val;
1788
1789 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1790 writel(val, gp->regs + TXDMA_CFG);
1791
1792 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1793 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1794 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1795
1796 writel(0, gp->regs + TXDMA_KICK);
1797
1798 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1799 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1800 writel(val, gp->regs + RXDMA_CFG);
1801
1802 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1803 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1804
1805 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1806
1807 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1808 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1809 writel(val, gp->regs + RXDMA_PTHRESH);
1810
1811 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1812 writel(((5 & RXDMA_BLANK_IPKTS) |
1813 ((8 << 12) & RXDMA_BLANK_ITIME)),
1814 gp->regs + RXDMA_BLANK);
1815 else
1816 writel(((5 & RXDMA_BLANK_IPKTS) |
1817 ((4 << 12) & RXDMA_BLANK_ITIME)),
1818 gp->regs + RXDMA_BLANK);
1819}
1820
1821/* Must be invoked under gp->lock and gp->tx_lock. */
1822static u32 gem_setup_multicast(struct gem *gp)
1823{
1824 u32 rxcfg = 0;
1825 int i;
6aa20a22 1826
1da177e4
LT		 1827 if ((gp->dev->flags & IFF_ALLMULTI) ||
1828 (gp->dev->mc_count > 256)) {
1829 for (i=0; i<16; i++)
1830 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1831 rxcfg |= MAC_RXCFG_HFE;
1832 } else if (gp->dev->flags & IFF_PROMISC) {
1833 rxcfg |= MAC_RXCFG_PROM;
1834 } else {
1835 u16 hash_table[16];
1836 u32 crc;
1837 struct dev_mc_list *dmi = gp->dev->mc_list;
1838 int i;
1839
1840 for (i = 0; i < 16; i++)
1841 hash_table[i] = 0;
1842
1843 for (i = 0; i < gp->dev->mc_count; i++) {
1844 char *addrs = dmi->dmi_addr;
1845
1846 dmi = dmi->next;
1847
1848 if (!(*addrs & 1))
1849 continue;
1850
1851 crc = ether_crc_le(6, addrs);
1852 crc >>= 24;
1853 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1854 }
1855 for (i=0; i<16; i++)
1856 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1857 rxcfg |= MAC_RXCFG_HFE;
1858 }
1859
1860 return rxcfg;
1861}
1862
1863/* Must be invoked under gp->lock and gp->tx_lock. */
1864static void gem_init_mac(struct gem *gp)
1865{
1866 unsigned char *e = &gp->dev->dev_addr[0];
1867
1868 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1869
1870 writel(0x00, gp->regs + MAC_IPG0);
1871 writel(0x08, gp->regs + MAC_IPG1);
1872 writel(0x04, gp->regs + MAC_IPG2);
1873 writel(0x40, gp->regs + MAC_STIME);
1874 writel(0x40, gp->regs + MAC_MINFSZ);
1875
1876 /* Ethernet payload + header + FCS + optional VLAN tag. */
1877 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1878
1879 writel(0x07, gp->regs + MAC_PASIZE);
1880 writel(0x04, gp->regs + MAC_JAMSIZE);
1881 writel(0x10, gp->regs + MAC_ATTLIM);
1882 writel(0x8808, gp->regs + MAC_MCTYPE);
1883
1884 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1885
1886 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1887 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1888 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1889
1890 writel(0, gp->regs + MAC_ADDR3);
1891 writel(0, gp->regs + MAC_ADDR4);
1892 writel(0, gp->regs + MAC_ADDR5);
1893
1894 writel(0x0001, gp->regs + MAC_ADDR6);
1895 writel(0xc200, gp->regs + MAC_ADDR7);
1896 writel(0x0180, gp->regs + MAC_ADDR8);
1897
1898 writel(0, gp->regs + MAC_AFILT0);
1899 writel(0, gp->regs + MAC_AFILT1);
1900 writel(0, gp->regs + MAC_AFILT2);
1901 writel(0, gp->regs + MAC_AF21MSK);
1902 writel(0, gp->regs + MAC_AF0MSK);
1903
1904 gp->mac_rx_cfg = gem_setup_multicast(gp);
1905#ifdef STRIP_FCS
1906 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1907#endif
1908 writel(0, gp->regs + MAC_NCOLL);
1909 writel(0, gp->regs + MAC_FASUCC);
1910 writel(0, gp->regs + MAC_ECOLL);
1911 writel(0, gp->regs + MAC_LCOLL);
1912 writel(0, gp->regs + MAC_DTIMER);
1913 writel(0, gp->regs + MAC_PATMPS);
1914 writel(0, gp->regs + MAC_RFCTR);
1915 writel(0, gp->regs + MAC_LERR);
1916 writel(0, gp->regs + MAC_AERR);
1917 writel(0, gp->regs + MAC_FCSERR);
1918 writel(0, gp->regs + MAC_RXCVERR);
1919
1920 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1921 * them once a link is established.
1922 */
1923 writel(0, gp->regs + MAC_TXCFG);
1924 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1925 writel(0, gp->regs + MAC_MCCFG);
1926 writel(0, gp->regs + MAC_XIFCFG);
1927
1928 /* Setup MAC interrupts. We want to get all of the interesting
1929 * counter expiration events, but we do not want to hear about
1930 * normal rx/tx as the DMA engine tells us that.
1931 */
1932 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1933 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1934
1935 /* Don't enable even the PAUSE interrupts for now, we
1936 * make no use of those events other than to record them.
1937 */
1938 writel(0xffffffff, gp->regs + MAC_MCMASK);
1939
1940 /* Don't enable GEM's WOL in normal operations
1941 */
1942 if (gp->has_wol)
1943 writel(0, gp->regs + WOL_WAKECSR);
1944}
1945
1946/* Must be invoked under gp->lock and gp->tx_lock. */
1947static void gem_init_pause_thresholds(struct gem *gp)
1948{
1949 u32 cfg;
1950
1951 /* Calculate pause thresholds. Setting the OFF threshold to the
1952 * full RX fifo size effectively disables PAUSE generation which
1953 * is what we do for 10/100 only GEMs which have FIFOs too small
1954 * to make real gains from PAUSE.
1955 */
1956 if (gp->rx_fifo_sz <= (2 * 1024)) {
1957 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1958 } else {
1959 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1960 int off = (gp->rx_fifo_sz - (max_frame * 2));
1961 int on = off - max_frame;
1962
1963 gp->rx_pause_off = off;
1964 gp->rx_pause_on = on;
1965 }
1966
1967
1968 /* Configure the chip "burst" DMA mode & enable some
1969 * HW bug fixes on Apple version
1970 */
1971 cfg = 0;
1972 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1973 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1974#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1975 cfg |= GREG_CFG_IBURST;
1976#endif
1977 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1978 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1979 writel(cfg, gp->regs + GREG_CFG);
1980
1981 /* If Infinite Burst didn't stick, then use different
1982 * thresholds (and Apple bug fixes don't exist)
1983 */
1984 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1985 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1986 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1987 writel(cfg, gp->regs + GREG_CFG);
6aa20a22 1988 }
1da177e4
LT		 1989}
1990
1991static int gem_check_invariants(struct gem *gp)
1992{
1993 struct pci_dev *pdev = gp->pdev;
1994 u32 mif_cfg;
1995
1996 /* On Apple's sungem, we can't rely on registers as the chip
1997 * was been powered down by the firmware. The PHY is looked
1998 * up later on.
1999 */
2000 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
2001 gp->phy_type = phy_mii_mdio0;
2002 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2003 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2004 gp->swrst_base = 0;
2005
2006 mif_cfg = readl(gp->regs + MIF_CFG);
2007 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2008 mif_cfg |= MIF_CFG_MDI0;
2009 writel(mif_cfg, gp->regs + MIF_CFG);
2010 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2011 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2012
2013 /* We hard-code the PHY address so we can properly bring it out of
2014 * reset later on, we can't really probe it at this point, though
2015 * that isn't an issue.
2016 */
2017 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2018 gp->mii_phy_addr = 1;
2019 else
2020 gp->mii_phy_addr = 0;
2021
2022 return 0;
2023 }
2024
2025 mif_cfg = readl(gp->regs + MIF_CFG);
2026
2027 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2028 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2029 /* One of the MII PHYs _must_ be present
2030 * as this chip has no gigabit PHY.
2031 */
2032 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2033 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2034 mif_cfg);
2035 return -1;
2036 }
2037 }
2038
2039 /* Determine initial PHY interface type guess. MDIO1 is the
2040 * external PHY and thus takes precedence over MDIO0.
2041 */
6aa20a22 2042
1da177e4
LT		 2043 if (mif_cfg & MIF_CFG_MDI1) {
2044 gp->phy_type = phy_mii_mdio1;
2045 mif_cfg |= MIF_CFG_PSELECT;
2046 writel(mif_cfg, gp->regs + MIF_CFG);
2047 } else if (mif_cfg & MIF_CFG_MDI0) {
2048 gp->phy_type = phy_mii_mdio0;
2049 mif_cfg &= ~MIF_CFG_PSELECT;
2050 writel(mif_cfg, gp->regs + MIF_CFG);
2051 } else {
2052 gp->phy_type = phy_serialink;
2053 }
2054 if (gp->phy_type == phy_mii_mdio1 ||
2055 gp->phy_type == phy_mii_mdio0) {
2056 int i;
2057
2058 for (i = 0; i < 32; i++) {
2059 gp->mii_phy_addr = i;
2060 if (phy_read(gp, MII_BMCR) != 0xffff)
2061 break;
2062 }
2063 if (i == 32) {
2064 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2065 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2066 return -1;
2067 }
2068 gp->phy_type = phy_serdes;
2069 }
2070 }
2071
2072 /* Fetch the FIFO configurations now too. */
2073 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2074 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2075
2076 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2077 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2078 if (gp->tx_fifo_sz != (9 * 1024) ||
2079 gp->rx_fifo_sz != (20 * 1024)) {
2080 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2081 gp->tx_fifo_sz, gp->rx_fifo_sz);
2082 return -1;
2083 }
2084 gp->swrst_base = 0;
2085 } else {
2086 if (gp->tx_fifo_sz != (2 * 1024) ||
2087 gp->rx_fifo_sz != (2 * 1024)) {
2088 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2089 gp->tx_fifo_sz, gp->rx_fifo_sz);
2090 return -1;
2091 }
2092 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2093 }
2094 }
2095
2096 return 0;
2097}
2098
2099/* Must be invoked under gp->lock and gp->tx_lock. */
2100static void gem_reinit_chip(struct gem *gp)
2101{
2102 /* Reset the chip */
2103 gem_reset(gp);
2104
2105 /* Make sure ints are disabled */
2106 gem_disable_ints(gp);
2107
2108 /* Allocate & setup ring buffers */
2109 gem_init_rings(gp);
2110
2111 /* Configure pause thresholds */
2112 gem_init_pause_thresholds(gp);
2113
2114 /* Init DMA & MAC engines */
2115 gem_init_dma(gp);
2116 gem_init_mac(gp);
2117}
2118
2119
2120/* Must be invoked with no lock held. */
2121static void gem_stop_phy(struct gem *gp, int wol)
2122{
7fb76aa0 2123 u32 mifcfg;
1da177e4
LT		 2124 unsigned long flags;
2125
2126 /* Let the chip settle down a bit, it seems that helps
2127 * for sleep mode on some models
2128 */
2129 msleep(10);
2130
2131 /* Make sure we aren't polling PHY status change. We
2132 * don't currently use that feature though
2133 */
7fb76aa0
DM		 2134 mifcfg = readl(gp->regs + MIF_CFG);
2135 mifcfg &= ~MIF_CFG_POLL;
2136 writel(mifcfg, gp->regs + MIF_CFG);
1da177e4
LT		 2137
2138 if (wol && gp->has_wol) {
2139 unsigned char *e = &gp->dev->dev_addr[0];
2140 u32 csr;
2141
2142 /* Setup wake-on-lan for MAGIC packet */
2143 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
6aa20a22 2144 gp->regs + MAC_RXCFG);
1da177e4
LT		 2145 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2146 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2147 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2148
2149 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2150 csr = WOL_WAKECSR_ENABLE;
2151 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2152 csr |= WOL_WAKECSR_MII;
2153 writel(csr, gp->regs + WOL_WAKECSR);
2154 } else {
2155 writel(0, gp->regs + MAC_RXCFG);
2156 (void)readl(gp->regs + MAC_RXCFG);
2157 /* Machine sleep will die in strange ways if we
2158 * dont wait a bit here, looks like the chip takes
2159 * some time to really shut down
2160 */
2161 msleep(10);
2162 }
2163
2164 writel(0, gp->regs + MAC_TXCFG);
2165 writel(0, gp->regs + MAC_XIFCFG);
2166 writel(0, gp->regs + TXDMA_CFG);
2167 writel(0, gp->regs + RXDMA_CFG);
2168
2169 if (!wol) {
2170 spin_lock_irqsave(&gp->lock, flags);
2171 spin_lock(&gp->tx_lock);
2172 gem_reset(gp);
2173 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2174 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2175 spin_unlock(&gp->tx_lock);
2176 spin_unlock_irqrestore(&gp->lock, flags);
2177
2178 /* No need to take the lock here */
2179
2180 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2181 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2182
2183 /* According to Apple, we must set the MDIO pins to this begnign
2184 * state or we may 1) eat more current, 2) damage some PHYs
2185 */
7fb76aa0 2186 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
1da177e4
LT		 2187 writel(0, gp->regs + MIF_BBCLK);
2188 writel(0, gp->regs + MIF_BBDATA);
2189 writel(0, gp->regs + MIF_BBOENAB);
2190 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2191 (void) readl(gp->regs + MAC_XIFCFG);
2192 }
2193}
2194
2195
2196static int gem_do_start(struct net_device *dev)
2197{
2198 struct gem *gp = dev->priv;
2199 unsigned long flags;
2200
2201 spin_lock_irqsave(&gp->lock, flags);
2202 spin_lock(&gp->tx_lock);
2203
2204 /* Enable the cell */
2205 gem_get_cell(gp);
2206
2207 /* Init & setup chip hardware */
2208 gem_reinit_chip(gp);
2209
2210 gp->running = 1;
2211
2212 if (gp->lstate == link_up) {
2213 netif_carrier_on(gp->dev);
2214 gem_set_link_modes(gp);
2215 }
2216
2217 netif_wake_queue(gp->dev);
2218
2219 spin_unlock(&gp->tx_lock);
2220 spin_unlock_irqrestore(&gp->lock, flags);
2221
2222 if (request_irq(gp->pdev->irq, gem_interrupt,
1fb9df5d 2223 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4
LT		 2224 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2225
2226 spin_lock_irqsave(&gp->lock, flags);
2227 spin_lock(&gp->tx_lock);
2228
2229 gp->running = 0;
2230 gem_reset(gp);
2231 gem_clean_rings(gp);
2232 gem_put_cell(gp);
6aa20a22 2233
1da177e4
LT		 2234 spin_unlock(&gp->tx_lock);
2235 spin_unlock_irqrestore(&gp->lock, flags);
2236
2237 return -EAGAIN;
2238 }
2239
2240 return 0;
2241}
2242
2243static void gem_do_stop(struct net_device *dev, int wol)
2244{
2245 struct gem *gp = dev->priv;
2246 unsigned long flags;
2247
2248 spin_lock_irqsave(&gp->lock, flags);
2249 spin_lock(&gp->tx_lock);
2250
2251 gp->running = 0;
2252
2253 /* Stop netif queue */
2254 netif_stop_queue(dev);
2255
2256 /* Make sure ints are disabled */
2257 gem_disable_ints(gp);
2258
2259 /* We can drop the lock now */
2260 spin_unlock(&gp->tx_lock);
2261 spin_unlock_irqrestore(&gp->lock, flags);
2262
2263 /* If we are going to sleep with WOL */
2264 gem_stop_dma(gp);
2265 msleep(10);
2266 if (!wol)
2267 gem_reset(gp);
2268 msleep(10);
2269
2270 /* Get rid of rings */
2271 gem_clean_rings(gp);
2272
2273 /* No irq needed anymore */
2274 free_irq(gp->pdev->irq, (void *) dev);
2275
2276 /* Cell not needed neither if no WOL */
2277 if (!wol) {
2278 spin_lock_irqsave(&gp->lock, flags);
2279 gem_put_cell(gp);
2280 spin_unlock_irqrestore(&gp->lock, flags);
2281 }
2282}
2283
2284static void gem_reset_task(void *data)
2285{
2286 struct gem *gp = (struct gem *) data;
2287
e3968fc0 2288 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2289
2290 netif_poll_disable(gp->dev);
2291
2292 spin_lock_irq(&gp->lock);
2293 spin_lock(&gp->tx_lock);
2294
2295 if (gp->running == 0)
2296 goto not_running;
2297
2298 if (gp->running) {
2299 netif_stop_queue(gp->dev);
2300
2301 /* Reset the chip & rings */
2302 gem_reinit_chip(gp);
2303 if (gp->lstate == link_up)
2304 gem_set_link_modes(gp);
2305 netif_wake_queue(gp->dev);
2306 }
2307 not_running:
2308 gp->reset_task_pending = 0;
2309
2310 spin_unlock(&gp->tx_lock);
2311 spin_unlock_irq(&gp->lock);
2312
2313 netif_poll_enable(gp->dev);
2314
e3968fc0 2315 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2316}
2317
2318
2319static int gem_open(struct net_device *dev)
2320{
2321 struct gem *gp = dev->priv;
2322 int rc = 0;
2323
e3968fc0 2324 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2325
2326 /* We need the cell enabled */
2327 if (!gp->asleep)
2328 rc = gem_do_start(dev);
2329 gp->opened = (rc == 0);
2330
e3968fc0 2331 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2332
2333 return rc;
2334}
2335
2336static int gem_close(struct net_device *dev)
2337{
2338 struct gem *gp = dev->priv;
2339
2340 /* Note: we don't need to call netif_poll_disable() here because
2341 * our caller (dev_close) already did it for us
2342 */
2343
e3968fc0 2344 mutex_lock(&gp->pm_mutex);
1da177e4 2345
6aa20a22 2346 gp->opened = 0;
1da177e4
LT		 2347 if (!gp->asleep)
2348 gem_do_stop(dev, 0);
2349
e3968fc0 2350 mutex_unlock(&gp->pm_mutex);
6aa20a22 2351
1da177e4
LT		 2352 return 0;
2353}
2354
2355#ifdef CONFIG_PM
2356static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2357{
2358 struct net_device *dev = pci_get_drvdata(pdev);
2359 struct gem *gp = dev->priv;
2360 unsigned long flags;
2361
e3968fc0 2362 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2363
2364 netif_poll_disable(dev);
2365
2366 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2367 dev->name,
2368 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
6aa20a22 2369
1da177e4
LT		 2370 /* Keep the cell enabled during the entire operation */
2371 spin_lock_irqsave(&gp->lock, flags);
2372 spin_lock(&gp->tx_lock);
2373 gem_get_cell(gp);
2374 spin_unlock(&gp->tx_lock);
2375 spin_unlock_irqrestore(&gp->lock, flags);
2376
2377 /* If the driver is opened, we stop the MAC */
2378 if (gp->opened) {
2379 /* Stop traffic, mark us closed */
2380 netif_device_detach(dev);
2381
2382 /* Switch off MAC, remember WOL setting */
2383 gp->asleep_wol = gp->wake_on_lan;
2384 gem_do_stop(dev, gp->asleep_wol);
2385 } else
2386 gp->asleep_wol = 0;
2387
2388 /* Mark us asleep */
2389 gp->asleep = 1;
2390 wmb();
2391
2392 /* Stop the link timer */
2393 del_timer_sync(&gp->link_timer);
2394
e3968fc0 2395 /* Now we release the mutex to not block the reset task who
1da177e4
LT		 2396 * can take it too. We are marked asleep, so there will be no
2397 * conflict here
2398 */
e3968fc0 2399 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2400
2401 /* Wait for a pending reset task to complete */
2402 while (gp->reset_task_pending)
2403 yield();
2404 flush_scheduled_work();
2405
2406 /* Shut the PHY down eventually and setup WOL */
2407 gem_stop_phy(gp, gp->asleep_wol);
2408
2409 /* Make sure bus master is disabled */
2410 pci_disable_device(gp->pdev);
2411
2412 /* Release the cell, no need to take a lock at this point since
2413 * nothing else can happen now
2414 */
2415 gem_put_cell(gp);
2416
2417 return 0;
2418}
2419
2420static int gem_resume(struct pci_dev *pdev)
2421{
2422 struct net_device *dev = pci_get_drvdata(pdev);
2423 struct gem *gp = dev->priv;
2424 unsigned long flags;
2425
2426 printk(KERN_INFO "%s: resuming\n", dev->name);
2427
e3968fc0 2428 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2429
2430 /* Keep the cell enabled during the entire operation, no need to
2431 * take a lock here tho since nothing else can happen while we are
2432 * marked asleep
2433 */
2434 gem_get_cell(gp);
2435
2436 /* Make sure PCI access and bus master are enabled */
2437 if (pci_enable_device(gp->pdev)) {
2438 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2439 dev->name);
2440 /* Put cell and forget it for now, it will be considered as
2441 * still asleep, a new sleep cycle may bring it back
2442 */
2443 gem_put_cell(gp);
e3968fc0 2444 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2445 return 0;
2446 }
2447 pci_set_master(gp->pdev);
2448
2449 /* Reset everything */
2450 gem_reset(gp);
2451
2452 /* Mark us woken up */
2453 gp->asleep = 0;
2454 wmb();
2455
2456 /* Bring the PHY back. Again, lock is useless at this point as
2457 * nothing can be happening until we restart the whole thing
2458 */
2459 gem_init_phy(gp);
2460
2461 /* If we were opened, bring everything back */
2462 if (gp->opened) {
2463 /* Restart MAC */
2464 gem_do_start(dev);
2465
2466 /* Re-attach net device */
2467 netif_device_attach(dev);
2468
2469 }
2470
2471 spin_lock_irqsave(&gp->lock, flags);
2472 spin_lock(&gp->tx_lock);
2473
2474 /* If we had WOL enabled, the cell clock was never turned off during
2475 * sleep, so we end up beeing unbalanced. Fix that here
2476 */
2477 if (gp->asleep_wol)
2478 gem_put_cell(gp);
2479
2480 /* This function doesn't need to hold the cell, it will be held if the
2481 * driver is open by gem_do_start().
2482 */
2483 gem_put_cell(gp);
2484
2485 spin_unlock(&gp->tx_lock);
2486 spin_unlock_irqrestore(&gp->lock, flags);
2487
2488 netif_poll_enable(dev);
6aa20a22 2489
e3968fc0 2490 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2491
2492 return 0;
2493}
2494#endif /* CONFIG_PM */
2495
2496static struct net_device_stats *gem_get_stats(struct net_device *dev)
2497{
2498 struct gem *gp = dev->priv;
2499 struct net_device_stats *stats = &gp->net_stats;
2500
2501 spin_lock_irq(&gp->lock);
2502 spin_lock(&gp->tx_lock);
2503
2504 /* I have seen this being called while the PM was in progress,
2505 * so we shield against this
2506 */
2507 if (gp->running) {
2508 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2509 writel(0, gp->regs + MAC_FCSERR);
2510
2511 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2512 writel(0, gp->regs + MAC_AERR);
2513
2514 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2515 writel(0, gp->regs + MAC_LERR);
2516
2517 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2518 stats->collisions +=
2519 (readl(gp->regs + MAC_ECOLL) +
2520 readl(gp->regs + MAC_LCOLL));
2521 writel(0, gp->regs + MAC_ECOLL);
2522 writel(0, gp->regs + MAC_LCOLL);
2523 }
2524
2525 spin_unlock(&gp->tx_lock);
2526 spin_unlock_irq(&gp->lock);
2527
2528 return &gp->net_stats;
2529}
2530
2531static void gem_set_multicast(struct net_device *dev)
2532{
2533 struct gem *gp = dev->priv;
2534 u32 rxcfg, rxcfg_new;
2535 int limit = 10000;
6aa20a22 2536
1da177e4
LT		 2537
2538 spin_lock_irq(&gp->lock);
2539 spin_lock(&gp->tx_lock);
2540
2541 if (!gp->running)
2542 goto bail;
2543
2544 netif_stop_queue(dev);
2545
2546 rxcfg = readl(gp->regs + MAC_RXCFG);
2547 rxcfg_new = gem_setup_multicast(gp);
2548#ifdef STRIP_FCS
2549 rxcfg_new |= MAC_RXCFG_SFCS;
2550#endif
2551 gp->mac_rx_cfg = rxcfg_new;
6aa20a22 2552
1da177e4
LT		 2553 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2554 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2555 if (!limit--)
2556 break;
2557 udelay(10);
2558 }
2559
2560 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2561 rxcfg |= rxcfg_new;
2562
2563 writel(rxcfg, gp->regs + MAC_RXCFG);
2564
2565 netif_wake_queue(dev);
2566
2567 bail:
2568 spin_unlock(&gp->tx_lock);
2569 spin_unlock_irq(&gp->lock);
2570}
2571
2572/* Jumbo-grams don't seem to work :-( */
2573#define GEM_MIN_MTU 68
2574#if 1
2575#define GEM_MAX_MTU 1500
2576#else
2577#define GEM_MAX_MTU 9000
2578#endif
2579
2580static int gem_change_mtu(struct net_device *dev, int new_mtu)
2581{
2582 struct gem *gp = dev->priv;
2583
2584 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2585 return -EINVAL;
2586
2587 if (!netif_running(dev) || !netif_device_present(dev)) {
2588 /* We'll just catch it later when the
2589 * device is up'd or resumed.
2590 */
2591 dev->mtu = new_mtu;
2592 return 0;
2593 }
2594
e3968fc0 2595 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2596 spin_lock_irq(&gp->lock);
2597 spin_lock(&gp->tx_lock);
2598 dev->mtu = new_mtu;
2599 if (gp->running) {
2600 gem_reinit_chip(gp);
2601 if (gp->lstate == link_up)
2602 gem_set_link_modes(gp);
2603 }
2604 spin_unlock(&gp->tx_lock);
2605 spin_unlock_irq(&gp->lock);
e3968fc0 2606 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2607
2608 return 0;
2609}
2610
2611static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2612{
2613 struct gem *gp = dev->priv;
6aa20a22 2614
1da177e4
LT		 2615 strcpy(info->driver, DRV_NAME);
2616 strcpy(info->version, DRV_VERSION);
2617 strcpy(info->bus_info, pci_name(gp->pdev));
2618}
6aa20a22 2619
1da177e4
LT		 2620static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2621{
2622 struct gem *gp = dev->priv;
2623
2624 if (gp->phy_type == phy_mii_mdio0 ||
2625 gp->phy_type == phy_mii_mdio1) {
2626 if (gp->phy_mii.def)
2627 cmd->supported = gp->phy_mii.def->features;
2628 else
2629 cmd->supported = (SUPPORTED_10baseT_Half |
2630 SUPPORTED_10baseT_Full);
2631
2632 /* XXX hardcoded stuff for now */
2633 cmd->port = PORT_MII;
2634 cmd->transceiver = XCVR_EXTERNAL;
2635 cmd->phy_address = 0; /* XXX fixed PHYAD */
2636
2637 /* Return current PHY settings */
2638 spin_lock_irq(&gp->lock);
2639 cmd->autoneg = gp->want_autoneg;
2640 cmd->speed = gp->phy_mii.speed;
6aa20a22 2641 cmd->duplex = gp->phy_mii.duplex;
1da177e4
LT		 2642 cmd->advertising = gp->phy_mii.advertising;
2643
2644 /* If we started with a forced mode, we don't have a default
2645 * advertise set, we need to return something sensible so
2646 * userland can re-enable autoneg properly.
2647 */
2648 if (cmd->advertising == 0)
2649 cmd->advertising = cmd->supported;
2650 spin_unlock_irq(&gp->lock);
2651 } else { // XXX PCS ?
2652 cmd->supported =
2653 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2654 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2655 SUPPORTED_Autoneg);
2656 cmd->advertising = cmd->supported;
2657 cmd->speed = 0;
2658 cmd->duplex = cmd->port = cmd->phy_address =
2659 cmd->transceiver = cmd->autoneg = 0;
2660 }
2661 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2662
2663 return 0;
2664}
2665
2666static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2667{
2668 struct gem *gp = dev->priv;
2669
2670 /* Verify the settings we care about. */
2671 if (cmd->autoneg != AUTONEG_ENABLE &&
2672 cmd->autoneg != AUTONEG_DISABLE)
2673 return -EINVAL;
2674
2675 if (cmd->autoneg == AUTONEG_ENABLE &&
2676 cmd->advertising == 0)
2677 return -EINVAL;
2678
2679 if (cmd->autoneg == AUTONEG_DISABLE &&
2680 ((cmd->speed != SPEED_1000 &&
2681 cmd->speed != SPEED_100 &&
2682 cmd->speed != SPEED_10) ||
2683 (cmd->duplex != DUPLEX_HALF &&
2684 cmd->duplex != DUPLEX_FULL)))
2685 return -EINVAL;
6aa20a22 2686
1da177e4
LT		 2687 /* Apply settings and restart link process. */
2688 spin_lock_irq(&gp->lock);
2689 gem_get_cell(gp);
2690 gem_begin_auto_negotiation(gp, cmd);
2691 gem_put_cell(gp);
2692 spin_unlock_irq(&gp->lock);
2693
2694 return 0;
2695}
2696
2697static int gem_nway_reset(struct net_device *dev)
2698{
2699 struct gem *gp = dev->priv;
2700
2701 if (!gp->want_autoneg)
2702 return -EINVAL;
2703
2704 /* Restart link process. */
2705 spin_lock_irq(&gp->lock);
2706 gem_get_cell(gp);
2707 gem_begin_auto_negotiation(gp, NULL);
2708 gem_put_cell(gp);
2709 spin_unlock_irq(&gp->lock);
2710
2711 return 0;
2712}
2713
2714static u32 gem_get_msglevel(struct net_device *dev)
2715{
2716 struct gem *gp = dev->priv;
2717 return gp->msg_enable;
2718}
6aa20a22 2719
1da177e4
LT		 2720static void gem_set_msglevel(struct net_device *dev, u32 value)
2721{
2722 struct gem *gp = dev->priv;
2723 gp->msg_enable = value;
2724}
2725
2726
2727/* Add more when I understand how to program the chip */
2728/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2729
2730#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2731
2732static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2733{
2734 struct gem *gp = dev->priv;
2735
2736 /* Add more when I understand how to program the chip */
2737 if (gp->has_wol) {
2738 wol->supported = WOL_SUPPORTED_MASK;
2739 wol->wolopts = gp->wake_on_lan;
2740 } else {
2741 wol->supported = 0;
2742 wol->wolopts = 0;
2743 }
2744}
2745
2746static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2747{
2748 struct gem *gp = dev->priv;
2749
2750 if (!gp->has_wol)
2751 return -EOPNOTSUPP;
2752 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2753 return 0;
2754}
2755
7282d491 2756static const struct ethtool_ops gem_ethtool_ops = {
1da177e4
LT		 2757 .get_drvinfo = gem_get_drvinfo,
2758 .get_link = ethtool_op_get_link,
2759 .get_settings = gem_get_settings,
2760 .set_settings = gem_set_settings,
2761 .nway_reset = gem_nway_reset,
2762 .get_msglevel = gem_get_msglevel,
2763 .set_msglevel = gem_set_msglevel,
2764 .get_wol = gem_get_wol,
2765 .set_wol = gem_set_wol,
2766};
2767
2768static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2769{
2770 struct gem *gp = dev->priv;
2771 struct mii_ioctl_data *data = if_mii(ifr);
2772 int rc = -EOPNOTSUPP;
2773 unsigned long flags;
2774
e3968fc0 2775 /* Hold the PM mutex while doing ioctl's or we may collide
1da177e4
LT		 2776 * with power management.
2777 */
e3968fc0 2778 mutex_lock(&gp->pm_mutex);
6aa20a22 2779
1da177e4
LT		 2780 spin_lock_irqsave(&gp->lock, flags);
2781 gem_get_cell(gp);
2782 spin_unlock_irqrestore(&gp->lock, flags);
2783
2784 switch (cmd) {
2785 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2786 data->phy_id = gp->mii_phy_addr;
2787 /* Fallthrough... */
2788
2789 case SIOCGMIIREG: /* Read MII PHY register. */
2790 if (!gp->running)
2791 rc = -EAGAIN;
2792 else {
2793 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2794 data->reg_num & 0x1f);
2795 rc = 0;
2796 }
2797 break;
2798
2799 case SIOCSMIIREG: /* Write MII PHY register. */
2800 if (!capable(CAP_NET_ADMIN))
2801 rc = -EPERM;
2802 else if (!gp->running)
2803 rc = -EAGAIN;
2804 else {
2805 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2806 data->val_in);
2807 rc = 0;
2808 }
2809 break;
2810 };
6aa20a22 2811
1da177e4
LT		 2812 spin_lock_irqsave(&gp->lock, flags);
2813 gem_put_cell(gp);
2814 spin_unlock_irqrestore(&gp->lock, flags);
2815
e3968fc0 2816 mutex_unlock(&gp->pm_mutex);
6aa20a22 2817
1da177e4
LT		 2818 return rc;
2819}
2820
2821#if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
2822/* Fetch MAC address from vital product data of PCI ROM. */
4120b028 2823static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
1da177e4
LT		 2824{
2825 int this_offset;
2826
2827 for (this_offset = 0x20; this_offset < len; this_offset++) {
2828 void __iomem *p = rom_base + this_offset;
2829 int i;
2830
2831 if (readb(p + 0) != 0x90 ||
2832 readb(p + 1) != 0x00 ||
2833 readb(p + 2) != 0x09 ||
2834 readb(p + 3) != 0x4e ||
2835 readb(p + 4) != 0x41 ||
2836 readb(p + 5) != 0x06)
2837 continue;
2838
2839 this_offset += 6;
2840 p += 6;
2841
2842 for (i = 0; i < 6; i++)
2843 dev_addr[i] = readb(p + i);
4120b028 2844 return 1;
1da177e4 2845 }
4120b028 2846 return 0;
1da177e4
LT		 2847}
2848
2849static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2850{
4120b028
LT		 2851 size_t size;
2852 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2853
4120b028
LT		 2854 if (p) {
2855 int found;
1da177e4 2856
4120b028
LT		 2857 found = readb(p) == 0x55 &&
2858 readb(p + 1) == 0xaa &&
2859 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2860 pci_unmap_rom(pdev, p);
2861 if (found)
2862 return;
2863 }
1da177e4 2864
1da177e4
LT		 2865 /* Sun MAC prefix then 3 random bytes. */
2866 dev_addr[0] = 0x08;
2867 dev_addr[1] = 0x00;
2868 dev_addr[2] = 0x20;
2869 get_random_bytes(dev_addr + 3, 3);
2870 return;
2871}
2872#endif /* not Sparc and not PPC */
2873
2874static int __devinit gem_get_device_address(struct gem *gp)
2875{
2876#if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2877 struct net_device *dev = gp->dev;
2878#endif
2879
2880#if defined(__sparc__)
2881 struct pci_dev *pdev = gp->pdev;
2882 struct pcidev_cookie *pcp = pdev->sysdata;
de8d28b1 2883 int use_idprom = 1;
1da177e4
LT		 2884
2885 if (pcp != NULL) {
de8d28b1
DM		 2886 unsigned char *addr;
2887 int len;
2888
2889 addr = of_get_property(pcp->prom_node, "local-mac-address",
2890 &len);
2891 if (addr && len == 6) {
2892 use_idprom = 0;
2893 memcpy(dev->dev_addr, addr, 6);
2894 }
1da177e4 2895 }
de8d28b1 2896 if (use_idprom)
1da177e4
LT		 2897 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2898#elif defined(CONFIG_PPC_PMAC)
1a2509c9 2899 const unsigned char *addr;
1da177e4
LT		 2900
2901 addr = get_property(gp->of_node, "local-mac-address", NULL);
2902 if (addr == NULL) {
2903 printk("\n");
2904 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2905 return -1;
2906 }
2907 memcpy(dev->dev_addr, addr, 6);
2908#else
2909 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2910#endif
2911 return 0;
2912}
2913
14904398 2914static void gem_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2915{
2916 struct net_device *dev = pci_get_drvdata(pdev);
2917
2918 if (dev) {
2919 struct gem *gp = dev->priv;
2920
2921 unregister_netdev(dev);
2922
2923 /* Stop the link timer */
2924 del_timer_sync(&gp->link_timer);
2925
2926 /* We shouldn't need any locking here */
2927 gem_get_cell(gp);
2928
2929 /* Wait for a pending reset task to complete */
2930 while (gp->reset_task_pending)
2931 yield();
2932 flush_scheduled_work();
2933
2934 /* Shut the PHY down */
2935 gem_stop_phy(gp, 0);
2936
2937 gem_put_cell(gp);
2938
2939 /* Make sure bus master is disabled */
2940 pci_disable_device(gp->pdev);
2941
2942 /* Free resources */
2943 pci_free_consistent(pdev,
2944 sizeof(struct gem_init_block),
2945 gp->init_block,
2946 gp->gblock_dvma);
2947 iounmap(gp->regs);
2948 pci_release_regions(pdev);
2949 free_netdev(dev);
2950
2951 pci_set_drvdata(pdev, NULL);
2952 }
2953}
2954
2955static int __devinit gem_init_one(struct pci_dev *pdev,
2956 const struct pci_device_id *ent)
2957{
2958 static int gem_version_printed = 0;
2959 unsigned long gemreg_base, gemreg_len;
2960 struct net_device *dev;
2961 struct gem *gp;
2962 int i, err, pci_using_dac;
2963
2964 if (gem_version_printed++ == 0)
2965 printk(KERN_INFO "%s", version);
2966
2967 /* Apple gmac note: during probe, the chip is powered up by
2968 * the arch code to allow the code below to work (and to let
2969 * the chip be probed on the config space. It won't stay powered
2970 * up until the interface is brought up however, so we can't rely
2971 * on register configuration done at this point.
2972 */
2973 err = pci_enable_device(pdev);
2974 if (err) {
2975 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2976 "aborting.\n");
2977 return err;
2978 }
2979 pci_set_master(pdev);
2980
2981 /* Configure DMA attributes. */
2982
2983 /* All of the GEM documentation states that 64-bit DMA addressing
2984 * is fully supported and should work just fine. However the
2985 * front end for RIO based GEMs is different and only supports
2986 * 32-bit addressing.
2987 *
2988 * For now we assume the various PPC GEMs are 32-bit only as well.
2989 */
2990 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2991 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
1e7f0bd8 2992 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 2993 pci_using_dac = 1;
2994 } else {
1e7f0bd8 2995 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 2996 if (err) {
2997 printk(KERN_ERR PFX "No usable DMA configuration, "
2998 "aborting.\n");
2999 goto err_disable_device;
3000 }
3001 pci_using_dac = 0;
3002 }
6aa20a22 3003
1da177e4
LT		 3004 gemreg_base = pci_resource_start(pdev, 0);
3005 gemreg_len = pci_resource_len(pdev, 0);
3006
3007 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3008 printk(KERN_ERR PFX "Cannot find proper PCI device "
3009 "base address, aborting.\n");
3010 err = -ENODEV;
3011 goto err_disable_device;
3012 }
3013
3014 dev = alloc_etherdev(sizeof(*gp));
3015 if (!dev) {
3016 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3017 err = -ENOMEM;
3018 goto err_disable_device;
3019 }
3020 SET_MODULE_OWNER(dev);
3021 SET_NETDEV_DEV(dev, &pdev->dev);
3022
3023 gp = dev->priv;
3024
3025 err = pci_request_regions(pdev, DRV_NAME);
3026 if (err) {
3027 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3028 "aborting.\n");
3029 goto err_out_free_netdev;
3030 }
3031
3032 gp->pdev = pdev;
3033 dev->base_addr = (long) pdev;
3034 gp->dev = dev;
3035
3036 gp->msg_enable = DEFAULT_MSG;
3037
3038 spin_lock_init(&gp->lock);
3039 spin_lock_init(&gp->tx_lock);
e3968fc0 3040 mutex_init(&gp->pm_mutex);
1da177e4
LT		 3041
3042 init_timer(&gp->link_timer);
3043 gp->link_timer.function = gem_link_timer;
3044 gp->link_timer.data = (unsigned long) gp;
3045
3046 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
6aa20a22 3047
1da177e4
LT		 3048 gp->lstate = link_down;
3049 gp->timer_ticks = 0;
3050 netif_carrier_off(dev);
3051
3052 gp->regs = ioremap(gemreg_base, gemreg_len);
3053 if (gp->regs == 0UL) {
3054 printk(KERN_ERR PFX "Cannot map device registers, "
3055 "aborting.\n");
3056 err = -EIO;
3057 goto err_out_free_res;
3058 }
3059
3060 /* On Apple, we want a reference to the Open Firmware device-tree
3061 * node. We use it for clock control.
3062 */
3063#ifdef CONFIG_PPC_PMAC
3064 gp->of_node = pci_device_to_OF_node(pdev);
3065#endif
3066
3067 /* Only Apple version supports WOL afaik */
3068 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3069 gp->has_wol = 1;
3070
3071 /* Make sure cell is enabled */
3072 gem_get_cell(gp);
3073
3074 /* Make sure everything is stopped and in init state */
3075 gem_reset(gp);
3076
3077 /* Fill up the mii_phy structure (even if we won't use it) */
3078 gp->phy_mii.dev = dev;
3079 gp->phy_mii.mdio_read = _phy_read;
3080 gp->phy_mii.mdio_write = _phy_write;
3c326fe9
BH		 3081#ifdef CONFIG_PPC_PMAC
3082 gp->phy_mii.platform_data = gp->of_node;
3083#endif
1da177e4
LT		 3084 /* By default, we start with autoneg */
3085 gp->want_autoneg = 1;
3086
3087 /* Check fifo sizes, PHY type, etc... */
3088 if (gem_check_invariants(gp)) {
3089 err = -ENODEV;
3090 goto err_out_iounmap;
3091 }
3092
3093 /* It is guaranteed that the returned buffer will be at least
3094 * PAGE_SIZE aligned.
3095 */
3096 gp->init_block = (struct gem_init_block *)
3097 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3098 &gp->gblock_dvma);
3099 if (!gp->init_block) {
3100 printk(KERN_ERR PFX "Cannot allocate init block, "
3101 "aborting.\n");
3102 err = -ENOMEM;
3103 goto err_out_iounmap;
3104 }
3105
3106 if (gem_get_device_address(gp))
3107 goto err_out_free_consistent;
3108
3109 dev->open = gem_open;
3110 dev->stop = gem_close;
3111 dev->hard_start_xmit = gem_start_xmit;
3112 dev->get_stats = gem_get_stats;
3113 dev->set_multicast_list = gem_set_multicast;
3114 dev->do_ioctl = gem_ioctl;
3115 dev->poll = gem_poll;
3116 dev->weight = 64;
3117 dev->ethtool_ops = &gem_ethtool_ops;
3118 dev->tx_timeout = gem_tx_timeout;
3119 dev->watchdog_timeo = 5 * HZ;
3120 dev->change_mtu = gem_change_mtu;
3121 dev->irq = pdev->irq;
3122 dev->dma = 0;
3123#ifdef CONFIG_NET_POLL_CONTROLLER
3124 dev->poll_controller = gem_poll_controller;
3125#endif
3126
3127 /* Set that now, in case PM kicks in now */
3128 pci_set_drvdata(pdev, dev);
3129
3130 /* Detect & init PHY, start autoneg, we release the cell now
3131 * too, it will be managed by whoever needs it
3132 */
3133 gem_init_phy(gp);
3134
3135 spin_lock_irq(&gp->lock);
3136 gem_put_cell(gp);
3137 spin_unlock_irq(&gp->lock);
3138
3139 /* Register with kernel */
3140 if (register_netdev(dev)) {
3141 printk(KERN_ERR PFX "Cannot register net device, "
3142 "aborting.\n");
3143 err = -ENOMEM;
3144 goto err_out_free_consistent;
3145 }
3146
3147 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
3148 dev->name);
3149 for (i = 0; i < 6; i++)
3150 printk("%2.2x%c", dev->dev_addr[i],
3151 i == 5 ? ' ' : ':');
3152 printk("\n");
3153
3154 if (gp->phy_type == phy_mii_mdio0 ||
3155 gp->phy_type == phy_mii_mdio1)
6aa20a22 3156 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
1da177e4
LT		 3157 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3158
3159 /* GEM can do it all... */
3160 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3161 if (pci_using_dac)
3162 dev->features |= NETIF_F_HIGHDMA;
3163
3164 return 0;
3165
3166err_out_free_consistent:
3167 gem_remove_one(pdev);
3168err_out_iounmap:
3169 gem_put_cell(gp);
3170 iounmap(gp->regs);
3171
3172err_out_free_res:
3173 pci_release_regions(pdev);
3174
3175err_out_free_netdev:
3176 free_netdev(dev);
3177err_disable_device:
3178 pci_disable_device(pdev);
3179 return err;
3180
3181}
3182
3183
3184static struct pci_driver gem_driver = {
3185 .name = GEM_MODULE_NAME,
3186 .id_table = gem_pci_tbl,
3187 .probe = gem_init_one,
14904398 3188 .remove = gem_remove_one,
1da177e4
LT		 3189#ifdef CONFIG_PM
3190 .suspend = gem_suspend,
3191 .resume = gem_resume,
3192#endif /* CONFIG_PM */
3193};
3194
3195static int __init gem_init(void)
3196{
29917620 3197 return pci_register_driver(&gem_driver);
1da177e4
LT		 3198}
3199
3200static void __exit gem_cleanup(void)
3201{
3202 pci_unregister_driver(&gem_driver);
3203}
3204
3205module_init(gem_init);
3206module_exit(gem_cleanup);
kernel source for telekom puls (alcatel/mediatek)