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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
31 | . Nicolas Pitre <nico@cam.org> | |
32 | . | |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
37 | ||
38 | /* | |
39 | * Define your architecture specific bus configuration parameters here. | |
40 | */ | |
41 | ||
42 | #if defined(CONFIG_ARCH_LUBBOCK) | |
43 | ||
44 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
45 | #define SMC_CAN_USE_8BIT 0 | |
46 | #define SMC_CAN_USE_16BIT 1 | |
47 | #define SMC_CAN_USE_32BIT 0 | |
48 | #define SMC_NOWAIT 1 | |
49 | ||
50 | /* The first two address lines aren't connected... */ | |
51 | #define SMC_IO_SHIFT 2 | |
52 | ||
53 | #define SMC_inw(a, r) readw((a) + (r)) | |
54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
e7b3dc7e | 57 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 58 | |
95af9feb | 59 | #elif defined(CONFIG_BLACKFIN) |
0851a284 WB |
60 | |
61 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH | |
c5760abd JCR |
62 | #define RPC_LSA_DEFAULT RPC_LED_100_10 |
63 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
0851a284 WB |
64 | |
65 | # if defined (CONFIG_BFIN561_EZKIT) | |
66 | #define SMC_CAN_USE_8BIT 0 | |
67 | #define SMC_CAN_USE_16BIT 1 | |
68 | #define SMC_CAN_USE_32BIT 1 | |
69 | #define SMC_IO_SHIFT 0 | |
70 | #define SMC_NOWAIT 1 | |
71 | #define SMC_USE_BFIN_DMA 0 | |
72 | ||
73 | ||
74 | #define SMC_inw(a, r) readw((a) + (r)) | |
75 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
76 | #define SMC_inl(a, r) readl((a) + (r)) | |
77 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
78 | #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) | |
79 | #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) | |
80 | # else | |
81 | #define SMC_CAN_USE_8BIT 0 | |
82 | #define SMC_CAN_USE_16BIT 1 | |
83 | #define SMC_CAN_USE_32BIT 0 | |
84 | #define SMC_IO_SHIFT 0 | |
85 | #define SMC_NOWAIT 1 | |
86 | #define SMC_USE_BFIN_DMA 0 | |
87 | ||
88 | ||
89 | #define SMC_inw(a, r) readw((a) + (r)) | |
90 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
91 | #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) | |
92 | #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) | |
93 | # endif | |
94 | /* check if the mac in reg is valid */ | |
95 | #define SMC_GET_MAC_ADDR(addr) \ | |
96 | do { \ | |
97 | unsigned int __v; \ | |
98 | __v = SMC_inw(ioaddr, ADDR0_REG); \ | |
99 | addr[0] = __v; addr[1] = __v >> 8; \ | |
100 | __v = SMC_inw(ioaddr, ADDR1_REG); \ | |
101 | addr[2] = __v; addr[3] = __v >> 8; \ | |
102 | __v = SMC_inw(ioaddr, ADDR2_REG); \ | |
103 | addr[4] = __v; addr[5] = __v >> 8; \ | |
104 | if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ | |
105 | random_ether_addr(addr); \ | |
106 | } \ | |
107 | } while (0) | |
1da177e4 LT |
108 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) |
109 | ||
110 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
111 | #define SMC_CAN_USE_8BIT 0 | |
112 | #define SMC_CAN_USE_16BIT 1 | |
113 | #define SMC_CAN_USE_32BIT 0 | |
114 | #define SMC_NOWAIT 1 | |
115 | ||
116 | #define SMC_IO_SHIFT 0 | |
117 | ||
118 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
119 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
120 | #define SMC_insw(a, r, p, l) \ | |
121 | do { \ | |
122 | unsigned long __port = (a) + (r); \ | |
123 | u16 *__p = (u16 *)(p); \ | |
124 | int __l = (l); \ | |
125 | insw(__port, __p, __l); \ | |
126 | while (__l > 0) { \ | |
127 | *__p = swab16(*__p); \ | |
128 | __p++; \ | |
129 | __l--; \ | |
130 | } \ | |
131 | } while (0) | |
132 | #define SMC_outsw(a, r, p, l) \ | |
133 | do { \ | |
134 | unsigned long __port = (a) + (r); \ | |
135 | u16 *__p = (u16 *)(p); \ | |
136 | int __l = (l); \ | |
137 | while (__l > 0) { \ | |
138 | /* Believe it or not, the swab isn't needed. */ \ | |
139 | outw( /* swab16 */ (*__p++), __port); \ | |
140 | __l--; \ | |
141 | } \ | |
142 | } while (0) | |
9ded96f2 | 143 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
144 | |
145 | #elif defined(CONFIG_SA1100_PLEB) | |
146 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
147 | #define SMC_CAN_USE_8BIT 1 | |
148 | #define SMC_CAN_USE_16BIT 1 | |
149 | #define SMC_CAN_USE_32BIT 0 | |
150 | #define SMC_IO_SHIFT 0 | |
151 | #define SMC_NOWAIT 1 | |
152 | ||
1cf99be5 RK |
153 | #define SMC_inb(a, r) readb((a) + (r)) |
154 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
155 | #define SMC_inw(a, r) readw((a) + (r)) | |
156 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
157 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
158 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
159 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
160 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 161 | |
e7b3dc7e | 162 | #define SMC_IRQ_FLAGS (-1) |
1da177e4 LT |
163 | |
164 | #elif defined(CONFIG_SA1100_ASSABET) | |
165 | ||
166 | #include <asm/arch/neponset.h> | |
167 | ||
168 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
169 | #define SMC_CAN_USE_8BIT 1 | |
170 | #define SMC_CAN_USE_16BIT 0 | |
171 | #define SMC_CAN_USE_32BIT 0 | |
172 | #define SMC_NOWAIT 1 | |
173 | ||
174 | /* The first two address lines aren't connected... */ | |
175 | #define SMC_IO_SHIFT 2 | |
176 | ||
177 | #define SMC_inb(a, r) readb((a) + (r)) | |
178 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
179 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
180 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
e7b3dc7e | 181 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 182 | |
b0348b90 LB |
183 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) |
184 | ||
185 | #define SMC_CAN_USE_8BIT 0 | |
186 | #define SMC_CAN_USE_16BIT 1 | |
187 | #define SMC_CAN_USE_32BIT 0 | |
188 | #define SMC_IO_SHIFT 0 | |
189 | #define SMC_NOWAIT 1 | |
b0348b90 | 190 | |
b0348b90 | 191 | #define SMC_inw(a, r) readw((a) + (r)) |
b0348b90 | 192 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
b0348b90 LB |
193 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
194 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
195 | ||
1da177e4 LT |
196 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
197 | defined(CONFIG_MACH_MAINSTONE) || \ | |
198 | defined(CONFIG_ARCH_PXA_IDP) || \ | |
199 | defined(CONFIG_ARCH_RAMSES) | |
200 | ||
201 | #define SMC_CAN_USE_8BIT 1 | |
202 | #define SMC_CAN_USE_16BIT 1 | |
203 | #define SMC_CAN_USE_32BIT 1 | |
204 | #define SMC_IO_SHIFT 0 | |
205 | #define SMC_NOWAIT 1 | |
206 | #define SMC_USE_PXA_DMA 1 | |
207 | ||
208 | #define SMC_inb(a, r) readb((a) + (r)) | |
209 | #define SMC_inw(a, r) readw((a) + (r)) | |
210 | #define SMC_inl(a, r) readl((a) + (r)) | |
211 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
212 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
213 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
214 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 215 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 LT |
216 | |
217 | /* We actually can't write halfwords properly if not word aligned */ | |
218 | static inline void | |
eb1d6988 | 219 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
1da177e4 LT |
220 | { |
221 | if (reg & 2) { | |
222 | unsigned int v = val << 16; | |
223 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
224 | writel(v, ioaddr + (reg & ~2)); | |
225 | } else { | |
226 | writew(val, ioaddr + reg); | |
227 | } | |
228 | } | |
229 | ||
7c826a0b | 230 | #elif defined(CONFIG_MACH_ZYLONITE) |
231 | ||
232 | #define SMC_CAN_USE_8BIT 1 | |
233 | #define SMC_CAN_USE_16BIT 1 | |
234 | #define SMC_CAN_USE_32BIT 0 | |
235 | #define SMC_IO_SHIFT 0 | |
236 | #define SMC_NOWAIT 1 | |
237 | #define SMC_USE_PXA_DMA 1 | |
238 | #define SMC_inb(a, r) readb((a) + (r)) | |
239 | #define SMC_inw(a, r) readw((a) + (r)) | |
240 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
241 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
242 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
243 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
e7b3dc7e | 244 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
7c826a0b | 245 | |
1da177e4 LT |
246 | #elif defined(CONFIG_ARCH_OMAP) |
247 | ||
248 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
249 | #define SMC_CAN_USE_8BIT 0 | |
250 | #define SMC_CAN_USE_16BIT 1 | |
251 | #define SMC_CAN_USE_32BIT 0 | |
252 | #define SMC_IO_SHIFT 0 | |
253 | #define SMC_NOWAIT 1 | |
254 | ||
1da177e4 LT |
255 | #define SMC_inw(a, r) readw((a) + (r)) |
256 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
257 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
258 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
e7b3dc7e | 259 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
5f13e7ec | 260 | |
1da177e4 LT |
261 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
262 | ||
263 | #define SMC_CAN_USE_8BIT 0 | |
264 | #define SMC_CAN_USE_16BIT 1 | |
265 | #define SMC_CAN_USE_32BIT 0 | |
266 | ||
267 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
268 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
269 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
270 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
271 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
272 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
273 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
274 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
275 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
276 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
277 | ||
9ded96f2 | 278 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
279 | |
280 | #elif defined(CONFIG_ISA) | |
281 | ||
282 | #define SMC_CAN_USE_8BIT 1 | |
283 | #define SMC_CAN_USE_16BIT 1 | |
284 | #define SMC_CAN_USE_32BIT 0 | |
285 | ||
286 | #define SMC_inb(a, r) inb((a) + (r)) | |
287 | #define SMC_inw(a, r) inw((a) + (r)) | |
288 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
289 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
290 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
291 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
292 | ||
5125ed91 NI |
293 | #elif defined(CONFIG_SUPERH) |
294 | ||
6026ee67 | 295 | #ifdef CONFIG_SOLUTION_ENGINE |
18ad4e70 | 296 | #define SMC_IRQ_FLAGS (0) |
5125ed91 NI |
297 | #define SMC_CAN_USE_8BIT 0 |
298 | #define SMC_CAN_USE_16BIT 1 | |
299 | #define SMC_CAN_USE_32BIT 0 | |
300 | #define SMC_IO_SHIFT 0 | |
301 | #define SMC_NOWAIT 1 | |
302 | ||
5125ed91 | 303 | #define SMC_inw(a, r) inw((a) + (r)) |
5125ed91 NI |
304 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) |
305 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
306 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
307 | ||
308 | #else /* BOARDS */ | |
309 | ||
310 | #define SMC_CAN_USE_8BIT 1 | |
311 | #define SMC_CAN_USE_16BIT 1 | |
092ed997 | 312 | #define SMC_CAN_USE_32BIT 0 |
5125ed91 NI |
313 | |
314 | #define SMC_inb(a, r) inb((a) + (r)) | |
315 | #define SMC_inw(a, r) inw((a) + (r)) | |
316 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
317 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
318 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
319 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
320 | ||
321 | #endif /* BOARDS */ | |
322 | ||
1da177e4 LT |
323 | #elif defined(CONFIG_M32R) |
324 | ||
325 | #define SMC_CAN_USE_8BIT 0 | |
326 | #define SMC_CAN_USE_16BIT 1 | |
327 | #define SMC_CAN_USE_32BIT 0 | |
328 | ||
59dc76a4 | 329 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
330 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
331 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
332 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
333 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
334 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 335 | |
9ded96f2 | 336 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
337 | |
338 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
339 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
340 | ||
d4adcffb MS |
341 | #elif defined(CONFIG_MACH_LPD79520) \ |
342 | || defined(CONFIG_MACH_LPD7A400) \ | |
343 | || defined(CONFIG_MACH_LPD7A404) | |
1da177e4 | 344 | |
d4adcffb MS |
345 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
346 | * way that the CPU handles chip selects and the way that the SMC chip | |
347 | * expects the chip select to operate. Refer to | |
1da177e4 | 348 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
d4adcffb MS |
349 | * IOBARRIER is a byte, in order that we read the least-common |
350 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
351 | * accessible region. | |
1da177e4 LT |
352 | * |
353 | * There is no explicit protection against interrupts intervening | |
354 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
355 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
356 | * that the driver interrupts itself between a writew to the chip an | |
357 | * the IOBARRIER that follows *and* the cache is large enough that the | |
358 | * first off-chip access while handing the interrupt is to the SMC | |
359 | * chip. Other devices in the same address space as the SMC chip must | |
360 | * be aware of the potential for trouble and perform a similar | |
361 | * IOBARRIER on entry to their ISR. | |
362 | */ | |
363 | ||
364 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
365 | ||
366 | #define SMC_CAN_USE_8BIT 0 | |
367 | #define SMC_CAN_USE_16BIT 1 | |
368 | #define SMC_CAN_USE_32BIT 0 | |
369 | #define SMC_NOWAIT 0 | |
d4adcffb | 370 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
1da177e4 | 371 | |
d4adcffb MS |
372 | #define SMC_inw(a,r)\ |
373 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
374 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
1da177e4 | 375 | |
d4adcffb MS |
376 | #define SMC_insw LPD7_SMC_insw |
377 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
378 | unsigned char* p, int l) | |
379 | { | |
380 | unsigned short* ps = (unsigned short*) p; | |
381 | while (l-- > 0) { | |
382 | *ps++ = readw (a + r); | |
383 | LPD7X_IOBARRIER; | |
384 | } | |
385 | } | |
09779c6d | 386 | |
d4adcffb MS |
387 | #define SMC_outsw LPD7_SMC_outsw |
388 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
389 | unsigned char* p, int l) | |
1da177e4 LT |
390 | { |
391 | unsigned short* ps = (unsigned short*) p; | |
392 | while (l-- > 0) { | |
393 | writew (*ps++, a + r); | |
d4adcffb | 394 | LPD7X_IOBARRIER; |
1da177e4 LT |
395 | } |
396 | } | |
397 | ||
d4adcffb | 398 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
1da177e4 LT |
399 | |
400 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
401 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
402 | ||
55793455 PP |
403 | #elif defined(CONFIG_SOC_AU1X00) |
404 | ||
405 | #include <au1xxx.h> | |
406 | ||
407 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
408 | #define SMC_CAN_USE_8BIT 0 | |
409 | #define SMC_CAN_USE_16BIT 1 | |
410 | #define SMC_CAN_USE_32BIT 0 | |
411 | #define SMC_IO_SHIFT 0 | |
412 | #define SMC_NOWAIT 1 | |
413 | ||
414 | #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) | |
415 | #define SMC_insw(a, r, p, l) \ | |
416 | do { \ | |
417 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
418 | int _l = (l); \ | |
419 | u16 *_p = (u16 *)(p); \ | |
420 | while (_l-- > 0) \ | |
421 | *_p++ = au_readw(_a); \ | |
422 | } while(0) | |
423 | #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) | |
424 | #define SMC_outsw(a, r, p, l) \ | |
425 | do { \ | |
426 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
427 | int _l = (l); \ | |
428 | const u16 *_p = (const u16 *)(p); \ | |
429 | while (_l-- > 0) \ | |
430 | au_writew(*_p++ , _a); \ | |
431 | } while(0) | |
432 | ||
9ded96f2 | 433 | #define SMC_IRQ_FLAGS (0) |
33fee56a DS |
434 | |
435 | #elif defined(CONFIG_ARCH_VERSATILE) | |
436 | ||
437 | #define SMC_CAN_USE_8BIT 1 | |
438 | #define SMC_CAN_USE_16BIT 1 | |
439 | #define SMC_CAN_USE_32BIT 1 | |
440 | #define SMC_NOWAIT 1 | |
441 | ||
442 | #define SMC_inb(a, r) readb((a) + (r)) | |
443 | #define SMC_inw(a, r) readw((a) + (r)) | |
444 | #define SMC_inl(a, r) readl((a) + (r)) | |
445 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
446 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
447 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
448 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
449 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 450 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
55793455 | 451 | |
1da177e4 LT |
452 | #else |
453 | ||
454 | #define SMC_CAN_USE_8BIT 1 | |
455 | #define SMC_CAN_USE_16BIT 1 | |
456 | #define SMC_CAN_USE_32BIT 1 | |
457 | #define SMC_NOWAIT 1 | |
458 | ||
459 | #define SMC_inb(a, r) readb((a) + (r)) | |
460 | #define SMC_inw(a, r) readw((a) + (r)) | |
461 | #define SMC_inl(a, r) readl((a) + (r)) | |
462 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
463 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
464 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
465 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
466 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
467 | ||
468 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
469 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
470 | ||
471 | #endif | |
472 | ||
073ac8fd RK |
473 | |
474 | /* store this information for the driver.. */ | |
475 | struct smc_local { | |
476 | /* | |
477 | * If I have to wait until memory is available to send a | |
478 | * packet, I will store the skbuff here, until I get the | |
479 | * desired memory. Then, I'll send it out and free it. | |
480 | */ | |
481 | struct sk_buff *pending_tx_skb; | |
482 | struct tasklet_struct tx_task; | |
483 | ||
484 | /* version/revision of the SMC91x chip */ | |
485 | int version; | |
486 | ||
487 | /* Contains the current active transmission mode */ | |
488 | int tcr_cur_mode; | |
489 | ||
490 | /* Contains the current active receive mode */ | |
491 | int rcr_cur_mode; | |
492 | ||
493 | /* Contains the current active receive/phy mode */ | |
494 | int rpc_cur_mode; | |
495 | int ctl_rfduplx; | |
496 | int ctl_rspeed; | |
497 | ||
498 | u32 msg_enable; | |
499 | u32 phy_type; | |
500 | struct mii_if_info mii; | |
501 | ||
502 | /* work queue */ | |
503 | struct work_struct phy_configure; | |
504 | struct net_device *dev; | |
505 | int work_pending; | |
506 | ||
507 | spinlock_t lock; | |
508 | ||
509 | #ifdef SMC_USE_PXA_DMA | |
510 | /* DMA needs the physical address of the chip */ | |
511 | u_long physaddr; | |
512 | struct device *device; | |
513 | #endif | |
514 | void __iomem *base; | |
515 | void __iomem *datacs; | |
516 | }; | |
517 | ||
518 | ||
1da177e4 LT |
519 | #ifdef SMC_USE_PXA_DMA |
520 | /* | |
521 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
522 | * always happening in irq context so no need to worry about races. TX is | |
523 | * different and probably not worth it for that reason, and not as critical | |
524 | * as RX which can overrun memory and lose packets. | |
525 | */ | |
526 | #include <linux/dma-mapping.h> | |
527 | #include <asm/dma.h> | |
528 | #include <asm/arch/pxa-regs.h> | |
529 | ||
530 | #ifdef SMC_insl | |
531 | #undef SMC_insl | |
532 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 533 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
1da177e4 | 534 | static inline void |
073ac8fd | 535 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
536 | u_char *buf, int len) |
537 | { | |
073ac8fd | 538 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
539 | dma_addr_t dmabuf; |
540 | ||
541 | /* fallback if no DMA available */ | |
542 | if (dma == (unsigned char)-1) { | |
543 | readsl(ioaddr + reg, buf, len); | |
544 | return; | |
545 | } | |
546 | ||
547 | /* 64 bit alignment is required for memory to memory DMA */ | |
548 | if ((long)buf & 4) { | |
549 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
550 | buf += 4; | |
551 | len--; | |
552 | } | |
553 | ||
554 | len *= 4; | |
073ac8fd | 555 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
556 | DCSR(dma) = DCSR_NODESC; |
557 | DTADR(dma) = dmabuf; | |
558 | DSADR(dma) = physaddr + reg; | |
559 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
560 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
561 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
562 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
563 | cpu_relax(); | |
564 | DCSR(dma) = 0; | |
073ac8fd | 565 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
566 | } |
567 | #endif | |
568 | ||
569 | #ifdef SMC_insw | |
570 | #undef SMC_insw | |
571 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 572 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 573 | static inline void |
073ac8fd | 574 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
575 | u_char *buf, int len) |
576 | { | |
073ac8fd | 577 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
578 | dma_addr_t dmabuf; |
579 | ||
580 | /* fallback if no DMA available */ | |
581 | if (dma == (unsigned char)-1) { | |
582 | readsw(ioaddr + reg, buf, len); | |
583 | return; | |
584 | } | |
585 | ||
586 | /* 64 bit alignment is required for memory to memory DMA */ | |
587 | while ((long)buf & 6) { | |
588 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
589 | buf += 2; | |
590 | len--; | |
591 | } | |
592 | ||
593 | len *= 2; | |
073ac8fd | 594 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
595 | DCSR(dma) = DCSR_NODESC; |
596 | DTADR(dma) = dmabuf; | |
597 | DSADR(dma) = physaddr + reg; | |
598 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
599 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
600 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
601 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
602 | cpu_relax(); | |
603 | DCSR(dma) = 0; | |
073ac8fd | 604 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
605 | } |
606 | #endif | |
607 | ||
608 | static void | |
7d12e780 | 609 | smc_pxa_dma_irq(int dma, void *dummy) |
1da177e4 LT |
610 | { |
611 | DCSR(dma) = 0; | |
612 | } | |
613 | #endif /* SMC_USE_PXA_DMA */ | |
614 | ||
615 | ||
09779c6d NP |
616 | /* |
617 | * Everything a particular hardware setup needs should have been defined | |
618 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
619 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
620 | * use of them. | |
621 | */ | |
622 | ||
623 | #if ! SMC_CAN_USE_32BIT | |
624 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
625 | #define SMC_outl(x, ioaddr, reg) BUG() | |
626 | #define SMC_insl(a, r, p, l) BUG() | |
627 | #define SMC_outsl(a, r, p, l) BUG() | |
628 | #endif | |
629 | ||
630 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
631 | #define SMC_insl(a, r, p, l) BUG() | |
632 | #define SMC_outsl(a, r, p, l) BUG() | |
633 | #endif | |
634 | ||
635 | #if ! SMC_CAN_USE_16BIT | |
636 | ||
637 | /* | |
638 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
639 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
640 | */ | |
641 | #define SMC_outw(x, ioaddr, reg) \ | |
642 | do { \ | |
643 | unsigned int __val16 = (x); \ | |
644 | SMC_outb( __val16, ioaddr, reg ); \ | |
645 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
646 | } while (0) | |
647 | #define SMC_inw(ioaddr, reg) \ | |
648 | ({ \ | |
649 | unsigned int __val16; \ | |
650 | __val16 = SMC_inb( ioaddr, reg ); \ | |
651 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
652 | __val16; \ | |
653 | }) | |
654 | ||
655 | #define SMC_insw(a, r, p, l) BUG() | |
656 | #define SMC_outsw(a, r, p, l) BUG() | |
657 | ||
658 | #endif | |
659 | ||
660 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
661 | #define SMC_insw(a, r, p, l) BUG() | |
662 | #define SMC_outsw(a, r, p, l) BUG() | |
663 | #endif | |
664 | ||
665 | #if ! SMC_CAN_USE_8BIT | |
666 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
667 | #define SMC_outb(x, ioaddr, reg) BUG() | |
668 | #define SMC_insb(a, r, p, l) BUG() | |
669 | #define SMC_outsb(a, r, p, l) BUG() | |
670 | #endif | |
671 | ||
672 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
673 | #define SMC_insb(a, r, p, l) BUG() | |
674 | #define SMC_outsb(a, r, p, l) BUG() | |
675 | #endif | |
676 | ||
677 | #ifndef SMC_CAN_USE_DATACS | |
678 | #define SMC_CAN_USE_DATACS 0 | |
679 | #endif | |
680 | ||
1da177e4 LT |
681 | #ifndef SMC_IO_SHIFT |
682 | #define SMC_IO_SHIFT 0 | |
683 | #endif | |
09779c6d NP |
684 | |
685 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 686 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
687 | #endif |
688 | ||
689 | #ifndef SMC_INTERRUPT_PREAMBLE | |
690 | #define SMC_INTERRUPT_PREAMBLE | |
691 | #endif | |
692 | ||
693 | ||
694 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
695 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
696 | #define SMC_DATA_EXTENT (4) | |
697 | ||
698 | /* | |
699 | . Bank Select Register: | |
700 | . | |
701 | . yyyy yyyy 0000 00xx | |
702 | . xx = bank number | |
703 | . yyyy yyyy = 0x33, for identification purposes. | |
704 | */ | |
705 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
706 | ||
707 | ||
708 | // Transmit Control Register | |
709 | /* BANK 0 */ | |
710 | #define TCR_REG SMC_REG(0x0000, 0) | |
711 | #define TCR_ENABLE 0x0001 // When 1 we can transmit | |
712 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
713 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
714 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
715 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
716 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
717 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
718 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
719 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
720 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
721 | ||
722 | #define TCR_CLEAR 0 /* do NOTHING */ | |
723 | /* the default settings for the TCR register : */ | |
724 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
725 | ||
726 | ||
727 | // EPH Status Register | |
728 | /* BANK 0 */ | |
729 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) | |
730 | #define ES_TX_SUC 0x0001 // Last TX was successful | |
731 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
732 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
733 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
734 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
735 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
736 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
737 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
738 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
739 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
740 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
741 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
742 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
743 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
744 | ||
745 | ||
746 | // Receive Control Register | |
747 | /* BANK 0 */ | |
748 | #define RCR_REG SMC_REG(0x0004, 0) | |
749 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted | |
750 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
751 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
752 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
753 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
754 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
755 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
756 | #define RCR_SOFTRST 0x8000 // resets the chip | |
757 | ||
758 | /* the normal settings for the RCR register : */ | |
759 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
760 | #define RCR_CLEAR 0x0 // set it to a base state | |
761 | ||
762 | ||
763 | // Counter Register | |
764 | /* BANK 0 */ | |
765 | #define COUNTER_REG SMC_REG(0x0006, 0) | |
766 | ||
767 | ||
768 | // Memory Information Register | |
769 | /* BANK 0 */ | |
770 | #define MIR_REG SMC_REG(0x0008, 0) | |
771 | ||
772 | ||
773 | // Receive/Phy Control Register | |
774 | /* BANK 0 */ | |
775 | #define RPC_REG SMC_REG(0x000A, 0) | |
776 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. | |
777 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
778 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
779 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
780 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
781 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
782 | #define RPC_LED_RES (0x01) // LED = Reserved | |
783 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
784 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
785 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
786 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
787 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
788 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
789 | ||
790 | #ifndef RPC_LSA_DEFAULT | |
791 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
792 | #endif | |
793 | #ifndef RPC_LSB_DEFAULT | |
794 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
795 | #endif | |
796 | ||
797 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
798 | ||
799 | ||
800 | /* Bank 0 0x0C is reserved */ | |
801 | ||
802 | // Bank Select Register | |
803 | /* All Banks */ | |
804 | #define BSR_REG 0x000E | |
805 | ||
806 | ||
807 | // Configuration Reg | |
808 | /* BANK 1 */ | |
809 | #define CONFIG_REG SMC_REG(0x0000, 1) | |
810 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy | |
811 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
812 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
813 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
814 | ||
815 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
816 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
817 | ||
818 | ||
819 | // Base Address Register | |
820 | /* BANK 1 */ | |
821 | #define BASE_REG SMC_REG(0x0002, 1) | |
822 | ||
823 | ||
824 | // Individual Address Registers | |
825 | /* BANK 1 */ | |
826 | #define ADDR0_REG SMC_REG(0x0004, 1) | |
827 | #define ADDR1_REG SMC_REG(0x0006, 1) | |
828 | #define ADDR2_REG SMC_REG(0x0008, 1) | |
829 | ||
830 | ||
831 | // General Purpose Register | |
832 | /* BANK 1 */ | |
833 | #define GP_REG SMC_REG(0x000A, 1) | |
834 | ||
835 | ||
836 | // Control Register | |
837 | /* BANK 1 */ | |
838 | #define CTL_REG SMC_REG(0x000C, 1) | |
839 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received | |
840 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
841 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
842 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
843 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
844 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
845 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
846 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
847 | ||
848 | ||
849 | // MMU Command Register | |
850 | /* BANK 2 */ | |
851 | #define MMU_CMD_REG SMC_REG(0x0000, 2) | |
852 | #define MC_BUSY 1 // When 1 the last release has not completed | |
853 | #define MC_NOP (0<<5) // No Op | |
854 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
855 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
856 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
857 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
858 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
859 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
860 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
861 | ||
862 | ||
863 | // Packet Number Register | |
864 | /* BANK 2 */ | |
865 | #define PN_REG SMC_REG(0x0002, 2) | |
866 | ||
867 | ||
868 | // Allocation Result Register | |
869 | /* BANK 2 */ | |
870 | #define AR_REG SMC_REG(0x0003, 2) | |
871 | #define AR_FAILED 0x80 // Alocation Failed | |
872 | ||
873 | ||
874 | // TX FIFO Ports Register | |
875 | /* BANK 2 */ | |
876 | #define TXFIFO_REG SMC_REG(0x0004, 2) | |
877 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty | |
878 | ||
879 | // RX FIFO Ports Register | |
880 | /* BANK 2 */ | |
881 | #define RXFIFO_REG SMC_REG(0x0005, 2) | |
882 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty | |
883 | ||
884 | #define FIFO_REG SMC_REG(0x0004, 2) | |
885 | ||
886 | // Pointer Register | |
887 | /* BANK 2 */ | |
888 | #define PTR_REG SMC_REG(0x0006, 2) | |
889 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area | |
890 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
891 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
892 | ||
893 | ||
894 | // Data Register | |
895 | /* BANK 2 */ | |
896 | #define DATA_REG SMC_REG(0x0008, 2) | |
897 | ||
898 | ||
899 | // Interrupt Status/Acknowledge Register | |
900 | /* BANK 2 */ | |
901 | #define INT_REG SMC_REG(0x000C, 2) | |
902 | ||
903 | ||
904 | // Interrupt Mask Register | |
905 | /* BANK 2 */ | |
906 | #define IM_REG SMC_REG(0x000D, 2) | |
907 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt | |
908 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
909 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
910 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
911 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
912 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
913 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
914 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
915 | ||
916 | ||
917 | // Multicast Table Registers | |
918 | /* BANK 3 */ | |
919 | #define MCAST_REG1 SMC_REG(0x0000, 3) | |
920 | #define MCAST_REG2 SMC_REG(0x0002, 3) | |
921 | #define MCAST_REG3 SMC_REG(0x0004, 3) | |
922 | #define MCAST_REG4 SMC_REG(0x0006, 3) | |
923 | ||
924 | ||
925 | // Management Interface Register (MII) | |
926 | /* BANK 3 */ | |
927 | #define MII_REG SMC_REG(0x0008, 3) | |
928 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup | |
929 | #define MII_MDOE 0x0008 // MII Output Enable | |
930 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
931 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
932 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
933 | ||
934 | ||
935 | // Revision Register | |
936 | /* BANK 3 */ | |
937 | /* ( hi: chip id low: rev # ) */ | |
938 | #define REV_REG SMC_REG(0x000A, 3) | |
939 | ||
940 | ||
941 | // Early RCV Register | |
942 | /* BANK 3 */ | |
943 | /* this is NOT on SMC9192 */ | |
944 | #define ERCV_REG SMC_REG(0x000C, 3) | |
945 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received | |
946 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
947 | ||
948 | ||
949 | // External Register | |
950 | /* BANK 7 */ | |
951 | #define EXT_REG SMC_REG(0x0000, 7) | |
952 | ||
953 | ||
954 | #define CHIP_9192 3 | |
955 | #define CHIP_9194 4 | |
956 | #define CHIP_9195 5 | |
957 | #define CHIP_9196 6 | |
958 | #define CHIP_91100 7 | |
959 | #define CHIP_91100FD 8 | |
960 | #define CHIP_91111FD 9 | |
961 | ||
962 | static const char * chip_ids[ 16 ] = { | |
963 | NULL, NULL, NULL, | |
964 | /* 3 */ "SMC91C90/91C92", | |
965 | /* 4 */ "SMC91C94", | |
966 | /* 5 */ "SMC91C95", | |
967 | /* 6 */ "SMC91C96", | |
968 | /* 7 */ "SMC91C100", | |
969 | /* 8 */ "SMC91C100FD", | |
970 | /* 9 */ "SMC91C11xFD", | |
971 | NULL, NULL, NULL, | |
972 | NULL, NULL, NULL}; | |
973 | ||
974 | ||
1da177e4 LT |
975 | /* |
976 | . Receive status bits | |
977 | */ | |
978 | #define RS_ALGNERR 0x8000 | |
979 | #define RS_BRODCAST 0x4000 | |
980 | #define RS_BADCRC 0x2000 | |
981 | #define RS_ODDFRAME 0x1000 | |
982 | #define RS_TOOLONG 0x0800 | |
983 | #define RS_TOOSHORT 0x0400 | |
984 | #define RS_MULTICAST 0x0001 | |
985 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
986 | ||
987 | ||
988 | /* | |
989 | * PHY IDs | |
990 | * LAN83C183 == LAN91C111 Internal PHY | |
991 | */ | |
992 | #define PHY_LAN83C183 0x0016f840 | |
993 | #define PHY_LAN83C180 0x02821c50 | |
994 | ||
995 | /* | |
996 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
997 | * | |
998 | * Generic PHY registers can be found in <linux/mii.h> | |
999 | * | |
1000 | * These phy registers are specific to our on-board phy. | |
1001 | */ | |
1002 | ||
1003 | // PHY Configuration Register 1 | |
1004 | #define PHY_CFG1_REG 0x10 | |
1005 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
1006 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
1007 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
1008 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
1009 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
1010 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
1011 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
1012 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
1013 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
1014 | #define PHY_CFG1_TLVL_MASK 0x003C | |
1015 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
1016 | ||
1017 | ||
1018 | // PHY Configuration Register 2 | |
1019 | #define PHY_CFG2_REG 0x11 | |
1020 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
1021 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
1022 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
1023 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
1024 | ||
1025 | // PHY Status Output (and Interrupt status) Register | |
1026 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
1027 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
1028 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
1029 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
1030 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
1031 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
1032 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
1033 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
1034 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
1035 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
1036 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
1037 | ||
1038 | // PHY Interrupt/Status Mask Register | |
1039 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
1040 | // Uses the same bit definitions as PHY_INT_REG | |
1041 | ||
1042 | ||
1043 | /* | |
1044 | * SMC91C96 ethernet config and status registers. | |
1045 | * These are in the "attribute" space. | |
1046 | */ | |
1047 | #define ECOR 0x8000 | |
1048 | #define ECOR_RESET 0x80 | |
1049 | #define ECOR_LEVEL_IRQ 0x40 | |
1050 | #define ECOR_WR_ATTRIB 0x04 | |
1051 | #define ECOR_ENABLE 0x01 | |
1052 | ||
1053 | #define ECSR 0x8002 | |
1054 | #define ECSR_IOIS8 0x20 | |
1055 | #define ECSR_PWRDWN 0x04 | |
1056 | #define ECSR_INT 0x02 | |
1057 | ||
1058 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
1059 | ||
1060 | ||
1061 | /* | |
1062 | * Macros to abstract register access according to the data bus | |
1063 | * capabilities. Please use those and not the in/out primitives. | |
1064 | * Note: the following macros do *not* select the bank -- this must | |
1065 | * be done separately as needed in the main code. The SMC_REG() macro | |
1066 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
1067 | * |
1068 | * Note: despite inline functions being safer, everything leading to this | |
1069 | * should preferably be macros to let BUG() display the line number in | |
1070 | * the core source code since we're interested in the top call site | |
1071 | * not in any inline function location. | |
1da177e4 LT |
1072 | */ |
1073 | ||
1074 | #if SMC_DEBUG > 0 | |
1075 | #define SMC_REG(reg, bank) \ | |
1076 | ({ \ | |
1077 | int __b = SMC_CURRENT_BANK(); \ | |
1078 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ | |
1079 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
1080 | CARDNAME, __b ); \ | |
1081 | BUG(); \ | |
1082 | } \ | |
1083 | reg<<SMC_IO_SHIFT; \ | |
1084 | }) | |
1085 | #else | |
1086 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) | |
1087 | #endif | |
1088 | ||
09779c6d NP |
1089 | /* |
1090 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
1091 | * aligned to a 32 bit boundary. I tell you that does exist! | |
1092 | * Fortunately the affected register accesses can be easily worked around | |
1093 | * since we can write zeroes to the preceeding 16 bits without adverse | |
1094 | * effects and use a 32-bit access. | |
1095 | * | |
1096 | * Enforce it on any 32-bit capable setup for now. | |
1097 | */ | |
1098 | #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT | |
1099 | ||
1100 | #define SMC_GET_PN() \ | |
1101 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ | |
1102 | : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) | |
1103 | ||
1104 | #define SMC_SET_PN(x) \ | |
1105 | do { \ | |
1106 | if (SMC_MUST_ALIGN_WRITE) \ | |
1107 | SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ | |
1108 | else if (SMC_CAN_USE_8BIT) \ | |
1109 | SMC_outb(x, ioaddr, PN_REG); \ | |
1110 | else \ | |
1111 | SMC_outw(x, ioaddr, PN_REG); \ | |
1112 | } while (0) | |
1113 | ||
1114 | #define SMC_GET_AR() \ | |
1115 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ | |
1116 | : (SMC_inw(ioaddr, PN_REG) >> 8) ) | |
1117 | ||
1118 | #define SMC_GET_TXFIFO() \ | |
1119 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ | |
1120 | : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) | |
1121 | ||
1122 | #define SMC_GET_RXFIFO() \ | |
1123 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ | |
1124 | : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) | |
1125 | ||
1126 | #define SMC_GET_INT() \ | |
1127 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ | |
1128 | : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) | |
1129 | ||
1da177e4 LT |
1130 | #define SMC_ACK_INT(x) \ |
1131 | do { \ | |
09779c6d NP |
1132 | if (SMC_CAN_USE_8BIT) \ |
1133 | SMC_outb(x, ioaddr, INT_REG); \ | |
1134 | else { \ | |
1135 | unsigned long __flags; \ | |
1136 | int __mask; \ | |
1137 | local_irq_save(__flags); \ | |
1138 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ | |
1139 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ | |
1140 | local_irq_restore(__flags); \ | |
1141 | } \ | |
1142 | } while (0) | |
1143 | ||
1144 | #define SMC_GET_INT_MASK() \ | |
1145 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ | |
1146 | : (SMC_inw( ioaddr, INT_REG ) >> 8) ) | |
1147 | ||
1148 | #define SMC_SET_INT_MASK(x) \ | |
1149 | do { \ | |
1150 | if (SMC_CAN_USE_8BIT) \ | |
1151 | SMC_outb(x, ioaddr, IM_REG); \ | |
1152 | else \ | |
1153 | SMC_outw((x) << 8, ioaddr, INT_REG); \ | |
1154 | } while (0) | |
1155 | ||
1156 | #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) | |
1157 | ||
1158 | #define SMC_SELECT_BANK(x) \ | |
1159 | do { \ | |
1160 | if (SMC_MUST_ALIGN_WRITE) \ | |
1161 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ | |
1162 | else \ | |
1163 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
1164 | } while (0) | |
1165 | ||
1166 | #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) | |
1167 | ||
1168 | #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) | |
1169 | ||
1170 | #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) | |
1171 | ||
1172 | #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) | |
1173 | ||
1174 | #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) | |
1175 | ||
1176 | #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) | |
1177 | ||
1178 | #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) | |
1179 | ||
1180 | #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) | |
1181 | ||
1182 | #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) | |
1183 | ||
1184 | #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) | |
1185 | ||
1186 | #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) | |
1187 | ||
1188 | #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) | |
1189 | ||
1190 | #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) | |
1191 | ||
1192 | #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) | |
1193 | ||
1194 | #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) | |
1195 | ||
1196 | #define SMC_SET_PTR(x) \ | |
1197 | do { \ | |
1198 | if (SMC_MUST_ALIGN_WRITE) \ | |
1199 | SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ | |
1200 | else \ | |
1201 | SMC_outw(x, ioaddr, PTR_REG); \ | |
1da177e4 | 1202 | } while (0) |
1da177e4 | 1203 | |
09779c6d NP |
1204 | #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) |
1205 | ||
1206 | #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) | |
1207 | ||
1208 | #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) | |
1209 | ||
1210 | #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) | |
1211 | ||
1212 | #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) | |
1213 | ||
1214 | #define SMC_SET_RPC(x) \ | |
1215 | do { \ | |
1216 | if (SMC_MUST_ALIGN_WRITE) \ | |
1217 | SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ | |
1218 | else \ | |
1219 | SMC_outw(x, ioaddr, RPC_REG); \ | |
1220 | } while (0) | |
1221 | ||
1222 | #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) | |
1223 | ||
1224 | #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) | |
1da177e4 LT |
1225 | |
1226 | #ifndef SMC_GET_MAC_ADDR | |
1227 | #define SMC_GET_MAC_ADDR(addr) \ | |
1228 | do { \ | |
1229 | unsigned int __v; \ | |
1230 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ | |
1231 | addr[0] = __v; addr[1] = __v >> 8; \ | |
1232 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ | |
1233 | addr[2] = __v; addr[3] = __v >> 8; \ | |
1234 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ | |
1235 | addr[4] = __v; addr[5] = __v >> 8; \ | |
1236 | } while (0) | |
1237 | #endif | |
1238 | ||
1239 | #define SMC_SET_MAC_ADDR(addr) \ | |
1240 | do { \ | |
1241 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ | |
1242 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ | |
1243 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ | |
1244 | } while (0) | |
1245 | ||
1246 | #define SMC_SET_MCAST(x) \ | |
1247 | do { \ | |
1248 | const unsigned char *mt = (x); \ | |
1249 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ | |
1250 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ | |
1251 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ | |
1252 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ | |
1253 | } while (0) | |
1254 | ||
1da177e4 LT |
1255 | #define SMC_PUT_PKT_HDR(status, length) \ |
1256 | do { \ | |
09779c6d NP |
1257 | if (SMC_CAN_USE_32BIT) \ |
1258 | SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ | |
1259 | else { \ | |
1260 | SMC_outw(status, ioaddr, DATA_REG); \ | |
1261 | SMC_outw(length, ioaddr, DATA_REG); \ | |
1262 | } \ | |
1da177e4 | 1263 | } while (0) |
1da177e4 | 1264 | |
09779c6d | 1265 | #define SMC_GET_PKT_HDR(status, length) \ |
1da177e4 | 1266 | do { \ |
09779c6d NP |
1267 | if (SMC_CAN_USE_32BIT) { \ |
1268 | unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ | |
1269 | (status) = __val & 0xffff; \ | |
1270 | (length) = __val >> 16; \ | |
1271 | } else { \ | |
1272 | (status) = SMC_inw(ioaddr, DATA_REG); \ | |
1273 | (length) = SMC_inw(ioaddr, DATA_REG); \ | |
1da177e4 LT |
1274 | } \ |
1275 | } while (0) | |
1da177e4 | 1276 | |
09779c6d | 1277 | #define SMC_PUSH_DATA(p, l) \ |
1da177e4 | 1278 | do { \ |
09779c6d NP |
1279 | if (SMC_CAN_USE_32BIT) { \ |
1280 | void *__ptr = (p); \ | |
1281 | int __len = (l); \ | |
fbd81976 | 1282 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1283 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1284 | __len -= 2; \ | |
1285 | SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ | |
1286 | __ptr += 2; \ | |
1287 | } \ | |
1288 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1289 | __ioaddr = lp->datacs; \ | |
1290 | SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ | |
1291 | if (__len & 2) { \ | |
1292 | __ptr += (__len & ~3); \ | |
1293 | SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ | |
1294 | } \ | |
1295 | } else if (SMC_CAN_USE_16BIT) \ | |
1296 | SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1297 | else if (SMC_CAN_USE_8BIT) \ | |
1298 | SMC_outsb(ioaddr, DATA_REG, p, l); \ | |
1da177e4 | 1299 | } while (0) |
1da177e4 LT |
1300 | |
1301 | #define SMC_PULL_DATA(p, l) \ | |
09779c6d NP |
1302 | do { \ |
1303 | if (SMC_CAN_USE_32BIT) { \ | |
1304 | void *__ptr = (p); \ | |
1305 | int __len = (l); \ | |
fbd81976 | 1306 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1307 | if ((unsigned long)__ptr & 2) { \ |
1308 | /* \ | |
1309 | * We want 32bit alignment here. \ | |
1310 | * Since some buses perform a full \ | |
1311 | * 32bit fetch even for 16bit data \ | |
1312 | * we can't use SMC_inw() here. \ | |
1313 | * Back both source (on-chip) and \ | |
1314 | * destination pointers of 2 bytes. \ | |
1315 | * This is possible since the call to \ | |
1316 | * SMC_GET_PKT_HDR() already advanced \ | |
1317 | * the source pointer of 4 bytes, and \ | |
1318 | * the skb_reserve(skb, 2) advanced \ | |
1319 | * the destination pointer of 2 bytes. \ | |
1320 | */ \ | |
1321 | __ptr -= 2; \ | |
1322 | __len += 2; \ | |
1323 | SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
1324 | } \ | |
1325 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1326 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1327 | __len += 2; \ |
09779c6d NP |
1328 | SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ |
1329 | } else if (SMC_CAN_USE_16BIT) \ | |
1330 | SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1331 | else if (SMC_CAN_USE_8BIT) \ | |
1332 | SMC_insb(ioaddr, DATA_REG, p, l); \ | |
1333 | } while (0) | |
1da177e4 LT |
1334 | |
1335 | #endif /* _SMC91X_H_ */ |