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[PATCH] new driver synclink_gt
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / smc91x.h
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1da177e4
LT		 1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
37
38/*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42#if defined(CONFIG_ARCH_LUBBOCK)
43
44/* We can only do 16-bit reads and writes in the static memory space. */
45#define SMC_CAN_USE_8BIT 0
46#define SMC_CAN_USE_16BIT 1
47#define SMC_CAN_USE_32BIT 0
48#define SMC_NOWAIT 1
49
50/* The first two address lines aren't connected... */
51#define SMC_IO_SHIFT 2
52
53#define SMC_inw(a, r) readw((a) + (r))
54#define SMC_outw(v, a, r) writew(v, (a) + (r))
55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60/* We can only do 16-bit reads and writes in the static memory space. */
61#define SMC_CAN_USE_8BIT 0
62#define SMC_CAN_USE_16BIT 1
63#define SMC_CAN_USE_32BIT 0
64#define SMC_NOWAIT 1
65
66#define SMC_IO_SHIFT 0
67
68#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70#define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82#define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93#define set_irq_type(irq, type)
94
95#elif defined(CONFIG_SA1100_PLEB)
96/* We can only do 16-bit reads and writes in the static memory space. */
97#define SMC_CAN_USE_8BIT 1
98#define SMC_CAN_USE_16BIT 1
99#define SMC_CAN_USE_32BIT 0
100#define SMC_IO_SHIFT 0
101#define SMC_NOWAIT 1
102
1cf99be5
RK		 103#define SMC_inb(a, r) readb((a) + (r))
104#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105#define SMC_inw(a, r) readw((a) + (r))
106#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107#define SMC_outb(v, a, r) writeb(v, (a) + (r))
108#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109#define SMC_outw(v, a, r) writew(v, (a) + (r))
110#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
1da177e4
LT		 111
112#define set_irq_type(irq, type) do {} while (0)
113
114#elif defined(CONFIG_SA1100_ASSABET)
115
116#include <asm/arch/neponset.h>
117
118/* We can only do 8-bit reads and writes in the static memory space. */
119#define SMC_CAN_USE_8BIT 1
120#define SMC_CAN_USE_16BIT 0
121#define SMC_CAN_USE_32BIT 0
122#define SMC_NOWAIT 1
123
124/* The first two address lines aren't connected... */
125#define SMC_IO_SHIFT 2
126
127#define SMC_inb(a, r) readb((a) + (r))
128#define SMC_outb(v, a, r) writeb(v, (a) + (r))
129#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132#elif defined(CONFIG_ARCH_INNOKOM) || \
133 defined(CONFIG_MACH_MAINSTONE) || \
134 defined(CONFIG_ARCH_PXA_IDP) || \
135 defined(CONFIG_ARCH_RAMSES)
136
137#define SMC_CAN_USE_8BIT 1
138#define SMC_CAN_USE_16BIT 1
139#define SMC_CAN_USE_32BIT 1
140#define SMC_IO_SHIFT 0
141#define SMC_NOWAIT 1
142#define SMC_USE_PXA_DMA 1
143
144#define SMC_inb(a, r) readb((a) + (r))
145#define SMC_inw(a, r) readw((a) + (r))
146#define SMC_inl(a, r) readl((a) + (r))
147#define SMC_outb(v, a, r) writeb(v, (a) + (r))
148#define SMC_outl(v, a, r) writel(v, (a) + (r))
149#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
150#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
151
152/* We actually can't write halfwords properly if not word aligned */
153static inline void
eb1d6988 154SMC_outw(u16 val, void __iomem *ioaddr, int reg)
1da177e4
LT		 155{
156 if (reg & 2) {
157 unsigned int v = val << 16;
158 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
159 writel(v, ioaddr + (reg & ~2));
160 } else {
161 writew(val, ioaddr + reg);
162 }
163}
164
165#elif defined(CONFIG_ARCH_OMAP)
166
167/* We can only do 16-bit reads and writes in the static memory space. */
168#define SMC_CAN_USE_8BIT 0
169#define SMC_CAN_USE_16BIT 1
170#define SMC_CAN_USE_32BIT 0
171#define SMC_IO_SHIFT 0
172#define SMC_NOWAIT 1
173
174#define SMC_inb(a, r) readb((a) + (r))
175#define SMC_outb(v, a, r) writeb(v, (a) + (r))
176#define SMC_inw(a, r) readw((a) + (r))
177#define SMC_outw(v, a, r) writew(v, (a) + (r))
178#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
179#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
180#define SMC_inl(a, r) readl((a) + (r))
181#define SMC_outl(v, a, r) writel(v, (a) + (r))
182#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
183#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
184
5f13e7ec
DB		 185#include <asm/mach-types.h>
186#include <asm/arch/cpu.h>
187
188#define SMC_IRQ_TRIGGER_TYPE (( \
189 machine_is_omap_h2() \
190 || machine_is_omap_h3() \
af44f5bf 191 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
5f13e7ec
DB		 192 ) ? IRQT_FALLING : IRQT_RISING)
193
194
1da177e4
LT		 195#elif defined(CONFIG_SH_SH4202_MICRODEV)
196
197#define SMC_CAN_USE_8BIT 0
198#define SMC_CAN_USE_16BIT 1
199#define SMC_CAN_USE_32BIT 0
200
201#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
202#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
203#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
204#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
205#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
206#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
207#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
208#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
209#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
210#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
211
212#define set_irq_type(irq, type) do {} while(0)
213
214#elif defined(CONFIG_ISA)
215
216#define SMC_CAN_USE_8BIT 1
217#define SMC_CAN_USE_16BIT 1
218#define SMC_CAN_USE_32BIT 0
219
220#define SMC_inb(a, r) inb((a) + (r))
221#define SMC_inw(a, r) inw((a) + (r))
222#define SMC_outb(v, a, r) outb(v, (a) + (r))
223#define SMC_outw(v, a, r) outw(v, (a) + (r))
224#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
225#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
226
227#elif defined(CONFIG_M32R)
228
229#define SMC_CAN_USE_8BIT 0
230#define SMC_CAN_USE_16BIT 1
231#define SMC_CAN_USE_32BIT 0
232
f3ac9fbf
HT		 233#define SMC_inb(a, r) inb((u32)a) + (r))
234#define SMC_inw(a, r) inw(((u32)a) + (r))
235#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
236#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
237#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
238#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
1da177e4
LT		 239
240#define set_irq_type(irq, type) do {} while(0)
241
242#define RPC_LSA_DEFAULT RPC_LED_TX_RX
243#define RPC_LSB_DEFAULT RPC_LED_100_10
244
245#elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
246
247/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
248 * the way that the CPU handles chip selects and the way that the SMC
249 * chip expects the chip select to operate. Refer to
250 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
251 * IOBARRIER is a byte as a least-common denominator of possible
252 * regions to use as the barrier. It would be wasteful to read 32
253 * bits from a byte oriented region.
254 *
255 * There is no explicit protection against interrupts intervening
256 * between the writew and the IOBARRIER. In SMC ISR there is a
257 * preamble that performs an IOBARRIER in the extremely unlikely event
258 * that the driver interrupts itself between a writew to the chip an
259 * the IOBARRIER that follows *and* the cache is large enough that the
260 * first off-chip access while handing the interrupt is to the SMC
261 * chip. Other devices in the same address space as the SMC chip must
262 * be aware of the potential for trouble and perform a similar
263 * IOBARRIER on entry to their ISR.
264 */
265
266#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
267
268#define SMC_CAN_USE_8BIT 0
269#define SMC_CAN_USE_16BIT 1
270#define SMC_CAN_USE_32BIT 0
271#define SMC_NOWAIT 0
272#define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT)
273
274#define SMC_inw(a,r) readw ((void*) ((a) + (r)))
275#define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l)
276#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
277
278static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l)
279{
280 unsigned short* ps = (unsigned short*) p;
281 while (l-- > 0) {
282 writew (*ps++, a + r);
283 LPD7A40X_IOBARRIER;
284 }
285}
286
287#define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER
288
289#define RPC_LSA_DEFAULT RPC_LED_TX_RX
290#define RPC_LSB_DEFAULT RPC_LED_100_10
291
55793455
PP		 292#elif defined(CONFIG_SOC_AU1X00)
293
294#include <au1xxx.h>
295
296/* We can only do 16-bit reads and writes in the static memory space. */
297#define SMC_CAN_USE_8BIT 0
298#define SMC_CAN_USE_16BIT 1
299#define SMC_CAN_USE_32BIT 0
300#define SMC_IO_SHIFT 0
301#define SMC_NOWAIT 1
302
303#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
304#define SMC_insw(a, r, p, l) \
305 do { \
306 unsigned long _a = (unsigned long)((a) + (r)); \
307 int _l = (l); \
308 u16 *_p = (u16 *)(p); \
309 while (_l-- > 0) \
310 *_p++ = au_readw(_a); \
311 } while(0)
312#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
313#define SMC_outsw(a, r, p, l) \
314 do { \
315 unsigned long _a = (unsigned long)((a) + (r)); \
316 int _l = (l); \
317 const u16 *_p = (const u16 *)(p); \
318 while (_l-- > 0) \
319 au_writew(*_p++ , _a); \
320 } while(0)
321
322#define set_irq_type(irq, type) do {} while (0)
323
1da177e4
LT		 324#else
325
326#define SMC_CAN_USE_8BIT 1
327#define SMC_CAN_USE_16BIT 1
328#define SMC_CAN_USE_32BIT 1
329#define SMC_NOWAIT 1
330
331#define SMC_inb(a, r) readb((a) + (r))
332#define SMC_inw(a, r) readw((a) + (r))
333#define SMC_inl(a, r) readl((a) + (r))
334#define SMC_outb(v, a, r) writeb(v, (a) + (r))
335#define SMC_outw(v, a, r) writew(v, (a) + (r))
336#define SMC_outl(v, a, r) writel(v, (a) + (r))
337#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
338#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
339
340#define RPC_LSA_DEFAULT RPC_LED_100_10
341#define RPC_LSB_DEFAULT RPC_LED_TX_RX
342
343#endif
344
5f13e7ec
DB		 345#ifndef SMC_IRQ_TRIGGER_TYPE
346#define SMC_IRQ_TRIGGER_TYPE IRQT_RISING
347#endif
1da177e4
LT		 348
349#ifdef SMC_USE_PXA_DMA
350/*
351 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
352 * always happening in irq context so no need to worry about races. TX is
353 * different and probably not worth it for that reason, and not as critical
354 * as RX which can overrun memory and lose packets.
355 */
356#include <linux/dma-mapping.h>
357#include <asm/dma.h>
358#include <asm/arch/pxa-regs.h>
359
360#ifdef SMC_insl
361#undef SMC_insl
362#define SMC_insl(a, r, p, l) \
363 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
364static inline void
eb1d6988 365smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 366 u_char *buf, int len)
367{
368 dma_addr_t dmabuf;
369
370 /* fallback if no DMA available */
371 if (dma == (unsigned char)-1) {
372 readsl(ioaddr + reg, buf, len);
373 return;
374 }
375
376 /* 64 bit alignment is required for memory to memory DMA */
377 if ((long)buf & 4) {
378 *((u32 *)buf) = SMC_inl(ioaddr, reg);
379 buf += 4;
380 len--;
381 }
382
383 len *= 4;
384 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
385 DCSR(dma) = DCSR_NODESC;
386 DTADR(dma) = dmabuf;
387 DSADR(dma) = physaddr + reg;
388 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
389 DCMD_WIDTH4 | (DCMD_LENGTH & len));
390 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
391 while (!(DCSR(dma) & DCSR_STOPSTATE))
392 cpu_relax();
393 DCSR(dma) = 0;
394 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
395}
396#endif
397
398#ifdef SMC_insw
399#undef SMC_insw
400#define SMC_insw(a, r, p, l) \
401 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
402static inline void
eb1d6988 403smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 404 u_char *buf, int len)
405{
406 dma_addr_t dmabuf;
407
408 /* fallback if no DMA available */
409 if (dma == (unsigned char)-1) {
410 readsw(ioaddr + reg, buf, len);
411 return;
412 }
413
414 /* 64 bit alignment is required for memory to memory DMA */
415 while ((long)buf & 6) {
416 *((u16 *)buf) = SMC_inw(ioaddr, reg);
417 buf += 2;
418 len--;
419 }
420
421 len *= 2;
422 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
423 DCSR(dma) = DCSR_NODESC;
424 DTADR(dma) = dmabuf;
425 DSADR(dma) = physaddr + reg;
426 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
427 DCMD_WIDTH2 | (DCMD_LENGTH & len));
428 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
429 while (!(DCSR(dma) & DCSR_STOPSTATE))
430 cpu_relax();
431 DCSR(dma) = 0;
432 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
433}
434#endif
435
436static void
437smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
438{
439 DCSR(dma) = 0;
440}
441#endif /* SMC_USE_PXA_DMA */
442
443
444/* Because of bank switching, the LAN91x uses only 16 I/O ports */
445#ifndef SMC_IO_SHIFT
446#define SMC_IO_SHIFT 0
447#endif
448#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
449#define SMC_DATA_EXTENT (4)
450
451/*
452 . Bank Select Register:
453 .
454 . yyyy yyyy 0000 00xx
455 . xx = bank number
456 . yyyy yyyy = 0x33, for identification purposes.
457*/
458#define BANK_SELECT (14 << SMC_IO_SHIFT)
459
460
461// Transmit Control Register
462/* BANK 0 */
463#define TCR_REG SMC_REG(0x0000, 0)
464#define TCR_ENABLE 0x0001 // When 1 we can transmit
465#define TCR_LOOP 0x0002 // Controls output pin LBK
466#define TCR_FORCOL 0x0004 // When 1 will force a collision
467#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
468#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
469#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
470#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
471#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
472#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
473#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
474
475#define TCR_CLEAR 0 /* do NOTHING */
476/* the default settings for the TCR register : */
477#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
478
479
480// EPH Status Register
481/* BANK 0 */
482#define EPH_STATUS_REG SMC_REG(0x0002, 0)
483#define ES_TX_SUC 0x0001 // Last TX was successful
484#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
485#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
486#define ES_LTX_MULT 0x0008 // Last tx was a multicast
487#define ES_16COL 0x0010 // 16 Collisions Reached
488#define ES_SQET 0x0020 // Signal Quality Error Test
489#define ES_LTXBRD 0x0040 // Last tx was a broadcast
490#define ES_TXDEFR 0x0080 // Transmit Deferred
491#define ES_LATCOL 0x0200 // Late collision detected on last tx
492#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
493#define ES_EXC_DEF 0x0800 // Excessive Deferral
494#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
495#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
496#define ES_TXUNRN 0x8000 // Tx Underrun
497
498
499// Receive Control Register
500/* BANK 0 */
501#define RCR_REG SMC_REG(0x0004, 0)
502#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
503#define RCR_PRMS 0x0002 // Enable promiscuous mode
504#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
505#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
506#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
507#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
508#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
509#define RCR_SOFTRST 0x8000 // resets the chip
510
511/* the normal settings for the RCR register : */
512#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
513#define RCR_CLEAR 0x0 // set it to a base state
514
515
516// Counter Register
517/* BANK 0 */
518#define COUNTER_REG SMC_REG(0x0006, 0)
519
520
521// Memory Information Register
522/* BANK 0 */
523#define MIR_REG SMC_REG(0x0008, 0)
524
525
526// Receive/Phy Control Register
527/* BANK 0 */
528#define RPC_REG SMC_REG(0x000A, 0)
529#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
530#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
531#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
532#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
533#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
534#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
535#define RPC_LED_RES (0x01) // LED = Reserved
536#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
537#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
538#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
539#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
540#define RPC_LED_TX (0x06) // LED = TX packet occurred
541#define RPC_LED_RX (0x07) // LED = RX packet occurred
542
543#ifndef RPC_LSA_DEFAULT
544#define RPC_LSA_DEFAULT RPC_LED_100
545#endif
546#ifndef RPC_LSB_DEFAULT
547#define RPC_LSB_DEFAULT RPC_LED_FD
548#endif
549
550#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
551
552
553/* Bank 0 0x0C is reserved */
554
555// Bank Select Register
556/* All Banks */
557#define BSR_REG 0x000E
558
559
560// Configuration Reg
561/* BANK 1 */
562#define CONFIG_REG SMC_REG(0x0000, 1)
563#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
564#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
565#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
566#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
567
568// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
569#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
570
571
572// Base Address Register
573/* BANK 1 */
574#define BASE_REG SMC_REG(0x0002, 1)
575
576
577// Individual Address Registers
578/* BANK 1 */
579#define ADDR0_REG SMC_REG(0x0004, 1)
580#define ADDR1_REG SMC_REG(0x0006, 1)
581#define ADDR2_REG SMC_REG(0x0008, 1)
582
583
584// General Purpose Register
585/* BANK 1 */
586#define GP_REG SMC_REG(0x000A, 1)
587
588
589// Control Register
590/* BANK 1 */
591#define CTL_REG SMC_REG(0x000C, 1)
592#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
593#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
594#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
595#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
596#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
597#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
598#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
599#define CTL_STORE 0x0001 // When set stores registers into EEPROM
600
601
602// MMU Command Register
603/* BANK 2 */
604#define MMU_CMD_REG SMC_REG(0x0000, 2)
605#define MC_BUSY 1 // When 1 the last release has not completed
606#define MC_NOP (0<<5) // No Op
607#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
608#define MC_RESET (2<<5) // Reset MMU to initial state
609#define MC_REMOVE (3<<5) // Remove the current rx packet
610#define MC_RELEASE (4<<5) // Remove and release the current rx packet
611#define MC_FREEPKT (5<<5) // Release packet in PNR register
612#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
613#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
614
615
616// Packet Number Register
617/* BANK 2 */
618#define PN_REG SMC_REG(0x0002, 2)
619
620
621// Allocation Result Register
622/* BANK 2 */
623#define AR_REG SMC_REG(0x0003, 2)
624#define AR_FAILED 0x80 // Alocation Failed
625
626
627// TX FIFO Ports Register
628/* BANK 2 */
629#define TXFIFO_REG SMC_REG(0x0004, 2)
630#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
631
632// RX FIFO Ports Register
633/* BANK 2 */
634#define RXFIFO_REG SMC_REG(0x0005, 2)
635#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
636
637#define FIFO_REG SMC_REG(0x0004, 2)
638
639// Pointer Register
640/* BANK 2 */
641#define PTR_REG SMC_REG(0x0006, 2)
642#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
643#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
644#define PTR_READ 0x2000 // When 1 the operation is a read
645
646
647// Data Register
648/* BANK 2 */
649#define DATA_REG SMC_REG(0x0008, 2)
650
651
652// Interrupt Status/Acknowledge Register
653/* BANK 2 */
654#define INT_REG SMC_REG(0x000C, 2)
655
656
657// Interrupt Mask Register
658/* BANK 2 */
659#define IM_REG SMC_REG(0x000D, 2)
660#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
661#define IM_ERCV_INT 0x40 // Early Receive Interrupt
662#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
663#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
664#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
665#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
666#define IM_TX_INT 0x02 // Transmit Interrupt
667#define IM_RCV_INT 0x01 // Receive Interrupt
668
669
670// Multicast Table Registers
671/* BANK 3 */
672#define MCAST_REG1 SMC_REG(0x0000, 3)
673#define MCAST_REG2 SMC_REG(0x0002, 3)
674#define MCAST_REG3 SMC_REG(0x0004, 3)
675#define MCAST_REG4 SMC_REG(0x0006, 3)
676
677
678// Management Interface Register (MII)
679/* BANK 3 */
680#define MII_REG SMC_REG(0x0008, 3)
681#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
682#define MII_MDOE 0x0008 // MII Output Enable
683#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
684#define MII_MDI 0x0002 // MII Input, pin MDI
685#define MII_MDO 0x0001 // MII Output, pin MDO
686
687
688// Revision Register
689/* BANK 3 */
690/* ( hi: chip id low: rev # ) */
691#define REV_REG SMC_REG(0x000A, 3)
692
693
694// Early RCV Register
695/* BANK 3 */
696/* this is NOT on SMC9192 */
697#define ERCV_REG SMC_REG(0x000C, 3)
698#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
699#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
700
701
702// External Register
703/* BANK 7 */
704#define EXT_REG SMC_REG(0x0000, 7)
705
706
707#define CHIP_9192 3
708#define CHIP_9194 4
709#define CHIP_9195 5
710#define CHIP_9196 6
711#define CHIP_91100 7
712#define CHIP_91100FD 8
713#define CHIP_91111FD 9
714
715static const char * chip_ids[ 16 ] = {
716 NULL, NULL, NULL,
717 /* 3 */ "SMC91C90/91C92",
718 /* 4 */ "SMC91C94",
719 /* 5 */ "SMC91C95",
720 /* 6 */ "SMC91C96",
721 /* 7 */ "SMC91C100",
722 /* 8 */ "SMC91C100FD",
723 /* 9 */ "SMC91C11xFD",
724 NULL, NULL, NULL,
725 NULL, NULL, NULL};
726
727
1da177e4
LT		 728/*
729 . Receive status bits
730*/
731#define RS_ALGNERR 0x8000
732#define RS_BRODCAST 0x4000
733#define RS_BADCRC 0x2000
734#define RS_ODDFRAME 0x1000
735#define RS_TOOLONG 0x0800
736#define RS_TOOSHORT 0x0400
737#define RS_MULTICAST 0x0001
738#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
739
740
741/*
742 * PHY IDs
743 * LAN83C183 == LAN91C111 Internal PHY
744 */
745#define PHY_LAN83C183 0x0016f840
746#define PHY_LAN83C180 0x02821c50
747
748/*
749 * PHY Register Addresses (LAN91C111 Internal PHY)
750 *
751 * Generic PHY registers can be found in <linux/mii.h>
752 *
753 * These phy registers are specific to our on-board phy.
754 */
755
756// PHY Configuration Register 1
757#define PHY_CFG1_REG 0x10
758#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
759#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
760#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
761#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
762#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
763#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
764#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
765#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
766#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
767#define PHY_CFG1_TLVL_MASK 0x003C
768#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
769
770
771// PHY Configuration Register 2
772#define PHY_CFG2_REG 0x11
773#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
774#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
775#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
776#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
777
778// PHY Status Output (and Interrupt status) Register
779#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
780#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
781#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
782#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
783#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
784#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
785#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
786#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
787#define PHY_INT_JAB 0x0100 // 1=Jabber detected
788#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
789#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
790
791// PHY Interrupt/Status Mask Register
792#define PHY_MASK_REG 0x13 // Interrupt Mask
793// Uses the same bit definitions as PHY_INT_REG
794
795
796/*
797 * SMC91C96 ethernet config and status registers.
798 * These are in the "attribute" space.
799 */
800#define ECOR 0x8000
801#define ECOR_RESET 0x80
802#define ECOR_LEVEL_IRQ 0x40
803#define ECOR_WR_ATTRIB 0x04
804#define ECOR_ENABLE 0x01
805
806#define ECSR 0x8002
807#define ECSR_IOIS8 0x20
808#define ECSR_PWRDWN 0x04
809#define ECSR_INT 0x02
810
811#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
812
813
814/*
815 * Macros to abstract register access according to the data bus
816 * capabilities. Please use those and not the in/out primitives.
817 * Note: the following macros do *not* select the bank -- this must
818 * be done separately as needed in the main code. The SMC_REG() macro
819 * only uses the bank argument for debugging purposes (when enabled).
820 */
821
822#if SMC_DEBUG > 0
823#define SMC_REG(reg, bank) \
824 ({ \
825 int __b = SMC_CURRENT_BANK(); \
826 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
827 printk( "%s: bank reg screwed (0x%04x)\n", \
828 CARDNAME, __b ); \
829 BUG(); \
830 } \
831 reg<<SMC_IO_SHIFT; \
832 })
833#else
834#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
835#endif
836
837#if SMC_CAN_USE_8BIT
838#define SMC_GET_PN() SMC_inb( ioaddr, PN_REG )
839#define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG )
840#define SMC_GET_AR() SMC_inb( ioaddr, AR_REG )
841#define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG )
842#define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG )
843#define SMC_GET_INT() SMC_inb( ioaddr, INT_REG )
844#define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG )
845#define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG )
846#define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG )
847#else
848#define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF)
849#define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG )
850#define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8)
851#define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF)
852#define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8)
853#define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF)
854#define SMC_ACK_INT(x) \
855 do { \
856 unsigned long __flags; \
857 int __mask; \
858 local_irq_save(__flags); \
859 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
860 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
861 local_irq_restore(__flags); \
862 } while (0)
863#define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8)
864#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG )
865#endif
866
867#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
868#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
869#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
870#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
871#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
872#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
873#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
874#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
875#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
876#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
877#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
878#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
879#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
880#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
881#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
882#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
883#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
884#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
8de90115 885#define SMC_GET_EPH_STATUS() SMC_inw( ioaddr, EPH_STATUS_REG )
1da177e4
LT		 886#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
887#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
888#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
889#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
890#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
891#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
892#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
893
894#ifndef SMC_GET_MAC_ADDR
895#define SMC_GET_MAC_ADDR(addr) \
896 do { \
897 unsigned int __v; \
898 __v = SMC_inw( ioaddr, ADDR0_REG ); \
899 addr[0] = __v; addr[1] = __v >> 8; \
900 __v = SMC_inw( ioaddr, ADDR1_REG ); \
901 addr[2] = __v; addr[3] = __v >> 8; \
902 __v = SMC_inw( ioaddr, ADDR2_REG ); \
903 addr[4] = __v; addr[5] = __v >> 8; \
904 } while (0)
905#endif
906
907#define SMC_SET_MAC_ADDR(addr) \
908 do { \
909 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
910 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
911 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
912 } while (0)
913
914#define SMC_SET_MCAST(x) \
915 do { \
916 const unsigned char *mt = (x); \
917 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
918 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
919 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
920 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
921 } while (0)
922
923#if SMC_CAN_USE_32BIT
924/*
925 * Some setups just can't write 8 or 16 bits reliably when not aligned
926 * to a 32 bit boundary. I tell you that exists!
927 * We re-do the ones here that can be easily worked around if they can have
928 * their low parts written to 0 without adverse effects.
929 */
930#undef SMC_SELECT_BANK
931#define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT )
932#undef SMC_SET_RPC
933#define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) )
934#undef SMC_SET_PN
935#define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) )
936#undef SMC_SET_PTR
937#define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) )
938#endif
939
940#if SMC_CAN_USE_32BIT
941#define SMC_PUT_PKT_HDR(status, length) \
942 SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG )
943#define SMC_GET_PKT_HDR(status, length) \
944 do { \
945 unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \
946 (status) = __val & 0xffff; \
947 (length) = __val >> 16; \
948 } while (0)
949#else
950#define SMC_PUT_PKT_HDR(status, length) \
951 do { \
952 SMC_outw( status, ioaddr, DATA_REG ); \
953 SMC_outw( length, ioaddr, DATA_REG ); \
954 } while (0)
955#define SMC_GET_PKT_HDR(status, length) \
956 do { \
957 (status) = SMC_inw( ioaddr, DATA_REG ); \
958 (length) = SMC_inw( ioaddr, DATA_REG ); \
959 } while (0)
960#endif
961
962#if SMC_CAN_USE_32BIT
963#define _SMC_PUSH_DATA(p, l) \
964 do { \
965 char *__ptr = (p); \
966 int __len = (l); \
967 if (__len >= 2 && (unsigned long)__ptr & 2) { \
968 __len -= 2; \
969 SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \
970 __ptr += 2; \
971 } \
972 SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \
973 if (__len & 2) { \
974 __ptr += (__len & ~3); \
975 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
976 } \
977 } while (0)
978#define _SMC_PULL_DATA(p, l) \
979 do { \
980 char *__ptr = (p); \
981 int __len = (l); \
982 if ((unsigned long)__ptr & 2) { \
983 /* \
984 * We want 32bit alignment here. \
985 * Since some buses perform a full 32bit \
986 * fetch even for 16bit data we can't use \
987 * SMC_inw() here. Back both source (on chip \
988 * and destination) pointers of 2 bytes. \
989 */ \
990 __ptr -= 2; \
991 __len += 2; \
992 SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
993 } \
994 __len += 2; \
995 SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \
996 } while (0)
997#elif SMC_CAN_USE_16BIT
998#define _SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 )
999#define _SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 )
1000#elif SMC_CAN_USE_8BIT
1001#define _SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l )
1002#define _SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l )
1003#endif
1004
1005#if ! SMC_CAN_USE_16BIT
1006#define SMC_outw(x, ioaddr, reg) \
1007 do { \
1008 unsigned int __val16 = (x); \
1009 SMC_outb( __val16, ioaddr, reg ); \
1010 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
1011 } while (0)
1012#define SMC_inw(ioaddr, reg) \
1013 ({ \
1014 unsigned int __val16; \
1015 __val16 = SMC_inb( ioaddr, reg ); \
1016 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
1017 __val16; \
1018 })
1019#endif
1020
4c86b114 1021#ifdef SMC_CAN_USE_DATACS
1da177e4
LT		 1022#define SMC_PUSH_DATA(p, l) \
1023 if ( lp->datacs ) { \
1024 unsigned char *__ptr = (p); \
1025 int __len = (l); \
1026 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1027 __len -= 2; \
1028 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
1029 __ptr += 2; \
1030 } \
1031 outsl(lp->datacs, __ptr, __len >> 2); \
1032 if (__len & 2) { \
1033 __ptr += (__len & ~3); \
1034 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
1035 } \
1036 } else { \
1037 _SMC_PUSH_DATA(p, l); \
1038 }
1039
1040#define SMC_PULL_DATA(p, l) \
1041 if ( lp->datacs ) { \
1042 unsigned char *__ptr = (p); \
1043 int __len = (l); \
1044 if ((unsigned long)__ptr & 2) { \
1045 /* \
1046 * We want 32bit alignment here. \
1047 * Since some buses perform a full 32bit \
1048 * fetch even for 16bit data we can't use \
1049 * SMC_inw() here. Back both source (on chip \
1050 * and destination) pointers of 2 bytes. \
1051 */ \
1052 __ptr -= 2; \
1053 __len += 2; \
1054 SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
1055 } \
1056 __len += 2; \
1057 insl( lp->datacs, __ptr, __len >> 2); \
1058 } else { \
1059 _SMC_PULL_DATA(p, l); \
1060 }
1061#else
1062#define SMC_PUSH_DATA(p, l) _SMC_PUSH_DATA(p, l)
1063#define SMC_PULL_DATA(p, l) _SMC_PULL_DATA(p, l)
1064#endif
1065
1066#if !defined (SMC_INTERRUPT_PREAMBLE)
1067# define SMC_INTERRUPT_PREAMBLE
1068#endif
1069
1070#endif /* _SMC91X_H_ */
kernel source for telekom puls (alcatel/mediatek)