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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
31 | . Nicolas Pitre <nico@cam.org> | |
32 | . | |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
37 | ||
38 | /* | |
39 | * Define your architecture specific bus configuration parameters here. | |
40 | */ | |
41 | ||
42 | #if defined(CONFIG_ARCH_LUBBOCK) | |
43 | ||
44 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
45 | #define SMC_CAN_USE_8BIT 0 | |
46 | #define SMC_CAN_USE_16BIT 1 | |
47 | #define SMC_CAN_USE_32BIT 0 | |
48 | #define SMC_NOWAIT 1 | |
49 | ||
50 | /* The first two address lines aren't connected... */ | |
51 | #define SMC_IO_SHIFT 2 | |
52 | ||
53 | #define SMC_inw(a, r) readw((a) + (r)) | |
54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
57 | ||
0851a284 WB |
58 | #elif defined(CONFIG_BFIN) |
59 | ||
60 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH | |
c5760abd JCR |
61 | #define RPC_LSA_DEFAULT RPC_LED_100_10 |
62 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
0851a284 WB |
63 | |
64 | # if defined (CONFIG_BFIN561_EZKIT) | |
65 | #define SMC_CAN_USE_8BIT 0 | |
66 | #define SMC_CAN_USE_16BIT 1 | |
67 | #define SMC_CAN_USE_32BIT 1 | |
68 | #define SMC_IO_SHIFT 0 | |
69 | #define SMC_NOWAIT 1 | |
70 | #define SMC_USE_BFIN_DMA 0 | |
71 | ||
72 | ||
73 | #define SMC_inw(a, r) readw((a) + (r)) | |
74 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
75 | #define SMC_inl(a, r) readl((a) + (r)) | |
76 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
77 | #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) | |
78 | #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) | |
79 | # else | |
80 | #define SMC_CAN_USE_8BIT 0 | |
81 | #define SMC_CAN_USE_16BIT 1 | |
82 | #define SMC_CAN_USE_32BIT 0 | |
83 | #define SMC_IO_SHIFT 0 | |
84 | #define SMC_NOWAIT 1 | |
85 | #define SMC_USE_BFIN_DMA 0 | |
86 | ||
87 | ||
88 | #define SMC_inw(a, r) readw((a) + (r)) | |
89 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
90 | #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) | |
91 | #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) | |
92 | # endif | |
93 | /* check if the mac in reg is valid */ | |
94 | #define SMC_GET_MAC_ADDR(addr) \ | |
95 | do { \ | |
96 | unsigned int __v; \ | |
97 | __v = SMC_inw(ioaddr, ADDR0_REG); \ | |
98 | addr[0] = __v; addr[1] = __v >> 8; \ | |
99 | __v = SMC_inw(ioaddr, ADDR1_REG); \ | |
100 | addr[2] = __v; addr[3] = __v >> 8; \ | |
101 | __v = SMC_inw(ioaddr, ADDR2_REG); \ | |
102 | addr[4] = __v; addr[5] = __v >> 8; \ | |
103 | if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ | |
104 | random_ether_addr(addr); \ | |
105 | } \ | |
106 | } while (0) | |
1da177e4 LT |
107 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) |
108 | ||
109 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
110 | #define SMC_CAN_USE_8BIT 0 | |
111 | #define SMC_CAN_USE_16BIT 1 | |
112 | #define SMC_CAN_USE_32BIT 0 | |
113 | #define SMC_NOWAIT 1 | |
114 | ||
115 | #define SMC_IO_SHIFT 0 | |
116 | ||
117 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
118 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
119 | #define SMC_insw(a, r, p, l) \ | |
120 | do { \ | |
121 | unsigned long __port = (a) + (r); \ | |
122 | u16 *__p = (u16 *)(p); \ | |
123 | int __l = (l); \ | |
124 | insw(__port, __p, __l); \ | |
125 | while (__l > 0) { \ | |
126 | *__p = swab16(*__p); \ | |
127 | __p++; \ | |
128 | __l--; \ | |
129 | } \ | |
130 | } while (0) | |
131 | #define SMC_outsw(a, r, p, l) \ | |
132 | do { \ | |
133 | unsigned long __port = (a) + (r); \ | |
134 | u16 *__p = (u16 *)(p); \ | |
135 | int __l = (l); \ | |
136 | while (__l > 0) { \ | |
137 | /* Believe it or not, the swab isn't needed. */ \ | |
138 | outw( /* swab16 */ (*__p++), __port); \ | |
139 | __l--; \ | |
140 | } \ | |
141 | } while (0) | |
9ded96f2 | 142 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
143 | |
144 | #elif defined(CONFIG_SA1100_PLEB) | |
145 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
146 | #define SMC_CAN_USE_8BIT 1 | |
147 | #define SMC_CAN_USE_16BIT 1 | |
148 | #define SMC_CAN_USE_32BIT 0 | |
149 | #define SMC_IO_SHIFT 0 | |
150 | #define SMC_NOWAIT 1 | |
151 | ||
1cf99be5 RK |
152 | #define SMC_inb(a, r) readb((a) + (r)) |
153 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
154 | #define SMC_inw(a, r) readw((a) + (r)) | |
155 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
156 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
157 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
158 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
159 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 160 | |
9ded96f2 | 161 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
162 | |
163 | #elif defined(CONFIG_SA1100_ASSABET) | |
164 | ||
165 | #include <asm/arch/neponset.h> | |
166 | ||
167 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
168 | #define SMC_CAN_USE_8BIT 1 | |
169 | #define SMC_CAN_USE_16BIT 0 | |
170 | #define SMC_CAN_USE_32BIT 0 | |
171 | #define SMC_NOWAIT 1 | |
172 | ||
173 | /* The first two address lines aren't connected... */ | |
174 | #define SMC_IO_SHIFT 2 | |
175 | ||
176 | #define SMC_inb(a, r) readb((a) + (r)) | |
177 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
178 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
179 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
180 | ||
b0348b90 LB |
181 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) |
182 | ||
183 | #define SMC_CAN_USE_8BIT 0 | |
184 | #define SMC_CAN_USE_16BIT 1 | |
185 | #define SMC_CAN_USE_32BIT 0 | |
186 | #define SMC_IO_SHIFT 0 | |
187 | #define SMC_NOWAIT 1 | |
b0348b90 | 188 | |
b0348b90 | 189 | #define SMC_inw(a, r) readw((a) + (r)) |
b0348b90 | 190 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
b0348b90 LB |
191 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
192 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
193 | ||
1da177e4 LT |
194 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
195 | defined(CONFIG_MACH_MAINSTONE) || \ | |
196 | defined(CONFIG_ARCH_PXA_IDP) || \ | |
197 | defined(CONFIG_ARCH_RAMSES) | |
198 | ||
199 | #define SMC_CAN_USE_8BIT 1 | |
200 | #define SMC_CAN_USE_16BIT 1 | |
201 | #define SMC_CAN_USE_32BIT 1 | |
202 | #define SMC_IO_SHIFT 0 | |
203 | #define SMC_NOWAIT 1 | |
204 | #define SMC_USE_PXA_DMA 1 | |
205 | ||
206 | #define SMC_inb(a, r) readb((a) + (r)) | |
207 | #define SMC_inw(a, r) readw((a) + (r)) | |
208 | #define SMC_inl(a, r) readl((a) + (r)) | |
209 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
210 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
211 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
212 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
213 | ||
214 | /* We actually can't write halfwords properly if not word aligned */ | |
215 | static inline void | |
eb1d6988 | 216 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
1da177e4 LT |
217 | { |
218 | if (reg & 2) { | |
219 | unsigned int v = val << 16; | |
220 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
221 | writel(v, ioaddr + (reg & ~2)); | |
222 | } else { | |
223 | writew(val, ioaddr + reg); | |
224 | } | |
225 | } | |
226 | ||
7c826a0b | 227 | #elif defined(CONFIG_MACH_ZYLONITE) |
228 | ||
229 | #define SMC_CAN_USE_8BIT 1 | |
230 | #define SMC_CAN_USE_16BIT 1 | |
231 | #define SMC_CAN_USE_32BIT 0 | |
232 | #define SMC_IO_SHIFT 0 | |
233 | #define SMC_NOWAIT 1 | |
234 | #define SMC_USE_PXA_DMA 1 | |
235 | #define SMC_inb(a, r) readb((a) + (r)) | |
236 | #define SMC_inw(a, r) readw((a) + (r)) | |
237 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
238 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
239 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
240 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
241 | ||
1da177e4 LT |
242 | #elif defined(CONFIG_ARCH_OMAP) |
243 | ||
244 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
245 | #define SMC_CAN_USE_8BIT 0 | |
246 | #define SMC_CAN_USE_16BIT 1 | |
247 | #define SMC_CAN_USE_32BIT 0 | |
248 | #define SMC_IO_SHIFT 0 | |
249 | #define SMC_NOWAIT 1 | |
250 | ||
1da177e4 LT |
251 | #define SMC_inw(a, r) readw((a) + (r)) |
252 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
253 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
254 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 255 | |
5f13e7ec DB |
256 | #include <asm/mach-types.h> |
257 | #include <asm/arch/cpu.h> | |
258 | ||
9ded96f2 | 259 | #define SMC_IRQ_FLAGS (( \ |
5f13e7ec DB |
260 | machine_is_omap_h2() \ |
261 | || machine_is_omap_h3() \ | |
f1b7c5f4 | 262 | || machine_is_omap_h4() \ |
af44f5bf | 263 | || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ |
1fb9df5d | 264 | ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) |
5f13e7ec DB |
265 | |
266 | ||
1da177e4 LT |
267 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
268 | ||
269 | #define SMC_CAN_USE_8BIT 0 | |
270 | #define SMC_CAN_USE_16BIT 1 | |
271 | #define SMC_CAN_USE_32BIT 0 | |
272 | ||
273 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
274 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
275 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
276 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
277 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
278 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
279 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
280 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
281 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
282 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
283 | ||
9ded96f2 | 284 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
285 | |
286 | #elif defined(CONFIG_ISA) | |
287 | ||
288 | #define SMC_CAN_USE_8BIT 1 | |
289 | #define SMC_CAN_USE_16BIT 1 | |
290 | #define SMC_CAN_USE_32BIT 0 | |
291 | ||
292 | #define SMC_inb(a, r) inb((a) + (r)) | |
293 | #define SMC_inw(a, r) inw((a) + (r)) | |
294 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
295 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
296 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
297 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
298 | ||
5125ed91 NI |
299 | #elif defined(CONFIG_SUPERH) |
300 | ||
6026ee67 | 301 | #ifdef CONFIG_SOLUTION_ENGINE |
18ad4e70 | 302 | #define SMC_IRQ_FLAGS (0) |
5125ed91 NI |
303 | #define SMC_CAN_USE_8BIT 0 |
304 | #define SMC_CAN_USE_16BIT 1 | |
305 | #define SMC_CAN_USE_32BIT 0 | |
306 | #define SMC_IO_SHIFT 0 | |
307 | #define SMC_NOWAIT 1 | |
308 | ||
5125ed91 | 309 | #define SMC_inw(a, r) inw((a) + (r)) |
5125ed91 NI |
310 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) |
311 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
312 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
313 | ||
314 | #else /* BOARDS */ | |
315 | ||
316 | #define SMC_CAN_USE_8BIT 1 | |
317 | #define SMC_CAN_USE_16BIT 1 | |
092ed997 | 318 | #define SMC_CAN_USE_32BIT 0 |
5125ed91 NI |
319 | |
320 | #define SMC_inb(a, r) inb((a) + (r)) | |
321 | #define SMC_inw(a, r) inw((a) + (r)) | |
322 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
323 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
324 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
325 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
326 | ||
327 | #endif /* BOARDS */ | |
328 | ||
1da177e4 LT |
329 | #elif defined(CONFIG_M32R) |
330 | ||
331 | #define SMC_CAN_USE_8BIT 0 | |
332 | #define SMC_CAN_USE_16BIT 1 | |
333 | #define SMC_CAN_USE_32BIT 0 | |
334 | ||
59dc76a4 | 335 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
336 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
337 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
338 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
339 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
340 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 341 | |
9ded96f2 | 342 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
343 | |
344 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
345 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
346 | ||
d4adcffb MS |
347 | #elif defined(CONFIG_MACH_LPD79520) \ |
348 | || defined(CONFIG_MACH_LPD7A400) \ | |
349 | || defined(CONFIG_MACH_LPD7A404) | |
1da177e4 | 350 | |
d4adcffb MS |
351 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
352 | * way that the CPU handles chip selects and the way that the SMC chip | |
353 | * expects the chip select to operate. Refer to | |
1da177e4 | 354 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
d4adcffb MS |
355 | * IOBARRIER is a byte, in order that we read the least-common |
356 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
357 | * accessible region. | |
1da177e4 LT |
358 | * |
359 | * There is no explicit protection against interrupts intervening | |
360 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
361 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
362 | * that the driver interrupts itself between a writew to the chip an | |
363 | * the IOBARRIER that follows *and* the cache is large enough that the | |
364 | * first off-chip access while handing the interrupt is to the SMC | |
365 | * chip. Other devices in the same address space as the SMC chip must | |
366 | * be aware of the potential for trouble and perform a similar | |
367 | * IOBARRIER on entry to their ISR. | |
368 | */ | |
369 | ||
370 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
371 | ||
372 | #define SMC_CAN_USE_8BIT 0 | |
373 | #define SMC_CAN_USE_16BIT 1 | |
374 | #define SMC_CAN_USE_32BIT 0 | |
375 | #define SMC_NOWAIT 0 | |
d4adcffb | 376 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
1da177e4 | 377 | |
d4adcffb MS |
378 | #define SMC_inw(a,r)\ |
379 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
380 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
1da177e4 | 381 | |
d4adcffb MS |
382 | #define SMC_insw LPD7_SMC_insw |
383 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
384 | unsigned char* p, int l) | |
385 | { | |
386 | unsigned short* ps = (unsigned short*) p; | |
387 | while (l-- > 0) { | |
388 | *ps++ = readw (a + r); | |
389 | LPD7X_IOBARRIER; | |
390 | } | |
391 | } | |
09779c6d | 392 | |
d4adcffb MS |
393 | #define SMC_outsw LPD7_SMC_outsw |
394 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
395 | unsigned char* p, int l) | |
1da177e4 LT |
396 | { |
397 | unsigned short* ps = (unsigned short*) p; | |
398 | while (l-- > 0) { | |
399 | writew (*ps++, a + r); | |
d4adcffb | 400 | LPD7X_IOBARRIER; |
1da177e4 LT |
401 | } |
402 | } | |
403 | ||
d4adcffb | 404 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
1da177e4 LT |
405 | |
406 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
407 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
408 | ||
55793455 PP |
409 | #elif defined(CONFIG_SOC_AU1X00) |
410 | ||
411 | #include <au1xxx.h> | |
412 | ||
413 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
414 | #define SMC_CAN_USE_8BIT 0 | |
415 | #define SMC_CAN_USE_16BIT 1 | |
416 | #define SMC_CAN_USE_32BIT 0 | |
417 | #define SMC_IO_SHIFT 0 | |
418 | #define SMC_NOWAIT 1 | |
419 | ||
420 | #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) | |
421 | #define SMC_insw(a, r, p, l) \ | |
422 | do { \ | |
423 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
424 | int _l = (l); \ | |
425 | u16 *_p = (u16 *)(p); \ | |
426 | while (_l-- > 0) \ | |
427 | *_p++ = au_readw(_a); \ | |
428 | } while(0) | |
429 | #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) | |
430 | #define SMC_outsw(a, r, p, l) \ | |
431 | do { \ | |
432 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
433 | int _l = (l); \ | |
434 | const u16 *_p = (const u16 *)(p); \ | |
435 | while (_l-- > 0) \ | |
436 | au_writew(*_p++ , _a); \ | |
437 | } while(0) | |
438 | ||
9ded96f2 | 439 | #define SMC_IRQ_FLAGS (0) |
33fee56a DS |
440 | |
441 | #elif defined(CONFIG_ARCH_VERSATILE) | |
442 | ||
443 | #define SMC_CAN_USE_8BIT 1 | |
444 | #define SMC_CAN_USE_16BIT 1 | |
445 | #define SMC_CAN_USE_32BIT 1 | |
446 | #define SMC_NOWAIT 1 | |
447 | ||
448 | #define SMC_inb(a, r) readb((a) + (r)) | |
449 | #define SMC_inw(a, r) readw((a) + (r)) | |
450 | #define SMC_inl(a, r) readl((a) + (r)) | |
451 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
452 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
453 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
454 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
455 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
456 | ||
457 | #define SMC_IRQ_FLAGS (0) | |
55793455 | 458 | |
1da177e4 LT |
459 | #else |
460 | ||
461 | #define SMC_CAN_USE_8BIT 1 | |
462 | #define SMC_CAN_USE_16BIT 1 | |
463 | #define SMC_CAN_USE_32BIT 1 | |
464 | #define SMC_NOWAIT 1 | |
465 | ||
466 | #define SMC_inb(a, r) readb((a) + (r)) | |
467 | #define SMC_inw(a, r) readw((a) + (r)) | |
468 | #define SMC_inl(a, r) readl((a) + (r)) | |
469 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
470 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
471 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
472 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
473 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
474 | ||
475 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
476 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
477 | ||
478 | #endif | |
479 | ||
073ac8fd RK |
480 | |
481 | /* store this information for the driver.. */ | |
482 | struct smc_local { | |
483 | /* | |
484 | * If I have to wait until memory is available to send a | |
485 | * packet, I will store the skbuff here, until I get the | |
486 | * desired memory. Then, I'll send it out and free it. | |
487 | */ | |
488 | struct sk_buff *pending_tx_skb; | |
489 | struct tasklet_struct tx_task; | |
490 | ||
491 | /* version/revision of the SMC91x chip */ | |
492 | int version; | |
493 | ||
494 | /* Contains the current active transmission mode */ | |
495 | int tcr_cur_mode; | |
496 | ||
497 | /* Contains the current active receive mode */ | |
498 | int rcr_cur_mode; | |
499 | ||
500 | /* Contains the current active receive/phy mode */ | |
501 | int rpc_cur_mode; | |
502 | int ctl_rfduplx; | |
503 | int ctl_rspeed; | |
504 | ||
505 | u32 msg_enable; | |
506 | u32 phy_type; | |
507 | struct mii_if_info mii; | |
508 | ||
509 | /* work queue */ | |
510 | struct work_struct phy_configure; | |
511 | struct net_device *dev; | |
512 | int work_pending; | |
513 | ||
514 | spinlock_t lock; | |
515 | ||
516 | #ifdef SMC_USE_PXA_DMA | |
517 | /* DMA needs the physical address of the chip */ | |
518 | u_long physaddr; | |
519 | struct device *device; | |
520 | #endif | |
521 | void __iomem *base; | |
522 | void __iomem *datacs; | |
523 | }; | |
524 | ||
525 | ||
1da177e4 LT |
526 | #ifdef SMC_USE_PXA_DMA |
527 | /* | |
528 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
529 | * always happening in irq context so no need to worry about races. TX is | |
530 | * different and probably not worth it for that reason, and not as critical | |
531 | * as RX which can overrun memory and lose packets. | |
532 | */ | |
533 | #include <linux/dma-mapping.h> | |
534 | #include <asm/dma.h> | |
535 | #include <asm/arch/pxa-regs.h> | |
536 | ||
537 | #ifdef SMC_insl | |
538 | #undef SMC_insl | |
539 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 540 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
1da177e4 | 541 | static inline void |
073ac8fd | 542 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
543 | u_char *buf, int len) |
544 | { | |
073ac8fd | 545 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
546 | dma_addr_t dmabuf; |
547 | ||
548 | /* fallback if no DMA available */ | |
549 | if (dma == (unsigned char)-1) { | |
550 | readsl(ioaddr + reg, buf, len); | |
551 | return; | |
552 | } | |
553 | ||
554 | /* 64 bit alignment is required for memory to memory DMA */ | |
555 | if ((long)buf & 4) { | |
556 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
557 | buf += 4; | |
558 | len--; | |
559 | } | |
560 | ||
561 | len *= 4; | |
073ac8fd | 562 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
563 | DCSR(dma) = DCSR_NODESC; |
564 | DTADR(dma) = dmabuf; | |
565 | DSADR(dma) = physaddr + reg; | |
566 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
567 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
568 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
569 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
570 | cpu_relax(); | |
571 | DCSR(dma) = 0; | |
073ac8fd | 572 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
573 | } |
574 | #endif | |
575 | ||
576 | #ifdef SMC_insw | |
577 | #undef SMC_insw | |
578 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 579 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 580 | static inline void |
073ac8fd | 581 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
582 | u_char *buf, int len) |
583 | { | |
073ac8fd | 584 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
585 | dma_addr_t dmabuf; |
586 | ||
587 | /* fallback if no DMA available */ | |
588 | if (dma == (unsigned char)-1) { | |
589 | readsw(ioaddr + reg, buf, len); | |
590 | return; | |
591 | } | |
592 | ||
593 | /* 64 bit alignment is required for memory to memory DMA */ | |
594 | while ((long)buf & 6) { | |
595 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
596 | buf += 2; | |
597 | len--; | |
598 | } | |
599 | ||
600 | len *= 2; | |
073ac8fd | 601 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
602 | DCSR(dma) = DCSR_NODESC; |
603 | DTADR(dma) = dmabuf; | |
604 | DSADR(dma) = physaddr + reg; | |
605 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
606 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
607 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
608 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
609 | cpu_relax(); | |
610 | DCSR(dma) = 0; | |
073ac8fd | 611 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
612 | } |
613 | #endif | |
614 | ||
615 | static void | |
7d12e780 | 616 | smc_pxa_dma_irq(int dma, void *dummy) |
1da177e4 LT |
617 | { |
618 | DCSR(dma) = 0; | |
619 | } | |
620 | #endif /* SMC_USE_PXA_DMA */ | |
621 | ||
622 | ||
09779c6d NP |
623 | /* |
624 | * Everything a particular hardware setup needs should have been defined | |
625 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
626 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
627 | * use of them. | |
628 | */ | |
629 | ||
630 | #if ! SMC_CAN_USE_32BIT | |
631 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
632 | #define SMC_outl(x, ioaddr, reg) BUG() | |
633 | #define SMC_insl(a, r, p, l) BUG() | |
634 | #define SMC_outsl(a, r, p, l) BUG() | |
635 | #endif | |
636 | ||
637 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
638 | #define SMC_insl(a, r, p, l) BUG() | |
639 | #define SMC_outsl(a, r, p, l) BUG() | |
640 | #endif | |
641 | ||
642 | #if ! SMC_CAN_USE_16BIT | |
643 | ||
644 | /* | |
645 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
646 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
647 | */ | |
648 | #define SMC_outw(x, ioaddr, reg) \ | |
649 | do { \ | |
650 | unsigned int __val16 = (x); \ | |
651 | SMC_outb( __val16, ioaddr, reg ); \ | |
652 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
653 | } while (0) | |
654 | #define SMC_inw(ioaddr, reg) \ | |
655 | ({ \ | |
656 | unsigned int __val16; \ | |
657 | __val16 = SMC_inb( ioaddr, reg ); \ | |
658 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
659 | __val16; \ | |
660 | }) | |
661 | ||
662 | #define SMC_insw(a, r, p, l) BUG() | |
663 | #define SMC_outsw(a, r, p, l) BUG() | |
664 | ||
665 | #endif | |
666 | ||
667 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
668 | #define SMC_insw(a, r, p, l) BUG() | |
669 | #define SMC_outsw(a, r, p, l) BUG() | |
670 | #endif | |
671 | ||
672 | #if ! SMC_CAN_USE_8BIT | |
673 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
674 | #define SMC_outb(x, ioaddr, reg) BUG() | |
675 | #define SMC_insb(a, r, p, l) BUG() | |
676 | #define SMC_outsb(a, r, p, l) BUG() | |
677 | #endif | |
678 | ||
679 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
680 | #define SMC_insb(a, r, p, l) BUG() | |
681 | #define SMC_outsb(a, r, p, l) BUG() | |
682 | #endif | |
683 | ||
684 | #ifndef SMC_CAN_USE_DATACS | |
685 | #define SMC_CAN_USE_DATACS 0 | |
686 | #endif | |
687 | ||
1da177e4 LT |
688 | #ifndef SMC_IO_SHIFT |
689 | #define SMC_IO_SHIFT 0 | |
690 | #endif | |
09779c6d NP |
691 | |
692 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 693 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
694 | #endif |
695 | ||
696 | #ifndef SMC_INTERRUPT_PREAMBLE | |
697 | #define SMC_INTERRUPT_PREAMBLE | |
698 | #endif | |
699 | ||
700 | ||
701 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
702 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
703 | #define SMC_DATA_EXTENT (4) | |
704 | ||
705 | /* | |
706 | . Bank Select Register: | |
707 | . | |
708 | . yyyy yyyy 0000 00xx | |
709 | . xx = bank number | |
710 | . yyyy yyyy = 0x33, for identification purposes. | |
711 | */ | |
712 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
713 | ||
714 | ||
715 | // Transmit Control Register | |
716 | /* BANK 0 */ | |
717 | #define TCR_REG SMC_REG(0x0000, 0) | |
718 | #define TCR_ENABLE 0x0001 // When 1 we can transmit | |
719 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
720 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
721 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
722 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
723 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
724 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
725 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
726 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
727 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
728 | ||
729 | #define TCR_CLEAR 0 /* do NOTHING */ | |
730 | /* the default settings for the TCR register : */ | |
731 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
732 | ||
733 | ||
734 | // EPH Status Register | |
735 | /* BANK 0 */ | |
736 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) | |
737 | #define ES_TX_SUC 0x0001 // Last TX was successful | |
738 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
739 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
740 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
741 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
742 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
743 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
744 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
745 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
746 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
747 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
748 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
749 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
750 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
751 | ||
752 | ||
753 | // Receive Control Register | |
754 | /* BANK 0 */ | |
755 | #define RCR_REG SMC_REG(0x0004, 0) | |
756 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted | |
757 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
758 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
759 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
760 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
761 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
762 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
763 | #define RCR_SOFTRST 0x8000 // resets the chip | |
764 | ||
765 | /* the normal settings for the RCR register : */ | |
766 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
767 | #define RCR_CLEAR 0x0 // set it to a base state | |
768 | ||
769 | ||
770 | // Counter Register | |
771 | /* BANK 0 */ | |
772 | #define COUNTER_REG SMC_REG(0x0006, 0) | |
773 | ||
774 | ||
775 | // Memory Information Register | |
776 | /* BANK 0 */ | |
777 | #define MIR_REG SMC_REG(0x0008, 0) | |
778 | ||
779 | ||
780 | // Receive/Phy Control Register | |
781 | /* BANK 0 */ | |
782 | #define RPC_REG SMC_REG(0x000A, 0) | |
783 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. | |
784 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
785 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
786 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
787 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
788 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
789 | #define RPC_LED_RES (0x01) // LED = Reserved | |
790 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
791 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
792 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
793 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
794 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
795 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
796 | ||
797 | #ifndef RPC_LSA_DEFAULT | |
798 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
799 | #endif | |
800 | #ifndef RPC_LSB_DEFAULT | |
801 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
802 | #endif | |
803 | ||
804 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
805 | ||
806 | ||
807 | /* Bank 0 0x0C is reserved */ | |
808 | ||
809 | // Bank Select Register | |
810 | /* All Banks */ | |
811 | #define BSR_REG 0x000E | |
812 | ||
813 | ||
814 | // Configuration Reg | |
815 | /* BANK 1 */ | |
816 | #define CONFIG_REG SMC_REG(0x0000, 1) | |
817 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy | |
818 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
819 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
820 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
821 | ||
822 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
823 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
824 | ||
825 | ||
826 | // Base Address Register | |
827 | /* BANK 1 */ | |
828 | #define BASE_REG SMC_REG(0x0002, 1) | |
829 | ||
830 | ||
831 | // Individual Address Registers | |
832 | /* BANK 1 */ | |
833 | #define ADDR0_REG SMC_REG(0x0004, 1) | |
834 | #define ADDR1_REG SMC_REG(0x0006, 1) | |
835 | #define ADDR2_REG SMC_REG(0x0008, 1) | |
836 | ||
837 | ||
838 | // General Purpose Register | |
839 | /* BANK 1 */ | |
840 | #define GP_REG SMC_REG(0x000A, 1) | |
841 | ||
842 | ||
843 | // Control Register | |
844 | /* BANK 1 */ | |
845 | #define CTL_REG SMC_REG(0x000C, 1) | |
846 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received | |
847 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
848 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
849 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
850 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
851 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
852 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
853 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
854 | ||
855 | ||
856 | // MMU Command Register | |
857 | /* BANK 2 */ | |
858 | #define MMU_CMD_REG SMC_REG(0x0000, 2) | |
859 | #define MC_BUSY 1 // When 1 the last release has not completed | |
860 | #define MC_NOP (0<<5) // No Op | |
861 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
862 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
863 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
864 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
865 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
866 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
867 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
868 | ||
869 | ||
870 | // Packet Number Register | |
871 | /* BANK 2 */ | |
872 | #define PN_REG SMC_REG(0x0002, 2) | |
873 | ||
874 | ||
875 | // Allocation Result Register | |
876 | /* BANK 2 */ | |
877 | #define AR_REG SMC_REG(0x0003, 2) | |
878 | #define AR_FAILED 0x80 // Alocation Failed | |
879 | ||
880 | ||
881 | // TX FIFO Ports Register | |
882 | /* BANK 2 */ | |
883 | #define TXFIFO_REG SMC_REG(0x0004, 2) | |
884 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty | |
885 | ||
886 | // RX FIFO Ports Register | |
887 | /* BANK 2 */ | |
888 | #define RXFIFO_REG SMC_REG(0x0005, 2) | |
889 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty | |
890 | ||
891 | #define FIFO_REG SMC_REG(0x0004, 2) | |
892 | ||
893 | // Pointer Register | |
894 | /* BANK 2 */ | |
895 | #define PTR_REG SMC_REG(0x0006, 2) | |
896 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area | |
897 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
898 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
899 | ||
900 | ||
901 | // Data Register | |
902 | /* BANK 2 */ | |
903 | #define DATA_REG SMC_REG(0x0008, 2) | |
904 | ||
905 | ||
906 | // Interrupt Status/Acknowledge Register | |
907 | /* BANK 2 */ | |
908 | #define INT_REG SMC_REG(0x000C, 2) | |
909 | ||
910 | ||
911 | // Interrupt Mask Register | |
912 | /* BANK 2 */ | |
913 | #define IM_REG SMC_REG(0x000D, 2) | |
914 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt | |
915 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
916 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
917 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
918 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
919 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
920 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
921 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
922 | ||
923 | ||
924 | // Multicast Table Registers | |
925 | /* BANK 3 */ | |
926 | #define MCAST_REG1 SMC_REG(0x0000, 3) | |
927 | #define MCAST_REG2 SMC_REG(0x0002, 3) | |
928 | #define MCAST_REG3 SMC_REG(0x0004, 3) | |
929 | #define MCAST_REG4 SMC_REG(0x0006, 3) | |
930 | ||
931 | ||
932 | // Management Interface Register (MII) | |
933 | /* BANK 3 */ | |
934 | #define MII_REG SMC_REG(0x0008, 3) | |
935 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup | |
936 | #define MII_MDOE 0x0008 // MII Output Enable | |
937 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
938 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
939 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
940 | ||
941 | ||
942 | // Revision Register | |
943 | /* BANK 3 */ | |
944 | /* ( hi: chip id low: rev # ) */ | |
945 | #define REV_REG SMC_REG(0x000A, 3) | |
946 | ||
947 | ||
948 | // Early RCV Register | |
949 | /* BANK 3 */ | |
950 | /* this is NOT on SMC9192 */ | |
951 | #define ERCV_REG SMC_REG(0x000C, 3) | |
952 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received | |
953 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
954 | ||
955 | ||
956 | // External Register | |
957 | /* BANK 7 */ | |
958 | #define EXT_REG SMC_REG(0x0000, 7) | |
959 | ||
960 | ||
961 | #define CHIP_9192 3 | |
962 | #define CHIP_9194 4 | |
963 | #define CHIP_9195 5 | |
964 | #define CHIP_9196 6 | |
965 | #define CHIP_91100 7 | |
966 | #define CHIP_91100FD 8 | |
967 | #define CHIP_91111FD 9 | |
968 | ||
969 | static const char * chip_ids[ 16 ] = { | |
970 | NULL, NULL, NULL, | |
971 | /* 3 */ "SMC91C90/91C92", | |
972 | /* 4 */ "SMC91C94", | |
973 | /* 5 */ "SMC91C95", | |
974 | /* 6 */ "SMC91C96", | |
975 | /* 7 */ "SMC91C100", | |
976 | /* 8 */ "SMC91C100FD", | |
977 | /* 9 */ "SMC91C11xFD", | |
978 | NULL, NULL, NULL, | |
979 | NULL, NULL, NULL}; | |
980 | ||
981 | ||
1da177e4 LT |
982 | /* |
983 | . Receive status bits | |
984 | */ | |
985 | #define RS_ALGNERR 0x8000 | |
986 | #define RS_BRODCAST 0x4000 | |
987 | #define RS_BADCRC 0x2000 | |
988 | #define RS_ODDFRAME 0x1000 | |
989 | #define RS_TOOLONG 0x0800 | |
990 | #define RS_TOOSHORT 0x0400 | |
991 | #define RS_MULTICAST 0x0001 | |
992 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
993 | ||
994 | ||
995 | /* | |
996 | * PHY IDs | |
997 | * LAN83C183 == LAN91C111 Internal PHY | |
998 | */ | |
999 | #define PHY_LAN83C183 0x0016f840 | |
1000 | #define PHY_LAN83C180 0x02821c50 | |
1001 | ||
1002 | /* | |
1003 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
1004 | * | |
1005 | * Generic PHY registers can be found in <linux/mii.h> | |
1006 | * | |
1007 | * These phy registers are specific to our on-board phy. | |
1008 | */ | |
1009 | ||
1010 | // PHY Configuration Register 1 | |
1011 | #define PHY_CFG1_REG 0x10 | |
1012 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
1013 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
1014 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
1015 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
1016 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
1017 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
1018 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
1019 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
1020 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
1021 | #define PHY_CFG1_TLVL_MASK 0x003C | |
1022 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
1023 | ||
1024 | ||
1025 | // PHY Configuration Register 2 | |
1026 | #define PHY_CFG2_REG 0x11 | |
1027 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
1028 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
1029 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
1030 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
1031 | ||
1032 | // PHY Status Output (and Interrupt status) Register | |
1033 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
1034 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
1035 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
1036 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
1037 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
1038 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
1039 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
1040 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
1041 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
1042 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
1043 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
1044 | ||
1045 | // PHY Interrupt/Status Mask Register | |
1046 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
1047 | // Uses the same bit definitions as PHY_INT_REG | |
1048 | ||
1049 | ||
1050 | /* | |
1051 | * SMC91C96 ethernet config and status registers. | |
1052 | * These are in the "attribute" space. | |
1053 | */ | |
1054 | #define ECOR 0x8000 | |
1055 | #define ECOR_RESET 0x80 | |
1056 | #define ECOR_LEVEL_IRQ 0x40 | |
1057 | #define ECOR_WR_ATTRIB 0x04 | |
1058 | #define ECOR_ENABLE 0x01 | |
1059 | ||
1060 | #define ECSR 0x8002 | |
1061 | #define ECSR_IOIS8 0x20 | |
1062 | #define ECSR_PWRDWN 0x04 | |
1063 | #define ECSR_INT 0x02 | |
1064 | ||
1065 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
1066 | ||
1067 | ||
1068 | /* | |
1069 | * Macros to abstract register access according to the data bus | |
1070 | * capabilities. Please use those and not the in/out primitives. | |
1071 | * Note: the following macros do *not* select the bank -- this must | |
1072 | * be done separately as needed in the main code. The SMC_REG() macro | |
1073 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
1074 | * |
1075 | * Note: despite inline functions being safer, everything leading to this | |
1076 | * should preferably be macros to let BUG() display the line number in | |
1077 | * the core source code since we're interested in the top call site | |
1078 | * not in any inline function location. | |
1da177e4 LT |
1079 | */ |
1080 | ||
1081 | #if SMC_DEBUG > 0 | |
1082 | #define SMC_REG(reg, bank) \ | |
1083 | ({ \ | |
1084 | int __b = SMC_CURRENT_BANK(); \ | |
1085 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ | |
1086 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
1087 | CARDNAME, __b ); \ | |
1088 | BUG(); \ | |
1089 | } \ | |
1090 | reg<<SMC_IO_SHIFT; \ | |
1091 | }) | |
1092 | #else | |
1093 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) | |
1094 | #endif | |
1095 | ||
09779c6d NP |
1096 | /* |
1097 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
1098 | * aligned to a 32 bit boundary. I tell you that does exist! | |
1099 | * Fortunately the affected register accesses can be easily worked around | |
1100 | * since we can write zeroes to the preceeding 16 bits without adverse | |
1101 | * effects and use a 32-bit access. | |
1102 | * | |
1103 | * Enforce it on any 32-bit capable setup for now. | |
1104 | */ | |
1105 | #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT | |
1106 | ||
1107 | #define SMC_GET_PN() \ | |
1108 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ | |
1109 | : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) | |
1110 | ||
1111 | #define SMC_SET_PN(x) \ | |
1112 | do { \ | |
1113 | if (SMC_MUST_ALIGN_WRITE) \ | |
1114 | SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ | |
1115 | else if (SMC_CAN_USE_8BIT) \ | |
1116 | SMC_outb(x, ioaddr, PN_REG); \ | |
1117 | else \ | |
1118 | SMC_outw(x, ioaddr, PN_REG); \ | |
1119 | } while (0) | |
1120 | ||
1121 | #define SMC_GET_AR() \ | |
1122 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ | |
1123 | : (SMC_inw(ioaddr, PN_REG) >> 8) ) | |
1124 | ||
1125 | #define SMC_GET_TXFIFO() \ | |
1126 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ | |
1127 | : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) | |
1128 | ||
1129 | #define SMC_GET_RXFIFO() \ | |
1130 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ | |
1131 | : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) | |
1132 | ||
1133 | #define SMC_GET_INT() \ | |
1134 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ | |
1135 | : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) | |
1136 | ||
1da177e4 LT |
1137 | #define SMC_ACK_INT(x) \ |
1138 | do { \ | |
09779c6d NP |
1139 | if (SMC_CAN_USE_8BIT) \ |
1140 | SMC_outb(x, ioaddr, INT_REG); \ | |
1141 | else { \ | |
1142 | unsigned long __flags; \ | |
1143 | int __mask; \ | |
1144 | local_irq_save(__flags); \ | |
1145 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ | |
1146 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ | |
1147 | local_irq_restore(__flags); \ | |
1148 | } \ | |
1149 | } while (0) | |
1150 | ||
1151 | #define SMC_GET_INT_MASK() \ | |
1152 | ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ | |
1153 | : (SMC_inw( ioaddr, INT_REG ) >> 8) ) | |
1154 | ||
1155 | #define SMC_SET_INT_MASK(x) \ | |
1156 | do { \ | |
1157 | if (SMC_CAN_USE_8BIT) \ | |
1158 | SMC_outb(x, ioaddr, IM_REG); \ | |
1159 | else \ | |
1160 | SMC_outw((x) << 8, ioaddr, INT_REG); \ | |
1161 | } while (0) | |
1162 | ||
1163 | #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) | |
1164 | ||
1165 | #define SMC_SELECT_BANK(x) \ | |
1166 | do { \ | |
1167 | if (SMC_MUST_ALIGN_WRITE) \ | |
1168 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ | |
1169 | else \ | |
1170 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
1171 | } while (0) | |
1172 | ||
1173 | #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) | |
1174 | ||
1175 | #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) | |
1176 | ||
1177 | #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) | |
1178 | ||
1179 | #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) | |
1180 | ||
1181 | #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) | |
1182 | ||
1183 | #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) | |
1184 | ||
1185 | #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) | |
1186 | ||
1187 | #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) | |
1188 | ||
1189 | #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) | |
1190 | ||
1191 | #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) | |
1192 | ||
1193 | #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) | |
1194 | ||
1195 | #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) | |
1196 | ||
1197 | #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) | |
1198 | ||
1199 | #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) | |
1200 | ||
1201 | #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) | |
1202 | ||
1203 | #define SMC_SET_PTR(x) \ | |
1204 | do { \ | |
1205 | if (SMC_MUST_ALIGN_WRITE) \ | |
1206 | SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ | |
1207 | else \ | |
1208 | SMC_outw(x, ioaddr, PTR_REG); \ | |
1da177e4 | 1209 | } while (0) |
1da177e4 | 1210 | |
09779c6d NP |
1211 | #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) |
1212 | ||
1213 | #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) | |
1214 | ||
1215 | #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) | |
1216 | ||
1217 | #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) | |
1218 | ||
1219 | #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) | |
1220 | ||
1221 | #define SMC_SET_RPC(x) \ | |
1222 | do { \ | |
1223 | if (SMC_MUST_ALIGN_WRITE) \ | |
1224 | SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ | |
1225 | else \ | |
1226 | SMC_outw(x, ioaddr, RPC_REG); \ | |
1227 | } while (0) | |
1228 | ||
1229 | #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) | |
1230 | ||
1231 | #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) | |
1da177e4 LT |
1232 | |
1233 | #ifndef SMC_GET_MAC_ADDR | |
1234 | #define SMC_GET_MAC_ADDR(addr) \ | |
1235 | do { \ | |
1236 | unsigned int __v; \ | |
1237 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ | |
1238 | addr[0] = __v; addr[1] = __v >> 8; \ | |
1239 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ | |
1240 | addr[2] = __v; addr[3] = __v >> 8; \ | |
1241 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ | |
1242 | addr[4] = __v; addr[5] = __v >> 8; \ | |
1243 | } while (0) | |
1244 | #endif | |
1245 | ||
1246 | #define SMC_SET_MAC_ADDR(addr) \ | |
1247 | do { \ | |
1248 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ | |
1249 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ | |
1250 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ | |
1251 | } while (0) | |
1252 | ||
1253 | #define SMC_SET_MCAST(x) \ | |
1254 | do { \ | |
1255 | const unsigned char *mt = (x); \ | |
1256 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ | |
1257 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ | |
1258 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ | |
1259 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ | |
1260 | } while (0) | |
1261 | ||
1da177e4 LT |
1262 | #define SMC_PUT_PKT_HDR(status, length) \ |
1263 | do { \ | |
09779c6d NP |
1264 | if (SMC_CAN_USE_32BIT) \ |
1265 | SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ | |
1266 | else { \ | |
1267 | SMC_outw(status, ioaddr, DATA_REG); \ | |
1268 | SMC_outw(length, ioaddr, DATA_REG); \ | |
1269 | } \ | |
1da177e4 | 1270 | } while (0) |
1da177e4 | 1271 | |
09779c6d | 1272 | #define SMC_GET_PKT_HDR(status, length) \ |
1da177e4 | 1273 | do { \ |
09779c6d NP |
1274 | if (SMC_CAN_USE_32BIT) { \ |
1275 | unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ | |
1276 | (status) = __val & 0xffff; \ | |
1277 | (length) = __val >> 16; \ | |
1278 | } else { \ | |
1279 | (status) = SMC_inw(ioaddr, DATA_REG); \ | |
1280 | (length) = SMC_inw(ioaddr, DATA_REG); \ | |
1da177e4 LT |
1281 | } \ |
1282 | } while (0) | |
1da177e4 | 1283 | |
09779c6d | 1284 | #define SMC_PUSH_DATA(p, l) \ |
1da177e4 | 1285 | do { \ |
09779c6d NP |
1286 | if (SMC_CAN_USE_32BIT) { \ |
1287 | void *__ptr = (p); \ | |
1288 | int __len = (l); \ | |
fbd81976 | 1289 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1290 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1291 | __len -= 2; \ | |
1292 | SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ | |
1293 | __ptr += 2; \ | |
1294 | } \ | |
1295 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1296 | __ioaddr = lp->datacs; \ | |
1297 | SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ | |
1298 | if (__len & 2) { \ | |
1299 | __ptr += (__len & ~3); \ | |
1300 | SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ | |
1301 | } \ | |
1302 | } else if (SMC_CAN_USE_16BIT) \ | |
1303 | SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1304 | else if (SMC_CAN_USE_8BIT) \ | |
1305 | SMC_outsb(ioaddr, DATA_REG, p, l); \ | |
1da177e4 | 1306 | } while (0) |
1da177e4 LT |
1307 | |
1308 | #define SMC_PULL_DATA(p, l) \ | |
09779c6d NP |
1309 | do { \ |
1310 | if (SMC_CAN_USE_32BIT) { \ | |
1311 | void *__ptr = (p); \ | |
1312 | int __len = (l); \ | |
fbd81976 | 1313 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1314 | if ((unsigned long)__ptr & 2) { \ |
1315 | /* \ | |
1316 | * We want 32bit alignment here. \ | |
1317 | * Since some buses perform a full \ | |
1318 | * 32bit fetch even for 16bit data \ | |
1319 | * we can't use SMC_inw() here. \ | |
1320 | * Back both source (on-chip) and \ | |
1321 | * destination pointers of 2 bytes. \ | |
1322 | * This is possible since the call to \ | |
1323 | * SMC_GET_PKT_HDR() already advanced \ | |
1324 | * the source pointer of 4 bytes, and \ | |
1325 | * the skb_reserve(skb, 2) advanced \ | |
1326 | * the destination pointer of 2 bytes. \ | |
1327 | */ \ | |
1328 | __ptr -= 2; \ | |
1329 | __len += 2; \ | |
1330 | SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
1331 | } \ | |
1332 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1333 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1334 | __len += 2; \ |
09779c6d NP |
1335 | SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ |
1336 | } else if (SMC_CAN_USE_16BIT) \ | |
1337 | SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ | |
1338 | else if (SMC_CAN_USE_8BIT) \ | |
1339 | SMC_insb(ioaddr, DATA_REG, p, l); \ | |
1340 | } while (0) | |
1da177e4 LT |
1341 | |
1342 | #endif /* _SMC91X_H_ */ |