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smc91x: introduce platform data flags V2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / smc91x.h
CommitLineData
1da177e4
LT		 1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
3e947943 37#include <linux/smc91x.h>
1da177e4
LT		 38
39/*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43#if defined(CONFIG_ARCH_LUBBOCK)
44
45/* We can only do 16-bit reads and writes in the static memory space. */
46#define SMC_CAN_USE_8BIT 0
47#define SMC_CAN_USE_16BIT 1
48#define SMC_CAN_USE_32BIT 0
49#define SMC_NOWAIT 1
50
51/* The first two address lines aren't connected... */
52#define SMC_IO_SHIFT 2
53
54#define SMC_inw(a, r) readw((a) + (r))
55#define SMC_outw(v, a, r) writew(v, (a) + (r))
56#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
57#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
e7b3dc7e 58#define SMC_IRQ_FLAGS (-1) /* from resource */
1da177e4 59
95af9feb 60#elif defined(CONFIG_BLACKFIN)
0851a284
WB		 61
62#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
c5760abd
JCR		 63#define RPC_LSA_DEFAULT RPC_LED_100_10
64#define RPC_LSB_DEFAULT RPC_LED_TX_RX
0851a284
WB		 65
66# if defined (CONFIG_BFIN561_EZKIT)
67#define SMC_CAN_USE_8BIT 0
68#define SMC_CAN_USE_16BIT 1
69#define SMC_CAN_USE_32BIT 1
70#define SMC_IO_SHIFT 0
71#define SMC_NOWAIT 1
72#define SMC_USE_BFIN_DMA 0
73
74
75#define SMC_inw(a, r) readw((a) + (r))
76#define SMC_outw(v, a, r) writew(v, (a) + (r))
77#define SMC_inl(a, r) readl((a) + (r))
78#define SMC_outl(v, a, r) writel(v, (a) + (r))
79#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
80#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
81# else
82#define SMC_CAN_USE_8BIT 0
83#define SMC_CAN_USE_16BIT 1
84#define SMC_CAN_USE_32BIT 0
85#define SMC_IO_SHIFT 0
86#define SMC_NOWAIT 1
87#define SMC_USE_BFIN_DMA 0
88
89
90#define SMC_inw(a, r) readw((a) + (r))
91#define SMC_outw(v, a, r) writew(v, (a) + (r))
92#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
93#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
94# endif
95/* check if the mac in reg is valid */
96#define SMC_GET_MAC_ADDR(addr) \
97 do { \
98 unsigned int __v; \
99 __v = SMC_inw(ioaddr, ADDR0_REG); \
100 addr[0] = __v; addr[1] = __v >> 8; \
101 __v = SMC_inw(ioaddr, ADDR1_REG); \
102 addr[2] = __v; addr[3] = __v >> 8; \
103 __v = SMC_inw(ioaddr, ADDR2_REG); \
104 addr[4] = __v; addr[5] = __v >> 8; \
105 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
106 random_ether_addr(addr); \
107 } \
108 } while (0)
1da177e4
LT		 109#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
110
111/* We can only do 16-bit reads and writes in the static memory space. */
112#define SMC_CAN_USE_8BIT 0
113#define SMC_CAN_USE_16BIT 1
114#define SMC_CAN_USE_32BIT 0
115#define SMC_NOWAIT 1
116
117#define SMC_IO_SHIFT 0
118
119#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
120#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
121#define SMC_insw(a, r, p, l) \
122 do { \
123 unsigned long __port = (a) + (r); \
124 u16 *__p = (u16 *)(p); \
125 int __l = (l); \
126 insw(__port, __p, __l); \
127 while (__l > 0) { \
128 *__p = swab16(*__p); \
129 __p++; \
130 __l--; \
131 } \
132 } while (0)
133#define SMC_outsw(a, r, p, l) \
134 do { \
135 unsigned long __port = (a) + (r); \
136 u16 *__p = (u16 *)(p); \
137 int __l = (l); \
138 while (__l > 0) { \
139 /* Believe it or not, the swab isn't needed. */ \
140 outw( /* swab16 */ (*__p++), __port); \
141 __l--; \
142 } \
143 } while (0)
9ded96f2 144#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 145
146#elif defined(CONFIG_SA1100_PLEB)
147/* We can only do 16-bit reads and writes in the static memory space. */
148#define SMC_CAN_USE_8BIT 1
149#define SMC_CAN_USE_16BIT 1
150#define SMC_CAN_USE_32BIT 0
151#define SMC_IO_SHIFT 0
152#define SMC_NOWAIT 1
153
1cf99be5
RK		 154#define SMC_inb(a, r) readb((a) + (r))
155#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
156#define SMC_inw(a, r) readw((a) + (r))
157#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
158#define SMC_outb(v, a, r) writeb(v, (a) + (r))
159#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
160#define SMC_outw(v, a, r) writew(v, (a) + (r))
161#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
1da177e4 162
e7b3dc7e 163#define SMC_IRQ_FLAGS (-1)
1da177e4
LT		 164
165#elif defined(CONFIG_SA1100_ASSABET)
166
167#include <asm/arch/neponset.h>
168
169/* We can only do 8-bit reads and writes in the static memory space. */
170#define SMC_CAN_USE_8BIT 1
171#define SMC_CAN_USE_16BIT 0
172#define SMC_CAN_USE_32BIT 0
173#define SMC_NOWAIT 1
174
175/* The first two address lines aren't connected... */
176#define SMC_IO_SHIFT 2
177
178#define SMC_inb(a, r) readb((a) + (r))
179#define SMC_outb(v, a, r) writeb(v, (a) + (r))
180#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
181#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
e7b3dc7e 182#define SMC_IRQ_FLAGS (-1) /* from resource */
1da177e4 183
b0348b90
LB		 184#elif defined(CONFIG_MACH_LOGICPD_PXA270)
185
186#define SMC_CAN_USE_8BIT 0
187#define SMC_CAN_USE_16BIT 1
188#define SMC_CAN_USE_32BIT 0
189#define SMC_IO_SHIFT 0
190#define SMC_NOWAIT 1
b0348b90 191
b0348b90 192#define SMC_inw(a, r) readw((a) + (r))
b0348b90 193#define SMC_outw(v, a, r) writew(v, (a) + (r))
b0348b90
LB		 194#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
195#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
196
1da177e4
LT		 197#elif defined(CONFIG_ARCH_INNOKOM) || \
198 defined(CONFIG_MACH_MAINSTONE) || \
199 defined(CONFIG_ARCH_PXA_IDP) || \
4f15a980
RS		 200 defined(CONFIG_ARCH_RAMSES) || \
201 defined(CONFIG_ARCH_PCM027)
1da177e4
LT		 202
203#define SMC_CAN_USE_8BIT 1
204#define SMC_CAN_USE_16BIT 1
205#define SMC_CAN_USE_32BIT 1
206#define SMC_IO_SHIFT 0
207#define SMC_NOWAIT 1
208#define SMC_USE_PXA_DMA 1
209
210#define SMC_inb(a, r) readb((a) + (r))
211#define SMC_inw(a, r) readw((a) + (r))
212#define SMC_inl(a, r) readl((a) + (r))
213#define SMC_outb(v, a, r) writeb(v, (a) + (r))
214#define SMC_outl(v, a, r) writel(v, (a) + (r))
215#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
216#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
e7b3dc7e 217#define SMC_IRQ_FLAGS (-1) /* from resource */
1da177e4
LT		 218
219/* We actually can't write halfwords properly if not word aligned */
220static inline void
eb1d6988 221SMC_outw(u16 val, void __iomem *ioaddr, int reg)
1da177e4
LT		 222{
223 if (reg & 2) {
224 unsigned int v = val << 16;
225 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
226 writel(v, ioaddr + (reg & ~2));
227 } else {
228 writew(val, ioaddr + reg);
229 }
230}
231
7c826a0b 232#elif defined(CONFIG_MACH_ZYLONITE)
233
234#define SMC_CAN_USE_8BIT 1
235#define SMC_CAN_USE_16BIT 1
236#define SMC_CAN_USE_32BIT 0
237#define SMC_IO_SHIFT 0
238#define SMC_NOWAIT 1
239#define SMC_USE_PXA_DMA 1
240#define SMC_inb(a, r) readb((a) + (r))
241#define SMC_inw(a, r) readw((a) + (r))
242#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244#define SMC_outb(v, a, r) writeb(v, (a) + (r))
245#define SMC_outw(v, a, r) writew(v, (a) + (r))
e7b3dc7e 246#define SMC_IRQ_FLAGS (-1) /* from resource */
7c826a0b 247
1da177e4
LT		 248#elif defined(CONFIG_ARCH_OMAP)
249
250/* We can only do 16-bit reads and writes in the static memory space. */
251#define SMC_CAN_USE_8BIT 0
252#define SMC_CAN_USE_16BIT 1
253#define SMC_CAN_USE_32BIT 0
254#define SMC_IO_SHIFT 0
255#define SMC_NOWAIT 1
256
1da177e4
LT		 257#define SMC_inw(a, r) readw((a) + (r))
258#define SMC_outw(v, a, r) writew(v, (a) + (r))
259#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
260#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
e7b3dc7e 261#define SMC_IRQ_FLAGS (-1) /* from resource */
5f13e7ec 262
1da177e4
LT		 263#elif defined(CONFIG_SH_SH4202_MICRODEV)
264
265#define SMC_CAN_USE_8BIT 0
266#define SMC_CAN_USE_16BIT 1
267#define SMC_CAN_USE_32BIT 0
268
269#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
270#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
271#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
272#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
273#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
274#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
275#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
276#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
277#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
278#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
279
9ded96f2 280#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 281
282#elif defined(CONFIG_ISA)
283
284#define SMC_CAN_USE_8BIT 1
285#define SMC_CAN_USE_16BIT 1
286#define SMC_CAN_USE_32BIT 0
287
288#define SMC_inb(a, r) inb((a) + (r))
289#define SMC_inw(a, r) inw((a) + (r))
290#define SMC_outb(v, a, r) outb(v, (a) + (r))
291#define SMC_outw(v, a, r) outw(v, (a) + (r))
292#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
293#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
294
5125ed91
NI		 295#elif defined(CONFIG_SUPERH)
296
6026ee67 297#ifdef CONFIG_SOLUTION_ENGINE
18ad4e70 298#define SMC_IRQ_FLAGS (0)
5125ed91
NI		 299#define SMC_CAN_USE_8BIT 0
300#define SMC_CAN_USE_16BIT 1
301#define SMC_CAN_USE_32BIT 0
302#define SMC_IO_SHIFT 0
303#define SMC_NOWAIT 1
304
5125ed91 305#define SMC_inw(a, r) inw((a) + (r))
5125ed91
NI		 306#define SMC_outw(v, a, r) outw(v, (a) + (r))
307#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
308#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
309
310#else /* BOARDS */
311
312#define SMC_CAN_USE_8BIT 1
313#define SMC_CAN_USE_16BIT 1
092ed997 314#define SMC_CAN_USE_32BIT 0
5125ed91
NI		 315
316#define SMC_inb(a, r) inb((a) + (r))
317#define SMC_inw(a, r) inw((a) + (r))
318#define SMC_outb(v, a, r) outb(v, (a) + (r))
319#define SMC_outw(v, a, r) outw(v, (a) + (r))
320#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
321#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
322
323#endif /* BOARDS */
324
1da177e4
LT		 325#elif defined(CONFIG_M32R)
326
327#define SMC_CAN_USE_8BIT 0
328#define SMC_CAN_USE_16BIT 1
329#define SMC_CAN_USE_32BIT 0
330
59dc76a4 331#define SMC_inb(a, r) inb(((u32)a) + (r))
f3ac9fbf
HT		 332#define SMC_inw(a, r) inw(((u32)a) + (r))
333#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
334#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
335#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
336#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
1da177e4 337
9ded96f2 338#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 339
340#define RPC_LSA_DEFAULT RPC_LED_TX_RX
341#define RPC_LSB_DEFAULT RPC_LED_100_10
342
d4adcffb
MS		 343#elif defined(CONFIG_MACH_LPD79520) \
344 || defined(CONFIG_MACH_LPD7A400) \
345 || defined(CONFIG_MACH_LPD7A404)
1da177e4 346
d4adcffb
MS		 347/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
348 * way that the CPU handles chip selects and the way that the SMC chip
349 * expects the chip select to operate. Refer to
1da177e4 350 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
d4adcffb
MS		 351 * IOBARRIER is a byte, in order that we read the least-common
352 * denominator. It would be wasteful to read 32 bits from an 8-bit
353 * accessible region.
1da177e4
LT		 354 *
355 * There is no explicit protection against interrupts intervening
356 * between the writew and the IOBARRIER. In SMC ISR there is a
357 * preamble that performs an IOBARRIER in the extremely unlikely event
358 * that the driver interrupts itself between a writew to the chip an
359 * the IOBARRIER that follows *and* the cache is large enough that the
360 * first off-chip access while handing the interrupt is to the SMC
361 * chip. Other devices in the same address space as the SMC chip must
362 * be aware of the potential for trouble and perform a similar
363 * IOBARRIER on entry to their ISR.
364 */
365
366#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
367
368#define SMC_CAN_USE_8BIT 0
369#define SMC_CAN_USE_16BIT 1
370#define SMC_CAN_USE_32BIT 0
371#define SMC_NOWAIT 0
d4adcffb 372#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
1da177e4 373
d4adcffb
MS		 374#define SMC_inw(a,r)\
375 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
376#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
1da177e4 377
d4adcffb
MS		 378#define SMC_insw LPD7_SMC_insw
379static inline void LPD7_SMC_insw (unsigned char* a, int r,
380 unsigned char* p, int l)
381{
382 unsigned short* ps = (unsigned short*) p;
383 while (l-- > 0) {
384 *ps++ = readw (a + r);
385 LPD7X_IOBARRIER;
386 }
387}
09779c6d 388
d4adcffb
MS		 389#define SMC_outsw LPD7_SMC_outsw
390static inline void LPD7_SMC_outsw (unsigned char* a, int r,
391 unsigned char* p, int l)
1da177e4
LT		 392{
393 unsigned short* ps = (unsigned short*) p;
394 while (l-- > 0) {
395 writew (*ps++, a + r);
d4adcffb 396 LPD7X_IOBARRIER;
1da177e4
LT		 397 }
398}
399
d4adcffb 400#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
1da177e4
LT		 401
402#define RPC_LSA_DEFAULT RPC_LED_TX_RX
403#define RPC_LSB_DEFAULT RPC_LED_100_10
404
55793455
PP		 405#elif defined(CONFIG_SOC_AU1X00)
406
407#include <au1xxx.h>
408
409/* We can only do 16-bit reads and writes in the static memory space. */
410#define SMC_CAN_USE_8BIT 0
411#define SMC_CAN_USE_16BIT 1
412#define SMC_CAN_USE_32BIT 0
413#define SMC_IO_SHIFT 0
414#define SMC_NOWAIT 1
415
416#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
417#define SMC_insw(a, r, p, l) \
418 do { \
419 unsigned long _a = (unsigned long)((a) + (r)); \
420 int _l = (l); \
421 u16 *_p = (u16 *)(p); \
422 while (_l-- > 0) \
423 *_p++ = au_readw(_a); \
424 } while(0)
425#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
426#define SMC_outsw(a, r, p, l) \
427 do { \
428 unsigned long _a = (unsigned long)((a) + (r)); \
429 int _l = (l); \
430 const u16 *_p = (const u16 *)(p); \
431 while (_l-- > 0) \
432 au_writew(*_p++ , _a); \
433 } while(0)
434
9ded96f2 435#define SMC_IRQ_FLAGS (0)
33fee56a
DS		 436
437#elif defined(CONFIG_ARCH_VERSATILE)
438
439#define SMC_CAN_USE_8BIT 1
440#define SMC_CAN_USE_16BIT 1
441#define SMC_CAN_USE_32BIT 1
442#define SMC_NOWAIT 1
443
444#define SMC_inb(a, r) readb((a) + (r))
445#define SMC_inw(a, r) readw((a) + (r))
446#define SMC_inl(a, r) readl((a) + (r))
447#define SMC_outb(v, a, r) writeb(v, (a) + (r))
448#define SMC_outw(v, a, r) writew(v, (a) + (r))
449#define SMC_outl(v, a, r) writel(v, (a) + (r))
450#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
451#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
e7b3dc7e 452#define SMC_IRQ_FLAGS (-1) /* from resource */
55793455 453
b920de1b
DH		 454#elif defined(CONFIG_MN10300)
455
456/*
457 * MN10300/AM33 configuration
458 */
459
460#include <asm/unit/smc91111.h>
461
1da177e4
LT		 462#else
463
b920de1b
DH		 464/*
465 * Default configuration
466 */
467
1da177e4
LT		 468#define SMC_CAN_USE_8BIT 1
469#define SMC_CAN_USE_16BIT 1
470#define SMC_CAN_USE_32BIT 1
471#define SMC_NOWAIT 1
472
473#define SMC_inb(a, r) readb((a) + (r))
474#define SMC_inw(a, r) readw((a) + (r))
475#define SMC_inl(a, r) readl((a) + (r))
476#define SMC_outb(v, a, r) writeb(v, (a) + (r))
477#define SMC_outw(v, a, r) writew(v, (a) + (r))
478#define SMC_outl(v, a, r) writel(v, (a) + (r))
479#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
480#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
481
482#define RPC_LSA_DEFAULT RPC_LED_100_10
483#define RPC_LSB_DEFAULT RPC_LED_TX_RX
484
3e947943 485#define SMC_DYNAMIC_BUS_CONFIG
1da177e4
LT		 486#endif
487
073ac8fd
RK		 488
489/* store this information for the driver.. */
490struct smc_local {
491 /*
492 * If I have to wait until memory is available to send a
493 * packet, I will store the skbuff here, until I get the
494 * desired memory. Then, I'll send it out and free it.
495 */
496 struct sk_buff *pending_tx_skb;
497 struct tasklet_struct tx_task;
498
499 /* version/revision of the SMC91x chip */
500 int version;
501
502 /* Contains the current active transmission mode */
503 int tcr_cur_mode;
504
505 /* Contains the current active receive mode */
506 int rcr_cur_mode;
507
508 /* Contains the current active receive/phy mode */
509 int rpc_cur_mode;
510 int ctl_rfduplx;
511 int ctl_rspeed;
512
513 u32 msg_enable;
514 u32 phy_type;
515 struct mii_if_info mii;
516
517 /* work queue */
518 struct work_struct phy_configure;
519 struct net_device *dev;
520 int work_pending;
521
522 spinlock_t lock;
523
524#ifdef SMC_USE_PXA_DMA
525 /* DMA needs the physical address of the chip */
526 u_long physaddr;
527 struct device *device;
528#endif
529 void __iomem *base;
530 void __iomem *datacs;
3e947943
MD		 531
532 struct smc91x_platdata cfg;
073ac8fd
RK		 533};
534
3e947943
MD		 535#ifdef SMC_DYNAMIC_BUS_CONFIG
536#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
537#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
538#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
539#else
540#define SMC_8BIT(p) SMC_CAN_USE_8BIT
541#define SMC_16BIT(p) SMC_CAN_USE_16BIT
542#define SMC_32BIT(p) SMC_CAN_USE_32BIT
543#endif
073ac8fd 544
1da177e4
LT		 545#ifdef SMC_USE_PXA_DMA
546/*
547 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
548 * always happening in irq context so no need to worry about races. TX is
549 * different and probably not worth it for that reason, and not as critical
550 * as RX which can overrun memory and lose packets.
551 */
552#include <linux/dma-mapping.h>
553#include <asm/dma.h>
554#include <asm/arch/pxa-regs.h>
555
556#ifdef SMC_insl
557#undef SMC_insl
558#define SMC_insl(a, r, p, l) \
073ac8fd 559 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
1da177e4 560static inline void
073ac8fd 561smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
1da177e4
LT		 562 u_char *buf, int len)
563{
073ac8fd 564 u_long physaddr = lp->physaddr;
1da177e4
LT		 565 dma_addr_t dmabuf;
566
567 /* fallback if no DMA available */
568 if (dma == (unsigned char)-1) {
569 readsl(ioaddr + reg, buf, len);
570 return;
571 }
572
573 /* 64 bit alignment is required for memory to memory DMA */
574 if ((long)buf & 4) {
575 *((u32 *)buf) = SMC_inl(ioaddr, reg);
576 buf += 4;
577 len--;
578 }
579
580 len *= 4;
073ac8fd 581 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
1da177e4
LT		 582 DCSR(dma) = DCSR_NODESC;
583 DTADR(dma) = dmabuf;
584 DSADR(dma) = physaddr + reg;
585 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
586 DCMD_WIDTH4 | (DCMD_LENGTH & len));
587 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
588 while (!(DCSR(dma) & DCSR_STOPSTATE))
589 cpu_relax();
590 DCSR(dma) = 0;
073ac8fd 591 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
1da177e4
LT		 592}
593#endif
594
595#ifdef SMC_insw
596#undef SMC_insw
597#define SMC_insw(a, r, p, l) \
073ac8fd 598 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
1da177e4 599static inline void
073ac8fd 600smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
1da177e4
LT		 601 u_char *buf, int len)
602{
073ac8fd 603 u_long physaddr = lp->physaddr;
1da177e4
LT		 604 dma_addr_t dmabuf;
605
606 /* fallback if no DMA available */
607 if (dma == (unsigned char)-1) {
608 readsw(ioaddr + reg, buf, len);
609 return;
610 }
611
612 /* 64 bit alignment is required for memory to memory DMA */
613 while ((long)buf & 6) {
614 *((u16 *)buf) = SMC_inw(ioaddr, reg);
615 buf += 2;
616 len--;
617 }
618
619 len *= 2;
073ac8fd 620 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
1da177e4
LT		 621 DCSR(dma) = DCSR_NODESC;
622 DTADR(dma) = dmabuf;
623 DSADR(dma) = physaddr + reg;
624 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
625 DCMD_WIDTH2 | (DCMD_LENGTH & len));
626 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
627 while (!(DCSR(dma) & DCSR_STOPSTATE))
628 cpu_relax();
629 DCSR(dma) = 0;
073ac8fd 630 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
1da177e4
LT		 631}
632#endif
633
634static void
7d12e780 635smc_pxa_dma_irq(int dma, void *dummy)
1da177e4
LT		 636{
637 DCSR(dma) = 0;
638}
639#endif /* SMC_USE_PXA_DMA */
640
641
09779c6d
NP		 642/*
643 * Everything a particular hardware setup needs should have been defined
644 * at this point. Add stubs for the undefined cases, mainly to avoid
645 * compilation warnings since they'll be optimized away, or to prevent buggy
646 * use of them.
647 */
648
649#if ! SMC_CAN_USE_32BIT
650#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
651#define SMC_outl(x, ioaddr, reg) BUG()
652#define SMC_insl(a, r, p, l) BUG()
653#define SMC_outsl(a, r, p, l) BUG()
654#endif
655
656#if !defined(SMC_insl) || !defined(SMC_outsl)
657#define SMC_insl(a, r, p, l) BUG()
658#define SMC_outsl(a, r, p, l) BUG()
659#endif
660
661#if ! SMC_CAN_USE_16BIT
662
663/*
664 * Any 16-bit access is performed with two 8-bit accesses if the hardware
665 * can't do it directly. Most registers are 16-bit so those are mandatory.
666 */
667#define SMC_outw(x, ioaddr, reg) \
668 do { \
669 unsigned int __val16 = (x); \
670 SMC_outb( __val16, ioaddr, reg ); \
671 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
672 } while (0)
673#define SMC_inw(ioaddr, reg) \
674 ({ \
675 unsigned int __val16; \
676 __val16 = SMC_inb( ioaddr, reg ); \
677 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
678 __val16; \
679 })
680
681#define SMC_insw(a, r, p, l) BUG()
682#define SMC_outsw(a, r, p, l) BUG()
683
684#endif
685
686#if !defined(SMC_insw) || !defined(SMC_outsw)
687#define SMC_insw(a, r, p, l) BUG()
688#define SMC_outsw(a, r, p, l) BUG()
689#endif
690
691#if ! SMC_CAN_USE_8BIT
692#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
693#define SMC_outb(x, ioaddr, reg) BUG()
694#define SMC_insb(a, r, p, l) BUG()
695#define SMC_outsb(a, r, p, l) BUG()
696#endif
697
698#if !defined(SMC_insb) || !defined(SMC_outsb)
699#define SMC_insb(a, r, p, l) BUG()
700#define SMC_outsb(a, r, p, l) BUG()
701#endif
702
703#ifndef SMC_CAN_USE_DATACS
704#define SMC_CAN_USE_DATACS 0
705#endif
706
1da177e4
LT		 707#ifndef SMC_IO_SHIFT
708#define SMC_IO_SHIFT 0
709#endif
09779c6d
NP		 710
711#ifndef SMC_IRQ_FLAGS
1fb9df5d 712#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
09779c6d
NP		 713#endif
714
715#ifndef SMC_INTERRUPT_PREAMBLE
716#define SMC_INTERRUPT_PREAMBLE
717#endif
718
719
720/* Because of bank switching, the LAN91x uses only 16 I/O ports */
1da177e4
LT		 721#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
722#define SMC_DATA_EXTENT (4)
723
724/*
725 . Bank Select Register:
726 .
727 . yyyy yyyy 0000 00xx
728 . xx = bank number
729 . yyyy yyyy = 0x33, for identification purposes.
730*/
731#define BANK_SELECT (14 << SMC_IO_SHIFT)
732
733
734// Transmit Control Register
735/* BANK 0 */
cfdfa865 736#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
1da177e4
LT		 737#define TCR_ENABLE 0x0001 // When 1 we can transmit
738#define TCR_LOOP 0x0002 // Controls output pin LBK
739#define TCR_FORCOL 0x0004 // When 1 will force a collision
740#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
741#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
742#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
743#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
744#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
745#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
746#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
747
748#define TCR_CLEAR 0 /* do NOTHING */
749/* the default settings for the TCR register : */
750#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
751
752
753// EPH Status Register
754/* BANK 0 */
cfdfa865 755#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
1da177e4
LT		 756#define ES_TX_SUC 0x0001 // Last TX was successful
757#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
758#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
759#define ES_LTX_MULT 0x0008 // Last tx was a multicast
760#define ES_16COL 0x0010 // 16 Collisions Reached
761#define ES_SQET 0x0020 // Signal Quality Error Test
762#define ES_LTXBRD 0x0040 // Last tx was a broadcast
763#define ES_TXDEFR 0x0080 // Transmit Deferred
764#define ES_LATCOL 0x0200 // Late collision detected on last tx
765#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
766#define ES_EXC_DEF 0x0800 // Excessive Deferral
767#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
768#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
769#define ES_TXUNRN 0x8000 // Tx Underrun
770
771
772// Receive Control Register
773/* BANK 0 */
cfdfa865 774#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
1da177e4
LT		 775#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
776#define RCR_PRMS 0x0002 // Enable promiscuous mode
777#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
778#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
779#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
780#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
781#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
782#define RCR_SOFTRST 0x8000 // resets the chip
783
784/* the normal settings for the RCR register : */
785#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
786#define RCR_CLEAR 0x0 // set it to a base state
787
788
789// Counter Register
790/* BANK 0 */
cfdfa865 791#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
1da177e4
LT		 792
793
794// Memory Information Register
795/* BANK 0 */
cfdfa865 796#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
1da177e4
LT		 797
798
799// Receive/Phy Control Register
800/* BANK 0 */
cfdfa865 801#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
1da177e4
LT		 802#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
803#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
804#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
805#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
806#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
807#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
808#define RPC_LED_RES (0x01) // LED = Reserved
809#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
810#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
811#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
812#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
813#define RPC_LED_TX (0x06) // LED = TX packet occurred
814#define RPC_LED_RX (0x07) // LED = RX packet occurred
815
816#ifndef RPC_LSA_DEFAULT
817#define RPC_LSA_DEFAULT RPC_LED_100
818#endif
819#ifndef RPC_LSB_DEFAULT
820#define RPC_LSB_DEFAULT RPC_LED_FD
821#endif
822
823#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
824
825
826/* Bank 0 0x0C is reserved */
827
828// Bank Select Register
829/* All Banks */
830#define BSR_REG 0x000E
831
832
833// Configuration Reg
834/* BANK 1 */
cfdfa865 835#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
1da177e4
LT		 836#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
837#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
838#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
839#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
840
841// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
842#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
843
844
845// Base Address Register
846/* BANK 1 */
cfdfa865 847#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
1da177e4
LT		 848
849
850// Individual Address Registers
851/* BANK 1 */
cfdfa865
MD		 852#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
853#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
854#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
1da177e4
LT		 855
856
857// General Purpose Register
858/* BANK 1 */
cfdfa865 859#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
1da177e4
LT		 860
861
862// Control Register
863/* BANK 1 */
cfdfa865 864#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
1da177e4
LT		 865#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
866#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
867#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
868#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
869#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
870#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
871#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
872#define CTL_STORE 0x0001 // When set stores registers into EEPROM
873
874
875// MMU Command Register
876/* BANK 2 */
cfdfa865 877#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
1da177e4
LT		 878#define MC_BUSY 1 // When 1 the last release has not completed
879#define MC_NOP (0<<5) // No Op
880#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
881#define MC_RESET (2<<5) // Reset MMU to initial state
882#define MC_REMOVE (3<<5) // Remove the current rx packet
883#define MC_RELEASE (4<<5) // Remove and release the current rx packet
884#define MC_FREEPKT (5<<5) // Release packet in PNR register
885#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
886#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
887
888
889// Packet Number Register
890/* BANK 2 */
cfdfa865 891#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
1da177e4
LT		 892
893
894// Allocation Result Register
895/* BANK 2 */
cfdfa865 896#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
1da177e4
LT		 897#define AR_FAILED 0x80 // Alocation Failed
898
899
900// TX FIFO Ports Register
901/* BANK 2 */
cfdfa865 902#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
1da177e4
LT		 903#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
904
905// RX FIFO Ports Register
906/* BANK 2 */
cfdfa865 907#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
1da177e4
LT		 908#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
909
cfdfa865 910#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
1da177e4
LT		 911
912// Pointer Register
913/* BANK 2 */
cfdfa865 914#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
1da177e4
LT		 915#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
916#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
917#define PTR_READ 0x2000 // When 1 the operation is a read
918
919
920// Data Register
921/* BANK 2 */
cfdfa865 922#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
1da177e4
LT		 923
924
925// Interrupt Status/Acknowledge Register
926/* BANK 2 */
cfdfa865 927#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
1da177e4
LT		 928
929
930// Interrupt Mask Register
931/* BANK 2 */
cfdfa865 932#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
1da177e4
LT		 933#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
934#define IM_ERCV_INT 0x40 // Early Receive Interrupt
935#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
936#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
937#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
938#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
939#define IM_TX_INT 0x02 // Transmit Interrupt
940#define IM_RCV_INT 0x01 // Receive Interrupt
941
942
943// Multicast Table Registers
944/* BANK 3 */
cfdfa865
MD		 945#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
946#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
947#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
948#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
1da177e4
LT		 949
950
951// Management Interface Register (MII)
952/* BANK 3 */
cfdfa865 953#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
1da177e4
LT		 954#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
955#define MII_MDOE 0x0008 // MII Output Enable
956#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
957#define MII_MDI 0x0002 // MII Input, pin MDI
958#define MII_MDO 0x0001 // MII Output, pin MDO
959
960
961// Revision Register
962/* BANK 3 */
963/* ( hi: chip id low: rev # ) */
cfdfa865 964#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
1da177e4
LT		 965
966
967// Early RCV Register
968/* BANK 3 */
969/* this is NOT on SMC9192 */
cfdfa865 970#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
1da177e4
LT		 971#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
972#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
973
974
975// External Register
976/* BANK 7 */
cfdfa865 977#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
1da177e4
LT		 978
979
980#define CHIP_9192 3
981#define CHIP_9194 4
982#define CHIP_9195 5
983#define CHIP_9196 6
984#define CHIP_91100 7
985#define CHIP_91100FD 8
986#define CHIP_91111FD 9
987
988static const char * chip_ids[ 16 ] = {
989 NULL, NULL, NULL,
990 /* 3 */ "SMC91C90/91C92",
991 /* 4 */ "SMC91C94",
992 /* 5 */ "SMC91C95",
993 /* 6 */ "SMC91C96",
994 /* 7 */ "SMC91C100",
995 /* 8 */ "SMC91C100FD",
996 /* 9 */ "SMC91C11xFD",
997 NULL, NULL, NULL,
998 NULL, NULL, NULL};
999
1000
1da177e4
LT		 1001/*
1002 . Receive status bits
1003*/
1004#define RS_ALGNERR 0x8000
1005#define RS_BRODCAST 0x4000
1006#define RS_BADCRC 0x2000
1007#define RS_ODDFRAME 0x1000
1008#define RS_TOOLONG 0x0800
1009#define RS_TOOSHORT 0x0400
1010#define RS_MULTICAST 0x0001
1011#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
1012
1013
1014/*
1015 * PHY IDs
1016 * LAN83C183 == LAN91C111 Internal PHY
1017 */
1018#define PHY_LAN83C183 0x0016f840
1019#define PHY_LAN83C180 0x02821c50
1020
1021/*
1022 * PHY Register Addresses (LAN91C111 Internal PHY)
1023 *
1024 * Generic PHY registers can be found in <linux/mii.h>
1025 *
1026 * These phy registers are specific to our on-board phy.
1027 */
1028
1029// PHY Configuration Register 1
1030#define PHY_CFG1_REG 0x10
1031#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1032#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1033#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1034#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1035#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1036#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1037#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1038#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1039#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1040#define PHY_CFG1_TLVL_MASK 0x003C
1041#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1042
1043
1044// PHY Configuration Register 2
1045#define PHY_CFG2_REG 0x11
1046#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1047#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1048#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1049#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1050
1051// PHY Status Output (and Interrupt status) Register
1052#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1053#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1054#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1055#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1056#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1057#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1058#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1059#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1060#define PHY_INT_JAB 0x0100 // 1=Jabber detected
1061#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1062#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1063
1064// PHY Interrupt/Status Mask Register
1065#define PHY_MASK_REG 0x13 // Interrupt Mask
1066// Uses the same bit definitions as PHY_INT_REG
1067
1068
1069/*
1070 * SMC91C96 ethernet config and status registers.
1071 * These are in the "attribute" space.
1072 */
1073#define ECOR 0x8000
1074#define ECOR_RESET 0x80
1075#define ECOR_LEVEL_IRQ 0x40
1076#define ECOR_WR_ATTRIB 0x04
1077#define ECOR_ENABLE 0x01
1078
1079#define ECSR 0x8002
1080#define ECSR_IOIS8 0x20
1081#define ECSR_PWRDWN 0x04
1082#define ECSR_INT 0x02
1083
1084#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1085
1086
1087/*
1088 * Macros to abstract register access according to the data bus
1089 * capabilities. Please use those and not the in/out primitives.
1090 * Note: the following macros do *not* select the bank -- this must
1091 * be done separately as needed in the main code. The SMC_REG() macro
1092 * only uses the bank argument for debugging purposes (when enabled).
09779c6d
NP		 1093 *
1094 * Note: despite inline functions being safer, everything leading to this
1095 * should preferably be macros to let BUG() display the line number in
1096 * the core source code since we're interested in the top call site
1097 * not in any inline function location.
1da177e4
LT		 1098 */
1099
1100#if SMC_DEBUG > 0
cfdfa865 1101#define SMC_REG(lp, reg, bank) \
1da177e4 1102 ({ \
cfdfa865 1103 int __b = SMC_CURRENT_BANK(lp); \
1da177e4
LT		 1104 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1105 printk( "%s: bank reg screwed (0x%04x)\n", \
1106 CARDNAME, __b ); \
1107 BUG(); \
1108 } \
1109 reg<<SMC_IO_SHIFT; \
1110 })
1111#else
cfdfa865 1112#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1da177e4
LT		 1113#endif
1114
09779c6d
NP		 1115/*
1116 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1117 * aligned to a 32 bit boundary. I tell you that does exist!
1118 * Fortunately the affected register accesses can be easily worked around
1119 * since we can write zeroes to the preceeding 16 bits without adverse
1120 * effects and use a 32-bit access.
1121 *
1122 * Enforce it on any 32-bit capable setup for now.
1123 */
3e947943 1124#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
09779c6d 1125
cfdfa865 1126#define SMC_GET_PN(lp) \
3e947943 1127 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
cfdfa865 1128 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
09779c6d 1129
cfdfa865 1130#define SMC_SET_PN(lp, x) \
09779c6d 1131 do { \
3e947943 1132 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 1133 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
3e947943 1134 else if (SMC_8BIT(lp)) \
cfdfa865 1135 SMC_outb(x, ioaddr, PN_REG(lp)); \
09779c6d 1136 else \
cfdfa865 1137 SMC_outw(x, ioaddr, PN_REG(lp)); \
09779c6d
NP		 1138 } while (0)
1139
cfdfa865 1140#define SMC_GET_AR(lp) \
3e947943 1141 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
cfdfa865 1142 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
09779c6d 1143
cfdfa865 1144#define SMC_GET_TXFIFO(lp) \
3e947943 1145 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
cfdfa865 1146 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
09779c6d 1147
cfdfa865 1148#define SMC_GET_RXFIFO(lp) \
3e947943 1149 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
cfdfa865 1150 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
09779c6d 1151
cfdfa865 1152#define SMC_GET_INT(lp) \
3e947943 1153 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
cfdfa865 1154 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
09779c6d 1155
cfdfa865 1156#define SMC_ACK_INT(lp, x) \
1da177e4 1157 do { \
3e947943 1158 if (SMC_8BIT(lp)) \
cfdfa865 1159 SMC_outb(x, ioaddr, INT_REG(lp)); \
09779c6d
NP		 1160 else { \
1161 unsigned long __flags; \
1162 int __mask; \
1163 local_irq_save(__flags); \
cfdfa865
MD		 1164 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1165 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
09779c6d
NP		 1166 local_irq_restore(__flags); \
1167 } \
1168 } while (0)
1169
cfdfa865 1170#define SMC_GET_INT_MASK(lp) \
3e947943 1171 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
cfdfa865 1172 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
09779c6d 1173
cfdfa865 1174#define SMC_SET_INT_MASK(lp, x) \
09779c6d 1175 do { \
3e947943 1176 if (SMC_8BIT(lp)) \
cfdfa865 1177 SMC_outb(x, ioaddr, IM_REG(lp)); \
09779c6d 1178 else \
cfdfa865 1179 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
09779c6d
NP		 1180 } while (0)
1181
cfdfa865 1182#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
09779c6d 1183
cfdfa865 1184#define SMC_SELECT_BANK(lp, x) \
09779c6d 1185 do { \
3e947943 1186 if (SMC_MUST_ALIGN_WRITE(lp)) \
09779c6d
NP		 1187 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1188 else \
1189 SMC_outw(x, ioaddr, BANK_SELECT); \
1190 } while (0)
1191
cfdfa865 1192#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
09779c6d 1193
cfdfa865 1194#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
09779c6d 1195
cfdfa865 1196#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
09779c6d 1197
cfdfa865 1198#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
09779c6d 1199
cfdfa865 1200#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
09779c6d 1201
cfdfa865 1202#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
09779c6d 1203
cfdfa865 1204#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
09779c6d 1205
cfdfa865 1206#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
09779c6d 1207
cfdfa865 1208#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
09779c6d 1209
cfdfa865 1210#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
09779c6d 1211
cfdfa865 1212#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
09779c6d 1213
cfdfa865 1214#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
09779c6d 1215
cfdfa865 1216#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
09779c6d 1217
cfdfa865 1218#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
09779c6d 1219
cfdfa865 1220#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
09779c6d 1221
cfdfa865 1222#define SMC_SET_PTR(lp, x) \
09779c6d 1223 do { \
3e947943 1224 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 1225 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
09779c6d 1226 else \
cfdfa865 1227 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1da177e4 1228 } while (0)
1da177e4 1229
cfdfa865 1230#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
09779c6d 1231
cfdfa865 1232#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
09779c6d 1233
cfdfa865 1234#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
09779c6d 1235
cfdfa865 1236#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
09779c6d 1237
cfdfa865 1238#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
09779c6d 1239
cfdfa865 1240#define SMC_SET_RPC(lp, x) \
09779c6d 1241 do { \
3e947943 1242 if (SMC_MUST_ALIGN_WRITE(lp)) \
cfdfa865 1243 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
09779c6d 1244 else \
cfdfa865 1245 SMC_outw(x, ioaddr, RPC_REG(lp)); \
09779c6d
NP		 1246 } while (0)
1247
cfdfa865 1248#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
09779c6d 1249
cfdfa865 1250#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1da177e4
LT		 1251
1252#ifndef SMC_GET_MAC_ADDR
cfdfa865 1253#define SMC_GET_MAC_ADDR(lp, addr) \
1da177e4
LT		 1254 do { \
1255 unsigned int __v; \
cfdfa865 1256 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1da177e4 1257 addr[0] = __v; addr[1] = __v >> 8; \
cfdfa865 1258 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1da177e4 1259 addr[2] = __v; addr[3] = __v >> 8; \
cfdfa865 1260 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1da177e4
LT		 1261 addr[4] = __v; addr[5] = __v >> 8; \
1262 } while (0)
1263#endif
1264
cfdfa865 1265#define SMC_SET_MAC_ADDR(lp, addr) \
1da177e4 1266 do { \
cfdfa865
MD		 1267 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1268 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1269 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1da177e4
LT		 1270 } while (0)
1271
cfdfa865 1272#define SMC_SET_MCAST(lp, x) \
1da177e4
LT		 1273 do { \
1274 const unsigned char *mt = (x); \
cfdfa865
MD		 1275 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1276 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1277 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1278 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1da177e4
LT		 1279 } while (0)
1280
cfdfa865 1281#define SMC_PUT_PKT_HDR(lp, status, length) \
1da177e4 1282 do { \
3e947943 1283 if (SMC_32BIT(lp)) \
cfdfa865
MD		 1284 SMC_outl((status) | (length)<<16, ioaddr, \
1285 DATA_REG(lp)); \
09779c6d 1286 else { \
cfdfa865
MD		 1287 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1288 SMC_outw(length, ioaddr, DATA_REG(lp)); \
09779c6d 1289 } \
1da177e4 1290 } while (0)
1da177e4 1291
cfdfa865 1292#define SMC_GET_PKT_HDR(lp, status, length) \
1da177e4 1293 do { \
3e947943 1294 if (SMC_32BIT(lp)) { \
cfdfa865 1295 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
09779c6d
NP		 1296 (status) = __val & 0xffff; \
1297 (length) = __val >> 16; \
1298 } else { \
cfdfa865
MD		 1299 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1300 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1da177e4
LT		 1301 } \
1302 } while (0)
1da177e4 1303
cfdfa865 1304#define SMC_PUSH_DATA(lp, p, l) \
1da177e4 1305 do { \
3e947943 1306 if (SMC_32BIT(lp)) { \
09779c6d
NP		 1307 void *__ptr = (p); \
1308 int __len = (l); \
fbd81976 1309 void __iomem *__ioaddr = ioaddr; \
09779c6d
NP		 1310 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1311 __len -= 2; \
cfdfa865
MD		 1312 SMC_outw(*(u16 *)__ptr, ioaddr, \
1313 DATA_REG(lp)); \
09779c6d
NP		 1314 __ptr += 2; \
1315 } \
1316 if (SMC_CAN_USE_DATACS && lp->datacs) \
1317 __ioaddr = lp->datacs; \
cfdfa865 1318 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
09779c6d
NP		 1319 if (__len & 2) { \
1320 __ptr += (__len & ~3); \
cfdfa865
MD		 1321 SMC_outw(*((u16 *)__ptr), ioaddr, \
1322 DATA_REG(lp)); \
09779c6d 1323 } \
3e947943 1324 } else if (SMC_16BIT(lp)) \
cfdfa865 1325 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
3e947943 1326 else if (SMC_8BIT(lp)) \
cfdfa865 1327 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1da177e4 1328 } while (0)
1da177e4 1329
cfdfa865 1330#define SMC_PULL_DATA(lp, p, l) \
09779c6d 1331 do { \
3e947943 1332 if (SMC_32BIT(lp)) { \
09779c6d
NP		 1333 void *__ptr = (p); \
1334 int __len = (l); \
fbd81976 1335 void __iomem *__ioaddr = ioaddr; \
09779c6d
NP		 1336 if ((unsigned long)__ptr & 2) { \
1337 /* \
1338 * We want 32bit alignment here. \
1339 * Since some buses perform a full \
1340 * 32bit fetch even for 16bit data \
1341 * we can't use SMC_inw() here. \
1342 * Back both source (on-chip) and \
1343 * destination pointers of 2 bytes. \
1344 * This is possible since the call to \
1345 * SMC_GET_PKT_HDR() already advanced \
1346 * the source pointer of 4 bytes, and \
1347 * the skb_reserve(skb, 2) advanced \
1348 * the destination pointer of 2 bytes. \
1349 */ \
1350 __ptr -= 2; \
1351 __len += 2; \
cfdfa865
MD		 1352 SMC_SET_PTR(lp, \
1353 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
09779c6d
NP		 1354 } \
1355 if (SMC_CAN_USE_DATACS && lp->datacs) \
1356 __ioaddr = lp->datacs; \
1da177e4 1357 __len += 2; \
cfdfa865 1358 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
3e947943 1359 } else if (SMC_16BIT(lp)) \
cfdfa865 1360 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
3e947943 1361 else if (SMC_8BIT(lp)) \
cfdfa865 1362 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
09779c6d 1363 } while (0)
1da177e4
LT		 1364
1365#endif /* _SMC91X_H_ */
kernel source for telekom puls (alcatel/mediatek)