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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
31 | . Nicolas Pitre <nico@cam.org> | |
32 | . | |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
3e947943 | 37 | #include <linux/smc91x.h> |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Define your architecture specific bus configuration parameters here. | |
41 | */ | |
42 | ||
38fd6c38 EM |
43 | #if defined(CONFIG_ARCH_LUBBOCK) ||\ |
44 | defined(CONFIG_MACH_MAINSTONE) | |
1da177e4 | 45 | |
38fd6c38 EM |
46 | #include <asm/mach-types.h> |
47 | ||
48 | /* Now the bus width is specified in the platform data | |
49 | * pretend here to support all I/O access types | |
50 | */ | |
51 | #define SMC_CAN_USE_8BIT 1 | |
1da177e4 | 52 | #define SMC_CAN_USE_16BIT 1 |
38fd6c38 | 53 | #define SMC_CAN_USE_32BIT 1 |
1da177e4 LT |
54 | #define SMC_NOWAIT 1 |
55 | ||
3aed74cd | 56 | #define SMC_IO_SHIFT (lp->io_shift) |
1da177e4 | 57 | |
38fd6c38 | 58 | #define SMC_inb(a, r) readb((a) + (r)) |
1da177e4 | 59 | #define SMC_inw(a, r) readw((a) + (r)) |
38fd6c38 EM |
60 | #define SMC_inl(a, r) readl((a) + (r)) |
61 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
62 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
1da177e4 LT |
63 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
64 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
38fd6c38 EM |
65 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
66 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 67 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 68 | |
38fd6c38 EM |
69 | /* We actually can't write halfwords properly if not word aligned */ |
70 | static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) | |
71 | { | |
72 | if (machine_is_mainstone() && reg & 2) { | |
73 | unsigned int v = val << 16; | |
74 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
75 | writel(v, ioaddr + (reg & ~2)); | |
76 | } else { | |
77 | writew(val, ioaddr + reg); | |
78 | } | |
79 | } | |
80 | ||
95af9feb | 81 | #elif defined(CONFIG_BLACKFIN) |
0851a284 WB |
82 | |
83 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH | |
c5760abd JCR |
84 | #define RPC_LSA_DEFAULT RPC_LED_100_10 |
85 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
0851a284 WB |
86 | |
87 | # if defined (CONFIG_BFIN561_EZKIT) | |
88 | #define SMC_CAN_USE_8BIT 0 | |
89 | #define SMC_CAN_USE_16BIT 1 | |
90 | #define SMC_CAN_USE_32BIT 1 | |
91 | #define SMC_IO_SHIFT 0 | |
92 | #define SMC_NOWAIT 1 | |
93 | #define SMC_USE_BFIN_DMA 0 | |
94 | ||
95 | ||
96 | #define SMC_inw(a, r) readw((a) + (r)) | |
97 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
98 | #define SMC_inl(a, r) readl((a) + (r)) | |
99 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
100 | #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) | |
101 | #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) | |
102 | # else | |
103 | #define SMC_CAN_USE_8BIT 0 | |
104 | #define SMC_CAN_USE_16BIT 1 | |
105 | #define SMC_CAN_USE_32BIT 0 | |
106 | #define SMC_IO_SHIFT 0 | |
107 | #define SMC_NOWAIT 1 | |
108 | #define SMC_USE_BFIN_DMA 0 | |
109 | ||
110 | ||
111 | #define SMC_inw(a, r) readw((a) + (r)) | |
112 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
113 | #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) | |
114 | #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) | |
115 | # endif | |
116 | /* check if the mac in reg is valid */ | |
7427d8b8 | 117 | #define SMC_GET_MAC_ADDR(lp, addr) \ |
0851a284 WB |
118 | do { \ |
119 | unsigned int __v; \ | |
7427d8b8 | 120 | __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ |
0851a284 | 121 | addr[0] = __v; addr[1] = __v >> 8; \ |
7427d8b8 | 122 | __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ |
0851a284 | 123 | addr[2] = __v; addr[3] = __v >> 8; \ |
7427d8b8 | 124 | __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ |
0851a284 WB |
125 | addr[4] = __v; addr[5] = __v >> 8; \ |
126 | if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ | |
127 | random_ether_addr(addr); \ | |
128 | } \ | |
129 | } while (0) | |
1da177e4 LT |
130 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) |
131 | ||
132 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
133 | #define SMC_CAN_USE_8BIT 0 | |
134 | #define SMC_CAN_USE_16BIT 1 | |
135 | #define SMC_CAN_USE_32BIT 0 | |
136 | #define SMC_NOWAIT 1 | |
137 | ||
138 | #define SMC_IO_SHIFT 0 | |
139 | ||
140 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
141 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
142 | #define SMC_insw(a, r, p, l) \ | |
143 | do { \ | |
144 | unsigned long __port = (a) + (r); \ | |
145 | u16 *__p = (u16 *)(p); \ | |
146 | int __l = (l); \ | |
147 | insw(__port, __p, __l); \ | |
148 | while (__l > 0) { \ | |
149 | *__p = swab16(*__p); \ | |
150 | __p++; \ | |
151 | __l--; \ | |
152 | } \ | |
153 | } while (0) | |
154 | #define SMC_outsw(a, r, p, l) \ | |
155 | do { \ | |
156 | unsigned long __port = (a) + (r); \ | |
157 | u16 *__p = (u16 *)(p); \ | |
158 | int __l = (l); \ | |
159 | while (__l > 0) { \ | |
160 | /* Believe it or not, the swab isn't needed. */ \ | |
161 | outw( /* swab16 */ (*__p++), __port); \ | |
162 | __l--; \ | |
163 | } \ | |
164 | } while (0) | |
9ded96f2 | 165 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
166 | |
167 | #elif defined(CONFIG_SA1100_PLEB) | |
168 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
169 | #define SMC_CAN_USE_8BIT 1 | |
170 | #define SMC_CAN_USE_16BIT 1 | |
171 | #define SMC_CAN_USE_32BIT 0 | |
172 | #define SMC_IO_SHIFT 0 | |
173 | #define SMC_NOWAIT 1 | |
174 | ||
1cf99be5 RK |
175 | #define SMC_inb(a, r) readb((a) + (r)) |
176 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
177 | #define SMC_inw(a, r) readw((a) + (r)) | |
178 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
179 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
180 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
181 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
182 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 183 | |
e7b3dc7e | 184 | #define SMC_IRQ_FLAGS (-1) |
1da177e4 LT |
185 | |
186 | #elif defined(CONFIG_SA1100_ASSABET) | |
187 | ||
188 | #include <asm/arch/neponset.h> | |
189 | ||
190 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
191 | #define SMC_CAN_USE_8BIT 1 | |
192 | #define SMC_CAN_USE_16BIT 0 | |
193 | #define SMC_CAN_USE_32BIT 0 | |
194 | #define SMC_NOWAIT 1 | |
195 | ||
196 | /* The first two address lines aren't connected... */ | |
197 | #define SMC_IO_SHIFT 2 | |
198 | ||
199 | #define SMC_inb(a, r) readb((a) + (r)) | |
200 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
201 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
202 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
e7b3dc7e | 203 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 204 | |
b0348b90 LB |
205 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) |
206 | ||
207 | #define SMC_CAN_USE_8BIT 0 | |
208 | #define SMC_CAN_USE_16BIT 1 | |
209 | #define SMC_CAN_USE_32BIT 0 | |
210 | #define SMC_IO_SHIFT 0 | |
211 | #define SMC_NOWAIT 1 | |
b0348b90 | 212 | |
b0348b90 | 213 | #define SMC_inw(a, r) readw((a) + (r)) |
b0348b90 | 214 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
b0348b90 LB |
215 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
216 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
217 | ||
1da177e4 | 218 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
1da177e4 | 219 | defined(CONFIG_ARCH_PXA_IDP) || \ |
4f15a980 RS |
220 | defined(CONFIG_ARCH_RAMSES) || \ |
221 | defined(CONFIG_ARCH_PCM027) | |
1da177e4 LT |
222 | |
223 | #define SMC_CAN_USE_8BIT 1 | |
224 | #define SMC_CAN_USE_16BIT 1 | |
225 | #define SMC_CAN_USE_32BIT 1 | |
226 | #define SMC_IO_SHIFT 0 | |
227 | #define SMC_NOWAIT 1 | |
228 | #define SMC_USE_PXA_DMA 1 | |
229 | ||
230 | #define SMC_inb(a, r) readb((a) + (r)) | |
231 | #define SMC_inw(a, r) readw((a) + (r)) | |
232 | #define SMC_inl(a, r) readl((a) + (r)) | |
233 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
234 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
235 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
236 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 237 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 LT |
238 | |
239 | /* We actually can't write halfwords properly if not word aligned */ | |
240 | static inline void | |
eb1d6988 | 241 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
1da177e4 LT |
242 | { |
243 | if (reg & 2) { | |
244 | unsigned int v = val << 16; | |
245 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
246 | writel(v, ioaddr + (reg & ~2)); | |
247 | } else { | |
248 | writew(val, ioaddr + reg); | |
249 | } | |
250 | } | |
251 | ||
7c826a0b | 252 | #elif defined(CONFIG_MACH_ZYLONITE) |
253 | ||
254 | #define SMC_CAN_USE_8BIT 1 | |
255 | #define SMC_CAN_USE_16BIT 1 | |
256 | #define SMC_CAN_USE_32BIT 0 | |
257 | #define SMC_IO_SHIFT 0 | |
258 | #define SMC_NOWAIT 1 | |
259 | #define SMC_USE_PXA_DMA 1 | |
260 | #define SMC_inb(a, r) readb((a) + (r)) | |
261 | #define SMC_inw(a, r) readw((a) + (r)) | |
262 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
263 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
264 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
265 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
e7b3dc7e | 266 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
7c826a0b | 267 | |
1da177e4 LT |
268 | #elif defined(CONFIG_ARCH_OMAP) |
269 | ||
270 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
271 | #define SMC_CAN_USE_8BIT 0 | |
272 | #define SMC_CAN_USE_16BIT 1 | |
273 | #define SMC_CAN_USE_32BIT 0 | |
274 | #define SMC_IO_SHIFT 0 | |
275 | #define SMC_NOWAIT 1 | |
276 | ||
1da177e4 LT |
277 | #define SMC_inw(a, r) readw((a) + (r)) |
278 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
279 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
280 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
e7b3dc7e | 281 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
5f13e7ec | 282 | |
1da177e4 LT |
283 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
284 | ||
285 | #define SMC_CAN_USE_8BIT 0 | |
286 | #define SMC_CAN_USE_16BIT 1 | |
287 | #define SMC_CAN_USE_32BIT 0 | |
288 | ||
289 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
290 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
291 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
292 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
293 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
294 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
295 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
296 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
297 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
298 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
299 | ||
9ded96f2 | 300 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
301 | |
302 | #elif defined(CONFIG_ISA) | |
303 | ||
304 | #define SMC_CAN_USE_8BIT 1 | |
305 | #define SMC_CAN_USE_16BIT 1 | |
306 | #define SMC_CAN_USE_32BIT 0 | |
307 | ||
308 | #define SMC_inb(a, r) inb((a) + (r)) | |
309 | #define SMC_inw(a, r) inw((a) + (r)) | |
310 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
311 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
312 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
313 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
314 | ||
315 | #elif defined(CONFIG_M32R) | |
316 | ||
317 | #define SMC_CAN_USE_8BIT 0 | |
318 | #define SMC_CAN_USE_16BIT 1 | |
319 | #define SMC_CAN_USE_32BIT 0 | |
320 | ||
59dc76a4 | 321 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
322 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
323 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
324 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
325 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
326 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 327 | |
9ded96f2 | 328 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
329 | |
330 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
331 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
332 | ||
d4adcffb MS |
333 | #elif defined(CONFIG_MACH_LPD79520) \ |
334 | || defined(CONFIG_MACH_LPD7A400) \ | |
335 | || defined(CONFIG_MACH_LPD7A404) | |
1da177e4 | 336 | |
d4adcffb MS |
337 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
338 | * way that the CPU handles chip selects and the way that the SMC chip | |
339 | * expects the chip select to operate. Refer to | |
1da177e4 | 340 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
d4adcffb MS |
341 | * IOBARRIER is a byte, in order that we read the least-common |
342 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
343 | * accessible region. | |
1da177e4 LT |
344 | * |
345 | * There is no explicit protection against interrupts intervening | |
346 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
347 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
348 | * that the driver interrupts itself between a writew to the chip an | |
349 | * the IOBARRIER that follows *and* the cache is large enough that the | |
350 | * first off-chip access while handing the interrupt is to the SMC | |
351 | * chip. Other devices in the same address space as the SMC chip must | |
352 | * be aware of the potential for trouble and perform a similar | |
353 | * IOBARRIER on entry to their ISR. | |
354 | */ | |
355 | ||
356 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
357 | ||
358 | #define SMC_CAN_USE_8BIT 0 | |
359 | #define SMC_CAN_USE_16BIT 1 | |
360 | #define SMC_CAN_USE_32BIT 0 | |
361 | #define SMC_NOWAIT 0 | |
d4adcffb | 362 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
1da177e4 | 363 | |
d4adcffb MS |
364 | #define SMC_inw(a,r)\ |
365 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
366 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
1da177e4 | 367 | |
d4adcffb MS |
368 | #define SMC_insw LPD7_SMC_insw |
369 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
370 | unsigned char* p, int l) | |
371 | { | |
372 | unsigned short* ps = (unsigned short*) p; | |
373 | while (l-- > 0) { | |
374 | *ps++ = readw (a + r); | |
375 | LPD7X_IOBARRIER; | |
376 | } | |
377 | } | |
09779c6d | 378 | |
d4adcffb MS |
379 | #define SMC_outsw LPD7_SMC_outsw |
380 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
381 | unsigned char* p, int l) | |
1da177e4 LT |
382 | { |
383 | unsigned short* ps = (unsigned short*) p; | |
384 | while (l-- > 0) { | |
385 | writew (*ps++, a + r); | |
d4adcffb | 386 | LPD7X_IOBARRIER; |
1da177e4 LT |
387 | } |
388 | } | |
389 | ||
d4adcffb | 390 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
1da177e4 LT |
391 | |
392 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
393 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
394 | ||
55793455 PP |
395 | #elif defined(CONFIG_SOC_AU1X00) |
396 | ||
397 | #include <au1xxx.h> | |
398 | ||
399 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
400 | #define SMC_CAN_USE_8BIT 0 | |
401 | #define SMC_CAN_USE_16BIT 1 | |
402 | #define SMC_CAN_USE_32BIT 0 | |
403 | #define SMC_IO_SHIFT 0 | |
404 | #define SMC_NOWAIT 1 | |
405 | ||
406 | #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) | |
407 | #define SMC_insw(a, r, p, l) \ | |
408 | do { \ | |
409 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
410 | int _l = (l); \ | |
411 | u16 *_p = (u16 *)(p); \ | |
412 | while (_l-- > 0) \ | |
413 | *_p++ = au_readw(_a); \ | |
414 | } while(0) | |
415 | #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) | |
416 | #define SMC_outsw(a, r, p, l) \ | |
417 | do { \ | |
418 | unsigned long _a = (unsigned long)((a) + (r)); \ | |
419 | int _l = (l); \ | |
420 | const u16 *_p = (const u16 *)(p); \ | |
421 | while (_l-- > 0) \ | |
422 | au_writew(*_p++ , _a); \ | |
423 | } while(0) | |
424 | ||
9ded96f2 | 425 | #define SMC_IRQ_FLAGS (0) |
33fee56a DS |
426 | |
427 | #elif defined(CONFIG_ARCH_VERSATILE) | |
428 | ||
429 | #define SMC_CAN_USE_8BIT 1 | |
430 | #define SMC_CAN_USE_16BIT 1 | |
431 | #define SMC_CAN_USE_32BIT 1 | |
432 | #define SMC_NOWAIT 1 | |
433 | ||
434 | #define SMC_inb(a, r) readb((a) + (r)) | |
435 | #define SMC_inw(a, r) readw((a) + (r)) | |
436 | #define SMC_inl(a, r) readl((a) + (r)) | |
437 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
438 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
439 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
440 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
441 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 442 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
55793455 | 443 | |
b920de1b DH |
444 | #elif defined(CONFIG_MN10300) |
445 | ||
446 | /* | |
447 | * MN10300/AM33 configuration | |
448 | */ | |
449 | ||
450 | #include <asm/unit/smc91111.h> | |
451 | ||
1da177e4 LT |
452 | #else |
453 | ||
b920de1b DH |
454 | /* |
455 | * Default configuration | |
456 | */ | |
457 | ||
1da177e4 LT |
458 | #define SMC_CAN_USE_8BIT 1 |
459 | #define SMC_CAN_USE_16BIT 1 | |
460 | #define SMC_CAN_USE_32BIT 1 | |
461 | #define SMC_NOWAIT 1 | |
462 | ||
463 | #define SMC_inb(a, r) readb((a) + (r)) | |
464 | #define SMC_inw(a, r) readw((a) + (r)) | |
465 | #define SMC_inl(a, r) readl((a) + (r)) | |
466 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
467 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
468 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
8a214c12 MD |
469 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
470 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 LT |
471 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
472 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
473 | ||
474 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
475 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
476 | ||
477 | #endif | |
478 | ||
073ac8fd RK |
479 | |
480 | /* store this information for the driver.. */ | |
481 | struct smc_local { | |
482 | /* | |
483 | * If I have to wait until memory is available to send a | |
484 | * packet, I will store the skbuff here, until I get the | |
485 | * desired memory. Then, I'll send it out and free it. | |
486 | */ | |
487 | struct sk_buff *pending_tx_skb; | |
488 | struct tasklet_struct tx_task; | |
489 | ||
490 | /* version/revision of the SMC91x chip */ | |
491 | int version; | |
492 | ||
493 | /* Contains the current active transmission mode */ | |
494 | int tcr_cur_mode; | |
495 | ||
496 | /* Contains the current active receive mode */ | |
497 | int rcr_cur_mode; | |
498 | ||
499 | /* Contains the current active receive/phy mode */ | |
500 | int rpc_cur_mode; | |
501 | int ctl_rfduplx; | |
502 | int ctl_rspeed; | |
503 | ||
504 | u32 msg_enable; | |
505 | u32 phy_type; | |
506 | struct mii_if_info mii; | |
507 | ||
508 | /* work queue */ | |
509 | struct work_struct phy_configure; | |
510 | struct net_device *dev; | |
511 | int work_pending; | |
512 | ||
513 | spinlock_t lock; | |
514 | ||
52256c0e | 515 | #ifdef CONFIG_ARCH_PXA |
073ac8fd RK |
516 | /* DMA needs the physical address of the chip */ |
517 | u_long physaddr; | |
518 | struct device *device; | |
519 | #endif | |
520 | void __iomem *base; | |
521 | void __iomem *datacs; | |
3e947943 | 522 | |
15919886 EM |
523 | /* the low address lines on some platforms aren't connected... */ |
524 | int io_shift; | |
525 | ||
3e947943 | 526 | struct smc91x_platdata cfg; |
073ac8fd RK |
527 | }; |
528 | ||
fa6d3be0 EM |
529 | #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) |
530 | #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) | |
531 | #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) | |
073ac8fd | 532 | |
52256c0e | 533 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
534 | /* |
535 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
536 | * always happening in irq context so no need to worry about races. TX is | |
537 | * different and probably not worth it for that reason, and not as critical | |
538 | * as RX which can overrun memory and lose packets. | |
539 | */ | |
540 | #include <linux/dma-mapping.h> | |
541 | #include <asm/dma.h> | |
542 | #include <asm/arch/pxa-regs.h> | |
543 | ||
544 | #ifdef SMC_insl | |
545 | #undef SMC_insl | |
546 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 547 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
1da177e4 | 548 | static inline void |
073ac8fd | 549 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
550 | u_char *buf, int len) |
551 | { | |
073ac8fd | 552 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
553 | dma_addr_t dmabuf; |
554 | ||
555 | /* fallback if no DMA available */ | |
556 | if (dma == (unsigned char)-1) { | |
557 | readsl(ioaddr + reg, buf, len); | |
558 | return; | |
559 | } | |
560 | ||
561 | /* 64 bit alignment is required for memory to memory DMA */ | |
562 | if ((long)buf & 4) { | |
563 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
564 | buf += 4; | |
565 | len--; | |
566 | } | |
567 | ||
568 | len *= 4; | |
073ac8fd | 569 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
570 | DCSR(dma) = DCSR_NODESC; |
571 | DTADR(dma) = dmabuf; | |
572 | DSADR(dma) = physaddr + reg; | |
573 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
574 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
575 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
576 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
577 | cpu_relax(); | |
578 | DCSR(dma) = 0; | |
073ac8fd | 579 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
580 | } |
581 | #endif | |
582 | ||
583 | #ifdef SMC_insw | |
584 | #undef SMC_insw | |
585 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 586 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 587 | static inline void |
073ac8fd | 588 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
589 | u_char *buf, int len) |
590 | { | |
073ac8fd | 591 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
592 | dma_addr_t dmabuf; |
593 | ||
594 | /* fallback if no DMA available */ | |
595 | if (dma == (unsigned char)-1) { | |
596 | readsw(ioaddr + reg, buf, len); | |
597 | return; | |
598 | } | |
599 | ||
600 | /* 64 bit alignment is required for memory to memory DMA */ | |
601 | while ((long)buf & 6) { | |
602 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
603 | buf += 2; | |
604 | len--; | |
605 | } | |
606 | ||
607 | len *= 2; | |
073ac8fd | 608 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
609 | DCSR(dma) = DCSR_NODESC; |
610 | DTADR(dma) = dmabuf; | |
611 | DSADR(dma) = physaddr + reg; | |
612 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
613 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
614 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
615 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
616 | cpu_relax(); | |
617 | DCSR(dma) = 0; | |
073ac8fd | 618 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
619 | } |
620 | #endif | |
621 | ||
622 | static void | |
7d12e780 | 623 | smc_pxa_dma_irq(int dma, void *dummy) |
1da177e4 LT |
624 | { |
625 | DCSR(dma) = 0; | |
626 | } | |
52256c0e | 627 | #endif /* CONFIG_ARCH_PXA */ |
1da177e4 LT |
628 | |
629 | ||
09779c6d NP |
630 | /* |
631 | * Everything a particular hardware setup needs should have been defined | |
632 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
633 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
634 | * use of them. | |
635 | */ | |
636 | ||
637 | #if ! SMC_CAN_USE_32BIT | |
638 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
639 | #define SMC_outl(x, ioaddr, reg) BUG() | |
640 | #define SMC_insl(a, r, p, l) BUG() | |
641 | #define SMC_outsl(a, r, p, l) BUG() | |
642 | #endif | |
643 | ||
644 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
645 | #define SMC_insl(a, r, p, l) BUG() | |
646 | #define SMC_outsl(a, r, p, l) BUG() | |
647 | #endif | |
648 | ||
649 | #if ! SMC_CAN_USE_16BIT | |
650 | ||
651 | /* | |
652 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
653 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
654 | */ | |
655 | #define SMC_outw(x, ioaddr, reg) \ | |
656 | do { \ | |
657 | unsigned int __val16 = (x); \ | |
658 | SMC_outb( __val16, ioaddr, reg ); \ | |
659 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
660 | } while (0) | |
661 | #define SMC_inw(ioaddr, reg) \ | |
662 | ({ \ | |
663 | unsigned int __val16; \ | |
664 | __val16 = SMC_inb( ioaddr, reg ); \ | |
665 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
666 | __val16; \ | |
667 | }) | |
668 | ||
669 | #define SMC_insw(a, r, p, l) BUG() | |
670 | #define SMC_outsw(a, r, p, l) BUG() | |
671 | ||
672 | #endif | |
673 | ||
674 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
675 | #define SMC_insw(a, r, p, l) BUG() | |
676 | #define SMC_outsw(a, r, p, l) BUG() | |
677 | #endif | |
678 | ||
679 | #if ! SMC_CAN_USE_8BIT | |
680 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
681 | #define SMC_outb(x, ioaddr, reg) BUG() | |
682 | #define SMC_insb(a, r, p, l) BUG() | |
683 | #define SMC_outsb(a, r, p, l) BUG() | |
684 | #endif | |
685 | ||
686 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
687 | #define SMC_insb(a, r, p, l) BUG() | |
688 | #define SMC_outsb(a, r, p, l) BUG() | |
689 | #endif | |
690 | ||
691 | #ifndef SMC_CAN_USE_DATACS | |
692 | #define SMC_CAN_USE_DATACS 0 | |
693 | #endif | |
694 | ||
1da177e4 LT |
695 | #ifndef SMC_IO_SHIFT |
696 | #define SMC_IO_SHIFT 0 | |
697 | #endif | |
09779c6d NP |
698 | |
699 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 700 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
701 | #endif |
702 | ||
703 | #ifndef SMC_INTERRUPT_PREAMBLE | |
704 | #define SMC_INTERRUPT_PREAMBLE | |
705 | #endif | |
706 | ||
707 | ||
708 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
709 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
710 | #define SMC_DATA_EXTENT (4) | |
711 | ||
712 | /* | |
713 | . Bank Select Register: | |
714 | . | |
715 | . yyyy yyyy 0000 00xx | |
716 | . xx = bank number | |
717 | . yyyy yyyy = 0x33, for identification purposes. | |
718 | */ | |
719 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
720 | ||
721 | ||
722 | // Transmit Control Register | |
723 | /* BANK 0 */ | |
cfdfa865 | 724 | #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) |
1da177e4 LT |
725 | #define TCR_ENABLE 0x0001 // When 1 we can transmit |
726 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
727 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
728 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
729 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
730 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
731 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
732 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
733 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
734 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
735 | ||
736 | #define TCR_CLEAR 0 /* do NOTHING */ | |
737 | /* the default settings for the TCR register : */ | |
738 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
739 | ||
740 | ||
741 | // EPH Status Register | |
742 | /* BANK 0 */ | |
cfdfa865 | 743 | #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) |
1da177e4 LT |
744 | #define ES_TX_SUC 0x0001 // Last TX was successful |
745 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
746 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
747 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
748 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
749 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
750 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
751 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
752 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
753 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
754 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
755 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
756 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
757 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
758 | ||
759 | ||
760 | // Receive Control Register | |
761 | /* BANK 0 */ | |
cfdfa865 | 762 | #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) |
1da177e4 LT |
763 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted |
764 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
765 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
766 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
767 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
768 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
769 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
770 | #define RCR_SOFTRST 0x8000 // resets the chip | |
771 | ||
772 | /* the normal settings for the RCR register : */ | |
773 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
774 | #define RCR_CLEAR 0x0 // set it to a base state | |
775 | ||
776 | ||
777 | // Counter Register | |
778 | /* BANK 0 */ | |
cfdfa865 | 779 | #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) |
1da177e4 LT |
780 | |
781 | ||
782 | // Memory Information Register | |
783 | /* BANK 0 */ | |
cfdfa865 | 784 | #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) |
1da177e4 LT |
785 | |
786 | ||
787 | // Receive/Phy Control Register | |
788 | /* BANK 0 */ | |
cfdfa865 | 789 | #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) |
1da177e4 LT |
790 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. |
791 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
792 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
793 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
794 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
795 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
796 | #define RPC_LED_RES (0x01) // LED = Reserved | |
797 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
798 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
799 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
800 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
801 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
802 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
803 | ||
804 | #ifndef RPC_LSA_DEFAULT | |
805 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
806 | #endif | |
807 | #ifndef RPC_LSB_DEFAULT | |
808 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
809 | #endif | |
810 | ||
811 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
812 | ||
813 | ||
814 | /* Bank 0 0x0C is reserved */ | |
815 | ||
816 | // Bank Select Register | |
817 | /* All Banks */ | |
818 | #define BSR_REG 0x000E | |
819 | ||
820 | ||
821 | // Configuration Reg | |
822 | /* BANK 1 */ | |
cfdfa865 | 823 | #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) |
1da177e4 LT |
824 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy |
825 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
826 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
827 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
828 | ||
829 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
830 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
831 | ||
832 | ||
833 | // Base Address Register | |
834 | /* BANK 1 */ | |
cfdfa865 | 835 | #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) |
1da177e4 LT |
836 | |
837 | ||
838 | // Individual Address Registers | |
839 | /* BANK 1 */ | |
cfdfa865 MD |
840 | #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) |
841 | #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) | |
842 | #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) | |
1da177e4 LT |
843 | |
844 | ||
845 | // General Purpose Register | |
846 | /* BANK 1 */ | |
cfdfa865 | 847 | #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) |
1da177e4 LT |
848 | |
849 | ||
850 | // Control Register | |
851 | /* BANK 1 */ | |
cfdfa865 | 852 | #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) |
1da177e4 LT |
853 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received |
854 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
855 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
856 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
857 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
858 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
859 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
860 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
861 | ||
862 | ||
863 | // MMU Command Register | |
864 | /* BANK 2 */ | |
cfdfa865 | 865 | #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) |
1da177e4 LT |
866 | #define MC_BUSY 1 // When 1 the last release has not completed |
867 | #define MC_NOP (0<<5) // No Op | |
868 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
869 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
870 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
871 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
872 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
873 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
874 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
875 | ||
876 | ||
877 | // Packet Number Register | |
878 | /* BANK 2 */ | |
cfdfa865 | 879 | #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) |
1da177e4 LT |
880 | |
881 | ||
882 | // Allocation Result Register | |
883 | /* BANK 2 */ | |
cfdfa865 | 884 | #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) |
1da177e4 LT |
885 | #define AR_FAILED 0x80 // Alocation Failed |
886 | ||
887 | ||
888 | // TX FIFO Ports Register | |
889 | /* BANK 2 */ | |
cfdfa865 | 890 | #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
891 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty |
892 | ||
893 | // RX FIFO Ports Register | |
894 | /* BANK 2 */ | |
cfdfa865 | 895 | #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) |
1da177e4 LT |
896 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty |
897 | ||
cfdfa865 | 898 | #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
899 | |
900 | // Pointer Register | |
901 | /* BANK 2 */ | |
cfdfa865 | 902 | #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) |
1da177e4 LT |
903 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area |
904 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
905 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
906 | ||
907 | ||
908 | // Data Register | |
909 | /* BANK 2 */ | |
cfdfa865 | 910 | #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) |
1da177e4 LT |
911 | |
912 | ||
913 | // Interrupt Status/Acknowledge Register | |
914 | /* BANK 2 */ | |
cfdfa865 | 915 | #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) |
1da177e4 LT |
916 | |
917 | ||
918 | // Interrupt Mask Register | |
919 | /* BANK 2 */ | |
cfdfa865 | 920 | #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) |
1da177e4 LT |
921 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt |
922 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
923 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
924 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
925 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
926 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
927 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
928 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
929 | ||
930 | ||
931 | // Multicast Table Registers | |
932 | /* BANK 3 */ | |
cfdfa865 MD |
933 | #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) |
934 | #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) | |
935 | #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) | |
936 | #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) | |
1da177e4 LT |
937 | |
938 | ||
939 | // Management Interface Register (MII) | |
940 | /* BANK 3 */ | |
cfdfa865 | 941 | #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) |
1da177e4 LT |
942 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup |
943 | #define MII_MDOE 0x0008 // MII Output Enable | |
944 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
945 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
946 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
947 | ||
948 | ||
949 | // Revision Register | |
950 | /* BANK 3 */ | |
951 | /* ( hi: chip id low: rev # ) */ | |
cfdfa865 | 952 | #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) |
1da177e4 LT |
953 | |
954 | ||
955 | // Early RCV Register | |
956 | /* BANK 3 */ | |
957 | /* this is NOT on SMC9192 */ | |
cfdfa865 | 958 | #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) |
1da177e4 LT |
959 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received |
960 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
961 | ||
962 | ||
963 | // External Register | |
964 | /* BANK 7 */ | |
cfdfa865 | 965 | #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) |
1da177e4 LT |
966 | |
967 | ||
968 | #define CHIP_9192 3 | |
969 | #define CHIP_9194 4 | |
970 | #define CHIP_9195 5 | |
971 | #define CHIP_9196 6 | |
972 | #define CHIP_91100 7 | |
973 | #define CHIP_91100FD 8 | |
974 | #define CHIP_91111FD 9 | |
975 | ||
976 | static const char * chip_ids[ 16 ] = { | |
977 | NULL, NULL, NULL, | |
978 | /* 3 */ "SMC91C90/91C92", | |
979 | /* 4 */ "SMC91C94", | |
980 | /* 5 */ "SMC91C95", | |
981 | /* 6 */ "SMC91C96", | |
982 | /* 7 */ "SMC91C100", | |
983 | /* 8 */ "SMC91C100FD", | |
984 | /* 9 */ "SMC91C11xFD", | |
985 | NULL, NULL, NULL, | |
986 | NULL, NULL, NULL}; | |
987 | ||
988 | ||
1da177e4 LT |
989 | /* |
990 | . Receive status bits | |
991 | */ | |
992 | #define RS_ALGNERR 0x8000 | |
993 | #define RS_BRODCAST 0x4000 | |
994 | #define RS_BADCRC 0x2000 | |
995 | #define RS_ODDFRAME 0x1000 | |
996 | #define RS_TOOLONG 0x0800 | |
997 | #define RS_TOOSHORT 0x0400 | |
998 | #define RS_MULTICAST 0x0001 | |
999 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
1000 | ||
1001 | ||
1002 | /* | |
1003 | * PHY IDs | |
1004 | * LAN83C183 == LAN91C111 Internal PHY | |
1005 | */ | |
1006 | #define PHY_LAN83C183 0x0016f840 | |
1007 | #define PHY_LAN83C180 0x02821c50 | |
1008 | ||
1009 | /* | |
1010 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
1011 | * | |
1012 | * Generic PHY registers can be found in <linux/mii.h> | |
1013 | * | |
1014 | * These phy registers are specific to our on-board phy. | |
1015 | */ | |
1016 | ||
1017 | // PHY Configuration Register 1 | |
1018 | #define PHY_CFG1_REG 0x10 | |
1019 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
1020 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
1021 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
1022 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
1023 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
1024 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
1025 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
1026 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
1027 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
1028 | #define PHY_CFG1_TLVL_MASK 0x003C | |
1029 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
1030 | ||
1031 | ||
1032 | // PHY Configuration Register 2 | |
1033 | #define PHY_CFG2_REG 0x11 | |
1034 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
1035 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
1036 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
1037 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
1038 | ||
1039 | // PHY Status Output (and Interrupt status) Register | |
1040 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
1041 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
1042 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
1043 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
1044 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
1045 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
1046 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
1047 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
1048 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
1049 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
1050 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
1051 | ||
1052 | // PHY Interrupt/Status Mask Register | |
1053 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
1054 | // Uses the same bit definitions as PHY_INT_REG | |
1055 | ||
1056 | ||
1057 | /* | |
1058 | * SMC91C96 ethernet config and status registers. | |
1059 | * These are in the "attribute" space. | |
1060 | */ | |
1061 | #define ECOR 0x8000 | |
1062 | #define ECOR_RESET 0x80 | |
1063 | #define ECOR_LEVEL_IRQ 0x40 | |
1064 | #define ECOR_WR_ATTRIB 0x04 | |
1065 | #define ECOR_ENABLE 0x01 | |
1066 | ||
1067 | #define ECSR 0x8002 | |
1068 | #define ECSR_IOIS8 0x20 | |
1069 | #define ECSR_PWRDWN 0x04 | |
1070 | #define ECSR_INT 0x02 | |
1071 | ||
1072 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
1073 | ||
1074 | ||
1075 | /* | |
1076 | * Macros to abstract register access according to the data bus | |
1077 | * capabilities. Please use those and not the in/out primitives. | |
1078 | * Note: the following macros do *not* select the bank -- this must | |
1079 | * be done separately as needed in the main code. The SMC_REG() macro | |
1080 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
1081 | * |
1082 | * Note: despite inline functions being safer, everything leading to this | |
1083 | * should preferably be macros to let BUG() display the line number in | |
1084 | * the core source code since we're interested in the top call site | |
1085 | * not in any inline function location. | |
1da177e4 LT |
1086 | */ |
1087 | ||
1088 | #if SMC_DEBUG > 0 | |
cfdfa865 | 1089 | #define SMC_REG(lp, reg, bank) \ |
1da177e4 | 1090 | ({ \ |
cfdfa865 | 1091 | int __b = SMC_CURRENT_BANK(lp); \ |
1da177e4 LT |
1092 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ |
1093 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
1094 | CARDNAME, __b ); \ | |
1095 | BUG(); \ | |
1096 | } \ | |
1097 | reg<<SMC_IO_SHIFT; \ | |
1098 | }) | |
1099 | #else | |
cfdfa865 | 1100 | #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) |
1da177e4 LT |
1101 | #endif |
1102 | ||
09779c6d NP |
1103 | /* |
1104 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
1105 | * aligned to a 32 bit boundary. I tell you that does exist! | |
1106 | * Fortunately the affected register accesses can be easily worked around | |
1107 | * since we can write zeroes to the preceeding 16 bits without adverse | |
1108 | * effects and use a 32-bit access. | |
1109 | * | |
1110 | * Enforce it on any 32-bit capable setup for now. | |
1111 | */ | |
3e947943 | 1112 | #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) |
09779c6d | 1113 | |
cfdfa865 | 1114 | #define SMC_GET_PN(lp) \ |
3e947943 | 1115 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ |
cfdfa865 | 1116 | : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) |
09779c6d | 1117 | |
cfdfa865 | 1118 | #define SMC_SET_PN(lp, x) \ |
09779c6d | 1119 | do { \ |
3e947943 | 1120 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1121 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ |
3e947943 | 1122 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1123 | SMC_outb(x, ioaddr, PN_REG(lp)); \ |
09779c6d | 1124 | else \ |
cfdfa865 | 1125 | SMC_outw(x, ioaddr, PN_REG(lp)); \ |
09779c6d NP |
1126 | } while (0) |
1127 | ||
cfdfa865 | 1128 | #define SMC_GET_AR(lp) \ |
3e947943 | 1129 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ |
cfdfa865 | 1130 | : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) |
09779c6d | 1131 | |
cfdfa865 | 1132 | #define SMC_GET_TXFIFO(lp) \ |
3e947943 | 1133 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ |
cfdfa865 | 1134 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) |
09779c6d | 1135 | |
cfdfa865 | 1136 | #define SMC_GET_RXFIFO(lp) \ |
3e947943 | 1137 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ |
cfdfa865 | 1138 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) |
09779c6d | 1139 | |
cfdfa865 | 1140 | #define SMC_GET_INT(lp) \ |
3e947943 | 1141 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ |
cfdfa865 | 1142 | : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) |
09779c6d | 1143 | |
cfdfa865 | 1144 | #define SMC_ACK_INT(lp, x) \ |
1da177e4 | 1145 | do { \ |
3e947943 | 1146 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 1147 | SMC_outb(x, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
1148 | else { \ |
1149 | unsigned long __flags; \ | |
1150 | int __mask; \ | |
1151 | local_irq_save(__flags); \ | |
cfdfa865 MD |
1152 | __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ |
1153 | SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ | |
09779c6d NP |
1154 | local_irq_restore(__flags); \ |
1155 | } \ | |
1156 | } while (0) | |
1157 | ||
cfdfa865 | 1158 | #define SMC_GET_INT_MASK(lp) \ |
3e947943 | 1159 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ |
cfdfa865 | 1160 | : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) |
09779c6d | 1161 | |
cfdfa865 | 1162 | #define SMC_SET_INT_MASK(lp, x) \ |
09779c6d | 1163 | do { \ |
3e947943 | 1164 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 1165 | SMC_outb(x, ioaddr, IM_REG(lp)); \ |
09779c6d | 1166 | else \ |
cfdfa865 | 1167 | SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
1168 | } while (0) |
1169 | ||
cfdfa865 | 1170 | #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) |
09779c6d | 1171 | |
cfdfa865 | 1172 | #define SMC_SELECT_BANK(lp, x) \ |
09779c6d | 1173 | do { \ |
3e947943 | 1174 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
09779c6d NP |
1175 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ |
1176 | else \ | |
1177 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
1178 | } while (0) | |
1179 | ||
cfdfa865 | 1180 | #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) |
09779c6d | 1181 | |
cfdfa865 | 1182 | #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) |
09779c6d | 1183 | |
cfdfa865 | 1184 | #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) |
09779c6d | 1185 | |
cfdfa865 | 1186 | #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) |
09779c6d | 1187 | |
cfdfa865 | 1188 | #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) |
09779c6d | 1189 | |
cfdfa865 | 1190 | #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) |
09779c6d | 1191 | |
cfdfa865 | 1192 | #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) |
09779c6d | 1193 | |
cfdfa865 | 1194 | #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) |
09779c6d | 1195 | |
cfdfa865 | 1196 | #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) |
09779c6d | 1197 | |
cfdfa865 | 1198 | #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) |
09779c6d | 1199 | |
cfdfa865 | 1200 | #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) |
09779c6d | 1201 | |
cfdfa865 | 1202 | #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1203 | |
cfdfa865 | 1204 | #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1205 | |
cfdfa865 | 1206 | #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) |
09779c6d | 1207 | |
cfdfa865 | 1208 | #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) |
09779c6d | 1209 | |
cfdfa865 | 1210 | #define SMC_SET_PTR(lp, x) \ |
09779c6d | 1211 | do { \ |
3e947943 | 1212 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1213 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ |
09779c6d | 1214 | else \ |
cfdfa865 | 1215 | SMC_outw(x, ioaddr, PTR_REG(lp)); \ |
1da177e4 | 1216 | } while (0) |
1da177e4 | 1217 | |
cfdfa865 | 1218 | #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) |
09779c6d | 1219 | |
cfdfa865 | 1220 | #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) |
09779c6d | 1221 | |
cfdfa865 | 1222 | #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) |
09779c6d | 1223 | |
cfdfa865 | 1224 | #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) |
09779c6d | 1225 | |
cfdfa865 | 1226 | #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) |
09779c6d | 1227 | |
cfdfa865 | 1228 | #define SMC_SET_RPC(lp, x) \ |
09779c6d | 1229 | do { \ |
3e947943 | 1230 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1231 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ |
09779c6d | 1232 | else \ |
cfdfa865 | 1233 | SMC_outw(x, ioaddr, RPC_REG(lp)); \ |
09779c6d NP |
1234 | } while (0) |
1235 | ||
cfdfa865 | 1236 | #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) |
09779c6d | 1237 | |
cfdfa865 | 1238 | #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) |
1da177e4 LT |
1239 | |
1240 | #ifndef SMC_GET_MAC_ADDR | |
cfdfa865 | 1241 | #define SMC_GET_MAC_ADDR(lp, addr) \ |
1da177e4 LT |
1242 | do { \ |
1243 | unsigned int __v; \ | |
cfdfa865 | 1244 | __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ |
1da177e4 | 1245 | addr[0] = __v; addr[1] = __v >> 8; \ |
cfdfa865 | 1246 | __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ |
1da177e4 | 1247 | addr[2] = __v; addr[3] = __v >> 8; \ |
cfdfa865 | 1248 | __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ |
1da177e4 LT |
1249 | addr[4] = __v; addr[5] = __v >> 8; \ |
1250 | } while (0) | |
1251 | #endif | |
1252 | ||
cfdfa865 | 1253 | #define SMC_SET_MAC_ADDR(lp, addr) \ |
1da177e4 | 1254 | do { \ |
cfdfa865 MD |
1255 | SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ |
1256 | SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ | |
1257 | SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ | |
1da177e4 LT |
1258 | } while (0) |
1259 | ||
cfdfa865 | 1260 | #define SMC_SET_MCAST(lp, x) \ |
1da177e4 LT |
1261 | do { \ |
1262 | const unsigned char *mt = (x); \ | |
cfdfa865 MD |
1263 | SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ |
1264 | SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ | |
1265 | SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ | |
1266 | SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ | |
1da177e4 LT |
1267 | } while (0) |
1268 | ||
cfdfa865 | 1269 | #define SMC_PUT_PKT_HDR(lp, status, length) \ |
1da177e4 | 1270 | do { \ |
3e947943 | 1271 | if (SMC_32BIT(lp)) \ |
cfdfa865 MD |
1272 | SMC_outl((status) | (length)<<16, ioaddr, \ |
1273 | DATA_REG(lp)); \ | |
09779c6d | 1274 | else { \ |
cfdfa865 MD |
1275 | SMC_outw(status, ioaddr, DATA_REG(lp)); \ |
1276 | SMC_outw(length, ioaddr, DATA_REG(lp)); \ | |
09779c6d | 1277 | } \ |
1da177e4 | 1278 | } while (0) |
1da177e4 | 1279 | |
cfdfa865 | 1280 | #define SMC_GET_PKT_HDR(lp, status, length) \ |
1da177e4 | 1281 | do { \ |
3e947943 | 1282 | if (SMC_32BIT(lp)) { \ |
cfdfa865 | 1283 | unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ |
09779c6d NP |
1284 | (status) = __val & 0xffff; \ |
1285 | (length) = __val >> 16; \ | |
1286 | } else { \ | |
cfdfa865 MD |
1287 | (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ |
1288 | (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ | |
1da177e4 LT |
1289 | } \ |
1290 | } while (0) | |
1da177e4 | 1291 | |
cfdfa865 | 1292 | #define SMC_PUSH_DATA(lp, p, l) \ |
1da177e4 | 1293 | do { \ |
3e947943 | 1294 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1295 | void *__ptr = (p); \ |
1296 | int __len = (l); \ | |
fbd81976 | 1297 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1298 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1299 | __len -= 2; \ | |
cfdfa865 MD |
1300 | SMC_outw(*(u16 *)__ptr, ioaddr, \ |
1301 | DATA_REG(lp)); \ | |
09779c6d NP |
1302 | __ptr += 2; \ |
1303 | } \ | |
1304 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1305 | __ioaddr = lp->datacs; \ | |
cfdfa865 | 1306 | SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
09779c6d NP |
1307 | if (__len & 2) { \ |
1308 | __ptr += (__len & ~3); \ | |
cfdfa865 MD |
1309 | SMC_outw(*((u16 *)__ptr), ioaddr, \ |
1310 | DATA_REG(lp)); \ | |
09779c6d | 1311 | } \ |
3e947943 | 1312 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1313 | SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1314 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1315 | SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ |
1da177e4 | 1316 | } while (0) |
1da177e4 | 1317 | |
cfdfa865 | 1318 | #define SMC_PULL_DATA(lp, p, l) \ |
09779c6d | 1319 | do { \ |
3e947943 | 1320 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1321 | void *__ptr = (p); \ |
1322 | int __len = (l); \ | |
fbd81976 | 1323 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1324 | if ((unsigned long)__ptr & 2) { \ |
1325 | /* \ | |
1326 | * We want 32bit alignment here. \ | |
1327 | * Since some buses perform a full \ | |
1328 | * 32bit fetch even for 16bit data \ | |
1329 | * we can't use SMC_inw() here. \ | |
1330 | * Back both source (on-chip) and \ | |
1331 | * destination pointers of 2 bytes. \ | |
1332 | * This is possible since the call to \ | |
1333 | * SMC_GET_PKT_HDR() already advanced \ | |
1334 | * the source pointer of 4 bytes, and \ | |
1335 | * the skb_reserve(skb, 2) advanced \ | |
1336 | * the destination pointer of 2 bytes. \ | |
1337 | */ \ | |
1338 | __ptr -= 2; \ | |
1339 | __len += 2; \ | |
cfdfa865 MD |
1340 | SMC_SET_PTR(lp, \ |
1341 | 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
09779c6d NP |
1342 | } \ |
1343 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1344 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1345 | __len += 2; \ |
cfdfa865 | 1346 | SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
3e947943 | 1347 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1348 | SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1349 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1350 | SMC_insb(ioaddr, DATA_REG(lp), p, l); \ |
09779c6d | 1351 | } while (0) |
1da177e4 LT |
1352 | |
1353 | #endif /* _SMC91X_H_ */ |