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[PATCH] irq-flags: drivers/net: Use the new IRQF_ constants
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / smc91x.h
CommitLineData
1da177e4
LT		 1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
37
38/*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42#if defined(CONFIG_ARCH_LUBBOCK)
43
44/* We can only do 16-bit reads and writes in the static memory space. */
45#define SMC_CAN_USE_8BIT 0
46#define SMC_CAN_USE_16BIT 1
47#define SMC_CAN_USE_32BIT 0
48#define SMC_NOWAIT 1
49
50/* The first two address lines aren't connected... */
51#define SMC_IO_SHIFT 2
52
53#define SMC_inw(a, r) readw((a) + (r))
54#define SMC_outw(v, a, r) writew(v, (a) + (r))
55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60/* We can only do 16-bit reads and writes in the static memory space. */
61#define SMC_CAN_USE_8BIT 0
62#define SMC_CAN_USE_16BIT 1
63#define SMC_CAN_USE_32BIT 0
64#define SMC_NOWAIT 1
65
66#define SMC_IO_SHIFT 0
67
68#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70#define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82#define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
9ded96f2 93#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 94
95#elif defined(CONFIG_SA1100_PLEB)
96/* We can only do 16-bit reads and writes in the static memory space. */
97#define SMC_CAN_USE_8BIT 1
98#define SMC_CAN_USE_16BIT 1
99#define SMC_CAN_USE_32BIT 0
100#define SMC_IO_SHIFT 0
101#define SMC_NOWAIT 1
102
1cf99be5
RK		 103#define SMC_inb(a, r) readb((a) + (r))
104#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105#define SMC_inw(a, r) readw((a) + (r))
106#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107#define SMC_outb(v, a, r) writeb(v, (a) + (r))
108#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109#define SMC_outw(v, a, r) writew(v, (a) + (r))
110#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
1da177e4 111
9ded96f2 112#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 113
114#elif defined(CONFIG_SA1100_ASSABET)
115
116#include <asm/arch/neponset.h>
117
118/* We can only do 8-bit reads and writes in the static memory space. */
119#define SMC_CAN_USE_8BIT 1
120#define SMC_CAN_USE_16BIT 0
121#define SMC_CAN_USE_32BIT 0
122#define SMC_NOWAIT 1
123
124/* The first two address lines aren't connected... */
125#define SMC_IO_SHIFT 2
126
127#define SMC_inb(a, r) readb((a) + (r))
128#define SMC_outb(v, a, r) writeb(v, (a) + (r))
129#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
b0348b90
LB		 132#elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134#define SMC_CAN_USE_8BIT 0
135#define SMC_CAN_USE_16BIT 1
136#define SMC_CAN_USE_32BIT 0
137#define SMC_IO_SHIFT 0
138#define SMC_NOWAIT 1
139#define SMC_USE_PXA_DMA 1
140
141#define SMC_inb(a, r) readb((a) + (r))
142#define SMC_inw(a, r) readw((a) + (r))
143#define SMC_inl(a, r) readl((a) + (r))
144#define SMC_outb(v, a, r) writeb(v, (a) + (r))
145#define SMC_outw(v, a, r) writew(v, (a) + (r))
146#define SMC_outl(v, a, r) writel(v, (a) + (r))
147#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
148#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
149
1da177e4
LT		 150#elif defined(CONFIG_ARCH_INNOKOM) || \
151 defined(CONFIG_MACH_MAINSTONE) || \
152 defined(CONFIG_ARCH_PXA_IDP) || \
153 defined(CONFIG_ARCH_RAMSES)
154
155#define SMC_CAN_USE_8BIT 1
156#define SMC_CAN_USE_16BIT 1
157#define SMC_CAN_USE_32BIT 1
158#define SMC_IO_SHIFT 0
159#define SMC_NOWAIT 1
160#define SMC_USE_PXA_DMA 1
161
162#define SMC_inb(a, r) readb((a) + (r))
163#define SMC_inw(a, r) readw((a) + (r))
164#define SMC_inl(a, r) readl((a) + (r))
165#define SMC_outb(v, a, r) writeb(v, (a) + (r))
166#define SMC_outl(v, a, r) writel(v, (a) + (r))
167#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
168#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
169
170/* We actually can't write halfwords properly if not word aligned */
171static inline void
eb1d6988 172SMC_outw(u16 val, void __iomem *ioaddr, int reg)
1da177e4
LT		 173{
174 if (reg & 2) {
175 unsigned int v = val << 16;
176 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
177 writel(v, ioaddr + (reg & ~2));
178 } else {
179 writew(val, ioaddr + reg);
180 }
181}
182
183#elif defined(CONFIG_ARCH_OMAP)
184
185/* We can only do 16-bit reads and writes in the static memory space. */
186#define SMC_CAN_USE_8BIT 0
187#define SMC_CAN_USE_16BIT 1
188#define SMC_CAN_USE_32BIT 0
189#define SMC_IO_SHIFT 0
190#define SMC_NOWAIT 1
191
192#define SMC_inb(a, r) readb((a) + (r))
193#define SMC_outb(v, a, r) writeb(v, (a) + (r))
194#define SMC_inw(a, r) readw((a) + (r))
195#define SMC_outw(v, a, r) writew(v, (a) + (r))
196#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
197#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
198#define SMC_inl(a, r) readl((a) + (r))
199#define SMC_outl(v, a, r) writel(v, (a) + (r))
200#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
201#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
202
5f13e7ec
DB		 203#include <asm/mach-types.h>
204#include <asm/arch/cpu.h>
205
9ded96f2 206#define SMC_IRQ_FLAGS (( \
5f13e7ec
DB		 207 machine_is_omap_h2() \
208 || machine_is_omap_h3() \
af44f5bf 209 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
1fb9df5d 210 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
5f13e7ec
DB		 211
212
1da177e4
LT		 213#elif defined(CONFIG_SH_SH4202_MICRODEV)
214
215#define SMC_CAN_USE_8BIT 0
216#define SMC_CAN_USE_16BIT 1
217#define SMC_CAN_USE_32BIT 0
218
219#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
220#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
221#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
222#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
223#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
224#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
225#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
226#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
227#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
228#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
229
9ded96f2 230#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 231
232#elif defined(CONFIG_ISA)
233
234#define SMC_CAN_USE_8BIT 1
235#define SMC_CAN_USE_16BIT 1
236#define SMC_CAN_USE_32BIT 0
237
238#define SMC_inb(a, r) inb((a) + (r))
239#define SMC_inw(a, r) inw((a) + (r))
240#define SMC_outb(v, a, r) outb(v, (a) + (r))
241#define SMC_outw(v, a, r) outw(v, (a) + (r))
242#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244
245#elif defined(CONFIG_M32R)
246
247#define SMC_CAN_USE_8BIT 0
248#define SMC_CAN_USE_16BIT 1
249#define SMC_CAN_USE_32BIT 0
250
f3ac9fbf
HT		 251#define SMC_inb(a, r) inb((u32)a) + (r))
252#define SMC_inw(a, r) inw(((u32)a) + (r))
253#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
254#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
255#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
256#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
1da177e4 257
9ded96f2 258#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 259
260#define RPC_LSA_DEFAULT RPC_LED_TX_RX
261#define RPC_LSB_DEFAULT RPC_LED_100_10
262
d4adcffb
MS		 263#elif defined(CONFIG_MACH_LPD79520) \
264 || defined(CONFIG_MACH_LPD7A400) \
265 || defined(CONFIG_MACH_LPD7A404)
1da177e4 266
d4adcffb
MS		 267/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
268 * way that the CPU handles chip selects and the way that the SMC chip
269 * expects the chip select to operate. Refer to
1da177e4 270 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
d4adcffb
MS		 271 * IOBARRIER is a byte, in order that we read the least-common
272 * denominator. It would be wasteful to read 32 bits from an 8-bit
273 * accessible region.
1da177e4
LT		 274 *
275 * There is no explicit protection against interrupts intervening
276 * between the writew and the IOBARRIER. In SMC ISR there is a
277 * preamble that performs an IOBARRIER in the extremely unlikely event
278 * that the driver interrupts itself between a writew to the chip an
279 * the IOBARRIER that follows *and* the cache is large enough that the
280 * first off-chip access while handing the interrupt is to the SMC
281 * chip. Other devices in the same address space as the SMC chip must
282 * be aware of the potential for trouble and perform a similar
283 * IOBARRIER on entry to their ISR.
284 */
285
286#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
287
288#define SMC_CAN_USE_8BIT 0
289#define SMC_CAN_USE_16BIT 1
290#define SMC_CAN_USE_32BIT 0
291#define SMC_NOWAIT 0
d4adcffb 292#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
1da177e4 293
d4adcffb
MS		 294#define SMC_inw(a,r)\
295 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
296#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
1da177e4 297
d4adcffb
MS		 298#define SMC_insw LPD7_SMC_insw
299static inline void LPD7_SMC_insw (unsigned char* a, int r,
300 unsigned char* p, int l)
301{
302 unsigned short* ps = (unsigned short*) p;
303 while (l-- > 0) {
304 *ps++ = readw (a + r);
305 LPD7X_IOBARRIER;
306 }
307}
09779c6d 308
d4adcffb
MS		 309#define SMC_outsw LPD7_SMC_outsw
310static inline void LPD7_SMC_outsw (unsigned char* a, int r,
311 unsigned char* p, int l)
1da177e4
LT		 312{
313 unsigned short* ps = (unsigned short*) p;
314 while (l-- > 0) {
315 writew (*ps++, a + r);
d4adcffb 316 LPD7X_IOBARRIER;
1da177e4
LT		 317 }
318}
319
d4adcffb 320#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
1da177e4
LT		 321
322#define RPC_LSA_DEFAULT RPC_LED_TX_RX
323#define RPC_LSB_DEFAULT RPC_LED_100_10
324
55793455
PP		 325#elif defined(CONFIG_SOC_AU1X00)
326
327#include <au1xxx.h>
328
329/* We can only do 16-bit reads and writes in the static memory space. */
330#define SMC_CAN_USE_8BIT 0
331#define SMC_CAN_USE_16BIT 1
332#define SMC_CAN_USE_32BIT 0
333#define SMC_IO_SHIFT 0
334#define SMC_NOWAIT 1
335
336#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
337#define SMC_insw(a, r, p, l) \
338 do { \
339 unsigned long _a = (unsigned long)((a) + (r)); \
340 int _l = (l); \
341 u16 *_p = (u16 *)(p); \
342 while (_l-- > 0) \
343 *_p++ = au_readw(_a); \
344 } while(0)
345#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
346#define SMC_outsw(a, r, p, l) \
347 do { \
348 unsigned long _a = (unsigned long)((a) + (r)); \
349 int _l = (l); \
350 const u16 *_p = (const u16 *)(p); \
351 while (_l-- > 0) \
352 au_writew(*_p++ , _a); \
353 } while(0)
354
9ded96f2 355#define SMC_IRQ_FLAGS (0)
55793455 356
1da177e4
LT		 357#else
358
359#define SMC_CAN_USE_8BIT 1
360#define SMC_CAN_USE_16BIT 1
361#define SMC_CAN_USE_32BIT 1
362#define SMC_NOWAIT 1
363
364#define SMC_inb(a, r) readb((a) + (r))
365#define SMC_inw(a, r) readw((a) + (r))
366#define SMC_inl(a, r) readl((a) + (r))
367#define SMC_outb(v, a, r) writeb(v, (a) + (r))
368#define SMC_outw(v, a, r) writew(v, (a) + (r))
369#define SMC_outl(v, a, r) writel(v, (a) + (r))
370#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
371#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
372
373#define RPC_LSA_DEFAULT RPC_LED_100_10
374#define RPC_LSB_DEFAULT RPC_LED_TX_RX
375
376#endif
377
1da177e4
LT		 378#ifdef SMC_USE_PXA_DMA
379/*
380 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
381 * always happening in irq context so no need to worry about races. TX is
382 * different and probably not worth it for that reason, and not as critical
383 * as RX which can overrun memory and lose packets.
384 */
385#include <linux/dma-mapping.h>
386#include <asm/dma.h>
387#include <asm/arch/pxa-regs.h>
388
389#ifdef SMC_insl
390#undef SMC_insl
391#define SMC_insl(a, r, p, l) \
392 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
393static inline void
eb1d6988 394smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 395 u_char *buf, int len)
396{
397 dma_addr_t dmabuf;
398
399 /* fallback if no DMA available */
400 if (dma == (unsigned char)-1) {
401 readsl(ioaddr + reg, buf, len);
402 return;
403 }
404
405 /* 64 bit alignment is required for memory to memory DMA */
406 if ((long)buf & 4) {
407 *((u32 *)buf) = SMC_inl(ioaddr, reg);
408 buf += 4;
409 len--;
410 }
411
412 len *= 4;
413 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
414 DCSR(dma) = DCSR_NODESC;
415 DTADR(dma) = dmabuf;
416 DSADR(dma) = physaddr + reg;
417 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
418 DCMD_WIDTH4 | (DCMD_LENGTH & len));
419 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
420 while (!(DCSR(dma) & DCSR_STOPSTATE))
421 cpu_relax();
422 DCSR(dma) = 0;
423 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
424}
425#endif
426
427#ifdef SMC_insw
428#undef SMC_insw
429#define SMC_insw(a, r, p, l) \
430 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
431static inline void
eb1d6988 432smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 433 u_char *buf, int len)
434{
435 dma_addr_t dmabuf;
436
437 /* fallback if no DMA available */
438 if (dma == (unsigned char)-1) {
439 readsw(ioaddr + reg, buf, len);
440 return;
441 }
442
443 /* 64 bit alignment is required for memory to memory DMA */
444 while ((long)buf & 6) {
445 *((u16 *)buf) = SMC_inw(ioaddr, reg);
446 buf += 2;
447 len--;
448 }
449
450 len *= 2;
451 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
452 DCSR(dma) = DCSR_NODESC;
453 DTADR(dma) = dmabuf;
454 DSADR(dma) = physaddr + reg;
455 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
456 DCMD_WIDTH2 | (DCMD_LENGTH & len));
457 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
458 while (!(DCSR(dma) & DCSR_STOPSTATE))
459 cpu_relax();
460 DCSR(dma) = 0;
461 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
462}
463#endif
464
465static void
466smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
467{
468 DCSR(dma) = 0;
469}
470#endif /* SMC_USE_PXA_DMA */
471
472
09779c6d
NP		 473/*
474 * Everything a particular hardware setup needs should have been defined
475 * at this point. Add stubs for the undefined cases, mainly to avoid
476 * compilation warnings since they'll be optimized away, or to prevent buggy
477 * use of them.
478 */
479
480#if ! SMC_CAN_USE_32BIT
481#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
482#define SMC_outl(x, ioaddr, reg) BUG()
483#define SMC_insl(a, r, p, l) BUG()
484#define SMC_outsl(a, r, p, l) BUG()
485#endif
486
487#if !defined(SMC_insl) || !defined(SMC_outsl)
488#define SMC_insl(a, r, p, l) BUG()
489#define SMC_outsl(a, r, p, l) BUG()
490#endif
491
492#if ! SMC_CAN_USE_16BIT
493
494/*
495 * Any 16-bit access is performed with two 8-bit accesses if the hardware
496 * can't do it directly. Most registers are 16-bit so those are mandatory.
497 */
498#define SMC_outw(x, ioaddr, reg) \
499 do { \
500 unsigned int __val16 = (x); \
501 SMC_outb( __val16, ioaddr, reg ); \
502 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
503 } while (0)
504#define SMC_inw(ioaddr, reg) \
505 ({ \
506 unsigned int __val16; \
507 __val16 = SMC_inb( ioaddr, reg ); \
508 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
509 __val16; \
510 })
511
512#define SMC_insw(a, r, p, l) BUG()
513#define SMC_outsw(a, r, p, l) BUG()
514
515#endif
516
517#if !defined(SMC_insw) || !defined(SMC_outsw)
518#define SMC_insw(a, r, p, l) BUG()
519#define SMC_outsw(a, r, p, l) BUG()
520#endif
521
522#if ! SMC_CAN_USE_8BIT
523#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
524#define SMC_outb(x, ioaddr, reg) BUG()
525#define SMC_insb(a, r, p, l) BUG()
526#define SMC_outsb(a, r, p, l) BUG()
527#endif
528
529#if !defined(SMC_insb) || !defined(SMC_outsb)
530#define SMC_insb(a, r, p, l) BUG()
531#define SMC_outsb(a, r, p, l) BUG()
532#endif
533
534#ifndef SMC_CAN_USE_DATACS
535#define SMC_CAN_USE_DATACS 0
536#endif
537
1da177e4
LT		 538#ifndef SMC_IO_SHIFT
539#define SMC_IO_SHIFT 0
540#endif
09779c6d
NP		 541
542#ifndef SMC_IRQ_FLAGS
1fb9df5d 543#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
09779c6d
NP		 544#endif
545
546#ifndef SMC_INTERRUPT_PREAMBLE
547#define SMC_INTERRUPT_PREAMBLE
548#endif
549
550
551/* Because of bank switching, the LAN91x uses only 16 I/O ports */
1da177e4
LT		 552#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
553#define SMC_DATA_EXTENT (4)
554
555/*
556 . Bank Select Register:
557 .
558 . yyyy yyyy 0000 00xx
559 . xx = bank number
560 . yyyy yyyy = 0x33, for identification purposes.
561*/
562#define BANK_SELECT (14 << SMC_IO_SHIFT)
563
564
565// Transmit Control Register
566/* BANK 0 */
567#define TCR_REG SMC_REG(0x0000, 0)
568#define TCR_ENABLE 0x0001 // When 1 we can transmit
569#define TCR_LOOP 0x0002 // Controls output pin LBK
570#define TCR_FORCOL 0x0004 // When 1 will force a collision
571#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
572#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
573#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
574#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
575#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
576#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
577#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
578
579#define TCR_CLEAR 0 /* do NOTHING */
580/* the default settings for the TCR register : */
581#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
582
583
584// EPH Status Register
585/* BANK 0 */
586#define EPH_STATUS_REG SMC_REG(0x0002, 0)
587#define ES_TX_SUC 0x0001 // Last TX was successful
588#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
589#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
590#define ES_LTX_MULT 0x0008 // Last tx was a multicast
591#define ES_16COL 0x0010 // 16 Collisions Reached
592#define ES_SQET 0x0020 // Signal Quality Error Test
593#define ES_LTXBRD 0x0040 // Last tx was a broadcast
594#define ES_TXDEFR 0x0080 // Transmit Deferred
595#define ES_LATCOL 0x0200 // Late collision detected on last tx
596#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
597#define ES_EXC_DEF 0x0800 // Excessive Deferral
598#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
599#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
600#define ES_TXUNRN 0x8000 // Tx Underrun
601
602
603// Receive Control Register
604/* BANK 0 */
605#define RCR_REG SMC_REG(0x0004, 0)
606#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
607#define RCR_PRMS 0x0002 // Enable promiscuous mode
608#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
609#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
610#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
611#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
612#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
613#define RCR_SOFTRST 0x8000 // resets the chip
614
615/* the normal settings for the RCR register : */
616#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
617#define RCR_CLEAR 0x0 // set it to a base state
618
619
620// Counter Register
621/* BANK 0 */
622#define COUNTER_REG SMC_REG(0x0006, 0)
623
624
625// Memory Information Register
626/* BANK 0 */
627#define MIR_REG SMC_REG(0x0008, 0)
628
629
630// Receive/Phy Control Register
631/* BANK 0 */
632#define RPC_REG SMC_REG(0x000A, 0)
633#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
634#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
635#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
636#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
637#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
638#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
639#define RPC_LED_RES (0x01) // LED = Reserved
640#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
641#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
642#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
643#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
644#define RPC_LED_TX (0x06) // LED = TX packet occurred
645#define RPC_LED_RX (0x07) // LED = RX packet occurred
646
647#ifndef RPC_LSA_DEFAULT
648#define RPC_LSA_DEFAULT RPC_LED_100
649#endif
650#ifndef RPC_LSB_DEFAULT
651#define RPC_LSB_DEFAULT RPC_LED_FD
652#endif
653
654#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
655
656
657/* Bank 0 0x0C is reserved */
658
659// Bank Select Register
660/* All Banks */
661#define BSR_REG 0x000E
662
663
664// Configuration Reg
665/* BANK 1 */
666#define CONFIG_REG SMC_REG(0x0000, 1)
667#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
668#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
669#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
670#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
671
672// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
673#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
674
675
676// Base Address Register
677/* BANK 1 */
678#define BASE_REG SMC_REG(0x0002, 1)
679
680
681// Individual Address Registers
682/* BANK 1 */
683#define ADDR0_REG SMC_REG(0x0004, 1)
684#define ADDR1_REG SMC_REG(0x0006, 1)
685#define ADDR2_REG SMC_REG(0x0008, 1)
686
687
688// General Purpose Register
689/* BANK 1 */
690#define GP_REG SMC_REG(0x000A, 1)
691
692
693// Control Register
694/* BANK 1 */
695#define CTL_REG SMC_REG(0x000C, 1)
696#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
697#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
698#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
699#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
700#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
701#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
702#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
703#define CTL_STORE 0x0001 // When set stores registers into EEPROM
704
705
706// MMU Command Register
707/* BANK 2 */
708#define MMU_CMD_REG SMC_REG(0x0000, 2)
709#define MC_BUSY 1 // When 1 the last release has not completed
710#define MC_NOP (0<<5) // No Op
711#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
712#define MC_RESET (2<<5) // Reset MMU to initial state
713#define MC_REMOVE (3<<5) // Remove the current rx packet
714#define MC_RELEASE (4<<5) // Remove and release the current rx packet
715#define MC_FREEPKT (5<<5) // Release packet in PNR register
716#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
717#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
718
719
720// Packet Number Register
721/* BANK 2 */
722#define PN_REG SMC_REG(0x0002, 2)
723
724
725// Allocation Result Register
726/* BANK 2 */
727#define AR_REG SMC_REG(0x0003, 2)
728#define AR_FAILED 0x80 // Alocation Failed
729
730
731// TX FIFO Ports Register
732/* BANK 2 */
733#define TXFIFO_REG SMC_REG(0x0004, 2)
734#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
735
736// RX FIFO Ports Register
737/* BANK 2 */
738#define RXFIFO_REG SMC_REG(0x0005, 2)
739#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
740
741#define FIFO_REG SMC_REG(0x0004, 2)
742
743// Pointer Register
744/* BANK 2 */
745#define PTR_REG SMC_REG(0x0006, 2)
746#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
747#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
748#define PTR_READ 0x2000 // When 1 the operation is a read
749
750
751// Data Register
752/* BANK 2 */
753#define DATA_REG SMC_REG(0x0008, 2)
754
755
756// Interrupt Status/Acknowledge Register
757/* BANK 2 */
758#define INT_REG SMC_REG(0x000C, 2)
759
760
761// Interrupt Mask Register
762/* BANK 2 */
763#define IM_REG SMC_REG(0x000D, 2)
764#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
765#define IM_ERCV_INT 0x40 // Early Receive Interrupt
766#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
767#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
768#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
769#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
770#define IM_TX_INT 0x02 // Transmit Interrupt
771#define IM_RCV_INT 0x01 // Receive Interrupt
772
773
774// Multicast Table Registers
775/* BANK 3 */
776#define MCAST_REG1 SMC_REG(0x0000, 3)
777#define MCAST_REG2 SMC_REG(0x0002, 3)
778#define MCAST_REG3 SMC_REG(0x0004, 3)
779#define MCAST_REG4 SMC_REG(0x0006, 3)
780
781
782// Management Interface Register (MII)
783/* BANK 3 */
784#define MII_REG SMC_REG(0x0008, 3)
785#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
786#define MII_MDOE 0x0008 // MII Output Enable
787#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
788#define MII_MDI 0x0002 // MII Input, pin MDI
789#define MII_MDO 0x0001 // MII Output, pin MDO
790
791
792// Revision Register
793/* BANK 3 */
794/* ( hi: chip id low: rev # ) */
795#define REV_REG SMC_REG(0x000A, 3)
796
797
798// Early RCV Register
799/* BANK 3 */
800/* this is NOT on SMC9192 */
801#define ERCV_REG SMC_REG(0x000C, 3)
802#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
803#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
804
805
806// External Register
807/* BANK 7 */
808#define EXT_REG SMC_REG(0x0000, 7)
809
810
811#define CHIP_9192 3
812#define CHIP_9194 4
813#define CHIP_9195 5
814#define CHIP_9196 6
815#define CHIP_91100 7
816#define CHIP_91100FD 8
817#define CHIP_91111FD 9
818
819static const char * chip_ids[ 16 ] = {
820 NULL, NULL, NULL,
821 /* 3 */ "SMC91C90/91C92",
822 /* 4 */ "SMC91C94",
823 /* 5 */ "SMC91C95",
824 /* 6 */ "SMC91C96",
825 /* 7 */ "SMC91C100",
826 /* 8 */ "SMC91C100FD",
827 /* 9 */ "SMC91C11xFD",
828 NULL, NULL, NULL,
829 NULL, NULL, NULL};
830
831
1da177e4
LT		 832/*
833 . Receive status bits
834*/
835#define RS_ALGNERR 0x8000
836#define RS_BRODCAST 0x4000
837#define RS_BADCRC 0x2000
838#define RS_ODDFRAME 0x1000
839#define RS_TOOLONG 0x0800
840#define RS_TOOSHORT 0x0400
841#define RS_MULTICAST 0x0001
842#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
843
844
845/*
846 * PHY IDs
847 * LAN83C183 == LAN91C111 Internal PHY
848 */
849#define PHY_LAN83C183 0x0016f840
850#define PHY_LAN83C180 0x02821c50
851
852/*
853 * PHY Register Addresses (LAN91C111 Internal PHY)
854 *
855 * Generic PHY registers can be found in <linux/mii.h>
856 *
857 * These phy registers are specific to our on-board phy.
858 */
859
860// PHY Configuration Register 1
861#define PHY_CFG1_REG 0x10
862#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
863#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
864#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
865#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
866#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
867#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
868#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
869#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
870#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
871#define PHY_CFG1_TLVL_MASK 0x003C
872#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
873
874
875// PHY Configuration Register 2
876#define PHY_CFG2_REG 0x11
877#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
878#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
879#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
880#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
881
882// PHY Status Output (and Interrupt status) Register
883#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
884#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
885#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
886#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
887#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
888#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
889#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
890#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
891#define PHY_INT_JAB 0x0100 // 1=Jabber detected
892#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
893#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
894
895// PHY Interrupt/Status Mask Register
896#define PHY_MASK_REG 0x13 // Interrupt Mask
897// Uses the same bit definitions as PHY_INT_REG
898
899
900/*
901 * SMC91C96 ethernet config and status registers.
902 * These are in the "attribute" space.
903 */
904#define ECOR 0x8000
905#define ECOR_RESET 0x80
906#define ECOR_LEVEL_IRQ 0x40
907#define ECOR_WR_ATTRIB 0x04
908#define ECOR_ENABLE 0x01
909
910#define ECSR 0x8002
911#define ECSR_IOIS8 0x20
912#define ECSR_PWRDWN 0x04
913#define ECSR_INT 0x02
914
915#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
916
917
918/*
919 * Macros to abstract register access according to the data bus
920 * capabilities. Please use those and not the in/out primitives.
921 * Note: the following macros do *not* select the bank -- this must
922 * be done separately as needed in the main code. The SMC_REG() macro
923 * only uses the bank argument for debugging purposes (when enabled).
09779c6d
NP		 924 *
925 * Note: despite inline functions being safer, everything leading to this
926 * should preferably be macros to let BUG() display the line number in
927 * the core source code since we're interested in the top call site
928 * not in any inline function location.
1da177e4
LT		 929 */
930
931#if SMC_DEBUG > 0
932#define SMC_REG(reg, bank) \
933 ({ \
934 int __b = SMC_CURRENT_BANK(); \
935 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
936 printk( "%s: bank reg screwed (0x%04x)\n", \
937 CARDNAME, __b ); \
938 BUG(); \
939 } \
940 reg<<SMC_IO_SHIFT; \
941 })
942#else
943#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
944#endif
945
09779c6d
NP		 946/*
947 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
948 * aligned to a 32 bit boundary. I tell you that does exist!
949 * Fortunately the affected register accesses can be easily worked around
950 * since we can write zeroes to the preceeding 16 bits without adverse
951 * effects and use a 32-bit access.
952 *
953 * Enforce it on any 32-bit capable setup for now.
954 */
955#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
956
957#define SMC_GET_PN() \
958 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
959 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
960
961#define SMC_SET_PN(x) \
962 do { \
963 if (SMC_MUST_ALIGN_WRITE) \
964 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
965 else if (SMC_CAN_USE_8BIT) \
966 SMC_outb(x, ioaddr, PN_REG); \
967 else \
968 SMC_outw(x, ioaddr, PN_REG); \
969 } while (0)
970
971#define SMC_GET_AR() \
972 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
973 : (SMC_inw(ioaddr, PN_REG) >> 8) )
974
975#define SMC_GET_TXFIFO() \
976 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
977 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
978
979#define SMC_GET_RXFIFO() \
980 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
981 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
982
983#define SMC_GET_INT() \
984 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
985 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
986
1da177e4
LT		 987#define SMC_ACK_INT(x) \
988 do { \
09779c6d
NP		 989 if (SMC_CAN_USE_8BIT) \
990 SMC_outb(x, ioaddr, INT_REG); \
991 else { \
992 unsigned long __flags; \
993 int __mask; \
994 local_irq_save(__flags); \
995 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
996 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
997 local_irq_restore(__flags); \
998 } \
999 } while (0)
1000
1001#define SMC_GET_INT_MASK() \
1002 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1003 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1004
1005#define SMC_SET_INT_MASK(x) \
1006 do { \
1007 if (SMC_CAN_USE_8BIT) \
1008 SMC_outb(x, ioaddr, IM_REG); \
1009 else \
1010 SMC_outw((x) << 8, ioaddr, INT_REG); \
1011 } while (0)
1012
1013#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1014
1015#define SMC_SELECT_BANK(x) \
1016 do { \
1017 if (SMC_MUST_ALIGN_WRITE) \
1018 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1019 else \
1020 SMC_outw(x, ioaddr, BANK_SELECT); \
1021 } while (0)
1022
1023#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1024
1025#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1026
1027#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1028
1029#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1030
1031#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1032
1033#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1034
1035#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1036
1037#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1038
1039#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1040
1041#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1042
1043#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1044
1045#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1046
1047#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1048
1049#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1050
1051#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1052
1053#define SMC_SET_PTR(x) \
1054 do { \
1055 if (SMC_MUST_ALIGN_WRITE) \
1056 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1057 else \
1058 SMC_outw(x, ioaddr, PTR_REG); \
1da177e4 1059 } while (0)
1da177e4 1060
09779c6d
NP		 1061#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1062
1063#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1064
1065#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1066
1067#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1068
1069#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1070
1071#define SMC_SET_RPC(x) \
1072 do { \
1073 if (SMC_MUST_ALIGN_WRITE) \
1074 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1075 else \
1076 SMC_outw(x, ioaddr, RPC_REG); \
1077 } while (0)
1078
1079#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1080
1081#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1da177e4
LT		 1082
1083#ifndef SMC_GET_MAC_ADDR
1084#define SMC_GET_MAC_ADDR(addr) \
1085 do { \
1086 unsigned int __v; \
1087 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1088 addr[0] = __v; addr[1] = __v >> 8; \
1089 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1090 addr[2] = __v; addr[3] = __v >> 8; \
1091 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1092 addr[4] = __v; addr[5] = __v >> 8; \
1093 } while (0)
1094#endif
1095
1096#define SMC_SET_MAC_ADDR(addr) \
1097 do { \
1098 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1099 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1100 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1101 } while (0)
1102
1103#define SMC_SET_MCAST(x) \
1104 do { \
1105 const unsigned char *mt = (x); \
1106 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1107 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1108 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1109 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1110 } while (0)
1111
1da177e4
LT		 1112#define SMC_PUT_PKT_HDR(status, length) \
1113 do { \
09779c6d
NP		 1114 if (SMC_CAN_USE_32BIT) \
1115 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1116 else { \
1117 SMC_outw(status, ioaddr, DATA_REG); \
1118 SMC_outw(length, ioaddr, DATA_REG); \
1119 } \
1da177e4 1120 } while (0)
1da177e4 1121
09779c6d 1122#define SMC_GET_PKT_HDR(status, length) \
1da177e4 1123 do { \
09779c6d
NP		 1124 if (SMC_CAN_USE_32BIT) { \
1125 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1126 (status) = __val & 0xffff; \
1127 (length) = __val >> 16; \
1128 } else { \
1129 (status) = SMC_inw(ioaddr, DATA_REG); \
1130 (length) = SMC_inw(ioaddr, DATA_REG); \
1da177e4
LT		 1131 } \
1132 } while (0)
1da177e4 1133
09779c6d 1134#define SMC_PUSH_DATA(p, l) \
1da177e4 1135 do { \
09779c6d
NP		 1136 if (SMC_CAN_USE_32BIT) { \
1137 void *__ptr = (p); \
1138 int __len = (l); \
1139 void *__ioaddr = ioaddr; \
1140 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1141 __len -= 2; \
1142 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1143 __ptr += 2; \
1144 } \
1145 if (SMC_CAN_USE_DATACS && lp->datacs) \
1146 __ioaddr = lp->datacs; \
1147 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1148 if (__len & 2) { \
1149 __ptr += (__len & ~3); \
1150 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1151 } \
1152 } else if (SMC_CAN_USE_16BIT) \
1153 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1154 else if (SMC_CAN_USE_8BIT) \
1155 SMC_outsb(ioaddr, DATA_REG, p, l); \
1da177e4 1156 } while (0)
1da177e4
LT		 1157
1158#define SMC_PULL_DATA(p, l) \
09779c6d
NP		 1159 do { \
1160 if (SMC_CAN_USE_32BIT) { \
1161 void *__ptr = (p); \
1162 int __len = (l); \
1163 void *__ioaddr = ioaddr; \
1164 if ((unsigned long)__ptr & 2) { \
1165 /* \
1166 * We want 32bit alignment here. \
1167 * Since some buses perform a full \
1168 * 32bit fetch even for 16bit data \
1169 * we can't use SMC_inw() here. \
1170 * Back both source (on-chip) and \
1171 * destination pointers of 2 bytes. \
1172 * This is possible since the call to \
1173 * SMC_GET_PKT_HDR() already advanced \
1174 * the source pointer of 4 bytes, and \
1175 * the skb_reserve(skb, 2) advanced \
1176 * the destination pointer of 2 bytes. \
1177 */ \
1178 __ptr -= 2; \
1179 __len += 2; \
1180 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1181 } \
1182 if (SMC_CAN_USE_DATACS && lp->datacs) \
1183 __ioaddr = lp->datacs; \
1da177e4 1184 __len += 2; \
09779c6d
NP		 1185 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1186 } else if (SMC_CAN_USE_16BIT) \
1187 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1188 else if (SMC_CAN_USE_8BIT) \
1189 SMC_insb(ioaddr, DATA_REG, p, l); \
1190 } while (0)
1da177e4
LT		 1191
1192#endif /* _SMC91X_H_ */