Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
31 | . Nicolas Pitre <nico@cam.org> | |
32 | . | |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
37 | ||
38 | /* | |
39 | * Define your architecture specific bus configuration parameters here. | |
40 | */ | |
41 | ||
42 | #if defined(CONFIG_ARCH_LUBBOCK) | |
43 | ||
44 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
45 | #define SMC_CAN_USE_8BIT 0 | |
46 | #define SMC_CAN_USE_16BIT 1 | |
47 | #define SMC_CAN_USE_32BIT 0 | |
48 | #define SMC_NOWAIT 1 | |
49 | ||
50 | /* The first two address lines aren't connected... */ | |
51 | #define SMC_IO_SHIFT 2 | |
52 | ||
53 | #define SMC_inw(a, r) readw((a) + (r)) | |
54 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
55 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
56 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
57 | ||
58 | #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) | |
59 | ||
60 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
61 | #define SMC_CAN_USE_8BIT 0 | |
62 | #define SMC_CAN_USE_16BIT 1 | |
63 | #define SMC_CAN_USE_32BIT 0 | |
64 | #define SMC_NOWAIT 1 | |
65 | ||
66 | #define SMC_IO_SHIFT 0 | |
67 | ||
68 | #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) | |
69 | #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) | |
70 | #define SMC_insw(a, r, p, l) \ | |
71 | do { \ | |
72 | unsigned long __port = (a) + (r); \ | |
73 | u16 *__p = (u16 *)(p); \ | |
74 | int __l = (l); \ | |
75 | insw(__port, __p, __l); \ | |
76 | while (__l > 0) { \ | |
77 | *__p = swab16(*__p); \ | |
78 | __p++; \ | |
79 | __l--; \ | |
80 | } \ | |
81 | } while (0) | |
82 | #define SMC_outsw(a, r, p, l) \ | |
83 | do { \ | |
84 | unsigned long __port = (a) + (r); \ | |
85 | u16 *__p = (u16 *)(p); \ | |
86 | int __l = (l); \ | |
87 | while (__l > 0) { \ | |
88 | /* Believe it or not, the swab isn't needed. */ \ | |
89 | outw( /* swab16 */ (*__p++), __port); \ | |
90 | __l--; \ | |
91 | } \ | |
92 | } while (0) | |
93 | #define set_irq_type(irq, type) | |
94 | ||
95 | #elif defined(CONFIG_SA1100_PLEB) | |
96 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
97 | #define SMC_CAN_USE_8BIT 1 | |
98 | #define SMC_CAN_USE_16BIT 1 | |
99 | #define SMC_CAN_USE_32BIT 0 | |
100 | #define SMC_IO_SHIFT 0 | |
101 | #define SMC_NOWAIT 1 | |
102 | ||
103 | #define SMC_inb(a, r) inb((a) + (r)) | |
104 | #define SMC_insb(a, r, p, l) insb((a) + (r), p, (l)) | |
105 | #define SMC_inw(a, r) inw((a) + (r)) | |
106 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
107 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
108 | #define SMC_outsb(a, r, p, l) outsb((a) + (r), p, (l)) | |
109 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
110 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
111 | ||
112 | #define set_irq_type(irq, type) do {} while (0) | |
113 | ||
114 | #elif defined(CONFIG_SA1100_ASSABET) | |
115 | ||
116 | #include <asm/arch/neponset.h> | |
117 | ||
118 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
119 | #define SMC_CAN_USE_8BIT 1 | |
120 | #define SMC_CAN_USE_16BIT 0 | |
121 | #define SMC_CAN_USE_32BIT 0 | |
122 | #define SMC_NOWAIT 1 | |
123 | ||
124 | /* The first two address lines aren't connected... */ | |
125 | #define SMC_IO_SHIFT 2 | |
126 | ||
127 | #define SMC_inb(a, r) readb((a) + (r)) | |
128 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
129 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
130 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
131 | ||
132 | #elif defined(CONFIG_ARCH_INNOKOM) || \ | |
133 | defined(CONFIG_MACH_MAINSTONE) || \ | |
134 | defined(CONFIG_ARCH_PXA_IDP) || \ | |
135 | defined(CONFIG_ARCH_RAMSES) | |
136 | ||
137 | #define SMC_CAN_USE_8BIT 1 | |
138 | #define SMC_CAN_USE_16BIT 1 | |
139 | #define SMC_CAN_USE_32BIT 1 | |
140 | #define SMC_IO_SHIFT 0 | |
141 | #define SMC_NOWAIT 1 | |
142 | #define SMC_USE_PXA_DMA 1 | |
143 | ||
144 | #define SMC_inb(a, r) readb((a) + (r)) | |
145 | #define SMC_inw(a, r) readw((a) + (r)) | |
146 | #define SMC_inl(a, r) readl((a) + (r)) | |
147 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
148 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
149 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
150 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
151 | ||
152 | /* We actually can't write halfwords properly if not word aligned */ | |
153 | static inline void | |
154 | SMC_outw(u16 val, unsigned long ioaddr, int reg) | |
155 | { | |
156 | if (reg & 2) { | |
157 | unsigned int v = val << 16; | |
158 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
159 | writel(v, ioaddr + (reg & ~2)); | |
160 | } else { | |
161 | writew(val, ioaddr + reg); | |
162 | } | |
163 | } | |
164 | ||
165 | #elif defined(CONFIG_ARCH_OMAP) | |
166 | ||
167 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
168 | #define SMC_CAN_USE_8BIT 0 | |
169 | #define SMC_CAN_USE_16BIT 1 | |
170 | #define SMC_CAN_USE_32BIT 0 | |
171 | #define SMC_IO_SHIFT 0 | |
172 | #define SMC_NOWAIT 1 | |
173 | ||
174 | #define SMC_inb(a, r) readb((a) + (r)) | |
175 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
176 | #define SMC_inw(a, r) readw((a) + (r)) | |
177 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
178 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
179 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
180 | #define SMC_inl(a, r) readl((a) + (r)) | |
181 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
182 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
183 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
184 | ||
185 | #elif defined(CONFIG_SH_SH4202_MICRODEV) | |
186 | ||
187 | #define SMC_CAN_USE_8BIT 0 | |
188 | #define SMC_CAN_USE_16BIT 1 | |
189 | #define SMC_CAN_USE_32BIT 0 | |
190 | ||
191 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
192 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
193 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
194 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
195 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
196 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
197 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
198 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
199 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
200 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
201 | ||
202 | #define set_irq_type(irq, type) do {} while(0) | |
203 | ||
204 | #elif defined(CONFIG_ISA) | |
205 | ||
206 | #define SMC_CAN_USE_8BIT 1 | |
207 | #define SMC_CAN_USE_16BIT 1 | |
208 | #define SMC_CAN_USE_32BIT 0 | |
209 | ||
210 | #define SMC_inb(a, r) inb((a) + (r)) | |
211 | #define SMC_inw(a, r) inw((a) + (r)) | |
212 | #define SMC_outb(v, a, r) outb(v, (a) + (r)) | |
213 | #define SMC_outw(v, a, r) outw(v, (a) + (r)) | |
214 | #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) | |
215 | #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) | |
216 | ||
217 | #elif defined(CONFIG_M32R) | |
218 | ||
219 | #define SMC_CAN_USE_8BIT 0 | |
220 | #define SMC_CAN_USE_16BIT 1 | |
221 | #define SMC_CAN_USE_32BIT 0 | |
222 | ||
223 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
224 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
225 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
226 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
227 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
228 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
229 | ||
230 | #define set_irq_type(irq, type) do {} while(0) | |
231 | ||
232 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
233 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
234 | ||
235 | #elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) | |
236 | ||
237 | /* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between | |
238 | * the way that the CPU handles chip selects and the way that the SMC | |
239 | * chip expects the chip select to operate. Refer to | |
240 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from | |
241 | * IOBARRIER is a byte as a least-common denominator of possible | |
242 | * regions to use as the barrier. It would be wasteful to read 32 | |
243 | * bits from a byte oriented region. | |
244 | * | |
245 | * There is no explicit protection against interrupts intervening | |
246 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
247 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
248 | * that the driver interrupts itself between a writew to the chip an | |
249 | * the IOBARRIER that follows *and* the cache is large enough that the | |
250 | * first off-chip access while handing the interrupt is to the SMC | |
251 | * chip. Other devices in the same address space as the SMC chip must | |
252 | * be aware of the potential for trouble and perform a similar | |
253 | * IOBARRIER on entry to their ISR. | |
254 | */ | |
255 | ||
256 | #include <asm/arch/constants.h> /* IOBARRIER_VIRT */ | |
257 | ||
258 | #define SMC_CAN_USE_8BIT 0 | |
259 | #define SMC_CAN_USE_16BIT 1 | |
260 | #define SMC_CAN_USE_32BIT 0 | |
261 | #define SMC_NOWAIT 0 | |
262 | #define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) | |
263 | ||
264 | #define SMC_inw(a,r) readw ((void*) ((a) + (r))) | |
265 | #define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) | |
266 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) | |
267 | ||
268 | static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l) | |
269 | { | |
270 | unsigned short* ps = (unsigned short*) p; | |
271 | while (l-- > 0) { | |
272 | writew (*ps++, a + r); | |
273 | LPD7A40X_IOBARRIER; | |
274 | } | |
275 | } | |
276 | ||
277 | #define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER | |
278 | ||
279 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
280 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
281 | ||
282 | #else | |
283 | ||
284 | #define SMC_CAN_USE_8BIT 1 | |
285 | #define SMC_CAN_USE_16BIT 1 | |
286 | #define SMC_CAN_USE_32BIT 1 | |
287 | #define SMC_NOWAIT 1 | |
288 | ||
289 | #define SMC_inb(a, r) readb((a) + (r)) | |
290 | #define SMC_inw(a, r) readw((a) + (r)) | |
291 | #define SMC_inl(a, r) readl((a) + (r)) | |
292 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
293 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
294 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
295 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
296 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
297 | ||
298 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
299 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
300 | ||
301 | #endif | |
302 | ||
303 | ||
304 | #ifdef SMC_USE_PXA_DMA | |
305 | /* | |
306 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
307 | * always happening in irq context so no need to worry about races. TX is | |
308 | * different and probably not worth it for that reason, and not as critical | |
309 | * as RX which can overrun memory and lose packets. | |
310 | */ | |
311 | #include <linux/dma-mapping.h> | |
312 | #include <asm/dma.h> | |
313 | #include <asm/arch/pxa-regs.h> | |
314 | ||
315 | #ifdef SMC_insl | |
316 | #undef SMC_insl | |
317 | #define SMC_insl(a, r, p, l) \ | |
318 | smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) | |
319 | static inline void | |
320 | smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma, | |
321 | u_char *buf, int len) | |
322 | { | |
323 | dma_addr_t dmabuf; | |
324 | ||
325 | /* fallback if no DMA available */ | |
326 | if (dma == (unsigned char)-1) { | |
327 | readsl(ioaddr + reg, buf, len); | |
328 | return; | |
329 | } | |
330 | ||
331 | /* 64 bit alignment is required for memory to memory DMA */ | |
332 | if ((long)buf & 4) { | |
333 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
334 | buf += 4; | |
335 | len--; | |
336 | } | |
337 | ||
338 | len *= 4; | |
339 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
340 | DCSR(dma) = DCSR_NODESC; | |
341 | DTADR(dma) = dmabuf; | |
342 | DSADR(dma) = physaddr + reg; | |
343 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
344 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
345 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
346 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
347 | cpu_relax(); | |
348 | DCSR(dma) = 0; | |
349 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
350 | } | |
351 | #endif | |
352 | ||
353 | #ifdef SMC_insw | |
354 | #undef SMC_insw | |
355 | #define SMC_insw(a, r, p, l) \ | |
356 | smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) | |
357 | static inline void | |
358 | smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma, | |
359 | u_char *buf, int len) | |
360 | { | |
361 | dma_addr_t dmabuf; | |
362 | ||
363 | /* fallback if no DMA available */ | |
364 | if (dma == (unsigned char)-1) { | |
365 | readsw(ioaddr + reg, buf, len); | |
366 | return; | |
367 | } | |
368 | ||
369 | /* 64 bit alignment is required for memory to memory DMA */ | |
370 | while ((long)buf & 6) { | |
371 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
372 | buf += 2; | |
373 | len--; | |
374 | } | |
375 | ||
376 | len *= 2; | |
377 | dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); | |
378 | DCSR(dma) = DCSR_NODESC; | |
379 | DTADR(dma) = dmabuf; | |
380 | DSADR(dma) = physaddr + reg; | |
381 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
382 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
383 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
384 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
385 | cpu_relax(); | |
386 | DCSR(dma) = 0; | |
387 | dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); | |
388 | } | |
389 | #endif | |
390 | ||
391 | static void | |
392 | smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs) | |
393 | { | |
394 | DCSR(dma) = 0; | |
395 | } | |
396 | #endif /* SMC_USE_PXA_DMA */ | |
397 | ||
398 | ||
399 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
400 | #ifndef SMC_IO_SHIFT | |
401 | #define SMC_IO_SHIFT 0 | |
402 | #endif | |
403 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) | |
404 | #define SMC_DATA_EXTENT (4) | |
405 | ||
406 | /* | |
407 | . Bank Select Register: | |
408 | . | |
409 | . yyyy yyyy 0000 00xx | |
410 | . xx = bank number | |
411 | . yyyy yyyy = 0x33, for identification purposes. | |
412 | */ | |
413 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
414 | ||
415 | ||
416 | // Transmit Control Register | |
417 | /* BANK 0 */ | |
418 | #define TCR_REG SMC_REG(0x0000, 0) | |
419 | #define TCR_ENABLE 0x0001 // When 1 we can transmit | |
420 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
421 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
422 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
423 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
424 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
425 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
426 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
427 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
428 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
429 | ||
430 | #define TCR_CLEAR 0 /* do NOTHING */ | |
431 | /* the default settings for the TCR register : */ | |
432 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
433 | ||
434 | ||
435 | // EPH Status Register | |
436 | /* BANK 0 */ | |
437 | #define EPH_STATUS_REG SMC_REG(0x0002, 0) | |
438 | #define ES_TX_SUC 0x0001 // Last TX was successful | |
439 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
440 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
441 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
442 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
443 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
444 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
445 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
446 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
447 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
448 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
449 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
450 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
451 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
452 | ||
453 | ||
454 | // Receive Control Register | |
455 | /* BANK 0 */ | |
456 | #define RCR_REG SMC_REG(0x0004, 0) | |
457 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted | |
458 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
459 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
460 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
461 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
462 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
463 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
464 | #define RCR_SOFTRST 0x8000 // resets the chip | |
465 | ||
466 | /* the normal settings for the RCR register : */ | |
467 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
468 | #define RCR_CLEAR 0x0 // set it to a base state | |
469 | ||
470 | ||
471 | // Counter Register | |
472 | /* BANK 0 */ | |
473 | #define COUNTER_REG SMC_REG(0x0006, 0) | |
474 | ||
475 | ||
476 | // Memory Information Register | |
477 | /* BANK 0 */ | |
478 | #define MIR_REG SMC_REG(0x0008, 0) | |
479 | ||
480 | ||
481 | // Receive/Phy Control Register | |
482 | /* BANK 0 */ | |
483 | #define RPC_REG SMC_REG(0x000A, 0) | |
484 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. | |
485 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
486 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
487 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
488 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
489 | #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect | |
490 | #define RPC_LED_RES (0x01) // LED = Reserved | |
491 | #define RPC_LED_10 (0x02) // LED = 10Mbps link detect | |
492 | #define RPC_LED_FD (0x03) // LED = Full Duplex Mode | |
493 | #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred | |
494 | #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect | |
495 | #define RPC_LED_TX (0x06) // LED = TX packet occurred | |
496 | #define RPC_LED_RX (0x07) // LED = RX packet occurred | |
497 | ||
498 | #ifndef RPC_LSA_DEFAULT | |
499 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
500 | #endif | |
501 | #ifndef RPC_LSB_DEFAULT | |
502 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
503 | #endif | |
504 | ||
505 | #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) | |
506 | ||
507 | ||
508 | /* Bank 0 0x0C is reserved */ | |
509 | ||
510 | // Bank Select Register | |
511 | /* All Banks */ | |
512 | #define BSR_REG 0x000E | |
513 | ||
514 | ||
515 | // Configuration Reg | |
516 | /* BANK 1 */ | |
517 | #define CONFIG_REG SMC_REG(0x0000, 1) | |
518 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy | |
519 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
520 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
521 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
522 | ||
523 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
524 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
525 | ||
526 | ||
527 | // Base Address Register | |
528 | /* BANK 1 */ | |
529 | #define BASE_REG SMC_REG(0x0002, 1) | |
530 | ||
531 | ||
532 | // Individual Address Registers | |
533 | /* BANK 1 */ | |
534 | #define ADDR0_REG SMC_REG(0x0004, 1) | |
535 | #define ADDR1_REG SMC_REG(0x0006, 1) | |
536 | #define ADDR2_REG SMC_REG(0x0008, 1) | |
537 | ||
538 | ||
539 | // General Purpose Register | |
540 | /* BANK 1 */ | |
541 | #define GP_REG SMC_REG(0x000A, 1) | |
542 | ||
543 | ||
544 | // Control Register | |
545 | /* BANK 1 */ | |
546 | #define CTL_REG SMC_REG(0x000C, 1) | |
547 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received | |
548 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
549 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
550 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
551 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
552 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
553 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
554 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
555 | ||
556 | ||
557 | // MMU Command Register | |
558 | /* BANK 2 */ | |
559 | #define MMU_CMD_REG SMC_REG(0x0000, 2) | |
560 | #define MC_BUSY 1 // When 1 the last release has not completed | |
561 | #define MC_NOP (0<<5) // No Op | |
562 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
563 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
564 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
565 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
566 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
567 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
568 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
569 | ||
570 | ||
571 | // Packet Number Register | |
572 | /* BANK 2 */ | |
573 | #define PN_REG SMC_REG(0x0002, 2) | |
574 | ||
575 | ||
576 | // Allocation Result Register | |
577 | /* BANK 2 */ | |
578 | #define AR_REG SMC_REG(0x0003, 2) | |
579 | #define AR_FAILED 0x80 // Alocation Failed | |
580 | ||
581 | ||
582 | // TX FIFO Ports Register | |
583 | /* BANK 2 */ | |
584 | #define TXFIFO_REG SMC_REG(0x0004, 2) | |
585 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty | |
586 | ||
587 | // RX FIFO Ports Register | |
588 | /* BANK 2 */ | |
589 | #define RXFIFO_REG SMC_REG(0x0005, 2) | |
590 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty | |
591 | ||
592 | #define FIFO_REG SMC_REG(0x0004, 2) | |
593 | ||
594 | // Pointer Register | |
595 | /* BANK 2 */ | |
596 | #define PTR_REG SMC_REG(0x0006, 2) | |
597 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area | |
598 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
599 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
600 | ||
601 | ||
602 | // Data Register | |
603 | /* BANK 2 */ | |
604 | #define DATA_REG SMC_REG(0x0008, 2) | |
605 | ||
606 | ||
607 | // Interrupt Status/Acknowledge Register | |
608 | /* BANK 2 */ | |
609 | #define INT_REG SMC_REG(0x000C, 2) | |
610 | ||
611 | ||
612 | // Interrupt Mask Register | |
613 | /* BANK 2 */ | |
614 | #define IM_REG SMC_REG(0x000D, 2) | |
615 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt | |
616 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
617 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
618 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
619 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
620 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
621 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
622 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
623 | ||
624 | ||
625 | // Multicast Table Registers | |
626 | /* BANK 3 */ | |
627 | #define MCAST_REG1 SMC_REG(0x0000, 3) | |
628 | #define MCAST_REG2 SMC_REG(0x0002, 3) | |
629 | #define MCAST_REG3 SMC_REG(0x0004, 3) | |
630 | #define MCAST_REG4 SMC_REG(0x0006, 3) | |
631 | ||
632 | ||
633 | // Management Interface Register (MII) | |
634 | /* BANK 3 */ | |
635 | #define MII_REG SMC_REG(0x0008, 3) | |
636 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup | |
637 | #define MII_MDOE 0x0008 // MII Output Enable | |
638 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
639 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
640 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
641 | ||
642 | ||
643 | // Revision Register | |
644 | /* BANK 3 */ | |
645 | /* ( hi: chip id low: rev # ) */ | |
646 | #define REV_REG SMC_REG(0x000A, 3) | |
647 | ||
648 | ||
649 | // Early RCV Register | |
650 | /* BANK 3 */ | |
651 | /* this is NOT on SMC9192 */ | |
652 | #define ERCV_REG SMC_REG(0x000C, 3) | |
653 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received | |
654 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
655 | ||
656 | ||
657 | // External Register | |
658 | /* BANK 7 */ | |
659 | #define EXT_REG SMC_REG(0x0000, 7) | |
660 | ||
661 | ||
662 | #define CHIP_9192 3 | |
663 | #define CHIP_9194 4 | |
664 | #define CHIP_9195 5 | |
665 | #define CHIP_9196 6 | |
666 | #define CHIP_91100 7 | |
667 | #define CHIP_91100FD 8 | |
668 | #define CHIP_91111FD 9 | |
669 | ||
670 | static const char * chip_ids[ 16 ] = { | |
671 | NULL, NULL, NULL, | |
672 | /* 3 */ "SMC91C90/91C92", | |
673 | /* 4 */ "SMC91C94", | |
674 | /* 5 */ "SMC91C95", | |
675 | /* 6 */ "SMC91C96", | |
676 | /* 7 */ "SMC91C100", | |
677 | /* 8 */ "SMC91C100FD", | |
678 | /* 9 */ "SMC91C11xFD", | |
679 | NULL, NULL, NULL, | |
680 | NULL, NULL, NULL}; | |
681 | ||
682 | ||
683 | /* | |
684 | . Transmit status bits | |
685 | */ | |
686 | #define TS_SUCCESS 0x0001 | |
687 | #define TS_LOSTCAR 0x0400 | |
688 | #define TS_LATCOL 0x0200 | |
689 | #define TS_16COL 0x0010 | |
690 | ||
691 | /* | |
692 | . Receive status bits | |
693 | */ | |
694 | #define RS_ALGNERR 0x8000 | |
695 | #define RS_BRODCAST 0x4000 | |
696 | #define RS_BADCRC 0x2000 | |
697 | #define RS_ODDFRAME 0x1000 | |
698 | #define RS_TOOLONG 0x0800 | |
699 | #define RS_TOOSHORT 0x0400 | |
700 | #define RS_MULTICAST 0x0001 | |
701 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
702 | ||
703 | ||
704 | /* | |
705 | * PHY IDs | |
706 | * LAN83C183 == LAN91C111 Internal PHY | |
707 | */ | |
708 | #define PHY_LAN83C183 0x0016f840 | |
709 | #define PHY_LAN83C180 0x02821c50 | |
710 | ||
711 | /* | |
712 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
713 | * | |
714 | * Generic PHY registers can be found in <linux/mii.h> | |
715 | * | |
716 | * These phy registers are specific to our on-board phy. | |
717 | */ | |
718 | ||
719 | // PHY Configuration Register 1 | |
720 | #define PHY_CFG1_REG 0x10 | |
721 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
722 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
723 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
724 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
725 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
726 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
727 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
728 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
729 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
730 | #define PHY_CFG1_TLVL_MASK 0x003C | |
731 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
732 | ||
733 | ||
734 | // PHY Configuration Register 2 | |
735 | #define PHY_CFG2_REG 0x11 | |
736 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
737 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
738 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
739 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
740 | ||
741 | // PHY Status Output (and Interrupt status) Register | |
742 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
743 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
744 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
745 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
746 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
747 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
748 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
749 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
750 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
751 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
752 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
753 | ||
754 | // PHY Interrupt/Status Mask Register | |
755 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
756 | // Uses the same bit definitions as PHY_INT_REG | |
757 | ||
758 | ||
759 | /* | |
760 | * SMC91C96 ethernet config and status registers. | |
761 | * These are in the "attribute" space. | |
762 | */ | |
763 | #define ECOR 0x8000 | |
764 | #define ECOR_RESET 0x80 | |
765 | #define ECOR_LEVEL_IRQ 0x40 | |
766 | #define ECOR_WR_ATTRIB 0x04 | |
767 | #define ECOR_ENABLE 0x01 | |
768 | ||
769 | #define ECSR 0x8002 | |
770 | #define ECSR_IOIS8 0x20 | |
771 | #define ECSR_PWRDWN 0x04 | |
772 | #define ECSR_INT 0x02 | |
773 | ||
774 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
775 | ||
776 | ||
777 | /* | |
778 | * Macros to abstract register access according to the data bus | |
779 | * capabilities. Please use those and not the in/out primitives. | |
780 | * Note: the following macros do *not* select the bank -- this must | |
781 | * be done separately as needed in the main code. The SMC_REG() macro | |
782 | * only uses the bank argument for debugging purposes (when enabled). | |
783 | */ | |
784 | ||
785 | #if SMC_DEBUG > 0 | |
786 | #define SMC_REG(reg, bank) \ | |
787 | ({ \ | |
788 | int __b = SMC_CURRENT_BANK(); \ | |
789 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ | |
790 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
791 | CARDNAME, __b ); \ | |
792 | BUG(); \ | |
793 | } \ | |
794 | reg<<SMC_IO_SHIFT; \ | |
795 | }) | |
796 | #else | |
797 | #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) | |
798 | #endif | |
799 | ||
800 | #if SMC_CAN_USE_8BIT | |
801 | #define SMC_GET_PN() SMC_inb( ioaddr, PN_REG ) | |
802 | #define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG ) | |
803 | #define SMC_GET_AR() SMC_inb( ioaddr, AR_REG ) | |
804 | #define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG ) | |
805 | #define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG ) | |
806 | #define SMC_GET_INT() SMC_inb( ioaddr, INT_REG ) | |
807 | #define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG ) | |
808 | #define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG ) | |
809 | #define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG ) | |
810 | #else | |
811 | #define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF) | |
812 | #define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG ) | |
813 | #define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8) | |
814 | #define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF) | |
815 | #define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8) | |
816 | #define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF) | |
817 | #define SMC_ACK_INT(x) \ | |
818 | do { \ | |
819 | unsigned long __flags; \ | |
820 | int __mask; \ | |
821 | local_irq_save(__flags); \ | |
822 | __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ | |
823 | SMC_outw( __mask | (x), ioaddr, INT_REG ); \ | |
824 | local_irq_restore(__flags); \ | |
825 | } while (0) | |
826 | #define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8) | |
827 | #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG ) | |
828 | #endif | |
829 | ||
830 | #define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT ) | |
831 | #define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT ) | |
832 | #define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG ) | |
833 | #define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG ) | |
834 | #define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG ) | |
835 | #define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG ) | |
836 | #define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG ) | |
837 | #define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG ) | |
838 | #define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG ) | |
839 | #define SMC_GET_MII() SMC_inw( ioaddr, MII_REG ) | |
840 | #define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG ) | |
841 | #define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG ) | |
842 | #define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG ) | |
843 | #define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG ) | |
844 | #define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG ) | |
845 | #define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) | |
846 | #define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) | |
847 | #define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) | |
848 | #define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) | |
849 | #define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) | |
850 | #define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) | |
851 | #define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG ) | |
852 | #define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG ) | |
853 | #define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG ) | |
854 | #define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG ) | |
855 | ||
856 | #ifndef SMC_GET_MAC_ADDR | |
857 | #define SMC_GET_MAC_ADDR(addr) \ | |
858 | do { \ | |
859 | unsigned int __v; \ | |
860 | __v = SMC_inw( ioaddr, ADDR0_REG ); \ | |
861 | addr[0] = __v; addr[1] = __v >> 8; \ | |
862 | __v = SMC_inw( ioaddr, ADDR1_REG ); \ | |
863 | addr[2] = __v; addr[3] = __v >> 8; \ | |
864 | __v = SMC_inw( ioaddr, ADDR2_REG ); \ | |
865 | addr[4] = __v; addr[5] = __v >> 8; \ | |
866 | } while (0) | |
867 | #endif | |
868 | ||
869 | #define SMC_SET_MAC_ADDR(addr) \ | |
870 | do { \ | |
871 | SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ | |
872 | SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ | |
873 | SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ | |
874 | } while (0) | |
875 | ||
876 | #define SMC_SET_MCAST(x) \ | |
877 | do { \ | |
878 | const unsigned char *mt = (x); \ | |
879 | SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ | |
880 | SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ | |
881 | SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ | |
882 | SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ | |
883 | } while (0) | |
884 | ||
885 | #if SMC_CAN_USE_32BIT | |
886 | /* | |
887 | * Some setups just can't write 8 or 16 bits reliably when not aligned | |
888 | * to a 32 bit boundary. I tell you that exists! | |
889 | * We re-do the ones here that can be easily worked around if they can have | |
890 | * their low parts written to 0 without adverse effects. | |
891 | */ | |
892 | #undef SMC_SELECT_BANK | |
893 | #define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT ) | |
894 | #undef SMC_SET_RPC | |
895 | #define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) ) | |
896 | #undef SMC_SET_PN | |
897 | #define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) ) | |
898 | #undef SMC_SET_PTR | |
899 | #define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) ) | |
900 | #endif | |
901 | ||
902 | #if SMC_CAN_USE_32BIT | |
903 | #define SMC_PUT_PKT_HDR(status, length) \ | |
904 | SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG ) | |
905 | #define SMC_GET_PKT_HDR(status, length) \ | |
906 | do { \ | |
907 | unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \ | |
908 | (status) = __val & 0xffff; \ | |
909 | (length) = __val >> 16; \ | |
910 | } while (0) | |
911 | #else | |
912 | #define SMC_PUT_PKT_HDR(status, length) \ | |
913 | do { \ | |
914 | SMC_outw( status, ioaddr, DATA_REG ); \ | |
915 | SMC_outw( length, ioaddr, DATA_REG ); \ | |
916 | } while (0) | |
917 | #define SMC_GET_PKT_HDR(status, length) \ | |
918 | do { \ | |
919 | (status) = SMC_inw( ioaddr, DATA_REG ); \ | |
920 | (length) = SMC_inw( ioaddr, DATA_REG ); \ | |
921 | } while (0) | |
922 | #endif | |
923 | ||
924 | #if SMC_CAN_USE_32BIT | |
925 | #define _SMC_PUSH_DATA(p, l) \ | |
926 | do { \ | |
927 | char *__ptr = (p); \ | |
928 | int __len = (l); \ | |
929 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ | |
930 | __len -= 2; \ | |
931 | SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \ | |
932 | __ptr += 2; \ | |
933 | } \ | |
934 | SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \ | |
935 | if (__len & 2) { \ | |
936 | __ptr += (__len & ~3); \ | |
937 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ | |
938 | } \ | |
939 | } while (0) | |
940 | #define _SMC_PULL_DATA(p, l) \ | |
941 | do { \ | |
942 | char *__ptr = (p); \ | |
943 | int __len = (l); \ | |
944 | if ((unsigned long)__ptr & 2) { \ | |
945 | /* \ | |
946 | * We want 32bit alignment here. \ | |
947 | * Since some buses perform a full 32bit \ | |
948 | * fetch even for 16bit data we can't use \ | |
949 | * SMC_inw() here. Back both source (on chip \ | |
950 | * and destination) pointers of 2 bytes. \ | |
951 | */ \ | |
952 | __ptr -= 2; \ | |
953 | __len += 2; \ | |
954 | SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ | |
955 | } \ | |
956 | __len += 2; \ | |
957 | SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \ | |
958 | } while (0) | |
959 | #elif SMC_CAN_USE_16BIT | |
960 | #define _SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 ) | |
961 | #define _SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 ) | |
962 | #elif SMC_CAN_USE_8BIT | |
963 | #define _SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l ) | |
964 | #define _SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l ) | |
965 | #endif | |
966 | ||
967 | #if ! SMC_CAN_USE_16BIT | |
968 | #define SMC_outw(x, ioaddr, reg) \ | |
969 | do { \ | |
970 | unsigned int __val16 = (x); \ | |
971 | SMC_outb( __val16, ioaddr, reg ); \ | |
972 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
973 | } while (0) | |
974 | #define SMC_inw(ioaddr, reg) \ | |
975 | ({ \ | |
976 | unsigned int __val16; \ | |
977 | __val16 = SMC_inb( ioaddr, reg ); \ | |
978 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
979 | __val16; \ | |
980 | }) | |
981 | #endif | |
982 | ||
983 | #if SMC_CAN_USE_DATACS | |
984 | #define SMC_PUSH_DATA(p, l) \ | |
985 | if ( lp->datacs ) { \ | |
986 | unsigned char *__ptr = (p); \ | |
987 | int __len = (l); \ | |
988 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ | |
989 | __len -= 2; \ | |
990 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ | |
991 | __ptr += 2; \ | |
992 | } \ | |
993 | outsl(lp->datacs, __ptr, __len >> 2); \ | |
994 | if (__len & 2) { \ | |
995 | __ptr += (__len & ~3); \ | |
996 | SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \ | |
997 | } \ | |
998 | } else { \ | |
999 | _SMC_PUSH_DATA(p, l); \ | |
1000 | } | |
1001 | ||
1002 | #define SMC_PULL_DATA(p, l) \ | |
1003 | if ( lp->datacs ) { \ | |
1004 | unsigned char *__ptr = (p); \ | |
1005 | int __len = (l); \ | |
1006 | if ((unsigned long)__ptr & 2) { \ | |
1007 | /* \ | |
1008 | * We want 32bit alignment here. \ | |
1009 | * Since some buses perform a full 32bit \ | |
1010 | * fetch even for 16bit data we can't use \ | |
1011 | * SMC_inw() here. Back both source (on chip \ | |
1012 | * and destination) pointers of 2 bytes. \ | |
1013 | */ \ | |
1014 | __ptr -= 2; \ | |
1015 | __len += 2; \ | |
1016 | SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \ | |
1017 | } \ | |
1018 | __len += 2; \ | |
1019 | insl( lp->datacs, __ptr, __len >> 2); \ | |
1020 | } else { \ | |
1021 | _SMC_PULL_DATA(p, l); \ | |
1022 | } | |
1023 | #else | |
1024 | #define SMC_PUSH_DATA(p, l) _SMC_PUSH_DATA(p, l) | |
1025 | #define SMC_PULL_DATA(p, l) _SMC_PULL_DATA(p, l) | |
1026 | #endif | |
1027 | ||
1028 | #if !defined (SMC_INTERRUPT_PREAMBLE) | |
1029 | # define SMC_INTERRUPT_PREAMBLE | |
1030 | #endif | |
1031 | ||
1032 | #endif /* _SMC91X_H_ */ |