Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * Definitions for the new Marvell Yukon 2 driver. | |
3 | */ | |
4 | #ifndef _SKY2_H | |
5 | #define _SKY2_H | |
6 | ||
14d0263f SH |
7 | #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ |
8 | ||
7bd656d1 | 9 | /* PCI config registers */ |
977bdf06 SH |
10 | enum { |
11 | PCI_DEV_REG1 = 0x40, | |
12 | PCI_DEV_REG2 = 0x44, | |
7bd656d1 | 13 | PCI_DEV_STATUS = 0x7c, |
977bdf06 SH |
14 | PCI_DEV_REG3 = 0x80, |
15 | PCI_DEV_REG4 = 0x84, | |
16 | PCI_DEV_REG5 = 0x88, | |
fc99fe06 SH |
17 | PCI_CFG_REG_0 = 0x90, |
18 | PCI_CFG_REG_1 = 0x94, | |
977bdf06 | 19 | }; |
cd28ab6a | 20 | |
7bd656d1 SH |
21 | enum { |
22 | PEX_DEV_CAP = 0xe4, | |
23 | PEX_DEV_CTRL = 0xe8, | |
24 | PEX_DEV_STA = 0xea, | |
25 | PEX_LNK_STAT = 0xf2, | |
26 | PEX_UNC_ERR_STAT= 0x104, | |
27 | }; | |
28 | ||
cd28ab6a SH |
29 | /* Yukon-2 */ |
30 | enum pci_dev_reg_1 { | |
31 | PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ | |
32 | PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ | |
fc99fe06 | 33 | PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ |
cd28ab6a SH |
34 | PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ |
35 | PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ | |
36 | PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ | |
37 | PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ | |
e3173832 | 38 | PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ |
cd28ab6a SH |
39 | }; |
40 | ||
41 | enum pci_dev_reg_2 { | |
42 | PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ | |
43 | PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ | |
44 | PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ | |
45 | ||
46 | PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ | |
47 | PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ | |
48 | PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ | |
49 | PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ | |
50 | ||
51 | PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ | |
52 | }; | |
53 | ||
977bdf06 SH |
54 | /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ |
55 | enum pci_dev_reg_4 { | |
56 | /* (Link Training & Status State Machine) */ | |
57 | P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ | |
58 | /* (Active State Power Management) */ | |
59 | P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ | |
60 | P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ | |
61 | P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ | |
62 | P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ | |
63 | ||
64 | P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ | |
65 | P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ | |
66 | P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ | |
67 | P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ | |
68 | P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ | |
69 | P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | |
70 | | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, | |
71 | }; | |
72 | ||
fc99fe06 SH |
73 | /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ |
74 | enum pci_dev_reg_5 { | |
75 | /* Bit 31..27: for A3 & later */ | |
76 | P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */ | |
77 | P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ | |
78 | P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */ | |
79 | P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */ | |
80 | /* Bit 26..16: Release Clock on Event */ | |
81 | P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */ | |
82 | P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */ | |
83 | P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */ | |
84 | P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */ | |
85 | P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */ | |
86 | P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */ | |
87 | P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */ | |
88 | P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */ | |
89 | P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */ | |
90 | P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */ | |
91 | P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */ | |
92 | ||
93 | /* Bit 10.. 0: Mask for Gate Clock */ | |
94 | P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */ | |
95 | P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */ | |
96 | P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */ | |
97 | P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */ | |
98 | P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */ | |
99 | P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */ | |
100 | P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */ | |
101 | P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */ | |
102 | P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */ | |
103 | P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */ | |
104 | P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */ | |
105 | ||
106 | PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET | | |
107 | P_REL_INT_FIFO_N_EMPTY | | |
108 | P_REL_PCIE_EXIT_L1_ST | | |
109 | P_REL_PCIE_RX_EX_IDLE | | |
110 | P_GAT_GPHY_N_REC_PACKET | | |
111 | P_GAT_INT_FIFO_EMPTY | | |
112 | P_GAT_PCIE_ENTER_L1_ST | | |
113 | P_GAT_PCIE_RX_EL_IDLE, | |
114 | }; | |
115 | ||
116 | #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */ | |
117 | enum pci_cfg_reg1 { | |
118 | P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */ | |
119 | /* Bit 23..21: Release Clock on Event */ | |
120 | P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */ | |
121 | P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */ | |
122 | P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */ | |
123 | /* Bit 20..18: Gate Clock on Event */ | |
124 | P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */ | |
125 | P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */ | |
126 | P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */ | |
127 | P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ | |
128 | P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */ | |
129 | ||
130 | P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */ | |
131 | ||
132 | P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */ | |
133 | P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */ | |
134 | ||
135 | PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST | | |
136 | P_CF1_REL_LDR_NOT_FIN | | |
137 | P_CF1_REL_VMAIN_AVLBL | | |
138 | P_CF1_REL_PCIE_RESET | | |
139 | P_CF1_GAT_LDR_NOT_FIN | | |
140 | P_CF1_GAT_PCIE_RESET | | |
141 | P_CF1_PRST_PHY_CLKREQ | | |
142 | P_CF1_ENA_CFG_LDR_DONE | | |
143 | P_CF1_ENA_TXBMU_RD_IDLE | | |
144 | P_CF1_ENA_TXBMU_WR_IDLE, | |
145 | }; | |
146 | ||
cd28ab6a SH |
147 | |
148 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ | |
149 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | |
150 | PCI_STATUS_REC_MASTER_ABORT | \ | |
151 | PCI_STATUS_REC_TARGET_ABORT | \ | |
152 | PCI_STATUS_PARITY) | |
7bd656d1 SH |
153 | |
154 | enum pex_dev_ctrl { | |
155 | PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */ | |
156 | PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */ | |
157 | PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */ | |
158 | PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */ | |
159 | PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */ | |
160 | PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */ | |
161 | PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */ | |
162 | PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */ | |
163 | PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */ | |
164 | PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */ | |
165 | PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */ | |
166 | }; | |
167 | #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK) | |
168 | ||
169 | /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ | |
170 | enum pex_err { | |
171 | PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */ | |
172 | ||
173 | PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */ | |
174 | ||
175 | PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */ | |
176 | ||
177 | PEX_COMP_TO = 1<<14, /* Completion Timeout */ | |
178 | PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */ | |
179 | PEX_POIS_TLP = 1<<12, /* Poisoned TLP */ | |
180 | ||
181 | PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */ | |
182 | PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P), | |
183 | }; | |
184 | ||
185 | ||
cd28ab6a SH |
186 | enum csr_regs { |
187 | B0_RAP = 0x0000, | |
188 | B0_CTST = 0x0004, | |
189 | B0_Y2LED = 0x0005, | |
190 | B0_POWER_CTRL = 0x0007, | |
191 | B0_ISRC = 0x0008, | |
192 | B0_IMSK = 0x000c, | |
193 | B0_HWE_ISRC = 0x0010, | |
194 | B0_HWE_IMSK = 0x0014, | |
cd28ab6a SH |
195 | |
196 | /* Special ISR registers (Yukon-2 only) */ | |
197 | B0_Y2_SP_ISRC2 = 0x001c, | |
198 | B0_Y2_SP_ISRC3 = 0x0020, | |
199 | B0_Y2_SP_EISR = 0x0024, | |
200 | B0_Y2_SP_LISR = 0x0028, | |
201 | B0_Y2_SP_ICR = 0x002c, | |
202 | ||
203 | B2_MAC_1 = 0x0100, | |
204 | B2_MAC_2 = 0x0108, | |
205 | B2_MAC_3 = 0x0110, | |
206 | B2_CONN_TYP = 0x0118, | |
207 | B2_PMD_TYP = 0x0119, | |
208 | B2_MAC_CFG = 0x011a, | |
209 | B2_CHIP_ID = 0x011b, | |
210 | B2_E_0 = 0x011c, | |
488f84fd | 211 | |
cd28ab6a SH |
212 | B2_Y2_CLK_GATE = 0x011d, |
213 | B2_Y2_HW_RES = 0x011e, | |
214 | B2_E_3 = 0x011f, | |
215 | B2_Y2_CLK_CTRL = 0x0120, | |
488f84fd | 216 | |
cd28ab6a SH |
217 | B2_TI_INI = 0x0130, |
218 | B2_TI_VAL = 0x0134, | |
219 | B2_TI_CTRL = 0x0138, | |
220 | B2_TI_TEST = 0x0139, | |
488f84fd | 221 | |
cd28ab6a SH |
222 | B2_TST_CTRL1 = 0x0158, |
223 | B2_TST_CTRL2 = 0x0159, | |
224 | B2_GP_IO = 0x015c, | |
488f84fd | 225 | |
cd28ab6a SH |
226 | B2_I2C_CTRL = 0x0160, |
227 | B2_I2C_DATA = 0x0164, | |
228 | B2_I2C_IRQ = 0x0168, | |
229 | B2_I2C_SW = 0x016c, | |
cd28ab6a SH |
230 | |
231 | B3_RAM_ADDR = 0x0180, | |
232 | B3_RAM_DATA_LO = 0x0184, | |
233 | B3_RAM_DATA_HI = 0x0188, | |
234 | ||
235 | /* RAM Interface Registers */ | |
236 | /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ | |
237 | /* | |
238 | * The HW-Spec. calls this registers Timeout Value 0..11. But this names are | |
239 | * not usable in SW. Please notice these are NOT real timeouts, these are | |
240 | * the number of qWords transferred continuously. | |
241 | */ | |
242 | #define RAM_BUFFER(port, reg) (reg | (port <<6)) | |
243 | ||
244 | B3_RI_WTO_R1 = 0x0190, | |
245 | B3_RI_WTO_XA1 = 0x0191, | |
246 | B3_RI_WTO_XS1 = 0x0192, | |
247 | B3_RI_RTO_R1 = 0x0193, | |
248 | B3_RI_RTO_XA1 = 0x0194, | |
249 | B3_RI_RTO_XS1 = 0x0195, | |
250 | B3_RI_WTO_R2 = 0x0196, | |
251 | B3_RI_WTO_XA2 = 0x0197, | |
252 | B3_RI_WTO_XS2 = 0x0198, | |
253 | B3_RI_RTO_R2 = 0x0199, | |
254 | B3_RI_RTO_XA2 = 0x019a, | |
255 | B3_RI_RTO_XS2 = 0x019b, | |
256 | B3_RI_TO_VAL = 0x019c, | |
257 | B3_RI_CTRL = 0x01a0, | |
258 | B3_RI_TEST = 0x01a2, | |
259 | B3_MA_TOINI_RX1 = 0x01b0, | |
260 | B3_MA_TOINI_RX2 = 0x01b1, | |
261 | B3_MA_TOINI_TX1 = 0x01b2, | |
262 | B3_MA_TOINI_TX2 = 0x01b3, | |
263 | B3_MA_TOVAL_RX1 = 0x01b4, | |
264 | B3_MA_TOVAL_RX2 = 0x01b5, | |
265 | B3_MA_TOVAL_TX1 = 0x01b6, | |
266 | B3_MA_TOVAL_TX2 = 0x01b7, | |
267 | B3_MA_TO_CTRL = 0x01b8, | |
268 | B3_MA_TO_TEST = 0x01ba, | |
269 | B3_MA_RCINI_RX1 = 0x01c0, | |
270 | B3_MA_RCINI_RX2 = 0x01c1, | |
271 | B3_MA_RCINI_TX1 = 0x01c2, | |
272 | B3_MA_RCINI_TX2 = 0x01c3, | |
273 | B3_MA_RCVAL_RX1 = 0x01c4, | |
274 | B3_MA_RCVAL_RX2 = 0x01c5, | |
275 | B3_MA_RCVAL_TX1 = 0x01c6, | |
276 | B3_MA_RCVAL_TX2 = 0x01c7, | |
277 | B3_MA_RC_CTRL = 0x01c8, | |
278 | B3_MA_RC_TEST = 0x01ca, | |
279 | B3_PA_TOINI_RX1 = 0x01d0, | |
280 | B3_PA_TOINI_RX2 = 0x01d4, | |
281 | B3_PA_TOINI_TX1 = 0x01d8, | |
282 | B3_PA_TOINI_TX2 = 0x01dc, | |
283 | B3_PA_TOVAL_RX1 = 0x01e0, | |
284 | B3_PA_TOVAL_RX2 = 0x01e4, | |
285 | B3_PA_TOVAL_TX1 = 0x01e8, | |
286 | B3_PA_TOVAL_TX2 = 0x01ec, | |
287 | B3_PA_CTRL = 0x01f0, | |
288 | B3_PA_TEST = 0x01f2, | |
289 | ||
290 | Y2_CFG_SPC = 0x1c00, | |
291 | }; | |
292 | ||
cd28ab6a SH |
293 | /* B0_CTST 16 bit Control/Status register */ |
294 | enum { | |
793b883e | 295 | Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ |
cd28ab6a | 296 | Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ |
86a31a75 SH |
297 | Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */ |
298 | Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */ | |
cd28ab6a SH |
299 | Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ |
300 | Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ | |
301 | Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ | |
302 | Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ | |
303 | Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ | |
304 | Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ | |
305 | ||
cd28ab6a SH |
306 | CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ |
307 | CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ | |
308 | CS_STOP_DONE = 1<<5, /* Stop Master is finished */ | |
309 | CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ | |
310 | CS_MRST_CLR = 1<<3, /* Clear Master reset */ | |
311 | CS_MRST_SET = 1<<2, /* Set Master reset */ | |
312 | CS_RST_CLR = 1<<1, /* Clear Software reset */ | |
313 | CS_RST_SET = 1, /* Set Software reset */ | |
793b883e | 314 | }; |
cd28ab6a SH |
315 | |
316 | /* B0_LED 8 Bit LED register */ | |
793b883e | 317 | enum { |
cd28ab6a SH |
318 | /* Bit 7.. 2: reserved */ |
319 | LED_STAT_ON = 1<<1, /* Status LED on */ | |
793b883e SH |
320 | LED_STAT_OFF = 1, /* Status LED off */ |
321 | }; | |
cd28ab6a SH |
322 | |
323 | /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ | |
793b883e | 324 | enum { |
cd28ab6a SH |
325 | PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ |
326 | PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ | |
327 | PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ | |
328 | PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ | |
329 | PC_VAUX_ON = 1<<3, /* Switch VAUX On */ | |
330 | PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ | |
331 | PC_VCC_ON = 1<<1, /* Switch VCC On */ | |
332 | PC_VCC_OFF = 1<<0, /* Switch VCC Off */ | |
333 | }; | |
334 | ||
335 | /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ | |
336 | ||
337 | /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ | |
338 | /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ | |
339 | /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ | |
340 | /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ | |
341 | enum { | |
342 | Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ | |
343 | Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ | |
344 | Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ | |
345 | ||
346 | Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ | |
347 | Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ | |
348 | Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ | |
349 | Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ | |
350 | ||
351 | Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ | |
352 | Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ | |
353 | Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ | |
354 | Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ | |
355 | Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ | |
356 | ||
357 | Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ | |
358 | Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ | |
359 | Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ | |
360 | Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ | |
361 | Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ | |
362 | ||
e07b1aa8 | 363 | Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, |
d257924e SH |
364 | Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
365 | | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, | |
366 | Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | |
367 | | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, | |
40b01727 SH |
368 | Y2_IS_ERROR = Y2_IS_HW_ERR | |
369 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | | |
370 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, | |
cd28ab6a SH |
371 | }; |
372 | ||
373 | /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ | |
374 | enum { | |
375 | IS_ERR_MSK = 0x00003fff,/* All Error bits */ | |
376 | ||
377 | IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ | |
378 | IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ | |
379 | IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ | |
380 | IS_IRQ_STAT = 1<<10, /* IRQ status exception */ | |
381 | IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ | |
382 | IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ | |
383 | IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ | |
384 | IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ | |
385 | IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ | |
386 | IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ | |
387 | IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ | |
388 | IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ | |
389 | IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ | |
390 | IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ | |
391 | }; | |
392 | ||
393 | /* Hardware error interrupt mask for Yukon 2 */ | |
394 | enum { | |
395 | Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ | |
396 | Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ | |
397 | Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ | |
398 | Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ | |
399 | Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ | |
400 | Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ | |
401 | /* Link 2 */ | |
402 | Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ | |
403 | Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ | |
404 | Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ | |
405 | Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ | |
406 | Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ | |
407 | Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ | |
408 | /* Link 1 */ | |
409 | Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ | |
410 | Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ | |
411 | Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ | |
412 | Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ | |
413 | Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ | |
414 | Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ | |
415 | ||
416 | Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | | |
417 | Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, | |
418 | Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | | |
419 | Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, | |
420 | ||
793b883e | 421 | Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | |
5a5b1ea0 | 422 | Y2_IS_PCI_EXP | |
cd28ab6a SH |
423 | Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, |
424 | }; | |
425 | ||
426 | /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ | |
427 | enum { | |
428 | DPT_START = 1<<1, | |
429 | DPT_STOP = 1<<0, | |
430 | }; | |
431 | ||
432 | /* B2_TST_CTRL1 8 bit Test Control Register 1 */ | |
433 | enum { | |
434 | TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ | |
435 | TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ | |
436 | TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ | |
437 | TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ | |
438 | TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ | |
439 | TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ | |
440 | TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ | |
441 | TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ | |
442 | }; | |
443 | ||
444 | /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ | |
445 | enum { | |
446 | CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ | |
447 | /* Bit 3.. 2: reserved */ | |
448 | CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ | |
449 | CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ | |
450 | }; | |
451 | ||
452 | /* B2_CHIP_ID 8 bit Chip Identification Number */ | |
453 | enum { | |
cd28ab6a | 454 | CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ |
5a5b1ea0 | 455 | CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ |
93745494 | 456 | CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */ |
cd28ab6a SH |
457 | CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ |
458 | CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ | |
459 | ||
460 | CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ | |
461 | CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ | |
462 | CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ | |
ed6d32c7 | 463 | |
8df9a876 SH |
464 | CHIP_REV_YU_EC_U_A0 = 1, |
465 | CHIP_REV_YU_EC_U_A1 = 2, | |
466 | CHIP_REV_YU_EC_U_B0 = 3, | |
467 | ||
468 | CHIP_REV_YU_FE_A1 = 1, | |
469 | CHIP_REV_YU_FE_A2 = 2, | |
470 | ||
cd28ab6a SH |
471 | }; |
472 | ||
473 | /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ | |
474 | enum { | |
d571b694 | 475 | Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ |
cd28ab6a SH |
476 | Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ |
477 | Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ | |
478 | Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ | |
d571b694 | 479 | Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ |
cd28ab6a SH |
480 | Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ |
481 | Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ | |
482 | Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ | |
483 | }; | |
484 | ||
485 | /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ | |
486 | enum { | |
487 | CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ | |
488 | CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ | |
489 | CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ | |
490 | }; | |
491 | #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) | |
492 | #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) | |
493 | ||
494 | ||
495 | /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ | |
496 | enum { | |
497 | Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ | |
498 | #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) | |
499 | Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ | |
500 | Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ | |
501 | #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) | |
502 | #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) | |
503 | Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ | |
504 | Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ | |
505 | }; | |
506 | ||
507 | /* B2_TI_CTRL 8 bit Timer control */ | |
508 | /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ | |
509 | enum { | |
510 | TIM_START = 1<<2, /* Start Timer */ | |
511 | TIM_STOP = 1<<1, /* Stop Timer */ | |
512 | TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ | |
513 | }; | |
514 | ||
515 | /* B2_TI_TEST 8 Bit Timer Test */ | |
516 | /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ | |
517 | /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ | |
518 | enum { | |
519 | TIM_T_ON = 1<<2, /* Test mode on */ | |
520 | TIM_T_OFF = 1<<1, /* Test mode off */ | |
521 | TIM_T_STEP = 1<<0, /* Test step */ | |
522 | }; | |
523 | ||
524 | /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ | |
525 | /* Bit 31..19: reserved */ | |
526 | #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ | |
527 | /* RAM Interface Registers */ | |
528 | ||
d571b694 | 529 | /* B3_RI_CTRL 16 bit RAM Interface Control Register */ |
cd28ab6a SH |
530 | enum { |
531 | RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ | |
532 | RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ | |
533 | ||
534 | RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ | |
535 | RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ | |
536 | }; | |
537 | ||
538 | #define SK_RI_TO_53 36 /* RAM interface timeout */ | |
539 | ||
540 | ||
541 | /* Port related registers FIFO, and Arbiter */ | |
542 | #define SK_REG(port,reg) (((port)<<7)+(reg)) | |
543 | ||
544 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ | |
545 | /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ | |
546 | /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ | |
547 | /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ | |
548 | /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ | |
549 | ||
550 | #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ | |
551 | ||
552 | /* TXA_CTRL 8 bit Tx Arbiter Control Register */ | |
553 | enum { | |
554 | TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ | |
555 | TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ | |
556 | TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ | |
557 | TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ | |
558 | TXA_START_RC = 1<<3, /* Start sync Rate Control */ | |
559 | TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ | |
560 | TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ | |
561 | TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ | |
562 | }; | |
563 | ||
564 | /* | |
565 | * Bank 4 - 5 | |
566 | */ | |
567 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ | |
568 | enum { | |
569 | TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ | |
570 | TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ | |
571 | TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ | |
572 | TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ | |
573 | TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ | |
574 | TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ | |
575 | TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ | |
576 | }; | |
577 | ||
578 | ||
579 | enum { | |
580 | B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ | |
581 | B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ | |
582 | B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ | |
583 | B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ | |
584 | B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ | |
585 | B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ | |
586 | B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ | |
587 | B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ | |
588 | B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ | |
589 | }; | |
590 | ||
591 | /* Queue Register Offsets, use Q_ADDR() to access */ | |
592 | enum { | |
593 | B8_Q_REGS = 0x0400, /* base of Queue registers */ | |
594 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ | |
595 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ | |
596 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ | |
597 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ | |
598 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ | |
599 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ | |
600 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ | |
601 | Q_F = 0x38, /* 32 bit Flag Register */ | |
602 | Q_T1 = 0x3c, /* 32 bit Test Register 1 */ | |
603 | Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ | |
604 | Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ | |
605 | Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ | |
606 | Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ | |
607 | Q_T2 = 0x40, /* 32 bit Test Register 2 */ | |
608 | Q_T3 = 0x44, /* 32 bit Test Register 3 */ | |
609 | ||
610 | /* Yukon-2 */ | |
611 | Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ | |
612 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ | |
613 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ | |
614 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ | |
615 | Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ | |
616 | Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ | |
617 | Q_RL = 0x4a, /* 8 bit FIFO Read Level */ | |
618 | Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ | |
619 | Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ | |
620 | Q_WL = 0x4e, /* 8 bit FIFO Write Level */ | |
621 | Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ | |
622 | }; | |
623 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) | |
624 | ||
977bdf06 SH |
625 | /* Q_F 32 bit Flag Register */ |
626 | enum { | |
627 | F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ | |
628 | F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ | |
629 | F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ | |
630 | F_WM_REACHED = 1<<25, /* Watermark reached */ | |
631 | F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ | |
632 | F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ | |
633 | F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ | |
634 | }; | |
cd28ab6a SH |
635 | |
636 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ | |
637 | enum { | |
638 | Y2_B8_PREF_REGS = 0x0450, | |
639 | ||
640 | PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ | |
641 | PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ | |
642 | PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ | |
643 | PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ | |
644 | PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ | |
645 | PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ | |
646 | PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ | |
647 | PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ | |
648 | PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ | |
649 | PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ | |
650 | ||
651 | PREF_UNIT_MASK_IDX = 0x0fff, | |
652 | }; | |
653 | #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) | |
654 | ||
655 | /* RAM Buffer Register Offsets */ | |
656 | enum { | |
657 | ||
658 | RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ | |
659 | RB_END = 0x04,/* 32 bit RAM Buffer End Address */ | |
660 | RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ | |
661 | RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ | |
662 | RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ | |
663 | RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ | |
664 | RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ | |
665 | RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ | |
666 | /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ | |
667 | RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ | |
668 | RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ | |
669 | RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ | |
670 | RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ | |
671 | RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ | |
672 | }; | |
673 | ||
674 | /* Receive and Transmit Queues */ | |
675 | enum { | |
676 | Q_R1 = 0x0000, /* Receive Queue 1 */ | |
677 | Q_R2 = 0x0080, /* Receive Queue 2 */ | |
678 | Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ | |
679 | Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ | |
680 | Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ | |
681 | Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ | |
682 | }; | |
683 | ||
684 | /* Different PHY Types */ | |
685 | enum { | |
686 | PHY_ADDR_MARV = 0, | |
687 | }; | |
688 | ||
0efdf262 | 689 | #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) |
cd28ab6a SH |
690 | |
691 | ||
692 | enum { | |
693 | LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ | |
694 | LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ | |
695 | LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ | |
696 | LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ | |
697 | ||
698 | LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ | |
699 | ||
700 | /* Receive GMAC FIFO (YUKON and Yukon-2) */ | |
701 | ||
702 | RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ | |
703 | RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ | |
704 | RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ | |
705 | RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ | |
706 | RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ | |
707 | RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ | |
5a5b1ea0 SH |
708 | RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ |
709 | RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ | |
cd28ab6a SH |
710 | RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ |
711 | RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ | |
712 | ||
713 | RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ | |
714 | ||
715 | RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ | |
716 | ||
717 | RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ | |
718 | }; | |
719 | ||
720 | ||
721 | /* Q_BC 32 bit Current Byte Counter */ | |
722 | ||
723 | /* BMU Control Status Registers */ | |
724 | /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ | |
725 | /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ | |
726 | /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ | |
727 | /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ | |
728 | /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ | |
729 | /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ | |
730 | /* Q_CSR 32 bit BMU Control/Status Register */ | |
731 | ||
732 | /* Rx BMU Control / Status Registers (Yukon-2) */ | |
733 | enum { | |
734 | BMU_IDLE = 1<<31, /* BMU Idle State */ | |
735 | BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ | |
736 | BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ | |
737 | ||
738 | BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ | |
739 | BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ | |
740 | BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ | |
741 | BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ | |
742 | BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ | |
d571b694 | 743 | BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ |
cd28ab6a SH |
744 | BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ |
745 | BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ | |
746 | BMU_START = 1<<8, /* Start Rx/Tx Queue */ | |
747 | BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ | |
748 | BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ | |
749 | BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ | |
750 | BMU_FIFO_RST = 1<<4, /* Reset FIFO */ | |
751 | BMU_OP_ON = 1<<3, /* BMU Operational On */ | |
752 | BMU_OP_OFF = 1<<2, /* BMU Operational Off */ | |
753 | BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ | |
754 | BMU_RST_SET = 1<<0, /* Set BMU Reset */ | |
755 | ||
756 | BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, | |
757 | BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | | |
758 | BMU_FIFO_ENA | BMU_OP_ON, | |
af4ed7e6 SH |
759 | |
760 | BMU_WM_DEFAULT = 0x600, | |
c3905bc4 | 761 | BMU_WM_PEX = 0x80, |
cd28ab6a SH |
762 | }; |
763 | ||
764 | /* Tx BMU Control / Status Registers (Yukon-2) */ | |
765 | /* Bit 31: same as for Rx */ | |
766 | enum { | |
767 | BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ | |
768 | BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ | |
d571b694 | 769 | BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ |
cd28ab6a SH |
770 | }; |
771 | ||
772 | /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ | |
773 | /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ | |
774 | enum { | |
775 | PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ | |
776 | PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ | |
777 | PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ | |
778 | PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ | |
779 | }; | |
780 | ||
781 | /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ | |
782 | /* RB_START 32 bit RAM Buffer Start Address */ | |
783 | /* RB_END 32 bit RAM Buffer End Address */ | |
784 | /* RB_WP 32 bit RAM Buffer Write Pointer */ | |
785 | /* RB_RP 32 bit RAM Buffer Read Pointer */ | |
786 | /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ | |
787 | /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ | |
788 | /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ | |
789 | /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ | |
790 | /* RB_PC 32 bit RAM Buffer Packet Counter */ | |
791 | /* RB_LEV 32 bit RAM Buffer Level Register */ | |
792 | ||
793 | #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ | |
794 | /* RB_TST2 8 bit RAM Buffer Test Register 2 */ | |
795 | /* RB_TST1 8 bit RAM Buffer Test Register 1 */ | |
796 | ||
797 | /* RB_CTRL 8 bit RAM Buffer Control Register */ | |
798 | enum { | |
799 | RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ | |
800 | RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ | |
801 | RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ | |
802 | RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ | |
803 | RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ | |
804 | RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ | |
805 | }; | |
806 | ||
807 | ||
808 | /* Transmit GMAC FIFO (YUKON only) */ | |
809 | enum { | |
810 | TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ | |
811 | TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ | |
812 | TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ | |
813 | ||
814 | TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ | |
815 | TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ | |
816 | TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ | |
817 | ||
818 | TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ | |
819 | TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ | |
820 | TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ | |
b628ed98 SH |
821 | |
822 | /* Threshold values for Yukon-EC Ultra and Extreme */ | |
823 | ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ | |
824 | ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ | |
825 | ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ | |
cd28ab6a SH |
826 | }; |
827 | ||
828 | /* Descriptor Poll Timer Registers */ | |
829 | enum { | |
830 | B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ | |
831 | B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ | |
832 | B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ | |
833 | ||
834 | B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ | |
835 | }; | |
836 | ||
837 | /* Time Stamp Timer Registers (YUKON only) */ | |
838 | enum { | |
839 | GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ | |
840 | GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ | |
841 | GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ | |
842 | }; | |
843 | ||
844 | /* Polling Unit Registers (Yukon-2 only) */ | |
845 | enum { | |
846 | POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ | |
847 | POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ | |
848 | ||
849 | POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ | |
850 | POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ | |
851 | }; | |
852 | ||
93745494 SH |
853 | enum { |
854 | SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ | |
855 | SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ | |
856 | }; | |
857 | ||
858 | enum { | |
859 | CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ | |
860 | CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ | |
861 | CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ | |
862 | CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ | |
863 | CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ | |
864 | CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ | |
865 | HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ | |
866 | CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ | |
867 | HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ | |
868 | HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ | |
869 | }; | |
870 | ||
cd28ab6a SH |
871 | /* ASF Subsystem Registers (Yukon-2 only) */ |
872 | enum { | |
873 | B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ | |
874 | B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ | |
875 | B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ | |
876 | ||
877 | B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ | |
878 | B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ | |
879 | B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ | |
880 | B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ | |
881 | B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ | |
882 | B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ | |
883 | }; | |
884 | ||
885 | /* Status BMU Registers (Yukon-2 only)*/ | |
886 | enum { | |
887 | STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ | |
888 | STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ | |
889 | ||
890 | STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ | |
891 | STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ | |
892 | STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ | |
893 | STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ | |
894 | STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ | |
895 | STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ | |
896 | STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ | |
897 | STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ | |
898 | ||
899 | /* FIFO Control/Status Registers (Yukon-2 only)*/ | |
900 | STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ | |
901 | STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ | |
902 | STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ | |
903 | STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ | |
904 | STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ | |
905 | STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ | |
906 | STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ | |
907 | ||
908 | /* Level and ISR Timer Registers (Yukon-2 only)*/ | |
909 | STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ | |
910 | STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ | |
911 | STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ | |
912 | STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ | |
913 | STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ | |
914 | STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ | |
915 | STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ | |
916 | STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ | |
917 | STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ | |
918 | STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ | |
919 | STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ | |
920 | STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ | |
cd28ab6a SH |
921 | }; |
922 | ||
923 | enum { | |
924 | LINKLED_OFF = 0x01, | |
925 | LINKLED_ON = 0x02, | |
926 | LINKLED_LINKSYNC_OFF = 0x04, | |
927 | LINKLED_LINKSYNC_ON = 0x08, | |
928 | LINKLED_BLINK_OFF = 0x10, | |
929 | LINKLED_BLINK_ON = 0x20, | |
930 | }; | |
931 | ||
932 | /* GMAC and GPHY Control Registers (YUKON only) */ | |
933 | enum { | |
934 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ | |
935 | GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ | |
936 | GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ | |
937 | GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ | |
938 | GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ | |
939 | ||
940 | /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ | |
cd28ab6a SH |
941 | WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ |
942 | WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ | |
943 | WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ | |
944 | WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ | |
cd28ab6a SH |
945 | WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ |
946 | ||
947 | /* WOL Pattern Length Registers (YUKON only) */ | |
cd28ab6a SH |
948 | WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ |
949 | WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ | |
950 | ||
951 | /* WOL Pattern Counter Registers (YUKON only) */ | |
cd28ab6a SH |
952 | WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ |
953 | WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ | |
954 | }; | |
e3173832 | 955 | #define WOL_REGS(port, x) (x + (port)*0x80) |
cd28ab6a SH |
956 | |
957 | enum { | |
958 | WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ | |
959 | WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ | |
960 | }; | |
e3173832 | 961 | #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) |
cd28ab6a SH |
962 | |
963 | enum { | |
964 | BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ | |
965 | BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ | |
966 | }; | |
967 | ||
968 | /* | |
969 | * Marvel-PHY Registers, indirect addressed over GMAC | |
970 | */ | |
971 | enum { | |
972 | PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ | |
973 | PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ | |
974 | PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ | |
975 | PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ | |
976 | PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ | |
977 | PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ | |
978 | PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ | |
979 | PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ | |
980 | PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ | |
981 | /* Marvel-specific registers */ | |
982 | PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ | |
983 | PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ | |
984 | PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ | |
985 | PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ | |
986 | PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ | |
987 | PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ | |
988 | PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ | |
989 | PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ | |
990 | PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ | |
991 | PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ | |
992 | PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ | |
993 | PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ | |
994 | PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ | |
995 | PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ | |
996 | PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ | |
997 | PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ | |
998 | PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ | |
999 | PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ | |
1000 | ||
1001 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ | |
1002 | PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ | |
1003 | PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ | |
1004 | PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ | |
1005 | PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ | |
1006 | PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ | |
1007 | }; | |
1008 | ||
1009 | enum { | |
1010 | PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ | |
1011 | PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ | |
1012 | PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ | |
1013 | PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ | |
1014 | PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ | |
1015 | PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ | |
1016 | PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ | |
1017 | PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ | |
1018 | PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ | |
1019 | PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ | |
1020 | }; | |
1021 | ||
1022 | enum { | |
1023 | PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ | |
1024 | PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ | |
1025 | PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ | |
1026 | }; | |
1027 | ||
1028 | enum { | |
1029 | PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ | |
1030 | ||
1031 | PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ | |
1032 | PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ | |
1033 | PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ | |
1034 | PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ | |
1035 | PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ | |
1036 | PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ | |
1037 | PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ | |
1038 | }; | |
1039 | ||
1040 | enum { | |
1041 | PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ | |
1042 | PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ | |
1043 | PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ | |
1044 | }; | |
1045 | ||
1046 | /* different Marvell PHY Ids */ | |
1047 | enum { | |
1048 | PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ | |
1049 | ||
1050 | PHY_BCOM_ID1_A1 = 0x6041, | |
1051 | PHY_BCOM_ID1_B2 = 0x6043, | |
1052 | PHY_BCOM_ID1_C0 = 0x6044, | |
1053 | PHY_BCOM_ID1_C5 = 0x6047, | |
1054 | ||
977bdf06 | 1055 | PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ |
cd28ab6a | 1056 | PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ |
977bdf06 SH |
1057 | PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ |
1058 | PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ | |
1059 | PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ | |
1060 | PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ | |
cd28ab6a SH |
1061 | }; |
1062 | ||
1063 | /* Advertisement register bits */ | |
1064 | enum { | |
1065 | PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ | |
1066 | PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ | |
1067 | PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ | |
1068 | ||
1069 | PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ | |
1070 | PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ | |
1071 | PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ | |
1072 | PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ | |
1073 | PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ | |
1074 | PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ | |
1075 | PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ | |
1076 | PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ | |
1077 | PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ | |
1078 | PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, | |
1079 | PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | | |
1080 | PHY_AN_100HALF | PHY_AN_100FULL, | |
1081 | }; | |
1082 | ||
1083 | /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ | |
1084 | /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ | |
1085 | enum { | |
1086 | PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ | |
1087 | PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ | |
1088 | PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ | |
1089 | PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ | |
1090 | PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ | |
1091 | PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ | |
1092 | /* Bit 9..8: reserved */ | |
1093 | PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ | |
1094 | }; | |
1095 | ||
1096 | /** Marvell-Specific */ | |
1097 | enum { | |
1098 | PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ | |
1099 | PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ | |
1100 | PHY_M_AN_RF = 1<<13, /* Remote Fault */ | |
1101 | ||
1102 | PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ | |
1103 | PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ | |
1104 | PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ | |
1105 | PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ | |
1106 | PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ | |
1107 | PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ | |
1108 | PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ | |
1109 | PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ | |
1110 | }; | |
1111 | ||
1112 | /* special defines for FIBER (88E1011S only) */ | |
1113 | enum { | |
1114 | PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ | |
1115 | PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ | |
1116 | PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ | |
1117 | PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ | |
1118 | }; | |
1119 | ||
1120 | /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ | |
1121 | enum { | |
1122 | PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ | |
1123 | PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ | |
1124 | PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ | |
1125 | PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ | |
1126 | }; | |
1127 | ||
1128 | /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ | |
1129 | enum { | |
1130 | PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ | |
1131 | PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ | |
1132 | PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ | |
1133 | PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ | |
1134 | PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ | |
1135 | PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ | |
1136 | }; | |
1137 | ||
1138 | /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ | |
1139 | enum { | |
1140 | PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ | |
1141 | PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ | |
1142 | PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ | |
1143 | PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ | |
1144 | PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ | |
1145 | PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ | |
1146 | PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ | |
1147 | PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ | |
1148 | PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ | |
1149 | PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ | |
1150 | PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ | |
1151 | PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ | |
1152 | }; | |
1153 | ||
1154 | enum { | |
1155 | PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ | |
1156 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ | |
1157 | }; | |
1158 | ||
0efdf262 | 1159 | #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) |
cd28ab6a SH |
1160 | |
1161 | enum { | |
1162 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ | |
1163 | PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ | |
1164 | PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ | |
1165 | }; | |
1166 | ||
1167 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ | |
1168 | enum { | |
1169 | PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ | |
1170 | PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ | |
1171 | PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ | |
1172 | PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ | |
1173 | PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ | |
1174 | ||
1175 | PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ | |
1176 | PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ | |
1177 | ||
1178 | PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ | |
1179 | PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ | |
1180 | }; | |
1181 | ||
1182 | /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ | |
1183 | enum { | |
1184 | PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ | |
1185 | PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ | |
1186 | PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ | |
1187 | PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ | |
1188 | PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ | |
1189 | PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ | |
1190 | PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ | |
1191 | PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ | |
1192 | PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ | |
1193 | PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ | |
1194 | PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ | |
1195 | PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ | |
1196 | PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ | |
1197 | PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ | |
1198 | PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ | |
1199 | PHY_M_PS_JABBER = 1<<0, /* Jabber */ | |
1200 | }; | |
1201 | ||
1202 | #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) | |
1203 | ||
1204 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ | |
1205 | enum { | |
1206 | PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ | |
1207 | PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ | |
1208 | }; | |
1209 | ||
1210 | enum { | |
1211 | PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ | |
1212 | PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ | |
1213 | PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ | |
1214 | PHY_M_IS_AN_PR = 1<<12, /* Page Received */ | |
1215 | PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ | |
1216 | PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ | |
1217 | PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ | |
1218 | PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ | |
1219 | PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ | |
1220 | PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ | |
1221 | PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ | |
1222 | PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ | |
1223 | ||
1224 | PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ | |
1225 | PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ | |
1226 | PHY_M_IS_JABBER = 1<<0, /* Jabber */ | |
1227 | ||
1228 | PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE | |
d8511f83 | 1229 | | PHY_M_IS_DUP_CHANGE, |
cd28ab6a SH |
1230 | PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, |
1231 | }; | |
1232 | ||
1233 | ||
1234 | /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ | |
1235 | enum { | |
1236 | PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ | |
1237 | PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ | |
1238 | ||
1239 | PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ | |
1240 | PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ | |
1241 | /* (88E1011 only) */ | |
1242 | PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ | |
1243 | /* (88E1011 only) */ | |
1244 | PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ | |
1245 | /* (88E1111 only) */ | |
1246 | PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ | |
1247 | /* !!! Errata in spec. (1 = disable) */ | |
1248 | PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ | |
1249 | PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ | |
1250 | PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ | |
1251 | PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ | |
1252 | PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ | |
1253 | PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; | |
1254 | ||
0efdf262 | 1255 | #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) |
cd28ab6a | 1256 | /* 00=1x; 01=2x; 10=3x; 11=4x */ |
0efdf262 | 1257 | #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) |
cd28ab6a | 1258 | /* 00=dis; 01=1x; 10=2x; 11=3x */ |
0efdf262 | 1259 | #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) |
cd28ab6a | 1260 | /* 000=1x; 001=2x; 010=3x; 011=4x */ |
0efdf262 | 1261 | #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) |
cd28ab6a SH |
1262 | /* 01X=0; 110=2.5; 111=25 (MHz) */ |
1263 | ||
1264 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ | |
1265 | enum { | |
1266 | PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ | |
1267 | PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ | |
1268 | PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ | |
1269 | }; | |
1270 | /* !!! Errata in spec. (1 = disable) */ | |
1271 | ||
0efdf262 | 1272 | #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) |
cd28ab6a SH |
1273 | /* 100=5x; 101=6x; 110=7x; 111=8x */ |
1274 | enum { | |
1275 | MAC_TX_CLK_0_MHZ = 2, | |
1276 | MAC_TX_CLK_2_5_MHZ = 6, | |
1277 | MAC_TX_CLK_25_MHZ = 7, | |
1278 | }; | |
1279 | ||
1280 | /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ | |
1281 | enum { | |
1282 | PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ | |
1283 | PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ | |
1284 | PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ | |
1285 | PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ | |
1286 | PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ | |
1287 | PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ | |
1288 | PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ | |
1289 | /* (88E1111 only) */ | |
1290 | }; | |
1291 | ||
1292 | enum { | |
1293 | PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ | |
1294 | /* (88E1011 only) */ | |
1295 | PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ | |
1296 | PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ | |
1297 | PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ | |
1298 | PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ | |
1299 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ | |
1300 | }; | |
1301 | ||
0efdf262 | 1302 | #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) |
cd28ab6a SH |
1303 | |
1304 | /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ | |
1305 | enum { | |
1306 | PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ | |
1307 | PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ | |
1308 | PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ | |
1309 | PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ | |
1310 | PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ | |
1311 | PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ | |
1312 | }; | |
1313 | ||
1314 | #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) | |
1315 | #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) | |
1316 | #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) | |
1317 | #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) | |
1318 | #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) | |
1319 | #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) | |
1320 | ||
1321 | enum { | |
1322 | PULS_NO_STR = 0,/* no pulse stretching */ | |
1323 | PULS_21MS = 1,/* 21 ms to 42 ms */ | |
1324 | PULS_42MS = 2,/* 42 ms to 84 ms */ | |
1325 | PULS_84MS = 3,/* 84 ms to 170 ms */ | |
1326 | PULS_170MS = 4,/* 170 ms to 340 ms */ | |
1327 | PULS_340MS = 5,/* 340 ms to 670 ms */ | |
1328 | PULS_670MS = 6,/* 670 ms to 1.3 s */ | |
1329 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ | |
1330 | }; | |
1331 | ||
0efdf262 | 1332 | #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) |
cd28ab6a SH |
1333 | |
1334 | enum { | |
1335 | BLINK_42MS = 0,/* 42 ms */ | |
1336 | BLINK_84MS = 1,/* 84 ms */ | |
1337 | BLINK_170MS = 2,/* 170 ms */ | |
1338 | BLINK_340MS = 3,/* 340 ms */ | |
1339 | BLINK_670MS = 4,/* 670 ms */ | |
1340 | }; | |
1341 | ||
0efdf262 | 1342 | /**** PHY_MARV_LED_OVER 16 bit r/w LED control */ |
cd28ab6a | 1343 | enum { |
0efdf262 SH |
1344 | PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */ |
1345 | PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */ | |
1346 | PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */ | |
1347 | PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */ | |
1348 | PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */ | |
1349 | PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */ | |
1350 | ||
1351 | PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 | |
1352 | | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000 | |
1353 | | PHY_M_LED_MO_RX, | |
cd28ab6a SH |
1354 | }; |
1355 | ||
1356 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ | |
1357 | enum { | |
1358 | PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ | |
1359 | PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ | |
1360 | PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ | |
1361 | PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ | |
1362 | PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ | |
1363 | }; | |
1364 | ||
1365 | /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ | |
1366 | enum { | |
1367 | PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ | |
1368 | PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ | |
1369 | PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ | |
1370 | PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ | |
1371 | PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ | |
1372 | PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ | |
1373 | PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ | |
1374 | /* (88E1111 only) */ | |
1375 | ||
1376 | PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ | |
1377 | PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ | |
1378 | PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ | |
1379 | }; | |
1380 | ||
1381 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ | |
1382 | /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ | |
1383 | /* Bit 15..12: reserved (used internally) */ | |
1384 | enum { | |
1385 | PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ | |
1386 | PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ | |
1387 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ | |
1388 | }; | |
1389 | ||
0efdf262 SH |
1390 | #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) |
1391 | #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) | |
1392 | #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) | |
cd28ab6a SH |
1393 | |
1394 | enum { | |
1395 | LED_PAR_CTRL_COLX = 0x00, | |
1396 | LED_PAR_CTRL_ERROR = 0x01, | |
1397 | LED_PAR_CTRL_DUPLEX = 0x02, | |
1398 | LED_PAR_CTRL_DP_COL = 0x03, | |
1399 | LED_PAR_CTRL_SPEED = 0x04, | |
1400 | LED_PAR_CTRL_LINK = 0x05, | |
1401 | LED_PAR_CTRL_TX = 0x06, | |
1402 | LED_PAR_CTRL_RX = 0x07, | |
1403 | LED_PAR_CTRL_ACT = 0x08, | |
1404 | LED_PAR_CTRL_LNK_RX = 0x09, | |
1405 | LED_PAR_CTRL_LNK_AC = 0x0a, | |
1406 | LED_PAR_CTRL_ACT_BL = 0x0b, | |
1407 | LED_PAR_CTRL_TX_BL = 0x0c, | |
1408 | LED_PAR_CTRL_RX_BL = 0x0d, | |
1409 | LED_PAR_CTRL_COL_BL = 0x0e, | |
1410 | LED_PAR_CTRL_INACT = 0x0f | |
1411 | }; | |
1412 | ||
1413 | /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ | |
1414 | enum { | |
1415 | PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ | |
1416 | PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ | |
1417 | PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ | |
1418 | }; | |
1419 | ||
b89165f2 SH |
1420 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
1421 | /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ | |
1422 | enum { | |
1423 | PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */ | |
1424 | PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */ | |
1425 | PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */ | |
1426 | }; | |
1427 | ||
cd28ab6a SH |
1428 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
1429 | /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ | |
1430 | enum { | |
1431 | PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ | |
1432 | PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ | |
1433 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ | |
1434 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ | |
1435 | }; | |
1436 | #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) | |
1437 | ||
1438 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ | |
1439 | enum { | |
1440 | PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ | |
1441 | PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ | |
1442 | PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ | |
1443 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ | |
1444 | }; | |
1445 | ||
1446 | #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) | |
1447 | #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) | |
1448 | #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) | |
1449 | #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) | |
1450 | ||
1451 | /* GMAC registers */ | |
1452 | /* Port Registers */ | |
1453 | enum { | |
1454 | GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ | |
1455 | GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ | |
1456 | GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ | |
1457 | GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ | |
1458 | GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ | |
1459 | GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ | |
1460 | GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ | |
1461 | /* Source Address Registers */ | |
1462 | GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ | |
1463 | GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ | |
1464 | GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ | |
1465 | GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ | |
1466 | GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ | |
1467 | GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ | |
1468 | ||
1469 | /* Multicast Address Hash Registers */ | |
1470 | GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ | |
1471 | GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ | |
1472 | GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ | |
1473 | GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ | |
1474 | ||
1475 | /* Interrupt Source Registers */ | |
1476 | GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ | |
1477 | GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ | |
1478 | GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ | |
1479 | ||
1480 | /* Interrupt Mask Registers */ | |
1481 | GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ | |
1482 | GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ | |
1483 | GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ | |
1484 | ||
1485 | /* Serial Management Interface (SMI) Registers */ | |
1486 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ | |
1487 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ | |
1488 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ | |
eadfa7dd SH |
1489 | /* MIB Counters */ |
1490 | GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ | |
43f2f104 | 1491 | GM_MIB_CNT_END = 0x025C, /* Last MIB counter */ |
cd28ab6a SH |
1492 | }; |
1493 | ||
cd28ab6a SH |
1494 | |
1495 | /* | |
1496 | * MIB Counters base address definitions (low word) - | |
1497 | * use offset 4 for access to high word (32 bit r/o) | |
1498 | */ | |
1499 | enum { | |
eadfa7dd | 1500 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ |
cd28ab6a SH |
1501 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ |
1502 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ | |
1503 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ | |
1504 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ | |
eadfa7dd | 1505 | |
cd28ab6a SH |
1506 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ |
1507 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ | |
1508 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ | |
1509 | GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ | |
1510 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ | |
1511 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ | |
1512 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ | |
eadfa7dd SH |
1513 | GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */ |
1514 | GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */ | |
1515 | GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */ | |
1516 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */ | |
1517 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */ | |
1518 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */ | |
1519 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */ | |
1520 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */ | |
1521 | ||
1522 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */ | |
1523 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */ | |
1524 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */ | |
1525 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */ | |
1526 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */ | |
1527 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */ | |
1528 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */ | |
1529 | GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */ | |
1530 | GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */ | |
1531 | GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */ | |
1532 | GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */ | |
1533 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */ | |
1534 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */ | |
1535 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */ | |
1536 | ||
1537 | GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */ | |
1538 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */ | |
1539 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */ | |
1540 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */ | |
1541 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */ | |
1542 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */ | |
cd28ab6a SH |
1543 | }; |
1544 | ||
1545 | /* GMAC Bit Definitions */ | |
1546 | /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ | |
1547 | enum { | |
1548 | GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ | |
1549 | GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ | |
1550 | GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ | |
1551 | GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ | |
1552 | GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ | |
1553 | GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ | |
1554 | GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ | |
1555 | GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ | |
1556 | ||
1557 | GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ | |
1558 | GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ | |
1559 | GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ | |
1560 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ | |
1561 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ | |
1562 | }; | |
1563 | ||
1564 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ | |
1565 | enum { | |
1566 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ | |
1567 | GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ | |
1568 | GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ | |
1569 | GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ | |
1570 | GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ | |
1571 | GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ | |
1572 | GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ | |
1573 | GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ | |
1574 | GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ | |
1575 | GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ | |
1576 | GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ | |
1577 | GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ | |
1578 | GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ | |
1579 | GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ | |
1580 | GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ | |
1581 | }; | |
1582 | ||
1583 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) | |
1584 | #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) | |
1585 | ||
1586 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ | |
1587 | enum { | |
1588 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ | |
1589 | GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ | |
1590 | GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ | |
fbb88b3e | 1591 | GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */ |
cd28ab6a SH |
1592 | }; |
1593 | ||
1594 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) | |
1595 | #define TX_COL_DEF 0x04 | |
1596 | ||
1597 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ | |
1598 | enum { | |
1599 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ | |
1600 | GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ | |
1601 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ | |
1602 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ | |
1603 | }; | |
1604 | ||
1605 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ | |
1606 | enum { | |
1607 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ | |
1608 | GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ | |
1609 | GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ | |
1610 | GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ | |
1611 | ||
1612 | TX_JAM_LEN_DEF = 0x03, | |
1613 | TX_JAM_IPG_DEF = 0x0b, | |
1614 | TX_IPG_JAM_DEF = 0x1c, | |
1615 | TX_BOF_LIM_DEF = 0x04, | |
1616 | }; | |
1617 | ||
1618 | #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) | |
1619 | #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) | |
1620 | #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) | |
1621 | #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) | |
1622 | ||
1623 | ||
1624 | /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ | |
1625 | enum { | |
1626 | GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ | |
1627 | GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ | |
1628 | GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ | |
1629 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ | |
1630 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ | |
1631 | }; | |
1632 | ||
1633 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) | |
1634 | #define DATA_BLIND_DEF 0x04 | |
1635 | ||
1636 | #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) | |
1637 | #define IPG_DATA_DEF 0x1e | |
1638 | ||
1639 | /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ | |
1640 | enum { | |
1641 | GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ | |
1642 | GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ | |
1643 | GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ | |
1644 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ | |
1645 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ | |
1646 | }; | |
1647 | ||
0efdf262 SH |
1648 | #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) |
1649 | #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) | |
cd28ab6a SH |
1650 | |
1651 | /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ | |
1652 | enum { | |
1653 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ | |
1654 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ | |
1655 | }; | |
1656 | ||
1657 | /* Receive Frame Status Encoding */ | |
1658 | enum { | |
1659 | GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ | |
793b883e SH |
1660 | GMR_FS_VLAN = 1<<13, /* VLAN Packet */ |
1661 | GMR_FS_JABBER = 1<<12, /* Jabber Packet */ | |
1662 | GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ | |
1663 | GMR_FS_MC = 1<<10, /* Multicast Packet */ | |
1664 | GMR_FS_BC = 1<<9, /* Broadcast Packet */ | |
1665 | GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ | |
1666 | GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ | |
1667 | GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ | |
1668 | GMR_FS_MII_ERR = 1<<5, /* MII Error */ | |
1669 | GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ | |
1670 | GMR_FS_FRAGMENT = 1<<3, /* Fragment */ | |
1671 | ||
1672 | GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ | |
1673 | GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ | |
cd28ab6a | 1674 | |
cd28ab6a SH |
1675 | GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | |
1676 | GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | | |
7e7c0982 | 1677 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | |
cd28ab6a | 1678 | GMR_FS_UN_SIZE | GMR_FS_JABBER, |
cd28ab6a SH |
1679 | }; |
1680 | ||
1681 | /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ | |
1682 | enum { | |
793b883e SH |
1683 | RX_TRUNC_ON = 1<<27, /* enable packet truncation */ |
1684 | RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ | |
1685 | RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ | |
1686 | RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ | |
1687 | ||
cd28ab6a SH |
1688 | GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ |
1689 | GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ | |
1690 | GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ | |
1691 | ||
1692 | GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ | |
1693 | GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ | |
1694 | GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ | |
1695 | GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ | |
1696 | GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ | |
1697 | GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ | |
793b883e SH |
1698 | GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ |
1699 | ||
cd28ab6a SH |
1700 | GMF_OPER_ON = 1<<3, /* Operational Mode On */ |
1701 | GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ | |
1702 | GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ | |
1703 | GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ | |
1704 | ||
1705 | RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ | |
d1f13708 SH |
1706 | |
1707 | GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, | |
cd28ab6a SH |
1708 | }; |
1709 | ||
1710 | ||
1711 | /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ | |
1712 | enum { | |
5a5b1ea0 SH |
1713 | TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ |
1714 | TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ | |
1715 | ||
793b883e SH |
1716 | TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ |
1717 | TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ | |
1718 | ||
b628ed98 SH |
1719 | TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ |
1720 | TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ | |
1721 | ||
cd28ab6a SH |
1722 | GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ |
1723 | GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ | |
1724 | GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ | |
1725 | ||
1726 | GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ | |
1727 | GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ | |
1728 | GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ | |
1729 | }; | |
1730 | ||
1731 | /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ | |
1732 | enum { | |
1733 | GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ | |
1734 | GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ | |
1735 | GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ | |
1736 | }; | |
1737 | ||
1738 | /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ | |
1739 | enum { | |
1740 | Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ | |
1741 | Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ | |
1742 | Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ | |
1743 | Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ | |
1744 | Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ | |
1745 | ||
1746 | Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ | |
1747 | Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ | |
1748 | }; | |
1749 | ||
1750 | /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ | |
1751 | enum { | |
1752 | Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ | |
1753 | Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ | |
1754 | }; | |
93745494 SH |
1755 | /* HCU_CCSR CPU Control and Status Register */ |
1756 | enum { | |
1757 | HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */ | |
1758 | HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */ | |
1759 | /* Clock Stretching Timeout */ | |
1760 | HCU_CCSR_CS_TO = 1<<25, | |
1761 | HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ | |
1762 | ||
1763 | HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */ | |
1764 | HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */ | |
1765 | ||
1766 | HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ | |
1767 | HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ | |
1768 | ||
1769 | HCU_CCSR_SET_SYNC_CPU = 1<<5, | |
1770 | HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */ | |
1771 | HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3, | |
1772 | HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */ | |
1773 | /* Microcontroller State */ | |
1774 | HCU_CCSR_UC_STATE_MSK = 3, | |
1775 | HCU_CCSR_UC_STATE_BASE = 1<<0, | |
1776 | HCU_CCSR_ASF_RESET = 0, | |
1777 | HCU_CCSR_ASF_HALTED = 1<<1, | |
1778 | HCU_CCSR_ASF_RUNNING = 1<<0, | |
1779 | }; | |
1780 | ||
1781 | /* HCU_HCSR Host Control and Status Register */ | |
1782 | enum { | |
1783 | HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */ | |
1784 | ||
1785 | HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */ | |
1786 | HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */ | |
1787 | }; | |
cd28ab6a SH |
1788 | |
1789 | /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ | |
1790 | enum { | |
1791 | SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ | |
1792 | SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ | |
1793 | SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ | |
1794 | SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ | |
1795 | SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ | |
1796 | }; | |
1797 | ||
1798 | /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ | |
1799 | enum { | |
1800 | GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ | |
1801 | GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ | |
1802 | GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ | |
1803 | GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ | |
1804 | GMC_PAUSE_ON = 1<<3, /* Pause On */ | |
1805 | GMC_PAUSE_OFF = 1<<2, /* Pause Off */ | |
1806 | GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ | |
1807 | GMC_RST_SET = 1<<0, /* Set GMAC Reset */ | |
1808 | }; | |
1809 | ||
1810 | /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ | |
1811 | enum { | |
cd28ab6a SH |
1812 | GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ |
1813 | GPC_RST_SET = 1<<0, /* Set GPHY Reset */ | |
1814 | }; | |
1815 | ||
1816 | /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ | |
1817 | /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ | |
1818 | enum { | |
1819 | GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ | |
1820 | GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ | |
1821 | GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ | |
1822 | GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ | |
1823 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ | |
1824 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ | |
1825 | ||
79e57d32 | 1826 | #define GMAC_DEF_MSK GM_IS_TX_FF_UR |
e3173832 | 1827 | }; |
cd28ab6a SH |
1828 | |
1829 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ | |
e3173832 | 1830 | enum { /* Bits 15.. 2: reserved */ |
cd28ab6a SH |
1831 | GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ |
1832 | GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ | |
e3173832 | 1833 | }; |
cd28ab6a SH |
1834 | |
1835 | ||
1836 | /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ | |
e3173832 | 1837 | enum { |
cd28ab6a SH |
1838 | WOL_CTL_LINK_CHG_OCC = 1<<15, |
1839 | WOL_CTL_MAGIC_PKT_OCC = 1<<14, | |
1840 | WOL_CTL_PATTERN_OCC = 1<<13, | |
1841 | WOL_CTL_CLEAR_RESULT = 1<<12, | |
1842 | WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, | |
1843 | WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, | |
1844 | WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, | |
1845 | WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, | |
1846 | WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, | |
1847 | WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, | |
1848 | WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, | |
1849 | WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, | |
1850 | WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, | |
1851 | WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, | |
1852 | WOL_CTL_ENA_PATTERN_UNIT = 1<<1, | |
1853 | WOL_CTL_DIS_PATTERN_UNIT = 1<<0, | |
1854 | }; | |
1855 | ||
cd28ab6a SH |
1856 | |
1857 | /* Control flags */ | |
1858 | enum { | |
1859 | UDPTCP = 1<<0, | |
1860 | CALSUM = 1<<1, | |
1861 | WR_SUM = 1<<2, | |
1862 | INIT_SUM= 1<<3, | |
1863 | LOCK_SUM= 1<<4, | |
1864 | INS_VLAN= 1<<5, | |
cd28ab6a SH |
1865 | EOP = 1<<7, |
1866 | }; | |
1867 | ||
1868 | enum { | |
1869 | HW_OWNER = 1<<7, | |
1870 | OP_TCPWRITE = 0x11, | |
1871 | OP_TCPSTART = 0x12, | |
1872 | OP_TCPINIT = 0x14, | |
1873 | OP_TCPLCK = 0x18, | |
1874 | OP_TCPCHKSUM = OP_TCPSTART, | |
1875 | OP_TCPIS = OP_TCPINIT | OP_TCPSTART, | |
1876 | OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, | |
1877 | OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, | |
1878 | OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, | |
1879 | ||
1880 | OP_ADDR64 = 0x21, | |
1881 | OP_VLAN = 0x22, | |
1882 | OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, | |
1883 | OP_LRGLEN = 0x24, | |
1884 | OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, | |
1885 | OP_BUFFER = 0x40, | |
1886 | OP_PACKET = 0x41, | |
1887 | OP_LARGESEND = 0x43, | |
1888 | ||
1889 | /* YUKON-2 STATUS opcodes defines */ | |
1890 | OP_RXSTAT = 0x60, | |
1891 | OP_RXTIMESTAMP = 0x61, | |
1892 | OP_RXVLAN = 0x62, | |
1893 | OP_RXCHKS = 0x64, | |
1894 | OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, | |
1895 | OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, | |
1896 | OP_RSS_HASH = 0x65, | |
1897 | OP_TXINDEXLE = 0x68, | |
cd28ab6a SH |
1898 | }; |
1899 | ||
f65b138c | 1900 | /* Yukon 2 hardware interface */ |
cd28ab6a | 1901 | struct sky2_tx_le { |
f65b138c | 1902 | __le32 addr; |
65497dac | 1903 | __le16 length; /* also vlan tag or checksum start */ |
cd28ab6a SH |
1904 | u8 ctrl; |
1905 | u8 opcode; | |
793b883e | 1906 | } __attribute((packed)); |
cd28ab6a SH |
1907 | |
1908 | struct sky2_rx_le { | |
65497dac SH |
1909 | __le32 addr; |
1910 | __le16 length; | |
cd28ab6a SH |
1911 | u8 ctrl; |
1912 | u8 opcode; | |
53b3531b | 1913 | } __attribute((packed)); |
cd28ab6a SH |
1914 | |
1915 | struct sky2_status_le { | |
65497dac SH |
1916 | __le32 status; /* also checksum */ |
1917 | __le16 length; /* also vlan tag */ | |
cd28ab6a SH |
1918 | u8 link; |
1919 | u8 opcode; | |
793b883e | 1920 | } __attribute((packed)); |
cd28ab6a | 1921 | |
6cdbbdf3 SH |
1922 | struct tx_ring_info { |
1923 | struct sk_buff *skb; | |
1924 | DECLARE_PCI_UNMAP_ADDR(mapaddr); | |
291ea614 | 1925 | DECLARE_PCI_UNMAP_ADDR(maplen); |
6cdbbdf3 SH |
1926 | }; |
1927 | ||
291ea614 | 1928 | struct rx_ring_info { |
cd28ab6a | 1929 | struct sk_buff *skb; |
14d0263f SH |
1930 | dma_addr_t data_addr; |
1931 | DECLARE_PCI_UNMAP_ADDR(data_size); | |
1932 | dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; | |
cd28ab6a SH |
1933 | }; |
1934 | ||
16ad91e1 SH |
1935 | enum flow_control { |
1936 | FC_NONE = 0, | |
1937 | FC_TX = 1, | |
1938 | FC_RX = 2, | |
1939 | FC_BOTH = 3, | |
1940 | }; | |
1941 | ||
cd28ab6a | 1942 | struct sky2_port { |
793b883e | 1943 | struct sky2_hw *hw; |
cd28ab6a SH |
1944 | struct net_device *netdev; |
1945 | unsigned port; | |
1946 | u32 msg_enable; | |
e07b1aa8 | 1947 | spinlock_t phy_lock; |
cd28ab6a | 1948 | |
6cdbbdf3 | 1949 | struct tx_ring_info *tx_ring; |
cd28ab6a | 1950 | struct sky2_tx_le *tx_le; |
cd28ab6a SH |
1951 | u16 tx_cons; /* next le to check */ |
1952 | u16 tx_prod; /* next le to use */ | |
6e23231b | 1953 | u32 tx_addr64; |
793b883e | 1954 | u16 tx_pending; |
793b883e | 1955 | u16 tx_last_mss; |
f65b138c | 1956 | u32 tx_tcpsum; |
cd28ab6a | 1957 | |
291ea614 | 1958 | struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp; |
cd28ab6a | 1959 | struct sky2_rx_le *rx_le; |
793b883e | 1960 | u32 rx_addr64; |
cd28ab6a SH |
1961 | u16 rx_next; /* next re to check */ |
1962 | u16 rx_put; /* next le index to use */ | |
793b883e | 1963 | u16 rx_pending; |
14d0263f SH |
1964 | u16 rx_data_size; |
1965 | u16 rx_nfrags; | |
1966 | ||
d1f13708 SH |
1967 | #ifdef SKY2_VLAN_TAG_USED |
1968 | u16 rx_tag; | |
1969 | struct vlan_group *vlgrp; | |
1970 | #endif | |
cd28ab6a SH |
1971 | |
1972 | dma_addr_t rx_le_map; | |
1973 | dma_addr_t tx_le_map; | |
0edea0f5 | 1974 | u16 advertising; /* ADVERTISED_ bits */ |
cd28ab6a SH |
1975 | u16 speed; /* SPEED_1000, SPEED_100, ... */ |
1976 | u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ | |
1977 | u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ | |
cd28ab6a | 1978 | u8 rx_csum; |
e3173832 | 1979 | u8 wol; |
16ad91e1 SH |
1980 | enum flow_control flow_mode; |
1981 | enum flow_control flow_status; | |
cd28ab6a | 1982 | |
cd28ab6a | 1983 | struct net_device_stats net_stats; |
91c86df5 | 1984 | |
cd28ab6a SH |
1985 | }; |
1986 | ||
1987 | struct sky2_hw { | |
1988 | void __iomem *regs; | |
1989 | struct pci_dev *pdev; | |
cd28ab6a SH |
1990 | struct net_device *dev[2]; |
1991 | ||
1992 | u8 chip_id; | |
1993 | u8 chip_rev; | |
b89165f2 | 1994 | u8 pmd_type; |
cd28ab6a SH |
1995 | u8 ports; |
1996 | ||
1997 | struct sky2_status_le *st_le; | |
1998 | u32 st_idx; | |
1999 | dma_addr_t st_dma; | |
d27ed387 SH |
2000 | |
2001 | struct timer_list idle_timer; | |
81906791 | 2002 | struct work_struct restart_work; |
b0a20ded | 2003 | int msi; |
fb2690a9 | 2004 | wait_queue_head_t msi_wait; |
cd28ab6a SH |
2005 | }; |
2006 | ||
b89165f2 SH |
2007 | static inline int sky2_is_copper(const struct sky2_hw *hw) |
2008 | { | |
2009 | return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P'); | |
2010 | } | |
2011 | ||
cd28ab6a SH |
2012 | /* Register accessor for memory mapped device */ |
2013 | static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) | |
2014 | { | |
2015 | return readl(hw->regs + reg); | |
2016 | } | |
2017 | ||
2018 | static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) | |
2019 | { | |
2020 | return readw(hw->regs + reg); | |
2021 | } | |
2022 | ||
2023 | static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) | |
2024 | { | |
2025 | return readb(hw->regs + reg); | |
2026 | } | |
2027 | ||
cd28ab6a SH |
2028 | static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) |
2029 | { | |
2030 | writel(val, hw->regs + reg); | |
2031 | } | |
2032 | ||
2033 | static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) | |
2034 | { | |
2035 | writew(val, hw->regs + reg); | |
2036 | } | |
2037 | ||
2038 | static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) | |
2039 | { | |
2040 | writeb(val, hw->regs + reg); | |
2041 | } | |
2042 | ||
2043 | /* Yukon PHY related registers */ | |
2044 | #define SK_GMAC_REG(port,reg) \ | |
2045 | (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) | |
2046 | #define GM_PHY_RETRIES 100 | |
2047 | ||
2048 | static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) | |
2049 | { | |
2050 | return sky2_read16(hw, SK_GMAC_REG(port,reg)); | |
2051 | } | |
2052 | ||
2053 | static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) | |
2054 | { | |
2055 | unsigned base = SK_GMAC_REG(port, reg); | |
2056 | return (u32) sky2_read16(hw, base) | |
2057 | | (u32) sky2_read16(hw, base+4) << 16; | |
2058 | } | |
2059 | ||
2060 | static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) | |
2061 | { | |
2062 | sky2_write16(hw, SK_GMAC_REG(port,r), v); | |
2063 | } | |
2064 | ||
2065 | static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, | |
2066 | const u8 *addr) | |
2067 | { | |
2068 | gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); | |
2069 | gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); | |
2070 | gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); | |
2071 | } | |
56a645cc SH |
2072 | |
2073 | /* PCI config space access */ | |
2074 | static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) | |
2075 | { | |
2076 | return sky2_read32(hw, Y2_CFG_SPC + reg); | |
2077 | } | |
2078 | ||
2079 | static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) | |
2080 | { | |
2081 | return sky2_read16(hw, Y2_CFG_SPC + reg); | |
2082 | } | |
2083 | ||
2084 | static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) | |
2085 | { | |
2086 | sky2_write32(hw, Y2_CFG_SPC + reg, val); | |
2087 | } | |
2088 | ||
2089 | static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) | |
2090 | { | |
2091 | sky2_write16(hw, Y2_CFG_SPC + reg, val); | |
2092 | } | |
cd28ab6a | 2093 | #endif |