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[PATCH] sky2: add hardware VLAN acceleration support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
cd28ab6a
SH		 29 *
30 * TOTEST
793b883e 31 * - variable ring size
cd28ab6a
SH		 32 * - speed setting
33 * - power management
793b883e 34 * - netpoll
cd28ab6a
SH		 35 */
36
37#include <linux/config.h>
793b883e 38#include <linux/crc32.h>
cd28ab6a
SH		 39#include <linux/kernel.h>
40#include <linux/version.h>
41#include <linux/module.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/ethtool.h>
45#include <linux/pci.h>
46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/in.h>
49#include <linux/delay.h>
d1f13708 50#include <linux/if_vlan.h>
cd28ab6a
SH		 51
52#include <asm/irq.h>
53
d1f13708
SH		 54#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55#define SKY2_VLAN_TAG_USED 1
56#endif
57
cd28ab6a
SH		 58#include "sky2.h"
59
60#define DRV_NAME "sky2"
ecfd7f32 61#define DRV_VERSION "0.5"
cd28ab6a
SH		 62#define PFX DRV_NAME " "
63
64/*
65 * The Yukon II chipset takes 64 bit command blocks (called list elements)
66 * that are organized into three (receive, transmit, status) different rings
67 * similar to Tigon3. A transmit can require several elements;
68 * a receive requires one (or two if using 64 bit dma).
69 */
70
71#ifdef CONFIG_SKY2_EC_A1
72#define is_ec_a1(hw) \
73 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
74 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
75#else
76#define is_ec_a1(hw) 0
77#endif
78
793b883e 79#define RX_LE_SIZE 256
cd28ab6a 80#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
793b883e
SH		 81#define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
82#define RX_DEF_PENDING 128
79e57d32 83#define RX_COPY_THRESHOLD 256
793b883e
SH		 84
85#define TX_RING_SIZE 512
86#define TX_DEF_PENDING (TX_RING_SIZE - 1)
87#define TX_MIN_PENDING 64
88#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 89
793b883e 90#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 91#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
92#define ETH_JUMBO_MTU 9000
93#define TX_WATCHDOG (5 * HZ)
94#define NAPI_WEIGHT 64
95#define PHY_RETRIES 1000
96
97static const u32 default_msg =
793b883e
SH		 98 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
99 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
100 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 101
793b883e 102static int debug = -1; /* defaults above */
cd28ab6a
SH		 103module_param(debug, int, 0);
104MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
105
106static const struct pci_device_id sky2_id_table[] = {
793b883e 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
124 { 0 }
125};
793b883e 126
cd28ab6a
SH		 127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132
793b883e
SH		 133static const char *yukon_name[] = {
134 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
135 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
136 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
cd28ab6a 137
793b883e
SH		 138 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
139 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
140};
141
142
143/* Access to external PHY */
cd28ab6a
SH		 144static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
145{
146 int i;
147
148 gma_write16(hw, port, GM_SMI_DATA, val);
149 gma_write16(hw, port, GM_SMI_CTRL,
150 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151
152 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 153 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
793b883e
SH		 154 return;
155 udelay(1);
cd28ab6a 156 }
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
cd28ab6a
SH		 158}
159
160static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
161{
162 int i;
163
793b883e 164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a
SH		 168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
169 goto ready;
793b883e 170 udelay(1);
cd28ab6a
SH		 171 }
172
793b883e
SH		 173 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
174ready:
cd28ab6a
SH		 175 return gma_read16(hw, port, GM_SMI_DATA);
176}
177
178static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
179{
180 u16 reg;
181
182 /* disable all GMAC IRQ's */
183 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
184 /* disable PHY IRQs */
185 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 186
cd28ab6a
SH		 187 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
188 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
189 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
190 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
191
192 reg = gma_read16(hw, port, GM_RX_CTRL);
193 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
194 gma_write16(hw, port, GM_RX_CTRL, reg);
195}
196
197static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
198{
199 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 200 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 201
793b883e 202 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 203 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
204
205 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 206 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 207 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
208
209 if (hw->chip_id == CHIP_ID_YUKON_EC)
210 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
211 else
212 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
213
214 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
215 }
216
217 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
218 if (hw->copper) {
219 if (hw->chip_id == CHIP_ID_YUKON_FE) {
220 /* enable automatic crossover */
221 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
222 } else {
223 /* disable energy detect */
224 ctrl &= ~PHY_M_PC_EN_DET_MSK;
225
226 /* enable automatic crossover */
227 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
228
229 if (sky2->autoneg == AUTONEG_ENABLE &&
230 hw->chip_id == CHIP_ID_YUKON_XL) {
231 ctrl &= ~PHY_M_PC_DSC_MSK;
232 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
233 }
234 }
235 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
236 } else {
237 /* workaround for deviation #4.88 (CRC errors) */
238 /* disable Automatic Crossover */
239
240 ctrl &= ~PHY_M_PC_MDIX_MSK;
241 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
242
243 if (hw->chip_id == CHIP_ID_YUKON_XL) {
244 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
245 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
246 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
247 ctrl &= ~PHY_M_MAC_MD_MSK;
248 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
249 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
250
251 /* select page 1 to access Fiber registers */
252 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
253 }
cd28ab6a
SH		 254 }
255
256 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
257 if (sky2->autoneg == AUTONEG_DISABLE)
258 ctrl &= ~PHY_CT_ANE;
259 else
260 ctrl |= PHY_CT_ANE;
261
262 ctrl |= PHY_CT_RESET;
263 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
264
265 ctrl = 0;
266 ct1000 = 0;
267 adv = PHY_AN_CSMA;
268
269 if (sky2->autoneg == AUTONEG_ENABLE) {
270 if (hw->copper) {
271 if (sky2->advertising & ADVERTISED_1000baseT_Full)
272 ct1000 |= PHY_M_1000C_AFD;
273 if (sky2->advertising & ADVERTISED_1000baseT_Half)
274 ct1000 |= PHY_M_1000C_AHD;
275 if (sky2->advertising & ADVERTISED_100baseT_Full)
276 adv |= PHY_M_AN_100_FD;
277 if (sky2->advertising & ADVERTISED_100baseT_Half)
278 adv |= PHY_M_AN_100_HD;
279 if (sky2->advertising & ADVERTISED_10baseT_Full)
280 adv |= PHY_M_AN_10_FD;
281 if (sky2->advertising & ADVERTISED_10baseT_Half)
282 adv |= PHY_M_AN_10_HD;
793b883e 283 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 284 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
285
286 /* Set Flow-control capabilities */
287 if (sky2->tx_pause && sky2->rx_pause)
793b883e 288 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 289 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 290 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 291 else if (!sky2->rx_pause && sky2->tx_pause)
292 adv |= PHY_AN_PAUSE_ASYM; /* local */
293
294 /* Restart Auto-negotiation */
295 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
296 } else {
297 /* forced speed/duplex settings */
298 ct1000 = PHY_M_1000C_MSE;
299
300 if (sky2->duplex == DUPLEX_FULL)
301 ctrl |= PHY_CT_DUP_MD;
302
303 switch (sky2->speed) {
304 case SPEED_1000:
305 ctrl |= PHY_CT_SP1000;
306 break;
307 case SPEED_100:
308 ctrl |= PHY_CT_SP100;
309 break;
310 }
311
312 ctrl |= PHY_CT_RESET;
313 }
314
315 if (hw->chip_id != CHIP_ID_YUKON_FE)
316 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
317
318 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
319 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
320
321 /* Setup Phy LED's */
322 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
323 ledover = 0;
324
325 switch (hw->chip_id) {
326 case CHIP_ID_YUKON_FE:
327 /* on 88E3082 these bits are at 11..9 (shifted left) */
328 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
329
330 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
331
332 /* delete ACT LED control bits */
333 ctrl &= ~PHY_M_FELP_LED1_MSK;
334 /* change ACT LED control to blink mode */
335 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
336 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
337 break;
338
339 case CHIP_ID_YUKON_XL:
793b883e 340 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 341
342 /* select page 3 to access LED control register */
343 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
344
345 /* set LED Function Control register */
793b883e
SH		 346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
347 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
348 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
349 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 350
351 /* set Polarity Control register */
352 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 353 (PHY_M_POLC_LS1_P_MIX(4) |
354 PHY_M_POLC_IS0_P_MIX(4) |
355 PHY_M_POLC_LOS_CTRL(2) |
356 PHY_M_POLC_INIT_CTRL(2) |
357 PHY_M_POLC_STA1_CTRL(2) |
358 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 359
360 /* restore page register */
793b883e 361 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 362 break;
363
364 default:
365 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
366 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
367 /* turn off the Rx LED (LED_RX) */
368 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
369 }
370
371 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
372
373 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
374 /* turn on 100 Mbps LED (LED_LINK100) */
375 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
376 }
377
378 if (ledover)
379 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
380
381 /* Enable phy interrupt on autonegotiation complete (or link up) */
382 if (sky2->autoneg == AUTONEG_ENABLE)
383 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
384 else
385 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
386}
387
388static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
389{
390 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
391 u16 reg;
392 int i;
393 const u8 *addr = hw->dev[port]->dev_addr;
394
395 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
396 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
397
398 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
399
793b883e 400 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 401 /* WA DEV_472 -- looks like crossed wires on port 2 */
402 /* clear GMAC 1 Control reset */
403 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
404 do {
405 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
406 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
407 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
408 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
409 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
410 }
411
cd28ab6a
SH		 412 if (sky2->autoneg == AUTONEG_DISABLE) {
413 reg = gma_read16(hw, port, GM_GP_CTRL);
414 reg |= GM_GPCR_AU_ALL_DIS;
415 gma_write16(hw, port, GM_GP_CTRL, reg);
416 gma_read16(hw, port, GM_GP_CTRL);
417
cd28ab6a
SH		 418 switch (sky2->speed) {
419 case SPEED_1000:
420 reg |= GM_GPCR_SPEED_1000;
421 /* fallthru */
422 case SPEED_100:
423 reg |= GM_GPCR_SPEED_100;
424 }
425
426 if (sky2->duplex == DUPLEX_FULL)
427 reg |= GM_GPCR_DUP_FULL;
428 } else
429 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
430
431 if (!sky2->tx_pause && !sky2->rx_pause) {
432 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 433 reg |=
434 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
435 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 436 /* disable Rx flow-control */
437 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
438 }
439
440 gma_write16(hw, port, GM_GP_CTRL, reg);
441
793b883e 442 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a
SH		 443
444 spin_lock_bh(&hw->phy_lock);
445 sky2_phy_init(hw, port);
446 spin_unlock_bh(&hw->phy_lock);
447
448 /* MIB clear */
449 reg = gma_read16(hw, port, GM_PHY_ADDR);
450 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
451
452 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 453 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 454 gma_write16(hw, port, GM_PHY_ADDR, reg);
455
456 /* transmit control */
457 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
458
459 /* receive control reg: unicast + multicast + no FCS */
460 gma_write16(hw, port, GM_RX_CTRL,
793b883e 461 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 462
463 /* transmit flow control */
464 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
465
466 /* transmit parameter */
467 gma_write16(hw, port, GM_TX_PARAM,
468 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
469 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
470 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
471 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
472
473 /* serial mode register */
474 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 475 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 476
6b1a3aef 477 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 478 reg |= GM_SMOD_JUMBO_ENA;
479
480 gma_write16(hw, port, GM_SERIAL_MODE, reg);
481
cd28ab6a
SH		 482 /* virtual address for data */
483 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
484
793b883e
SH		 485 /* physical address: used for pause frames */
486 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
487
488 /* ignore counter overflows */
cd28ab6a
SH		 489 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
490 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
491 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
492
493 /* Configure Rx MAC FIFO */
494 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 495 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 496 GMF_RX_CTRL_DEF);
cd28ab6a 497
793b883e
SH		 498 /* Flush Rx MAC FIFO on any flowcontrol or error */
499 reg = GMR_FS_ANY_ERR;
cd28ab6a
SH		 500 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
501 reg = 0; /* WA Dev #4115 */
502
503 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
793b883e
SH		 504 /* Set threshold to 0xa (64 bytes)
505 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 506 */
507 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
508
509 /* Configure Tx MAC FIFO */
510 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
511 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
cd28ab6a
SH		 512}
513
514static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
515{
516 u32 end;
517
518 start /= 8;
519 len /= 8;
520 end = start + len - 1;
793b883e 521
cd28ab6a
SH		 522 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
523 sky2_write32(hw, RB_ADDR(q, RB_START), start);
524 sky2_write32(hw, RB_ADDR(q, RB_END), end);
525 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
526 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
527
528 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 529 u32 rxup, rxlo;
530
531 rxlo = len/2;
532 rxup = rxlo + len/4;
793b883e 533
cd28ab6a 534 /* Set thresholds on receive queue's */
793b883e
SH		 535 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
536 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 537 } else {
538 /* Enable store & forward on Tx queue's because
539 * Tx FIFO is only 1K on Yukon
540 */
541 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
542 }
543
544 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 545 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 546}
547
cd28ab6a
SH		 548/* Setup Bus Memory Interface */
549static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
550{
551 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
552 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
553 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
554 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
555}
556
cd28ab6a
SH		 557/* Setup prefetch unit registers. This is the interface between
558 * hardware and driver list elements
559 */
560static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
561 u64 addr, u32 last)
562{
cd28ab6a
SH		 563 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
564 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
565 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
566 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
567 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
568 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 569
570 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 571}
572
793b883e
SH		 573static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
574{
575 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
576
577 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
578 return le;
579}
cd28ab6a
SH		 580
581/*
582 * This is a workaround code taken from syskonnect sk98lin driver
793b883e 583 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 584 */
585static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
586 u16 idx, u16 *last, u16 size)
cd28ab6a 587{
cd28ab6a
SH		 588 if (is_ec_a1(hw) && idx < *last) {
589 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
590
591 if (hwget == 0) {
592 /* Start prefetching again */
793b883e 593 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 594 goto setnew;
595 }
596
793b883e 597 if (hwget == size - 1) {
cd28ab6a
SH		 598 /* set watermark to one list element */
599 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
600
601 /* set put index to first list element */
602 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 603 } else /* have hardware go to end of list */
604 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
605 size - 1);
cd28ab6a 606 } else {
793b883e 607setnew:
cd28ab6a 608 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 609 }
793b883e 610 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 611}
612
793b883e 613
cd28ab6a
SH		 614static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
615{
616 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
617 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
618 return le;
619}
620
793b883e
SH		 621/* Build description to hardware about buffer */
622static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
cd28ab6a
SH		 623{
624 struct sky2_rx_le *le;
793b883e 625 u32 hi = (re->mapaddr >> 16) >> 16;
cd28ab6a 626
793b883e
SH		 627 re->idx = sky2->rx_put;
628 if (sky2->rx_addr64 != hi) {
cd28ab6a 629 le = sky2_next_rx(sky2);
793b883e 630 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 631 le->ctrl = 0;
632 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 633 sky2->rx_addr64 = hi;
cd28ab6a 634 }
793b883e 635
cd28ab6a 636 le = sky2_next_rx(sky2);
793b883e
SH		 637 le->addr = cpu_to_le32((u32) re->mapaddr);
638 le->length = cpu_to_le16(re->maplen);
cd28ab6a
SH		 639 le->ctrl = 0;
640 le->opcode = OP_PACKET | HW_OWNER;
641}
642
793b883e
SH		 643/* Tell receiver about new buffers. */
644static inline void rx_set_put(struct net_device *dev)
645{
646 struct sky2_port *sky2 = netdev_priv(dev);
647
648 if (sky2->rx_last_put != sky2->rx_put)
649 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
650 &sky2->rx_last_put, RX_LE_SIZE);
651}
652
cd28ab6a
SH		 653/* Tell chip where to start receive checksum.
654 * Actually has two checksums, but set both same to avoid possible byte
655 * order problems.
656 */
793b883e 657static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 658{
659 struct sky2_rx_le *le;
660
cd28ab6a 661 le = sky2_next_rx(sky2);
793b883e 662 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 663 le->ctrl = 0;
664 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 665
793b883e
SH		 666 sky2_write32(sky2->hw,
667 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
668 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 669
670}
671
6b1a3aef
SH		 672/*
673 * The RX Stop command will not work for Yukon-2 if the BMU does not
674 * reach the end of packet and since we can't make sure that we have
675 * incoming data, we must reset the BMU while it is not doing a DMA
676 * transfer. Since it is possible that the RX path is still active,
677 * the RX RAM buffer will be stopped first, so any possible incoming
678 * data will not trigger a DMA. After the RAM buffer is stopped, the
679 * BMU is polled until any DMA in progress is ended and only then it
680 * will be reset.
681 */
682static void sky2_rx_stop(struct sky2_port *sky2)
683{
684 struct sky2_hw *hw = sky2->hw;
685 unsigned rxq = rxqaddr[sky2->port];
686 int i;
687
688 /* disable the RAM Buffer receive queue */
689 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
690
691 for (i = 0; i < 0xffff; i++)
692 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
693 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
694 goto stopped;
695
696 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
697 sky2->netdev->name);
698stopped:
699 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
700
701 /* reset the Rx prefetch unit */
702 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
703}
793b883e 704
cd28ab6a
SH		 705/* Cleanout receive buffer area, assumes receiver hardware stopped */
706static void sky2_rx_clean(struct sky2_port *sky2)
707{
708 unsigned i;
709
710 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 711 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 712 struct ring_info *re = sky2->rx_ring + i;
713
714 if (re->skb) {
793b883e
SH		 715 pci_unmap_single(sky2->hw->pdev,
716 re->mapaddr, re->maplen,
cd28ab6a
SH		 717 PCI_DMA_FROMDEVICE);
718 kfree_skb(re->skb);
719 re->skb = NULL;
720 }
721 }
722}
723
d1f13708
SH		 724#ifdef SKY2_VLAN_TAG_USED
725static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
726{
727 struct sky2_port *sky2 = netdev_priv(dev);
728 struct sky2_hw *hw = sky2->hw;
729 u16 port = sky2->port;
730 unsigned long flags;
731
732 spin_lock_irqsave(&sky2->tx_lock, flags);
733
734 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
735 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
736 sky2->vlgrp = grp;
737
738 spin_unlock_irqrestore(&sky2->tx_lock, flags);
739}
740
741static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
742{
743 struct sky2_port *sky2 = netdev_priv(dev);
744 struct sky2_hw *hw = sky2->hw;
745 u16 port = sky2->port;
746 unsigned long flags;
747
748 spin_lock_irqsave(&sky2->tx_lock, flags);
749
750 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
751 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
752 if (sky2->vlgrp)
753 sky2->vlgrp->vlan_devices[vid] = NULL;
754
755 spin_unlock_irqrestore(&sky2->tx_lock, flags);
756}
757#endif
758
79e57d32 759#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
6b1a3aef 760static inline unsigned rx_size(const struct sky2_port *sky2)
cd28ab6a 761{
79e57d32 762 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
cd28ab6a
SH		 763}
764
765/*
766 * Allocate and setup receiver buffer pool.
767 * In case of 64 bit dma, there are 2X as many list elements
768 * available as ring entries
769 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 770 *
771 * It appears the hardware has a bug in the FIFO logic that
772 * cause it to hang if the FIFO gets overrun and the receive buffer
773 * is not aligned. This means we can't use skb_reserve to align
774 * the IP header.
cd28ab6a 775 */
6b1a3aef 776static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 777{
6b1a3aef
SH		 778 struct sky2_hw *hw = sky2->hw;
779 unsigned size = rx_size(sky2);
780 unsigned rxq = rxqaddr[sky2->port];
781 int i;
cd28ab6a 782
6b1a3aef
SH		 783 sky2->rx_put = sky2->rx_next = 0;
784 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
785 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
786
787 rx_set_checksum(sky2);
793b883e 788 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 789 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 790
79e57d32 791 re->skb = dev_alloc_skb(size);
cd28ab6a
SH		 792 if (!re->skb)
793 goto nomem;
794
6b1a3aef 795 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
79e57d32
SH		 796 size, PCI_DMA_FROMDEVICE);
797 re->maplen = size;
793b883e 798 sky2_rx_add(sky2, re);
cd28ab6a
SH		 799 }
800
6b1a3aef
SH		 801 /* Tell chip about available buffers */
802 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
803 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 804 return 0;
805nomem:
806 sky2_rx_clean(sky2);
807 return -ENOMEM;
808}
809
810/* Bring up network interface. */
811static int sky2_up(struct net_device *dev)
812{
813 struct sky2_port *sky2 = netdev_priv(dev);
814 struct sky2_hw *hw = sky2->hw;
815 unsigned port = sky2->port;
816 u32 ramsize, rxspace;
817 int err = -ENOMEM;
818
819 if (netif_msg_ifup(sky2))
820 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
821
822 /* must be power of 2 */
823 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 824 TX_RING_SIZE *
825 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 826 &sky2->tx_le_map);
827 if (!sky2->tx_le)
828 goto err_out;
829
830 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
831 GFP_KERNEL);
832 if (!sky2->tx_ring)
833 goto err_out;
834 sky2->tx_prod = sky2->tx_cons = 0;
835 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
836
837 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
838 &sky2->rx_le_map);
839 if (!sky2->rx_le)
840 goto err_out;
841 memset(sky2->rx_le, 0, RX_LE_BYTES);
842
793b883e 843 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 844 GFP_KERNEL);
845 if (!sky2->rx_ring)
846 goto err_out;
847
848 sky2_mac_init(hw, port);
849
850 /* Configure RAM buffers */
851 if (hw->chip_id == CHIP_ID_YUKON_FE ||
852 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
853 ramsize = 4096;
854 else {
793b883e
SH		 855 u8 e0 = sky2_read8(hw, B2_E_0);
856 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 857 }
858
859 /* 2/3 for Rx */
860 rxspace = (2 * ramsize) / 3;
861 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
862 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
863
793b883e
SH		 864 /* Make sure SyncQ is disabled */
865 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
866 RB_RST_SET);
867
cd28ab6a 868 sky2_qset(hw, txqaddr[port], 0x600);
6b1a3aef
SH		 869 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
870 TX_RING_SIZE - 1);
cd28ab6a 871
6b1a3aef 872 err = sky2_rx_start(sky2);
cd28ab6a
SH		 873 if (err)
874 goto err_out;
875
cd28ab6a
SH		 876 /* Enable interrupts from phy/mac for port */
877 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
878 sky2_write32(hw, B0_IMSK, hw->intr_mask);
879 return 0;
880
881err_out:
882 if (sky2->rx_le)
883 pci_free_consistent(hw->pdev, RX_LE_BYTES,
884 sky2->rx_le, sky2->rx_le_map);
885 if (sky2->tx_le)
886 pci_free_consistent(hw->pdev,
887 TX_RING_SIZE * sizeof(struct sky2_tx_le),
888 sky2->tx_le, sky2->tx_le_map);
889 if (sky2->tx_ring)
890 kfree(sky2->tx_ring);
891 if (sky2->rx_ring)
892 kfree(sky2->rx_ring);
893
894 return err;
895}
896
793b883e
SH		 897/* Modular subtraction in ring */
898static inline int tx_dist(unsigned tail, unsigned head)
899{
900 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
901}
cd28ab6a 902
793b883e
SH		 903/* Number of list elements available for next tx */
904static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 905{
793b883e 906 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 907}
908
793b883e
SH		 909/* Estimate of number of transmit list elements required */
910static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 911{
793b883e
SH		 912 unsigned count;
913
914 count = sizeof(dma_addr_t) / sizeof(u32);
915 count += skb_shinfo(skb)->nr_frags * count;
916
917 if (skb_shinfo(skb)->tso_size)
918 ++count;
919
920 if (skb->ip_summed)
921 ++count;
922
923 return count;
cd28ab6a
SH		 924}
925
793b883e
SH		 926/*
927 * Put one packet in ring for transmit.
928 * A single packet can generate multiple list elements, and
929 * the number of ring elements will probably be less than the number
930 * of list elements used.
931 */
cd28ab6a
SH		 932static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
933{
934 struct sky2_port *sky2 = netdev_priv(dev);
935 struct sky2_hw *hw = sky2->hw;
d1f13708 936 struct sky2_tx_le *le = NULL;
cd28ab6a 937 struct ring_info *re;
793b883e 938 unsigned long flags;
cd28ab6a
SH		 939 unsigned i, len;
940 dma_addr_t mapping;
941 u32 addr64;
942 u16 mss;
943 u8 ctrl;
944
793b883e
SH		 945 local_irq_save(flags);
946 if (!spin_trylock(&sky2->tx_lock)) {
947 local_irq_restore(flags);
cd28ab6a 948 return NETDEV_TX_LOCKED;
793b883e 949 }
cd28ab6a 950
793b883e 951 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 952 netif_stop_queue(dev);
793b883e 953 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 954
955 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
956 dev->name);
957 return NETDEV_TX_BUSY;
958 }
959
793b883e 960 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 961 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
962 dev->name, sky2->tx_prod, skb->len);
963
cd28ab6a
SH		 964 len = skb_headlen(skb);
965 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e
SH		 966 addr64 = (mapping >> 16) >> 16;
967
968 re = sky2->tx_ring + sky2->tx_prod;
969
970 /* Send high bits if changed */
971 if (addr64 != sky2->tx_addr64) {
972 le = get_tx_le(sky2);
973 le->tx.addr = cpu_to_le32(addr64);
974 le->ctrl = 0;
975 le->opcode = OP_ADDR64 | HW_OWNER;
976 sky2->tx_addr64 = addr64;
977 }
cd28ab6a
SH		 978
979 /* Check for TCP Segmentation Offload */
980 mss = skb_shinfo(skb)->tso_size;
793b883e 981 if (mss != 0) {
cd28ab6a
SH		 982 /* just drop the packet if non-linear expansion fails */
983 if (skb_header_cloned(skb) &&
984 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 985 dev_kfree_skb_any(skb);
986 goto out_unlock;
cd28ab6a
SH		 987 }
988
989 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
990 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
991 mss += ETH_HLEN;
793b883e 992 }
cd28ab6a 993
793b883e 994 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 995 le = get_tx_le(sky2);
996 le->tx.tso.size = cpu_to_le16(mss);
793b883e 997 le->tx.tso.rsvd = 0;
cd28ab6a 998 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 999 le->ctrl = 0;
793b883e 1000 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1001 }
1002
cd28ab6a 1003 ctrl = 0;
d1f13708
SH		 1004#ifdef SKY2_VLAN_TAG_USED
1005 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1006 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1007 if (!le) {
1008 le = get_tx_le(sky2);
1009 le->tx.addr = 0;
1010 le->opcode = OP_VLAN|HW_OWNER;
1011 le->ctrl = 0;
1012 } else
1013 le->opcode |= OP_VLAN;
1014 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1015 ctrl |= INS_VLAN;
1016 }
1017#endif
1018
1019 /* Handle TCP checksum offload */
cd28ab6a 1020 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1021 u16 hdr = skb->h.raw - skb->data;
1022 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1023
1024 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1025 if (skb->nh.iph->protocol == IPPROTO_UDP)
1026 ctrl |= UDPTCP;
1027
1028 le = get_tx_le(sky2);
1029 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1030 le->tx.csum.offset = cpu_to_le16(offset);
1031 le->length = 0; /* initial checksum value */
cd28ab6a 1032 le->ctrl = 1; /* one packet */
793b883e 1033 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1034 }
1035
1036 le = get_tx_le(sky2);
1037 le->tx.addr = cpu_to_le32((u32) mapping);
1038 le->length = cpu_to_le16(len);
1039 le->ctrl = ctrl;
793b883e 1040 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1041
793b883e 1042 /* Record the transmit mapping info */
cd28ab6a 1043 re->skb = skb;
793b883e
SH		 1044 re->mapaddr = mapping;
1045 re->maplen = len;
cd28ab6a
SH		 1046
1047 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1048 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1049 struct ring_info *fre;
cd28ab6a
SH		 1050
1051 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1052 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1053 addr64 = (mapping >> 16) >> 16;
1054 if (addr64 != sky2->tx_addr64) {
1055 le = get_tx_le(sky2);
1056 le->tx.addr = cpu_to_le32(addr64);
1057 le->ctrl = 0;
1058 le->opcode = OP_ADDR64 | HW_OWNER;
1059 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1060 }
1061
1062 le = get_tx_le(sky2);
1063 le->tx.addr = cpu_to_le32((u32) mapping);
1064 le->length = cpu_to_le16(frag->size);
1065 le->ctrl = ctrl;
793b883e 1066 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1067
793b883e
SH		 1068 fre = sky2->tx_ring
1069 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1070 fre->skb = NULL;
1071 fre->mapaddr = mapping;
1072 fre->maplen = frag->size;
cd28ab6a 1073 }
793b883e 1074 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1075 le->ctrl |= EOP;
1076
1077 sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
1078 &sky2->tx_last_put, TX_RING_SIZE);
1079
793b883e 1080 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1081 netif_stop_queue(dev);
793b883e
SH		 1082
1083out_unlock:
1084 mmiowb();
1085 spin_unlock_irqrestore(&sky2->tx_lock, flags);
cd28ab6a
SH		 1086
1087 dev->trans_start = jiffies;
1088 return NETDEV_TX_OK;
1089}
1090
cd28ab6a 1091/*
793b883e
SH		 1092 * Free ring elements from starting at tx_cons until "done"
1093 *
1094 * NB: the hardware will tell us about partial completion of multi-part
1095 * buffers; these are defered until completion.
cd28ab6a 1096 */
d11c13e7 1097static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1098{
d11c13e7 1099 struct net_device *dev = sky2->netdev;
793b883e 1100 unsigned i;
cd28ab6a 1101
d11c13e7
SH		 1102 if (unlikely(netif_msg_tx_done(sky2)))
1103 printk(KERN_DEBUG "%s: tx done, upto %u\n",
1104 dev->name, done);
cd28ab6a
SH		 1105
1106 spin_lock(&sky2->tx_lock);
cd28ab6a 1107
793b883e
SH		 1108 while (sky2->tx_cons != done) {
1109 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1110 struct sk_buff *skb;
cd28ab6a 1111
793b883e
SH		 1112 /* Check for partial status */
1113 if (tx_dist(sky2->tx_cons, done)
1114 < tx_dist(sky2->tx_cons, re->idx))
1115 goto out;
1116
1117 skb = re->skb;
1118 pci_unmap_single(sky2->hw->pdev,
1119 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1120
1121 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1122 struct ring_info *fre;
1123 fre =
1124 sky2->tx_ring + (sky2->tx_cons + i +
1125 1) % TX_RING_SIZE;
1126 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1127 fre->maplen, PCI_DMA_TODEVICE);
cd28ab6a
SH		 1128 }
1129
cd28ab6a 1130 dev_kfree_skb_any(skb);
cd28ab6a 1131
793b883e
SH		 1132 sky2->tx_cons = re->idx;
1133 }
1134out:
1135
1136 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1137 netif_wake_queue(dev);
1138 spin_unlock(&sky2->tx_lock);
1139}
1140
1141/* Cleanup all untransmitted buffers, assume transmitter not running */
1142static inline void sky2_tx_clean(struct sky2_port *sky2)
1143{
d11c13e7 1144 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1145}
1146
1147/* Network shutdown */
1148static int sky2_down(struct net_device *dev)
1149{
1150 struct sky2_port *sky2 = netdev_priv(dev);
1151 struct sky2_hw *hw = sky2->hw;
1152 unsigned port = sky2->port;
1153 u16 ctrl;
cd28ab6a
SH		 1154
1155 if (netif_msg_ifdown(sky2))
1156 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1157
1158 netif_stop_queue(dev);
1159
793b883e
SH		 1160 sky2_phy_reset(hw, port);
1161
cd28ab6a
SH		 1162 /* Stop transmitter */
1163 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1164 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1165
1166 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1167 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1168
1169 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1170 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1171 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1172
1173 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1174
1175 /* Workaround shared GMAC reset */
793b883e
SH		 1176 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1177 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1178 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1179
1180 /* Disable Force Sync bit and Enable Alloc bit */
1181 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1182 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1183
1184 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1185 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1186 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1187
1188 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1189 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1190 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1191
1192 /* Reset the Tx prefetch units */
1193 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1194 PREF_UNIT_RST_SET);
1195
1196 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1197
6b1a3aef 1198 sky2_rx_stop(sky2);
cd28ab6a
SH		 1199
1200 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1201 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1202
1203 /* turn off led's */
1204 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1205
1206 sky2_tx_clean(sky2);
1207 sky2_rx_clean(sky2);
1208
1209 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1210 sky2->rx_le, sky2->rx_le_map);
1211 kfree(sky2->rx_ring);
1212
1213 pci_free_consistent(hw->pdev,
1214 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1215 sky2->tx_le, sky2->tx_le_map);
1216 kfree(sky2->tx_ring);
1217
1218 return 0;
1219}
1220
1221static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1222{
793b883e
SH		 1223 if (!hw->copper)
1224 return SPEED_1000;
1225
cd28ab6a
SH		 1226 if (hw->chip_id == CHIP_ID_YUKON_FE)
1227 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1228
1229 switch (aux & PHY_M_PS_SPEED_MSK) {
1230 case PHY_M_PS_SPEED_1000:
1231 return SPEED_1000;
1232 case PHY_M_PS_SPEED_100:
1233 return SPEED_100;
1234 default:
1235 return SPEED_10;
1236 }
1237}
1238
1239static void sky2_link_up(struct sky2_port *sky2)
1240{
1241 struct sky2_hw *hw = sky2->hw;
1242 unsigned port = sky2->port;
1243 u16 reg;
1244
793b883e
SH		 1245 /* disable Rx GMAC FIFO flush mode */
1246 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1247
cd28ab6a 1248 /* Enable Transmit FIFO Underrun */
793b883e 1249 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1250
1251 reg = gma_read16(hw, port, GM_GP_CTRL);
1252 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1253 reg |= GM_GPCR_DUP_FULL;
1254
cd28ab6a
SH		 1255 /* enable Rx/Tx */
1256 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1257 gma_write16(hw, port, GM_GP_CTRL, reg);
1258 gma_read16(hw, port, GM_GP_CTRL);
1259
1260 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1261
1262 netif_carrier_on(sky2->netdev);
1263 netif_wake_queue(sky2->netdev);
1264
1265 /* Turn on link LED */
793b883e 1266 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1267 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1268
793b883e
SH		 1269 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1270 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1271
1272 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1273 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1274 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1275 SPEED_10 ? 7 : 0) |
1276 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1277 SPEED_100 ? 7 : 0) |
1278 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1279 SPEED_1000 ? 7 : 0));
1280 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1281 }
1282
cd28ab6a
SH		 1283 if (netif_msg_link(sky2))
1284 printk(KERN_INFO PFX
1285 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1286 sky2->netdev->name, sky2->speed,
1287 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1288 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1289 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1290}
1291
1292static void sky2_link_down(struct sky2_port *sky2)
1293{
1294 struct sky2_hw *hw = sky2->hw;
1295 unsigned port = sky2->port;
1296 u16 reg;
1297
1298 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1299
1300 reg = gma_read16(hw, port, GM_GP_CTRL);
1301 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1302 gma_write16(hw, port, GM_GP_CTRL, reg);
1303 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1304
1305 if (sky2->rx_pause && !sky2->tx_pause) {
1306 /* restore Asymmetric Pause bit */
1307 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1308 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1309 | PHY_M_AN_ASP);
cd28ab6a
SH		 1310 }
1311
1312 sky2_phy_reset(hw, port);
1313
1314 netif_carrier_off(sky2->netdev);
1315 netif_stop_queue(sky2->netdev);
1316
1317 /* Turn on link LED */
1318 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1319
1320 if (netif_msg_link(sky2))
1321 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1322 sky2_phy_init(hw, port);
1323}
1324
793b883e
SH		 1325static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1326{
1327 struct sky2_hw *hw = sky2->hw;
1328 unsigned port = sky2->port;
1329 u16 lpa;
1330
1331 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1332
1333 if (lpa & PHY_M_AN_RF) {
1334 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1335 return -1;
1336 }
1337
1338 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1339 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1340 printk(KERN_ERR PFX "%s: master/slave fault",
1341 sky2->netdev->name);
1342 return -1;
1343 }
1344
1345 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1346 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1347 sky2->netdev->name);
1348 return -1;
1349 }
1350
1351 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1352
1353 sky2->speed = sky2_phy_speed(hw, aux);
1354
1355 /* Pause bits are offset (9..8) */
1356 if (hw->chip_id == CHIP_ID_YUKON_XL)
1357 aux >>= 6;
1358
1359 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1360 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1361
1362 if ((sky2->tx_pause || sky2->rx_pause)
1363 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1364 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1365 else
1366 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1367
1368 return 0;
1369}
cd28ab6a
SH		 1370
1371/*
1372 * Interrrupt from PHY are handled in tasklet (soft irq)
1373 * because accessing phy registers requires spin wait which might
1374 * cause excess interrupt latency.
1375 */
1376static void sky2_phy_task(unsigned long data)
1377{
793b883e 1378 struct sky2_port *sky2 = (struct sky2_port *)data;
cd28ab6a 1379 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1380 u16 istatus, phystat;
1381
793b883e
SH		 1382 spin_lock(&hw->phy_lock);
1383 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1384 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1385
1386 if (netif_msg_intr(sky2))
1387 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1388 sky2->netdev->name, istatus, phystat);
1389
1390 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1391 if (sky2_autoneg_done(sky2, phystat) == 0)
1392 sky2_link_up(sky2);
1393 goto out;
1394 }
cd28ab6a 1395
793b883e
SH		 1396 if (istatus & PHY_M_IS_LSP_CHANGE)
1397 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1398
793b883e
SH		 1399 if (istatus & PHY_M_IS_DUP_CHANGE)
1400 sky2->duplex =
1401 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1402
793b883e
SH		 1403 if (istatus & PHY_M_IS_LST_CHANGE) {
1404 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1405 sky2_link_up(sky2);
793b883e
SH		 1406 else
1407 sky2_link_down(sky2);
cd28ab6a 1408 }
793b883e
SH		 1409out:
1410 spin_unlock(&hw->phy_lock);
cd28ab6a
SH		 1411
1412 local_irq_disable();
793b883e 1413 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1414 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1415 local_irq_enable();
1416}
1417
1418static void sky2_tx_timeout(struct net_device *dev)
1419{
1420 struct sky2_port *sky2 = netdev_priv(dev);
1421
1422 if (netif_msg_timer(sky2))
1423 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1424
1425 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1426 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1427
1428 sky2_tx_clean(sky2);
1429}
1430
1431static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1432{
6b1a3aef
SH		 1433 struct sky2_port *sky2 = netdev_priv(dev);
1434 struct sky2_hw *hw = sky2->hw;
1435 int err;
1436 u16 ctl, mode;
cd28ab6a
SH		 1437
1438 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1439 return -EINVAL;
1440
6b1a3aef
SH		 1441 if (!netif_running(dev)) {
1442 dev->mtu = new_mtu;
1443 return 0;
1444 }
1445
1446 local_irq_disable();
1447 sky2_write32(hw, B0_IMSK, 0);
1448
1449 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1450 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1451 sky2_rx_stop(sky2);
1452 sky2_rx_clean(sky2);
cd28ab6a
SH		 1453
1454 dev->mtu = new_mtu;
6b1a3aef
SH		 1455 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1456 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1457
1458 if (dev->mtu > ETH_DATA_LEN)
1459 mode |= GM_SMOD_JUMBO_ENA;
1460
1461 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1462
6b1a3aef 1463 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1464
6b1a3aef
SH		 1465 err = sky2_rx_start(sky2);
1466 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1467
1468 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1469 sky2_read32(hw, B0_IMSK);
1470 local_irq_enable();
cd28ab6a
SH		 1471 return err;
1472}
1473
1474/*
1475 * Receive one packet.
1476 * For small packets or errors, just reuse existing skb.
1477 * For larger pakects, get new buffer.
1478 */
d11c13e7 1479static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1480 u16 length, u32 status)
1481{
cd28ab6a 1482 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1483 struct sk_buff *skb = NULL;
d11c13e7 1484 struct net_device *dev;
6b1a3aef 1485 const unsigned int bufsize = rx_size(sky2);
cd28ab6a
SH		 1486
1487 if (unlikely(netif_msg_rx_status(sky2)))
1488 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1489 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1490
793b883e 1491 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1492
d1f13708 1493 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
cd28ab6a
SH		 1494 goto error;
1495
793b883e 1496 if (length < RX_COPY_THRESHOLD) {
79e57d32
SH		 1497 skb = alloc_skb(length + 2, GFP_ATOMIC);
1498 if (!skb)
793b883e
SH		 1499 goto resubmit;
1500
79e57d32 1501 skb_reserve(skb, 2);
793b883e
SH		 1502 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1503 length, PCI_DMA_FROMDEVICE);
79e57d32 1504 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1505 skb->ip_summed = re->skb->ip_summed;
1506 skb->csum = re->skb->csum;
793b883e
SH		 1507 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1508 length, PCI_DMA_FROMDEVICE);
793b883e 1509 } else {
79e57d32
SH		 1510 struct sk_buff *nskb;
1511
1512 nskb = dev_alloc_skb(bufsize);
793b883e
SH		 1513 if (!nskb)
1514 goto resubmit;
cd28ab6a 1515
793b883e 1516 skb = re->skb;
79e57d32 1517 re->skb = nskb;
793b883e
SH		 1518 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1519 re->maplen, PCI_DMA_FROMDEVICE);
1520 prefetch(skb->data);
cd28ab6a 1521
793b883e 1522 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
79e57d32
SH		 1523 bufsize, PCI_DMA_FROMDEVICE);
1524 re->maplen = bufsize;
793b883e 1525 }
cd28ab6a 1526
79e57d32 1527 skb_put(skb, length);
d11c13e7
SH		 1528 dev = sky2->netdev;
1529 skb->dev = dev;
79e57d32
SH		 1530 skb->protocol = eth_type_trans(skb, dev);
1531 dev->last_rx = jiffies;
1532
793b883e 1533resubmit:
d11c13e7 1534 re->skb->ip_summed = CHECKSUM_NONE;
793b883e 1535 sky2_rx_add(sky2, re);
79e57d32 1536
cd28ab6a
SH		 1537 return skb;
1538
1539error:
793b883e
SH		 1540 if (status & GMR_FS_GOOD_FC)
1541 goto resubmit;
1542
cd28ab6a
SH		 1543 if (netif_msg_rx_err(sky2))
1544 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1545 sky2->netdev->name, status, length);
793b883e
SH		 1546
1547 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1548 sky2->net_stats.rx_length_errors++;
1549 if (status & GMR_FS_FRAGMENT)
1550 sky2->net_stats.rx_frame_errors++;
1551 if (status & GMR_FS_CRC_ERR)
1552 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1553 if (status & GMR_FS_RX_FF_OV)
1554 sky2->net_stats.rx_fifo_errors++;
79e57d32 1555
793b883e 1556 goto resubmit;
cd28ab6a
SH		 1557}
1558
793b883e
SH		 1559/* Transmit ring index in reported status block is encoded as:
1560 *
1561 * | TXS2 | TXA2 | TXS1 | TXA1
1562 */
1563static inline u16 tx_index(u8 port, u32 status, u16 len)
cd28ab6a
SH		 1564{
1565 if (port == 0)
1566 return status & 0xfff;
1567 else
1568 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1569}
1570
1571/*
cd28ab6a
SH		 1572 * Both ports share the same status interrupt, therefore there is only
1573 * one poll routine.
cd28ab6a 1574 */
d11c13e7 1575static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1576{
d11c13e7
SH		 1577 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1578 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1579 unsigned int work_done = 0;
793b883e 1580 u16 hwidx;
cd28ab6a 1581
793b883e 1582 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1583 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e
SH		 1584 rmb();
1585 while (hw->st_idx != hwidx && work_done < to_do) {
cd28ab6a 1586 struct sky2_status_le *le = hw->st_le + hw->st_idx;
d11c13e7 1587 struct sky2_port *sky2;
cd28ab6a 1588 struct sk_buff *skb;
cd28ab6a
SH		 1589 u32 status;
1590 u16 length;
1591
d11c13e7 1592 BUG_ON(le->link >= hw->ports);
d1f13708
SH		 1593 if (!hw->dev[le->link])
1594 goto skip;
1595
d11c13e7 1596 sky2 = netdev_priv(hw->dev[le->link]);
cd28ab6a
SH		 1597 status = le32_to_cpu(le->status);
1598 length = le16_to_cpu(le->length);
cd28ab6a 1599
793b883e 1600 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1601 case OP_RXSTAT:
d11c13e7 1602 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1603 if (!skb)
1604 break;
1605#ifdef SKY2_VLAN_TAG_USED
1606 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1607 vlan_hwaccel_receive_skb(skb,
1608 sky2->vlgrp,
1609 be16_to_cpu(sky2->rx_tag));
1610 } else
1611#endif
cd28ab6a 1612 netif_receive_skb(skb);
cd28ab6a
SH		 1613 break;
1614
d1f13708
SH		 1615#ifdef SKY2_VLAN_TAG_USED
1616 case OP_RXVLAN:
1617 sky2->rx_tag = length;
1618 break;
1619
1620 case OP_RXCHKSVLAN:
1621 sky2->rx_tag = length;
1622 /* fall through */
1623#endif
cd28ab6a 1624 case OP_RXCHKS:
d11c13e7
SH		 1625 skb = sky2->rx_ring[sky2->rx_next].skb;
1626 skb->ip_summed = CHECKSUM_HW;
1627 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1628 break;
1629
1630 case OP_TXINDEXLE:
d11c13e7
SH		 1631 sky2_tx_complete(sky2,
1632 tx_index(sky2->port, status, length));
cd28ab6a
SH		 1633 break;
1634
cd28ab6a
SH		 1635 default:
1636 if (net_ratelimit())
793b883e
SH		 1637 printk(KERN_WARNING PFX
1638 "unknown status opcode 0x%x\n",
cd28ab6a
SH		 1639 le->opcode);
1640 break;
1641 }
1642
d1f13708 1643 skip:
793b883e
SH		 1644 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1645 if (hw->st_idx == hwidx) {
1646 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1647 rmb();
1648 }
cd28ab6a
SH		 1649 }
1650
793b883e
SH		 1651 mmiowb();
1652
1653 if (hw->dev[0])
1654 rx_set_put(hw->dev[0]);
1655
1656 if (hw->dev[1])
1657 rx_set_put(hw->dev[1]);
1658
cd28ab6a 1659 *budget -= work_done;
d11c13e7 1660 dev0->quota -= work_done;
cd28ab6a
SH		 1661 if (work_done < to_do) {
1662 /*
1663 * Another chip workaround, need to restart TX timer if status
1664 * LE was handled. WA_DEV_43_418
1665 */
1666 if (is_ec_a1(hw)) {
1667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1668 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1669 }
1670
1671 hw->intr_mask |= Y2_IS_STAT_BMU;
1672 sky2_write32(hw, B0_IMSK, hw->intr_mask);
793b883e 1673 sky2_read32(hw, B0_IMSK);
d11c13e7 1674 netif_rx_complete(dev0);
cd28ab6a
SH		 1675 }
1676
1677 return work_done >= to_do;
1678
1679}
1680
1681static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1682{
1683 struct net_device *dev = hw->dev[port];
1684
1685 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1686 dev->name, status);
1687
1688 if (status & Y2_IS_PAR_RD1) {
1689 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1690 dev->name);
1691 /* Clear IRQ */
1692 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1693 }
1694
1695 if (status & Y2_IS_PAR_WR1) {
1696 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1697 dev->name);
1698
1699 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1700 }
1701
1702 if (status & Y2_IS_PAR_MAC1) {
1703 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1704 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1705 }
1706
1707 if (status & Y2_IS_PAR_RX1) {
1708 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1709 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1710 }
1711
1712 if (status & Y2_IS_TCP_TXA1) {
1713 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1714 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1715 }
1716}
1717
1718static void sky2_hw_intr(struct sky2_hw *hw)
1719{
1720 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1721
793b883e 1722 if (status & Y2_IS_TIST_OV)
cd28ab6a 1723 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1724
1725 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1726 u16 pci_err;
1727
1728 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1729 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1730 pci_name(hw->pdev), pci_err);
1731
1732 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1733 pci_write_config_word(hw->pdev, PCI_STATUS,
1734 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1735 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1736 }
1737
1738 if (status & Y2_IS_PCI_EXP) {
1739 /* PCI-Express uncorrectable Error occured */
793b883e
SH		 1740 u32 pex_err;
1741
1742 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1743
cd28ab6a
SH		 1744 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1745 pci_name(hw->pdev), pex_err);
1746
1747 /* clear the interrupt */
1748 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1749 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1750 0xffffffffUL);
cd28ab6a
SH		 1751 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1752
1753 if (pex_err & PEX_FATAL_ERRORS) {
1754 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1755 hwmsk &= ~Y2_IS_PCI_EXP;
1756 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1757 }
1758 }
1759
1760 if (status & Y2_HWE_L1_MASK)
1761 sky2_hw_error(hw, 0, status);
1762 status >>= 8;
1763 if (status & Y2_HWE_L1_MASK)
1764 sky2_hw_error(hw, 1, status);
1765}
1766
1767static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1768{
1769 struct net_device *dev = hw->dev[port];
1770 struct sky2_port *sky2 = netdev_priv(dev);
1771 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1772
1773 if (netif_msg_intr(sky2))
1774 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1775 dev->name, status);
1776
1777 if (status & GM_IS_RX_FF_OR) {
1778 ++sky2->net_stats.rx_fifo_errors;
1779 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1780 }
1781
1782 if (status & GM_IS_TX_FF_UR) {
1783 ++sky2->net_stats.tx_fifo_errors;
1784 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1785 }
cd28ab6a
SH		 1786}
1787
1788static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1789{
1790 struct net_device *dev = hw->dev[port];
1791 struct sky2_port *sky2 = netdev_priv(dev);
1792
1793 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1794 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1795 tasklet_schedule(&sky2->phy_task);
1796}
1797
1798static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1799{
1800 struct sky2_hw *hw = dev_id;
1801 u32 status;
1802
1803 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1804 if (status == 0 || status == ~0)
cd28ab6a
SH		 1805 return IRQ_NONE;
1806
1807 if (status & Y2_IS_HW_ERR)
1808 sky2_hw_intr(hw);
1809
793b883e
SH		 1810 /* Do NAPI for Rx and Tx status */
1811 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1812 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1813
cd28ab6a
SH		 1814 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1815 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1816 __netif_rx_schedule(hw->dev[0]);
1817 }
1818
793b883e 1819 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1820 sky2_phy_intr(hw, 0);
1821
1822 if (status & Y2_IS_IRQ_PHY2)
1823 sky2_phy_intr(hw, 1);
1824
1825 if (status & Y2_IS_IRQ_MAC1)
1826 sky2_mac_intr(hw, 0);
1827
1828 if (status & Y2_IS_IRQ_MAC2)
1829 sky2_mac_intr(hw, 1);
1830
cd28ab6a 1831 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 1832
1833 sky2_read32(hw, B0_IMSK);
1834
cd28ab6a
SH		 1835 return IRQ_HANDLED;
1836}
1837
1838#ifdef CONFIG_NET_POLL_CONTROLLER
1839static void sky2_netpoll(struct net_device *dev)
1840{
1841 struct sky2_port *sky2 = netdev_priv(dev);
1842
793b883e 1843 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 1844}
1845#endif
1846
1847/* Chip internal frequency for clock calculations */
1848static inline u32 sky2_khz(const struct sky2_hw *hw)
1849{
793b883e 1850 switch (hw->chip_id) {
cd28ab6a
SH		 1851 case CHIP_ID_YUKON_EC:
1852 return 125000; /* 125 Mhz */
1853 case CHIP_ID_YUKON_FE:
1854 return 100000; /* 100 Mhz */
793b883e 1855 default: /* YUKON_XL */
cd28ab6a
SH		 1856 return 156000; /* 156 Mhz */
1857 }
1858}
1859
1860static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1861{
1862 return sky2_khz(hw) * ms;
1863}
1864
1865static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1866{
793b883e 1867 return (sky2_khz(hw) * us) / 1000;
cd28ab6a
SH		 1868}
1869
1870static int sky2_reset(struct sky2_hw *hw)
1871{
1872 u32 ctst, power;
1873 u16 status;
1874 u8 t8, pmd_type;
1875 int i;
1876
1877 ctst = sky2_read32(hw, B0_CTST);
1878
1879 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1880 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1881 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1882 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1883 pci_name(hw->pdev), hw->chip_id);
1884 return -EOPNOTSUPP;
1885 }
1886
793b883e
SH		 1887 /* ring for status responses */
1888 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1889 &hw->st_dma);
1890 if (!hw->st_le)
1891 return -ENOMEM;
1892
cd28ab6a
SH		 1893 /* disable ASF */
1894 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1895 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1896 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1897 }
1898
1899 /* do a SW reset */
1900 sky2_write8(hw, B0_CTST, CS_RST_SET);
1901 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1902
1903 /* clear PCI errors, if any */
793b883e 1904 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 1905 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1906 pci_write_config_word(hw->pdev, PCI_STATUS,
1907 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1908
1909 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1910
1911 /* clear any PEX errors */
1912 if (is_pciex(hw)) {
793b883e
SH		 1913 u16 lstat;
1914 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1915 0xffffffffUL);
1916 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 1917 }
1918
1919 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1920 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1921
1922 hw->ports = 1;
1923 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1924 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1925 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1926 ++hw->ports;
1927 }
1928 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1929
1930 /* switch power to VCC (WA for VAUX problem) */
1931 sky2_write8(hw, B0_POWER_CTRL,
1932 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1933
1934 /* disable Core Clock Division, */
1935 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1936
1937 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
1938 /* enable bits are inverted */
1939 sky2_write8(hw, B2_Y2_CLK_GATE,
1940 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1941 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1942 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
793b883e
SH		 1943 else
1944 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
cd28ab6a
SH		 1945
1946 /* Turn off phy power saving */
793b883e
SH		 1947 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
1948 power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
cd28ab6a 1949
793b883e 1950 /* looks like this xl is back asswards .. */
cd28ab6a
SH		 1951 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
1952 power |= PCI_Y2_PHY1_COMA;
1953 if (hw->ports > 1)
1954 power |= PCI_Y2_PHY2_COMA;
1955 }
793b883e 1956 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
cd28ab6a
SH		 1957
1958 for (i = 0; i < hw->ports; i++) {
1959 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1960 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1961 }
1962
1963 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1964
793b883e
SH		 1965 /* Clear I2C IRQ noise */
1966 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 1967
1968 /* turn off hardware timer (unused) */
1969 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
1970 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 1971
cd28ab6a
SH		 1972 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
1973
793b883e 1974 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 1975 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
1976 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
1977
1978 /* Turn off receive timestamp */
1979 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 1980 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1981
1982 /* enable the Tx Arbiters */
1983 for (i = 0; i < hw->ports; i++)
1984 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
1985
1986 /* Initialize ram interface */
1987 for (i = 0; i < hw->ports; i++) {
793b883e 1988 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 1989
1990 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
1991 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
1992 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
1993 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
1994 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
1995 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
1996 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
1997 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
1998 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
1999 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2000 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2001 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2002 }
2003
cd28ab6a 2004 if (is_pciex(hw)) {
793b883e
SH		 2005 u16 pctrl;
2006
2007 /* change Max. Read Request Size to 2048 bytes */
2008 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2009 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2010 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2011
2012
cd28ab6a 2013 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e 2014 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
cd28ab6a
SH		 2015 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2016 }
2017
2018 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2019
cd28ab6a
SH		 2020 spin_lock_bh(&hw->phy_lock);
2021 for (i = 0; i < hw->ports; i++)
2022 sky2_phy_reset(hw, i);
2023 spin_unlock_bh(&hw->phy_lock);
2024
cd28ab6a
SH		 2025 memset(hw->st_le, 0, STATUS_LE_BYTES);
2026 hw->st_idx = 0;
2027
2028 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2029 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2030
2031 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2032 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2033
2034 /* Set the list last index */
793b883e 2035 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2036
793b883e
SH		 2037 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2038
2039 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2040 if (is_ec_a1(hw)) {
2041 /* WA for dev. #4.3 */
793b883e 2042 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2043
2044 /* set Status-FIFO watermark */
2045 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2046
2047 /* set Status-FIFO ISR watermark */
793b883e 2048 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2049
cd28ab6a 2050 } else {
cd28ab6a
SH		 2051 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2052
2053 /* set Status-FIFO watermark */
2054 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2055
2056 /* set Status-FIFO ISR watermark */
2057 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2058 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2059
793b883e 2060 else /* WA 4109 */
cd28ab6a
SH		 2061 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2062
2063 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2064 }
2065
793b883e 2066 /* enable status unit */
cd28ab6a
SH		 2067 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2068
2069 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2070 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2071 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2072
2073 return 0;
2074}
2075
2076static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2077{
2078 u32 modes;
2079 if (hw->copper) {
793b883e
SH		 2080 modes = SUPPORTED_10baseT_Half
2081 | SUPPORTED_10baseT_Full
2082 | SUPPORTED_100baseT_Half
2083 | SUPPORTED_100baseT_Full
2084 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2085
2086 if (hw->chip_id != CHIP_ID_YUKON_FE)
2087 modes |= SUPPORTED_1000baseT_Half
793b883e 2088 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2089 } else
2090 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2091 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2092 return modes;
2093}
2094
793b883e 2095static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2096{
2097 struct sky2_port *sky2 = netdev_priv(dev);
2098 struct sky2_hw *hw = sky2->hw;
2099
2100 ecmd->transceiver = XCVR_INTERNAL;
2101 ecmd->supported = sky2_supported_modes(hw);
2102 ecmd->phy_address = PHY_ADDR_MARV;
2103 if (hw->copper) {
2104 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2105 | SUPPORTED_10baseT_Full
2106 | SUPPORTED_100baseT_Half
2107 | SUPPORTED_100baseT_Full
2108 | SUPPORTED_1000baseT_Half
2109 | SUPPORTED_1000baseT_Full
2110 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2111 ecmd->port = PORT_TP;
2112 } else
2113 ecmd->port = PORT_FIBRE;
2114
2115 ecmd->advertising = sky2->advertising;
2116 ecmd->autoneg = sky2->autoneg;
2117 ecmd->speed = sky2->speed;
2118 ecmd->duplex = sky2->duplex;
2119 return 0;
2120}
2121
2122static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2123{
2124 struct sky2_port *sky2 = netdev_priv(dev);
2125 const struct sky2_hw *hw = sky2->hw;
2126 u32 supported = sky2_supported_modes(hw);
2127
2128 if (ecmd->autoneg == AUTONEG_ENABLE) {
2129 ecmd->advertising = supported;
2130 sky2->duplex = -1;
2131 sky2->speed = -1;
2132 } else {
2133 u32 setting;
2134
793b883e 2135 switch (ecmd->speed) {
cd28ab6a
SH		 2136 case SPEED_1000:
2137 if (ecmd->duplex == DUPLEX_FULL)
2138 setting = SUPPORTED_1000baseT_Full;
2139 else if (ecmd->duplex == DUPLEX_HALF)
2140 setting = SUPPORTED_1000baseT_Half;
2141 else
2142 return -EINVAL;
2143 break;
2144 case SPEED_100:
2145 if (ecmd->duplex == DUPLEX_FULL)
2146 setting = SUPPORTED_100baseT_Full;
2147 else if (ecmd->duplex == DUPLEX_HALF)
2148 setting = SUPPORTED_100baseT_Half;
2149 else
2150 return -EINVAL;
2151 break;
2152
2153 case SPEED_10:
2154 if (ecmd->duplex == DUPLEX_FULL)
2155 setting = SUPPORTED_10baseT_Full;
2156 else if (ecmd->duplex == DUPLEX_HALF)
2157 setting = SUPPORTED_10baseT_Half;
2158 else
2159 return -EINVAL;
2160 break;
2161 default:
2162 return -EINVAL;
2163 }
2164
2165 if ((setting & supported) == 0)
2166 return -EINVAL;
2167
2168 sky2->speed = ecmd->speed;
2169 sky2->duplex = ecmd->duplex;
2170 }
2171
2172 sky2->autoneg = ecmd->autoneg;
2173 sky2->advertising = ecmd->advertising;
2174
2175 if (netif_running(dev)) {
2176 sky2_down(dev);
2177 sky2_up(dev);
2178 }
2179
2180 return 0;
2181}
2182
2183static void sky2_get_drvinfo(struct net_device *dev,
2184 struct ethtool_drvinfo *info)
2185{
2186 struct sky2_port *sky2 = netdev_priv(dev);
2187
2188 strcpy(info->driver, DRV_NAME);
2189 strcpy(info->version, DRV_VERSION);
2190 strcpy(info->fw_version, "N/A");
2191 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2192}
2193
2194static const struct sky2_stat {
793b883e
SH		 2195 char name[ETH_GSTRING_LEN];
2196 u16 offset;
cd28ab6a
SH		 2197} sky2_stats[] = {
2198 { "tx_bytes", GM_TXO_OK_HI },
2199 { "rx_bytes", GM_RXO_OK_HI },
2200 { "tx_broadcast", GM_TXF_BC_OK },
2201 { "rx_broadcast", GM_RXF_BC_OK },
2202 { "tx_multicast", GM_TXF_MC_OK },
2203 { "rx_multicast", GM_RXF_MC_OK },
2204 { "tx_unicast", GM_TXF_UC_OK },
2205 { "rx_unicast", GM_RXF_UC_OK },
2206 { "tx_mac_pause", GM_TXF_MPAUSE },
2207 { "rx_mac_pause", GM_RXF_MPAUSE },
2208 { "collisions", GM_TXF_SNG_COL },
2209 { "late_collision",GM_TXF_LAT_COL },
2210 { "aborted", GM_TXF_ABO_COL },
2211 { "multi_collisions", GM_TXF_MUL_COL },
2212 { "fifo_underrun", GM_TXE_FIFO_UR },
2213 { "fifo_overflow", GM_RXE_FIFO_OV },
2214 { "rx_toolong", GM_RXF_LNG_ERR },
2215 { "rx_jabber", GM_RXF_JAB_PKT },
2216 { "rx_runt", GM_RXE_FRAG },
2217 { "rx_too_long", GM_RXF_LNG_ERR },
2218 { "rx_fcs_error", GM_RXF_FCS_ERR },
2219};
2220
cd28ab6a
SH		 2221static u32 sky2_get_rx_csum(struct net_device *dev)
2222{
2223 struct sky2_port *sky2 = netdev_priv(dev);
2224
2225 return sky2->rx_csum;
2226}
2227
2228static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2229{
2230 struct sky2_port *sky2 = netdev_priv(dev);
2231
2232 sky2->rx_csum = data;
793b883e 2233
cd28ab6a
SH		 2234 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2235 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2236
2237 return 0;
2238}
2239
2240static u32 sky2_get_msglevel(struct net_device *netdev)
2241{
2242 struct sky2_port *sky2 = netdev_priv(netdev);
2243 return sky2->msg_enable;
2244}
2245
793b883e 2246static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2247{
2248 struct sky2_hw *hw = sky2->hw;
2249 unsigned port = sky2->port;
2250 int i;
2251
2252 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2253 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2254 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2255 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2256
793b883e 2257 for (i = 2; i < count; i++)
cd28ab6a
SH		 2258 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2259}
2260
cd28ab6a
SH		 2261static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2262{
2263 struct sky2_port *sky2 = netdev_priv(netdev);
2264 sky2->msg_enable = value;
2265}
2266
2267static int sky2_get_stats_count(struct net_device *dev)
2268{
2269 return ARRAY_SIZE(sky2_stats);
2270}
2271
2272static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2273 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2274{
2275 struct sky2_port *sky2 = netdev_priv(dev);
2276
793b883e 2277 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2278}
2279
793b883e 2280static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2281{
2282 int i;
2283
2284 switch (stringset) {
2285 case ETH_SS_STATS:
2286 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2287 memcpy(data + i * ETH_GSTRING_LEN,
2288 sky2_stats[i].name, ETH_GSTRING_LEN);
2289 break;
2290 }
2291}
2292
2293/* Use hardware MIB variables for critical path statistics and
2294 * transmit feedback not reported at interrupt.
2295 * Other errors are accounted for in interrupt handler.
2296 */
2297static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2298{
2299 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2300 u64 data[13];
cd28ab6a 2301
793b883e 2302 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2303
2304 sky2->net_stats.tx_bytes = data[0];
2305 sky2->net_stats.rx_bytes = data[1];
2306 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2307 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2308 sky2->net_stats.multicast = data[5] + data[7];
2309 sky2->net_stats.collisions = data[10];
2310 sky2->net_stats.tx_aborted_errors = data[12];
2311
2312 return &sky2->net_stats;
2313}
2314
2315static int sky2_set_mac_address(struct net_device *dev, void *p)
2316{
2317 struct sky2_port *sky2 = netdev_priv(dev);
2318 struct sockaddr *addr = p;
2319 int err = 0;
2320
2321 if (!is_valid_ether_addr(addr->sa_data))
2322 return -EADDRNOTAVAIL;
2323
2324 sky2_down(dev);
2325 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2326 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2327 dev->dev_addr, ETH_ALEN);
793b883e 2328 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2329 dev->dev_addr, ETH_ALEN);
2330 if (dev->flags & IFF_UP)
2331 err = sky2_up(dev);
2332 return err;
2333}
2334
2335static void sky2_set_multicast(struct net_device *dev)
2336{
2337 struct sky2_port *sky2 = netdev_priv(dev);
2338 struct sky2_hw *hw = sky2->hw;
2339 unsigned port = sky2->port;
2340 struct dev_mc_list *list = dev->mc_list;
2341 u16 reg;
2342 u8 filter[8];
2343
2344 memset(filter, 0, sizeof(filter));
2345
2346 reg = gma_read16(hw, port, GM_RX_CTRL);
2347 reg |= GM_RXCR_UCF_ENA;
2348
793b883e 2349 if (dev->flags & IFF_PROMISC) /* promiscious */
cd28ab6a 2350 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2351 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2352 memset(filter, 0xff, sizeof(filter));
793b883e 2353 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2354 reg &= ~GM_RXCR_MCF_ENA;
2355 else {
2356 int i;
2357 reg |= GM_RXCR_MCF_ENA;
2358
2359 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2360 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2361 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2362 }
2363 }
2364
cd28ab6a 2365 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2366 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2367 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2368 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2369 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2370 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2371 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2372 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2373
2374 gma_write16(hw, port, GM_RX_CTRL, reg);
2375}
2376
2377/* Can have one global because blinking is controlled by
2378 * ethtool and that is always under RTNL mutex
2379 */
2380static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2381{
793b883e
SH		 2382 u16 pg;
2383
cd28ab6a 2384 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2385 switch (hw->chip_id) {
2386 case CHIP_ID_YUKON_XL:
2387 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2390 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2391 PHY_M_LEDC_INIT_CTRL(7) |
2392 PHY_M_LEDC_STA1_CTRL(7) |
2393 PHY_M_LEDC_STA0_CTRL(7))
2394 : 0);
2395
2396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2397 break;
2398
2399 default:
2400 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2401 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2402 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2403 PHY_M_LED_MO_10(MO_LED_ON) |
2404 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2405 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2406 PHY_M_LED_MO_RX(MO_LED_ON)
2407 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2408 PHY_M_LED_MO_10(MO_LED_OFF) |
2409 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2410 PHY_M_LED_MO_1000(MO_LED_OFF) |
2411 PHY_M_LED_MO_RX(MO_LED_OFF));
2412
793b883e 2413 }
cd28ab6a
SH		 2414 spin_unlock_bh(&hw->phy_lock);
2415}
2416
2417/* blink LED's for finding board */
2418static int sky2_phys_id(struct net_device *dev, u32 data)
2419{
2420 struct sky2_port *sky2 = netdev_priv(dev);
2421 struct sky2_hw *hw = sky2->hw;
2422 unsigned port = sky2->port;
793b883e 2423 u16 ledctrl, ledover = 0;
cd28ab6a
SH		 2424 long ms;
2425 int onoff = 1;
2426
793b883e 2427 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2428 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2429 else
2430 ms = data * 1000;
2431
2432 /* save initial values */
2433 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2434 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2435 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2436 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2437 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2439 } else {
2440 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2441 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2442 }
cd28ab6a
SH		 2443 spin_unlock_bh(&hw->phy_lock);
2444
2445 while (ms > 0) {
2446 sky2_led(hw, port, onoff);
2447 onoff = !onoff;
2448
2449 if (msleep_interruptible(250))
2450 break; /* interrupted */
2451 ms -= 250;
2452 }
2453
2454 /* resume regularly scheduled programming */
2455 spin_lock_bh(&hw->phy_lock);
793b883e
SH		 2456 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2457 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2459 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2461 } else {
2462 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2463 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2464 }
cd28ab6a
SH		 2465 spin_unlock_bh(&hw->phy_lock);
2466
2467 return 0;
2468}
2469
2470static void sky2_get_pauseparam(struct net_device *dev,
2471 struct ethtool_pauseparam *ecmd)
2472{
2473 struct sky2_port *sky2 = netdev_priv(dev);
2474
2475 ecmd->tx_pause = sky2->tx_pause;
2476 ecmd->rx_pause = sky2->rx_pause;
2477 ecmd->autoneg = sky2->autoneg;
2478}
2479
2480static int sky2_set_pauseparam(struct net_device *dev,
2481 struct ethtool_pauseparam *ecmd)
2482{
2483 struct sky2_port *sky2 = netdev_priv(dev);
2484 int err = 0;
2485
2486 sky2->autoneg = ecmd->autoneg;
2487 sky2->tx_pause = ecmd->tx_pause != 0;
2488 sky2->rx_pause = ecmd->rx_pause != 0;
2489
2490 if (netif_running(dev)) {
2491 sky2_down(dev);
2492 err = sky2_up(dev);
2493 }
2494
2495 return err;
2496}
2497
2498#ifdef CONFIG_PM
2499static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2500{
2501 struct sky2_port *sky2 = netdev_priv(dev);
2502
2503 wol->supported = WAKE_MAGIC;
2504 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2505}
2506
2507static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2508{
2509 struct sky2_port *sky2 = netdev_priv(dev);
2510 struct sky2_hw *hw = sky2->hw;
2511
2512 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2513 return -EOPNOTSUPP;
2514
2515 sky2->wol = wol->wolopts == WAKE_MAGIC;
2516
2517 if (sky2->wol) {
2518 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2519
2520 sky2_write16(hw, WOL_CTRL_STAT,
2521 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2522 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2523 } else
2524 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2525
2526 return 0;
2527}
2528#endif
2529
793b883e
SH		 2530static void sky2_get_ringparam(struct net_device *dev,
2531 struct ethtool_ringparam *ering)
2532{
2533 struct sky2_port *sky2 = netdev_priv(dev);
2534
2535 ering->rx_max_pending = RX_MAX_PENDING;
2536 ering->rx_mini_max_pending = 0;
2537 ering->rx_jumbo_max_pending = 0;
2538 ering->tx_max_pending = TX_RING_SIZE - 1;
2539
2540 ering->rx_pending = sky2->rx_pending;
2541 ering->rx_mini_pending = 0;
2542 ering->rx_jumbo_pending = 0;
2543 ering->tx_pending = sky2->tx_pending;
2544}
2545
2546static int sky2_set_ringparam(struct net_device *dev,
2547 struct ethtool_ringparam *ering)
2548{
2549 struct sky2_port *sky2 = netdev_priv(dev);
2550 int err = 0;
2551
2552 if (ering->rx_pending > RX_MAX_PENDING ||
2553 ering->rx_pending < 8 ||
2554 ering->tx_pending < MAX_SKB_TX_LE ||
2555 ering->tx_pending > TX_RING_SIZE - 1)
2556 return -EINVAL;
2557
2558 if (netif_running(dev))
2559 sky2_down(dev);
2560
2561 sky2->rx_pending = ering->rx_pending;
2562 sky2->tx_pending = ering->tx_pending;
2563
2564 if (netif_running(dev))
2565 err = sky2_up(dev);
2566
2567 return err;
2568}
2569
793b883e
SH		 2570static int sky2_get_regs_len(struct net_device *dev)
2571{
6e4cbb34 2572 return 0x4000;
793b883e
SH		 2573}
2574
2575/*
2576 * Returns copy of control register region
6e4cbb34 2577 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2578 */
2579static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2580 void *p)
2581{
2582 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2583 const void __iomem *io = sky2->hw->regs;
793b883e 2584
6e4cbb34 2585 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2586 regs->version = 1;
6e4cbb34 2587 memset(p, 0, regs->len);
793b883e 2588
6e4cbb34
SH		 2589 memcpy_fromio(p, io, B3_RAM_ADDR);
2590
2591 memcpy_fromio(p + B3_RI_WTO_R1,
2592 io + B3_RI_WTO_R1,
2593 regs->len - B3_RI_WTO_R1);
793b883e 2594}
cd28ab6a
SH		 2595
2596static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2597 .get_settings = sky2_get_settings,
2598 .set_settings = sky2_set_settings,
2599 .get_drvinfo = sky2_get_drvinfo,
2600 .get_msglevel = sky2_get_msglevel,
2601 .set_msglevel = sky2_set_msglevel,
2602 .get_regs_len = sky2_get_regs_len,
2603 .get_regs = sky2_get_regs,
2604 .get_link = ethtool_op_get_link,
2605 .get_sg = ethtool_op_get_sg,
2606 .set_sg = ethtool_op_set_sg,
2607 .get_tx_csum = ethtool_op_get_tx_csum,
2608 .set_tx_csum = ethtool_op_set_tx_csum,
2609 .get_tso = ethtool_op_get_tso,
2610 .set_tso = ethtool_op_set_tso,
2611 .get_rx_csum = sky2_get_rx_csum,
2612 .set_rx_csum = sky2_set_rx_csum,
2613 .get_strings = sky2_get_strings,
2614 .get_ringparam = sky2_get_ringparam,
2615 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2616 .get_pauseparam = sky2_get_pauseparam,
2617 .set_pauseparam = sky2_set_pauseparam,
2618#ifdef CONFIG_PM
793b883e
SH		 2619 .get_wol = sky2_get_wol,
2620 .set_wol = sky2_set_wol,
cd28ab6a 2621#endif
793b883e 2622 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2623 .get_stats_count = sky2_get_stats_count,
2624 .get_ethtool_stats = sky2_get_ethtool_stats,
2625};
2626
2627/* Initialize network device */
2628static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2629 unsigned port, int highmem)
2630{
2631 struct sky2_port *sky2;
2632 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2633
2634 if (!dev) {
2635 printk(KERN_ERR "sky2 etherdev alloc failed");
2636 return NULL;
2637 }
2638
2639 SET_MODULE_OWNER(dev);
2640 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2641 dev->open = sky2_up;
2642 dev->stop = sky2_down;
2643 dev->hard_start_xmit = sky2_xmit_frame;
2644 dev->get_stats = sky2_get_stats;
2645 dev->set_multicast_list = sky2_set_multicast;
2646 dev->set_mac_address = sky2_set_mac_address;
2647 dev->change_mtu = sky2_change_mtu;
2648 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2649 dev->tx_timeout = sky2_tx_timeout;
2650 dev->watchdog_timeo = TX_WATCHDOG;
2651 if (port == 0)
2652 dev->poll = sky2_poll;
2653 dev->weight = NAPI_WEIGHT;
2654#ifdef CONFIG_NET_POLL_CONTROLLER
2655 dev->poll_controller = sky2_netpoll;
2656#endif
cd28ab6a
SH		 2657
2658 sky2 = netdev_priv(dev);
2659 sky2->netdev = dev;
2660 sky2->hw = hw;
2661 sky2->msg_enable = netif_msg_init(debug, default_msg);
2662
2663 spin_lock_init(&sky2->tx_lock);
2664 /* Auto speed and flow control */
2665 sky2->autoneg = AUTONEG_ENABLE;
2666 sky2->tx_pause = 0;
2667 sky2->rx_pause = 1;
2668 sky2->duplex = -1;
2669 sky2->speed = -1;
2670 sky2->advertising = sky2_supported_modes(hw);
2671 sky2->rx_csum = 1;
793b883e
SH		 2672 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2673 sky2->tx_pending = TX_DEF_PENDING;
2674 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
cd28ab6a
SH		 2675
2676 hw->dev[port] = dev;
2677
2678 sky2->port = port;
2679
793b883e 2680 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
cd28ab6a
SH		 2681 if (highmem)
2682 dev->features |= NETIF_F_HIGHDMA;
793b883e 2683 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2684
d1f13708
SH		 2685#ifdef SKY2_VLAN_TAG_USED
2686 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2687 dev->vlan_rx_register = sky2_vlan_rx_register;
2688 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2689#endif
2690
cd28ab6a 2691 /* read the mac address */
793b883e 2692 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
cd28ab6a
SH		 2693
2694 /* device is off until link detection */
2695 netif_carrier_off(dev);
2696 netif_stop_queue(dev);
2697
2698 return dev;
2699}
2700
2701static inline void sky2_show_addr(struct net_device *dev)
2702{
2703 const struct sky2_port *sky2 = netdev_priv(dev);
2704
2705 if (netif_msg_probe(sky2))
2706 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2707 dev->name,
2708 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2709 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2710}
2711
2712static int __devinit sky2_probe(struct pci_dev *pdev,
2713 const struct pci_device_id *ent)
2714{
793b883e 2715 struct net_device *dev, *dev1 = NULL;
cd28ab6a
SH		 2716 struct sky2_hw *hw;
2717 int err, using_dac = 0;
2718
793b883e
SH		 2719 err = pci_enable_device(pdev);
2720 if (err) {
cd28ab6a
SH		 2721 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2722 pci_name(pdev));
2723 goto err_out;
2724 }
2725
793b883e
SH		 2726 err = pci_request_regions(pdev, DRV_NAME);
2727 if (err) {
cd28ab6a
SH		 2728 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2729 pci_name(pdev));
793b883e 2730 goto err_out;
cd28ab6a
SH		 2731 }
2732
2733 pci_set_master(pdev);
2734
2735 if (sizeof(dma_addr_t) > sizeof(u32)) {
2736 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2737 if (!err)
2738 using_dac = 1;
2739 }
2740
2741 if (!using_dac) {
2742 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2743 if (err) {
2744 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2745 pci_name(pdev));
2746 goto err_out_free_regions;
2747 }
2748 }
cd28ab6a
SH		 2749#ifdef __BIG_ENDIAN
2750 /* byte swap decriptors in hardware */
2751 {
2752 u32 reg;
2753
2754 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2755 reg |= PCI_REV_DESC;
2756 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2757 }
2758#endif
2759
2760 err = -ENOMEM;
2761 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2762 if (!hw) {
2763 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2764 pci_name(pdev));
2765 goto err_out_free_regions;
2766 }
2767
2768 memset(hw, 0, sizeof(*hw));
2769 hw->pdev = pdev;
2770 spin_lock_init(&hw->phy_lock);
2771
2772 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2773 if (!hw->regs) {
2774 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2775 pci_name(pdev));
2776 goto err_out_free_hw;
2777 }
2778
cd28ab6a
SH		 2779 err = sky2_reset(hw);
2780 if (err)
793b883e 2781 goto err_out_iounmap;
cd28ab6a 2782
793b883e 2783 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
cd28ab6a 2784 pci_resource_start(pdev, 0), pdev->irq,
793b883e
SH		 2785 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2786 hw->chip_id, hw->chip_rev);
cd28ab6a 2787
793b883e
SH		 2788 dev = sky2_init_netdev(hw, 0, using_dac);
2789 if (!dev)
cd28ab6a
SH		 2790 goto err_out_free_pci;
2791
793b883e
SH		 2792 err = register_netdev(dev);
2793 if (err) {
cd28ab6a
SH		 2794 printk(KERN_ERR PFX "%s: cannot register net device\n",
2795 pci_name(pdev));
2796 goto err_out_free_netdev;
2797 }
2798
2799 sky2_show_addr(dev);
2800
2801 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2802 if (register_netdev(dev1) == 0)
2803 sky2_show_addr(dev1);
2804 else {
2805 /* Failure to register second port need not be fatal */
793b883e
SH		 2806 printk(KERN_WARNING PFX
2807 "register of second port failed\n");
cd28ab6a
SH		 2808 hw->dev[1] = NULL;
2809 free_netdev(dev1);
2810 }
2811 }
2812
793b883e
SH		 2813 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2814 if (err) {
2815 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2816 pci_name(pdev), pdev->irq);
2817 goto err_out_unregister;
2818 }
2819
2820 hw->intr_mask = Y2_IS_BASE;
2821 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2822
2823 pci_set_drvdata(pdev, hw);
2824
cd28ab6a
SH		 2825 return 0;
2826
793b883e
SH		 2827err_out_unregister:
2828 if (dev1) {
2829 unregister_netdev(dev1);
2830 free_netdev(dev1);
2831 }
2832 unregister_netdev(dev);
cd28ab6a
SH		 2833err_out_free_netdev:
2834 free_netdev(dev);
cd28ab6a 2835err_out_free_pci:
793b883e 2836 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 2837 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2838err_out_iounmap:
2839 iounmap(hw->regs);
2840err_out_free_hw:
2841 kfree(hw);
2842err_out_free_regions:
2843 pci_release_regions(pdev);
cd28ab6a 2844 pci_disable_device(pdev);
cd28ab6a
SH		 2845err_out:
2846 return err;
2847}
2848
2849static void __devexit sky2_remove(struct pci_dev *pdev)
2850{
793b883e 2851 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2852 struct net_device *dev0, *dev1;
2853
793b883e 2854 if (!hw)
cd28ab6a
SH		 2855 return;
2856
cd28ab6a 2857 dev0 = hw->dev[0];
793b883e
SH		 2858 dev1 = hw->dev[1];
2859 if (dev1)
2860 unregister_netdev(dev1);
cd28ab6a
SH		 2861 unregister_netdev(dev0);
2862
793b883e 2863 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 2864 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 2865 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 2866
2867 free_irq(pdev->irq, hw);
793b883e 2868 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 2869 pci_release_regions(pdev);
2870 pci_disable_device(pdev);
793b883e 2871
cd28ab6a
SH		 2872 if (dev1)
2873 free_netdev(dev1);
2874 free_netdev(dev0);
2875 iounmap(hw->regs);
2876 kfree(hw);
2877 pci_set_drvdata(pdev, NULL);
2878}
2879
2880#ifdef CONFIG_PM
2881static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2882{
793b883e 2883 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2884 int i, wol = 0;
2885
2886 for (i = 0; i < 2; i++) {
2887 struct net_device *dev = hw->dev[i];
2888
2889 if (dev) {
2890 struct sky2_port *sky2 = netdev_priv(dev);
2891 if (netif_running(dev)) {
2892 netif_carrier_off(dev);
2893 sky2_down(dev);
2894 }
2895 netif_device_detach(dev);
2896 wol |= sky2->wol;
2897 }
2898 }
2899
2900 pci_save_state(pdev);
2901 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
2902 pci_disable_device(pdev);
2903 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2904
2905 return 0;
2906}
2907
2908static int sky2_resume(struct pci_dev *pdev)
2909{
793b883e 2910 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 2911 int i;
2912
2913 pci_set_power_state(pdev, PCI_D0);
2914 pci_restore_state(pdev);
2915 pci_enable_wake(pdev, PCI_D0, 0);
2916
2917 sky2_reset(hw);
2918
2919 for (i = 0; i < 2; i++) {
2920 struct net_device *dev = hw->dev[i];
2921 if (dev) {
2922 netif_device_attach(dev);
2923 if (netif_running(dev))
2924 sky2_up(dev);
2925 }
2926 }
2927 return 0;
2928}
2929#endif
2930
2931static struct pci_driver sky2_driver = {
793b883e
SH		 2932 .name = DRV_NAME,
2933 .id_table = sky2_id_table,
2934 .probe = sky2_probe,
2935 .remove = __devexit_p(sky2_remove),
cd28ab6a 2936#ifdef CONFIG_PM
793b883e
SH		 2937 .suspend = sky2_suspend,
2938 .resume = sky2_resume,
cd28ab6a
SH		 2939#endif
2940};
2941
2942static int __init sky2_init_module(void)
2943{
cd28ab6a
SH		 2944 return pci_module_init(&sky2_driver);
2945}
2946
2947static void __exit sky2_cleanup_module(void)
2948{
2949 pci_unregister_driver(&sky2_driver);
2950}
2951
2952module_init(sky2_init_module);
2953module_exit(sky2_cleanup_module);
2954
2955MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
2956MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
2957MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)