Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | /* | |
cd28ab6a SH |
27 | * TOTEST |
28 | * - speed setting | |
724bca3c | 29 | * - suspend/resume |
cd28ab6a SH |
30 | */ |
31 | ||
32 | #include <linux/config.h> | |
793b883e | 33 | #include <linux/crc32.h> |
cd28ab6a SH |
34 | #include <linux/kernel.h> |
35 | #include <linux/version.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/netdevice.h> | |
d0bbccfa | 38 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
39 | #include <linux/etherdevice.h> |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/ip.h> | |
43 | #include <linux/tcp.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/delay.h> | |
91c86df5 | 46 | #include <linux/workqueue.h> |
d1f13708 | 47 | #include <linux/if_vlan.h> |
ef743d33 | 48 | #include <linux/mii.h> |
cd28ab6a SH |
49 | |
50 | #include <asm/irq.h> | |
51 | ||
d1f13708 SH |
52 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
53 | #define SKY2_VLAN_TAG_USED 1 | |
54 | #endif | |
55 | ||
cd28ab6a SH |
56 | #include "sky2.h" |
57 | ||
58 | #define DRV_NAME "sky2" | |
5f4f9dc1 | 59 | #define DRV_VERSION "0.9" |
cd28ab6a SH |
60 | #define PFX DRV_NAME " " |
61 | ||
62 | /* | |
63 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
64 | * that are organized into three (receive, transmit, status) different rings | |
65 | * similar to Tigon3. A transmit can require several elements; | |
66 | * a receive requires one (or two if using 64 bit dma). | |
67 | */ | |
68 | ||
cd28ab6a | 69 | #define is_ec_a1(hw) \ |
21437643 SH |
70 | unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \ |
71 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
cd28ab6a | 72 | |
13210ce5 | 73 | #define RX_LE_SIZE 512 |
cd28ab6a | 74 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 75 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 76 | #define RX_DEF_PENDING RX_MAX_PENDING |
793b883e SH |
77 | |
78 | #define TX_RING_SIZE 512 | |
79 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
80 | #define TX_MIN_PENDING 64 | |
81 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 82 | |
793b883e | 83 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
84 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
85 | #define ETH_JUMBO_MTU 9000 | |
86 | #define TX_WATCHDOG (5 * HZ) | |
87 | #define NAPI_WEIGHT 64 | |
88 | #define PHY_RETRIES 1000 | |
89 | ||
90 | static const u32 default_msg = | |
793b883e SH |
91 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
92 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
93 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR; | |
cd28ab6a | 94 | |
793b883e | 95 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
96 | module_param(debug, int, 0); |
97 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
98 | ||
bdb5c58e SH |
99 | static int copybreak __read_mostly = 256; |
100 | module_param(copybreak, int, 0); | |
101 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
102 | ||
cd28ab6a | 103 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 104 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
105 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
106 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
107 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
123 | { 0 } |
124 | }; | |
793b883e | 125 | |
cd28ab6a SH |
126 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
127 | ||
128 | /* Avoid conditionals by using array */ | |
129 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
130 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
131 | ||
92f965e8 SH |
132 | /* This driver supports yukon2 chipset only */ |
133 | static const char *yukon2_name[] = { | |
134 | "XL", /* 0xb3 */ | |
135 | "EC Ultra", /* 0xb4 */ | |
136 | "UNKNOWN", /* 0xb5 */ | |
137 | "EC", /* 0xb6 */ | |
138 | "FE", /* 0xb7 */ | |
793b883e SH |
139 | }; |
140 | ||
793b883e | 141 | /* Access to external PHY */ |
ef743d33 | 142 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
143 | { |
144 | int i; | |
145 | ||
146 | gma_write16(hw, port, GM_SMI_DATA, val); | |
147 | gma_write16(hw, port, GM_SMI_CTRL, | |
148 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
149 | ||
150 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 151 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 152 | return 0; |
793b883e | 153 | udelay(1); |
cd28ab6a | 154 | } |
ef743d33 | 155 | |
793b883e | 156 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 157 | return -ETIMEDOUT; |
cd28ab6a SH |
158 | } |
159 | ||
ef743d33 | 160 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
161 | { |
162 | int i; | |
163 | ||
793b883e | 164 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
165 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
166 | ||
167 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
168 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
169 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
170 | return 0; | |
171 | } | |
172 | ||
793b883e | 173 | udelay(1); |
cd28ab6a SH |
174 | } |
175 | ||
ef743d33 SH |
176 | return -ETIMEDOUT; |
177 | } | |
178 | ||
179 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
180 | { | |
181 | u16 v; | |
182 | ||
183 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
184 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
185 | return v; | |
cd28ab6a SH |
186 | } |
187 | ||
5afa0a9c SH |
188 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
189 | { | |
190 | u16 power_control; | |
191 | u32 reg1; | |
192 | int vaux; | |
193 | int ret = 0; | |
194 | ||
195 | pr_debug("sky2_set_power_state %d\n", state); | |
196 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
197 | ||
198 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | |
199 | vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
200 | (power_control & PCI_PM_CAP_PME_D3cold); | |
201 | ||
202 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | |
203 | ||
204 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
205 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
206 | ||
207 | switch (state) { | |
208 | case PCI_D0: | |
209 | /* switch power to VCC (WA for VAUX problem) */ | |
210 | sky2_write8(hw, B0_POWER_CTRL, | |
211 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
212 | ||
213 | /* disable Core Clock Division, */ | |
214 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
215 | ||
216 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
217 | /* enable bits are inverted */ | |
218 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
219 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
220 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
221 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
222 | else | |
223 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
224 | ||
225 | /* Turn off phy power saving */ | |
226 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
227 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
228 | ||
d571b694 | 229 | /* looks like this XL is back asswards .. */ |
5afa0a9c SH |
230 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
231 | reg1 |= PCI_Y2_PHY1_COMA; | |
232 | if (hw->ports > 1) | |
233 | reg1 |= PCI_Y2_PHY2_COMA; | |
234 | } | |
235 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
236 | break; | |
237 | ||
238 | case PCI_D3hot: | |
239 | case PCI_D3cold: | |
240 | /* Turn on phy power saving */ | |
241 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
242 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
243 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
244 | else | |
245 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
246 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
247 | ||
248 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
249 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
250 | else | |
251 | /* enable bits are inverted */ | |
252 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
253 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
254 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
255 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
256 | ||
257 | /* switch power to VAUX */ | |
258 | if (vaux && state != PCI_D3cold) | |
259 | sky2_write8(hw, B0_POWER_CTRL, | |
260 | (PC_VAUX_ENA | PC_VCC_ENA | | |
261 | PC_VAUX_ON | PC_VCC_OFF)); | |
262 | break; | |
263 | default: | |
264 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
265 | ret = -1; | |
266 | } | |
267 | ||
268 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | |
269 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
270 | return ret; | |
271 | } | |
272 | ||
cd28ab6a SH |
273 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
274 | { | |
275 | u16 reg; | |
276 | ||
277 | /* disable all GMAC IRQ's */ | |
278 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
279 | /* disable PHY IRQs */ | |
280 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 281 | |
cd28ab6a SH |
282 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
283 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
284 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
285 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
286 | ||
287 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
288 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
289 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
290 | } | |
291 | ||
292 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
293 | { | |
294 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 295 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 296 | |
793b883e | 297 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
298 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
299 | ||
300 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 301 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
302 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
303 | ||
304 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
305 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
306 | else | |
307 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
308 | ||
309 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
310 | } | |
311 | ||
312 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
313 | if (hw->copper) { | |
314 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
315 | /* enable automatic crossover */ | |
316 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
317 | } else { | |
318 | /* disable energy detect */ | |
319 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
320 | ||
321 | /* enable automatic crossover */ | |
322 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
323 | ||
324 | if (sky2->autoneg == AUTONEG_ENABLE && | |
325 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
326 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
327 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
328 | } | |
329 | } | |
330 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
331 | } else { | |
332 | /* workaround for deviation #4.88 (CRC errors) */ | |
333 | /* disable Automatic Crossover */ | |
334 | ||
335 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
336 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
337 | ||
338 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
339 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
340 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
341 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
342 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
343 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
344 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
345 | ||
346 | /* select page 1 to access Fiber registers */ | |
347 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
348 | } | |
cd28ab6a SH |
349 | } |
350 | ||
351 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
352 | if (sky2->autoneg == AUTONEG_DISABLE) | |
353 | ctrl &= ~PHY_CT_ANE; | |
354 | else | |
355 | ctrl |= PHY_CT_ANE; | |
356 | ||
357 | ctrl |= PHY_CT_RESET; | |
358 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
359 | ||
360 | ctrl = 0; | |
361 | ct1000 = 0; | |
362 | adv = PHY_AN_CSMA; | |
363 | ||
364 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
365 | if (hw->copper) { | |
366 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
367 | ct1000 |= PHY_M_1000C_AFD; | |
368 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
369 | ct1000 |= PHY_M_1000C_AHD; | |
370 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
371 | adv |= PHY_M_AN_100_FD; | |
372 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
373 | adv |= PHY_M_AN_100_HD; | |
374 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
375 | adv |= PHY_M_AN_10_FD; | |
376 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
377 | adv |= PHY_M_AN_10_HD; | |
793b883e | 378 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
379 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
380 | ||
381 | /* Set Flow-control capabilities */ | |
382 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 383 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 384 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 385 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
386 | else if (!sky2->rx_pause && sky2->tx_pause) |
387 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
388 | ||
389 | /* Restart Auto-negotiation */ | |
390 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
391 | } else { | |
392 | /* forced speed/duplex settings */ | |
393 | ct1000 = PHY_M_1000C_MSE; | |
394 | ||
395 | if (sky2->duplex == DUPLEX_FULL) | |
396 | ctrl |= PHY_CT_DUP_MD; | |
397 | ||
398 | switch (sky2->speed) { | |
399 | case SPEED_1000: | |
400 | ctrl |= PHY_CT_SP1000; | |
401 | break; | |
402 | case SPEED_100: | |
403 | ctrl |= PHY_CT_SP100; | |
404 | break; | |
405 | } | |
406 | ||
407 | ctrl |= PHY_CT_RESET; | |
408 | } | |
409 | ||
410 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
411 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
412 | ||
413 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
414 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
415 | ||
416 | /* Setup Phy LED's */ | |
417 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
418 | ledover = 0; | |
419 | ||
420 | switch (hw->chip_id) { | |
421 | case CHIP_ID_YUKON_FE: | |
422 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
423 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
424 | ||
425 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
426 | ||
427 | /* delete ACT LED control bits */ | |
428 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
429 | /* change ACT LED control to blink mode */ | |
430 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
431 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
432 | break; | |
433 | ||
434 | case CHIP_ID_YUKON_XL: | |
793b883e | 435 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
436 | |
437 | /* select page 3 to access LED control register */ | |
438 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
439 | ||
440 | /* set LED Function Control register */ | |
793b883e SH |
441 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
442 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
443 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
444 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
445 | |
446 | /* set Polarity Control register */ | |
447 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
448 | (PHY_M_POLC_LS1_P_MIX(4) | |
449 | PHY_M_POLC_IS0_P_MIX(4) | | |
450 | PHY_M_POLC_LOS_CTRL(2) | | |
451 | PHY_M_POLC_INIT_CTRL(2) | | |
452 | PHY_M_POLC_STA1_CTRL(2) | | |
453 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
454 | |
455 | /* restore page register */ | |
793b883e | 456 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
457 | break; |
458 | ||
459 | default: | |
460 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
461 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
462 | /* turn off the Rx LED (LED_RX) */ | |
463 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
464 | } | |
465 | ||
466 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
467 | ||
468 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | |
469 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
470 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
471 | } | |
472 | ||
473 | if (ledover) | |
474 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
475 | ||
d571b694 | 476 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
477 | if (sky2->autoneg == AUTONEG_ENABLE) |
478 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
479 | else | |
480 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
481 | } | |
482 | ||
483 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |
484 | { | |
485 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
486 | u16 reg; | |
487 | int i; | |
488 | const u8 *addr = hw->dev[port]->dev_addr; | |
489 | ||
42eeea01 SH |
490 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
491 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
492 | |
493 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
494 | ||
793b883e | 495 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
496 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
497 | /* clear GMAC 1 Control reset */ | |
498 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
499 | do { | |
500 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
501 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
502 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
503 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
504 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
505 | } | |
506 | ||
cd28ab6a SH |
507 | if (sky2->autoneg == AUTONEG_DISABLE) { |
508 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
509 | reg |= GM_GPCR_AU_ALL_DIS; | |
510 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
511 | gma_read16(hw, port, GM_GP_CTRL); | |
512 | ||
cd28ab6a SH |
513 | switch (sky2->speed) { |
514 | case SPEED_1000: | |
515 | reg |= GM_GPCR_SPEED_1000; | |
516 | /* fallthru */ | |
517 | case SPEED_100: | |
518 | reg |= GM_GPCR_SPEED_100; | |
519 | } | |
520 | ||
521 | if (sky2->duplex == DUPLEX_FULL) | |
522 | reg |= GM_GPCR_DUP_FULL; | |
523 | } else | |
524 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
525 | ||
526 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
527 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
528 | reg |= |
529 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
530 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
531 | /* disable Rx flow-control */ |
532 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
533 | } | |
534 | ||
535 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
536 | ||
793b883e | 537 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 538 | |
91c86df5 | 539 | down(&sky2->phy_sema); |
cd28ab6a | 540 | sky2_phy_init(hw, port); |
91c86df5 | 541 | up(&sky2->phy_sema); |
cd28ab6a SH |
542 | |
543 | /* MIB clear */ | |
544 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
545 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
546 | ||
547 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 548 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
549 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
550 | ||
551 | /* transmit control */ | |
552 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
553 | ||
554 | /* receive control reg: unicast + multicast + no FCS */ | |
555 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 556 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
557 | |
558 | /* transmit flow control */ | |
559 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
560 | ||
561 | /* transmit parameter */ | |
562 | gma_write16(hw, port, GM_TX_PARAM, | |
563 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
564 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
565 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
566 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
567 | ||
568 | /* serial mode register */ | |
569 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 570 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 571 | |
6b1a3aef | 572 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
573 | reg |= GM_SMOD_JUMBO_ENA; |
574 | ||
575 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
576 | ||
cd28ab6a SH |
577 | /* virtual address for data */ |
578 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
579 | ||
793b883e SH |
580 | /* physical address: used for pause frames */ |
581 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
582 | ||
583 | /* ignore counter overflows */ | |
cd28ab6a SH |
584 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
585 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
586 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
587 | ||
588 | /* Configure Rx MAC FIFO */ | |
589 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 590 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
d1f13708 | 591 | GMF_RX_CTRL_DEF); |
cd28ab6a | 592 | |
d571b694 | 593 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 594 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 595 | |
793b883e SH |
596 | /* Set threshold to 0xa (64 bytes) |
597 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
598 | */ |
599 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
600 | ||
601 | /* Configure Tx MAC FIFO */ | |
602 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
603 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 SH |
604 | |
605 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
606 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
607 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
608 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
609 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
610 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
611 | /* Disable Store & Forward mode for TX */ | |
612 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
613 | } | |
614 | } | |
615 | ||
cd28ab6a SH |
616 | } |
617 | ||
618 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len) | |
619 | { | |
620 | u32 end; | |
621 | ||
622 | start /= 8; | |
623 | len /= 8; | |
624 | end = start + len - 1; | |
793b883e | 625 | |
cd28ab6a SH |
626 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
627 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
628 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
629 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
630 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
631 | ||
632 | if (q == Q_R1 || q == Q_R2) { | |
793b883e SH |
633 | u32 rxup, rxlo; |
634 | ||
635 | rxlo = len/2; | |
636 | rxup = rxlo + len/4; | |
793b883e | 637 | |
cd28ab6a | 638 | /* Set thresholds on receive queue's */ |
793b883e SH |
639 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup); |
640 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo); | |
cd28ab6a SH |
641 | } else { |
642 | /* Enable store & forward on Tx queue's because | |
643 | * Tx FIFO is only 1K on Yukon | |
644 | */ | |
645 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
646 | } | |
647 | ||
648 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 649 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
650 | } |
651 | ||
cd28ab6a | 652 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 653 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
654 | { |
655 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
656 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
657 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 658 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
659 | } |
660 | ||
cd28ab6a SH |
661 | /* Setup prefetch unit registers. This is the interface between |
662 | * hardware and driver list elements | |
663 | */ | |
8cc048e3 | 664 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
665 | u64 addr, u32 last) |
666 | { | |
cd28ab6a SH |
667 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
668 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
669 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
670 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
671 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
672 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
673 | |
674 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
675 | } |
676 | ||
793b883e SH |
677 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
678 | { | |
679 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
680 | ||
681 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
682 | return le; | |
683 | } | |
cd28ab6a SH |
684 | |
685 | /* | |
d571b694 | 686 | * This is a workaround code taken from SysKonnect sk98lin driver |
793b883e | 687 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a SH |
688 | */ |
689 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, | |
690 | u16 idx, u16 *last, u16 size) | |
cd28ab6a | 691 | { |
cd28ab6a SH |
692 | if (is_ec_a1(hw) && idx < *last) { |
693 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
694 | ||
695 | if (hwget == 0) { | |
696 | /* Start prefetching again */ | |
793b883e | 697 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
698 | goto setnew; |
699 | } | |
700 | ||
793b883e | 701 | if (hwget == size - 1) { |
cd28ab6a SH |
702 | /* set watermark to one list element */ |
703 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
704 | ||
705 | /* set put index to first list element */ | |
706 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
707 | } else /* have hardware go to end of list */ |
708 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
709 | size - 1); | |
cd28ab6a | 710 | } else { |
793b883e | 711 | setnew: |
cd28ab6a | 712 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 713 | } |
bea86103 | 714 | *last = idx; |
cd28ab6a SH |
715 | } |
716 | ||
793b883e | 717 | |
cd28ab6a SH |
718 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
719 | { | |
720 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
721 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
722 | return le; | |
723 | } | |
724 | ||
a018e330 SH |
725 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
726 | static inline u32 high32(dma_addr_t a) | |
727 | { | |
728 | return (a >> 16) >> 16; | |
729 | } | |
730 | ||
793b883e | 731 | /* Build description to hardware about buffer */ |
734d1868 | 732 | static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
733 | { |
734 | struct sky2_rx_le *le; | |
734d1868 SH |
735 | u32 hi = high32(map); |
736 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 737 | |
793b883e | 738 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 739 | le = sky2_next_rx(sky2); |
793b883e | 740 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
741 | le->ctrl = 0; |
742 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 743 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 744 | } |
793b883e | 745 | |
cd28ab6a | 746 | le = sky2_next_rx(sky2); |
734d1868 SH |
747 | le->addr = cpu_to_le32((u32) map); |
748 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
749 | le->ctrl = 0; |
750 | le->opcode = OP_PACKET | HW_OWNER; | |
751 | } | |
752 | ||
793b883e | 753 | |
cd28ab6a SH |
754 | /* Tell chip where to start receive checksum. |
755 | * Actually has two checksums, but set both same to avoid possible byte | |
756 | * order problems. | |
757 | */ | |
793b883e | 758 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
759 | { |
760 | struct sky2_rx_le *le; | |
761 | ||
cd28ab6a | 762 | le = sky2_next_rx(sky2); |
793b883e | 763 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
764 | le->ctrl = 0; |
765 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 766 | |
793b883e SH |
767 | sky2_write32(sky2->hw, |
768 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
769 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
770 | |
771 | } | |
772 | ||
6b1a3aef SH |
773 | /* |
774 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
775 | * reach the end of packet and since we can't make sure that we have | |
776 | * incoming data, we must reset the BMU while it is not doing a DMA | |
777 | * transfer. Since it is possible that the RX path is still active, | |
778 | * the RX RAM buffer will be stopped first, so any possible incoming | |
779 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
780 | * BMU is polled until any DMA in progress is ended and only then it | |
781 | * will be reset. | |
782 | */ | |
783 | static void sky2_rx_stop(struct sky2_port *sky2) | |
784 | { | |
785 | struct sky2_hw *hw = sky2->hw; | |
786 | unsigned rxq = rxqaddr[sky2->port]; | |
787 | int i; | |
788 | ||
789 | /* disable the RAM Buffer receive queue */ | |
790 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
791 | ||
792 | for (i = 0; i < 0xffff; i++) | |
793 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
794 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
795 | goto stopped; | |
796 | ||
797 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
798 | sky2->netdev->name); | |
799 | stopped: | |
800 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
801 | ||
802 | /* reset the Rx prefetch unit */ | |
803 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
804 | } | |
793b883e | 805 | |
d571b694 | 806 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
807 | static void sky2_rx_clean(struct sky2_port *sky2) |
808 | { | |
809 | unsigned i; | |
810 | ||
811 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 812 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
813 | struct ring_info *re = sky2->rx_ring + i; |
814 | ||
815 | if (re->skb) { | |
793b883e | 816 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 817 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
818 | PCI_DMA_FROMDEVICE); |
819 | kfree_skb(re->skb); | |
820 | re->skb = NULL; | |
821 | } | |
822 | } | |
823 | } | |
824 | ||
ef743d33 SH |
825 | /* Basic MII support */ |
826 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
827 | { | |
828 | struct mii_ioctl_data *data = if_mii(ifr); | |
829 | struct sky2_port *sky2 = netdev_priv(dev); | |
830 | struct sky2_hw *hw = sky2->hw; | |
831 | int err = -EOPNOTSUPP; | |
832 | ||
833 | if (!netif_running(dev)) | |
834 | return -ENODEV; /* Phy still in reset */ | |
835 | ||
836 | switch(cmd) { | |
837 | case SIOCGMIIPHY: | |
838 | data->phy_id = PHY_ADDR_MARV; | |
839 | ||
840 | /* fallthru */ | |
841 | case SIOCGMIIREG: { | |
842 | u16 val = 0; | |
91c86df5 SH |
843 | |
844 | down(&sky2->phy_sema); | |
ef743d33 | 845 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
91c86df5 SH |
846 | up(&sky2->phy_sema); |
847 | ||
ef743d33 SH |
848 | data->val_out = val; |
849 | break; | |
850 | } | |
851 | ||
852 | case SIOCSMIIREG: | |
853 | if (!capable(CAP_NET_ADMIN)) | |
854 | return -EPERM; | |
855 | ||
91c86df5 | 856 | down(&sky2->phy_sema); |
ef743d33 SH |
857 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
858 | data->val_in); | |
91c86df5 | 859 | up(&sky2->phy_sema); |
ef743d33 SH |
860 | break; |
861 | } | |
862 | return err; | |
863 | } | |
864 | ||
d1f13708 SH |
865 | #ifdef SKY2_VLAN_TAG_USED |
866 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
867 | { | |
868 | struct sky2_port *sky2 = netdev_priv(dev); | |
869 | struct sky2_hw *hw = sky2->hw; | |
870 | u16 port = sky2->port; | |
d1f13708 | 871 | |
f2e46561 | 872 | spin_lock(&sky2->tx_lock); |
d1f13708 SH |
873 | |
874 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
875 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
876 | sky2->vlgrp = grp; | |
877 | ||
f2e46561 | 878 | spin_unlock(&sky2->tx_lock); |
d1f13708 SH |
879 | } |
880 | ||
881 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
882 | { | |
883 | struct sky2_port *sky2 = netdev_priv(dev); | |
884 | struct sky2_hw *hw = sky2->hw; | |
885 | u16 port = sky2->port; | |
d1f13708 | 886 | |
f2e46561 | 887 | spin_lock(&sky2->tx_lock); |
d1f13708 SH |
888 | |
889 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
890 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
891 | if (sky2->vlgrp) | |
892 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
893 | ||
f2e46561 | 894 | spin_unlock(&sky2->tx_lock); |
d1f13708 SH |
895 | } |
896 | #endif | |
897 | ||
cd28ab6a SH |
898 | /* |
899 | * Allocate and setup receiver buffer pool. | |
900 | * In case of 64 bit dma, there are 2X as many list elements | |
901 | * available as ring entries | |
902 | * and need to reserve one list element so we don't wrap around. | |
79e57d32 SH |
903 | * |
904 | * It appears the hardware has a bug in the FIFO logic that | |
905 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
906 | * is not aligned. This means we can't use skb_reserve to align | |
907 | * the IP header. | |
cd28ab6a | 908 | */ |
6b1a3aef | 909 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 910 | { |
6b1a3aef | 911 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef SH |
912 | unsigned rxq = rxqaddr[sky2->port]; |
913 | int i; | |
cd28ab6a | 914 | |
6b1a3aef | 915 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 916 | sky2_qset(hw, rxq); |
6b1a3aef SH |
917 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
918 | ||
919 | rx_set_checksum(sky2); | |
793b883e | 920 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 921 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 922 | |
734d1868 | 923 | re->skb = dev_alloc_skb(sky2->rx_bufsize); |
cd28ab6a SH |
924 | if (!re->skb) |
925 | goto nomem; | |
926 | ||
6b1a3aef | 927 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
928 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
929 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
930 | } |
931 | ||
6b1a3aef SH |
932 | /* Tell chip about available buffers */ |
933 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
934 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
935 | return 0; |
936 | nomem: | |
937 | sky2_rx_clean(sky2); | |
938 | return -ENOMEM; | |
939 | } | |
940 | ||
941 | /* Bring up network interface. */ | |
942 | static int sky2_up(struct net_device *dev) | |
943 | { | |
944 | struct sky2_port *sky2 = netdev_priv(dev); | |
945 | struct sky2_hw *hw = sky2->hw; | |
946 | unsigned port = sky2->port; | |
947 | u32 ramsize, rxspace; | |
948 | int err = -ENOMEM; | |
949 | ||
950 | if (netif_msg_ifup(sky2)) | |
951 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
952 | ||
953 | /* must be power of 2 */ | |
954 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
955 | TX_RING_SIZE * |
956 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
957 | &sky2->tx_le_map); |
958 | if (!sky2->tx_le) | |
959 | goto err_out; | |
960 | ||
6cdbbdf3 | 961 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
962 | GFP_KERNEL); |
963 | if (!sky2->tx_ring) | |
964 | goto err_out; | |
965 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
966 | |
967 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
968 | &sky2->rx_le_map); | |
969 | if (!sky2->rx_le) | |
970 | goto err_out; | |
971 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
972 | ||
6cdbbdf3 | 973 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
974 | GFP_KERNEL); |
975 | if (!sky2->rx_ring) | |
976 | goto err_out; | |
977 | ||
978 | sky2_mac_init(hw, port); | |
979 | ||
980 | /* Configure RAM buffers */ | |
981 | if (hw->chip_id == CHIP_ID_YUKON_FE || | |
982 | (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2)) | |
983 | ramsize = 4096; | |
984 | else { | |
793b883e SH |
985 | u8 e0 = sky2_read8(hw, B2_E_0); |
986 | ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096); | |
cd28ab6a SH |
987 | } |
988 | ||
989 | /* 2/3 for Rx */ | |
990 | rxspace = (2 * ramsize) / 3; | |
991 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); | |
992 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); | |
993 | ||
793b883e SH |
994 | /* Make sure SyncQ is disabled */ |
995 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
996 | RB_RST_SET); | |
997 | ||
af4ed7e6 | 998 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 SH |
999 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) |
1000 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
1001 | ||
1002 | ||
6b1a3aef SH |
1003 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1004 | TX_RING_SIZE - 1); | |
cd28ab6a | 1005 | |
6b1a3aef | 1006 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1007 | if (err) |
1008 | goto err_out; | |
1009 | ||
cd28ab6a SH |
1010 | /* Enable interrupts from phy/mac for port */ |
1011 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1012 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1013 | return 0; | |
1014 | ||
1015 | err_out: | |
1016 | if (sky2->rx_le) | |
1017 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1018 | sky2->rx_le, sky2->rx_le_map); | |
1019 | if (sky2->tx_le) | |
1020 | pci_free_consistent(hw->pdev, | |
1021 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1022 | sky2->tx_le, sky2->tx_le_map); | |
1023 | if (sky2->tx_ring) | |
1024 | kfree(sky2->tx_ring); | |
1025 | if (sky2->rx_ring) | |
1026 | kfree(sky2->rx_ring); | |
1027 | ||
1028 | return err; | |
1029 | } | |
1030 | ||
793b883e SH |
1031 | /* Modular subtraction in ring */ |
1032 | static inline int tx_dist(unsigned tail, unsigned head) | |
1033 | { | |
129372d0 | 1034 | return (head - tail) % TX_RING_SIZE; |
793b883e | 1035 | } |
cd28ab6a | 1036 | |
793b883e SH |
1037 | /* Number of list elements available for next tx */ |
1038 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1039 | { |
793b883e | 1040 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1041 | } |
1042 | ||
793b883e SH |
1043 | /* Estimate of number of transmit list elements required */ |
1044 | static inline unsigned tx_le_req(const struct sk_buff *skb) | |
cd28ab6a | 1045 | { |
793b883e SH |
1046 | unsigned count; |
1047 | ||
1048 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1049 | count += skb_shinfo(skb)->nr_frags * count; | |
1050 | ||
1051 | if (skb_shinfo(skb)->tso_size) | |
1052 | ++count; | |
1053 | ||
0e3ff6aa | 1054 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1055 | ++count; |
1056 | ||
1057 | return count; | |
cd28ab6a SH |
1058 | } |
1059 | ||
793b883e SH |
1060 | /* |
1061 | * Put one packet in ring for transmit. | |
1062 | * A single packet can generate multiple list elements, and | |
1063 | * the number of ring elements will probably be less than the number | |
1064 | * of list elements used. | |
f2e46561 SH |
1065 | * |
1066 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1067 | */ |
cd28ab6a SH |
1068 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1069 | { | |
1070 | struct sky2_port *sky2 = netdev_priv(dev); | |
1071 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1072 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1073 | struct tx_ring_info *re; |
cd28ab6a SH |
1074 | unsigned i, len; |
1075 | dma_addr_t mapping; | |
1076 | u32 addr64; | |
1077 | u16 mss; | |
1078 | u8 ctrl; | |
1079 | ||
f2e46561 | 1080 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1081 | return NETDEV_TX_LOCKED; |
1082 | ||
793b883e | 1083 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1084 | /* There is a known but harmless race with lockless tx |
1085 | * and netif_stop_queue. | |
1086 | */ | |
1087 | if (!netif_queue_stopped(dev)) { | |
1088 | netif_stop_queue(dev); | |
1089 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1090 | dev->name); | |
1091 | } | |
f2e46561 | 1092 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1093 | |
cd28ab6a SH |
1094 | return NETDEV_TX_BUSY; |
1095 | } | |
1096 | ||
793b883e | 1097 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1098 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1099 | dev->name, sky2->tx_prod, skb->len); | |
1100 | ||
cd28ab6a SH |
1101 | len = skb_headlen(skb); |
1102 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1103 | addr64 = high32(mapping); |
793b883e SH |
1104 | |
1105 | re = sky2->tx_ring + sky2->tx_prod; | |
1106 | ||
a018e330 SH |
1107 | /* Send high bits if changed or crosses boundary */ |
1108 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1109 | le = get_tx_le(sky2); |
1110 | le->tx.addr = cpu_to_le32(addr64); | |
1111 | le->ctrl = 0; | |
1112 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1113 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1114 | } |
cd28ab6a SH |
1115 | |
1116 | /* Check for TCP Segmentation Offload */ | |
1117 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1118 | if (mss != 0) { |
cd28ab6a SH |
1119 | /* just drop the packet if non-linear expansion fails */ |
1120 | if (skb_header_cloned(skb) && | |
1121 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
1122 | dev_kfree_skb_any(skb); |
1123 | goto out_unlock; | |
cd28ab6a SH |
1124 | } |
1125 | ||
1126 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1127 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1128 | mss += ETH_HLEN; | |
793b883e | 1129 | } |
cd28ab6a | 1130 | |
793b883e | 1131 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1132 | le = get_tx_le(sky2); |
1133 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1134 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1135 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1136 | le->ctrl = 0; |
793b883e | 1137 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1138 | } |
1139 | ||
cd28ab6a | 1140 | ctrl = 0; |
d1f13708 SH |
1141 | #ifdef SKY2_VLAN_TAG_USED |
1142 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1143 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1144 | if (!le) { | |
1145 | le = get_tx_le(sky2); | |
1146 | le->tx.addr = 0; | |
1147 | le->opcode = OP_VLAN|HW_OWNER; | |
1148 | le->ctrl = 0; | |
1149 | } else | |
1150 | le->opcode |= OP_VLAN; | |
1151 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1152 | ctrl |= INS_VLAN; | |
1153 | } | |
1154 | #endif | |
1155 | ||
1156 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1157 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1158 | u16 hdr = skb->h.raw - skb->data; |
1159 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1160 | |
1161 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1162 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1163 | ctrl |= UDPTCP; | |
1164 | ||
1165 | le = get_tx_le(sky2); | |
1166 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1167 | le->tx.csum.offset = cpu_to_le16(offset); |
1168 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1169 | le->ctrl = 1; /* one packet */ |
793b883e | 1170 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1171 | } |
1172 | ||
1173 | le = get_tx_le(sky2); | |
1174 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1175 | le->length = cpu_to_le16(len); | |
1176 | le->ctrl = ctrl; | |
793b883e | 1177 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1178 | |
793b883e | 1179 | /* Record the transmit mapping info */ |
cd28ab6a | 1180 | re->skb = skb; |
6cdbbdf3 | 1181 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1182 | |
1183 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1184 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1185 | struct tx_ring_info *fre; |
cd28ab6a SH |
1186 | |
1187 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1188 | frag->size, PCI_DMA_TODEVICE); | |
793b883e SH |
1189 | addr64 = (mapping >> 16) >> 16; |
1190 | if (addr64 != sky2->tx_addr64) { | |
1191 | le = get_tx_le(sky2); | |
1192 | le->tx.addr = cpu_to_le32(addr64); | |
1193 | le->ctrl = 0; | |
1194 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1195 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1196 | } |
1197 | ||
1198 | le = get_tx_le(sky2); | |
1199 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1200 | le->length = cpu_to_le16(frag->size); | |
1201 | le->ctrl = ctrl; | |
793b883e | 1202 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1203 | |
793b883e SH |
1204 | fre = sky2->tx_ring |
1205 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
6cdbbdf3 | 1206 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1207 | } |
6cdbbdf3 | 1208 | |
793b883e | 1209 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1210 | le->ctrl |= EOP; |
1211 | ||
724bca3c | 1212 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod, |
cd28ab6a SH |
1213 | &sky2->tx_last_put, TX_RING_SIZE); |
1214 | ||
0e3ff6aa | 1215 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
cd28ab6a | 1216 | netif_stop_queue(dev); |
793b883e SH |
1217 | |
1218 | out_unlock: | |
1219 | mmiowb(); | |
f2e46561 | 1220 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1221 | |
1222 | dev->trans_start = jiffies; | |
1223 | return NETDEV_TX_OK; | |
1224 | } | |
1225 | ||
cd28ab6a | 1226 | /* |
793b883e SH |
1227 | * Free ring elements from starting at tx_cons until "done" |
1228 | * | |
1229 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1230 | * buffers; these are deferred until completion. |
cd28ab6a | 1231 | */ |
d11c13e7 | 1232 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1233 | { |
d11c13e7 | 1234 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1235 | struct pci_dev *pdev = sky2->hw->pdev; |
1236 | u16 nxt, put; | |
793b883e | 1237 | unsigned i; |
cd28ab6a | 1238 | |
0e3ff6aa | 1239 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1240 | |
d11c13e7 | 1241 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1242 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1243 | dev->name, done); |
cd28ab6a | 1244 | |
af2a58ac SH |
1245 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1246 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1247 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1248 | |
af2a58ac SH |
1249 | nxt = re->idx; |
1250 | BUG_ON(nxt >= TX_RING_SIZE); | |
cd28ab6a | 1251 | |
793b883e | 1252 | /* Check for partial status */ |
af2a58ac SH |
1253 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1254 | break; | |
793b883e SH |
1255 | |
1256 | skb = re->skb; | |
af2a58ac | 1257 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1258 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1259 | |
1260 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1261 | struct tx_ring_info *fre; |
af2a58ac SH |
1262 | fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; |
1263 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), | |
1264 | skb_shinfo(skb)->frags[i].size, | |
734d1868 | 1265 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1266 | } |
1267 | ||
cd28ab6a | 1268 | dev_kfree_skb_any(skb); |
793b883e | 1269 | } |
793b883e | 1270 | |
af2a58ac SH |
1271 | spin_lock(&sky2->tx_lock); |
1272 | sky2->tx_cons = put; | |
793b883e | 1273 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a SH |
1274 | netif_wake_queue(dev); |
1275 | spin_unlock(&sky2->tx_lock); | |
1276 | } | |
1277 | ||
1278 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1279 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1280 | { |
d11c13e7 | 1281 | sky2_tx_complete(sky2, sky2->tx_prod); |
cd28ab6a SH |
1282 | } |
1283 | ||
1284 | /* Network shutdown */ | |
1285 | static int sky2_down(struct net_device *dev) | |
1286 | { | |
1287 | struct sky2_port *sky2 = netdev_priv(dev); | |
1288 | struct sky2_hw *hw = sky2->hw; | |
1289 | unsigned port = sky2->port; | |
1290 | u16 ctrl; | |
cd28ab6a SH |
1291 | |
1292 | if (netif_msg_ifdown(sky2)) | |
1293 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1294 | ||
018d1c66 | 1295 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1296 | netif_stop_queue(dev); |
1297 | ||
018d1c66 SH |
1298 | /* Disable port IRQ */ |
1299 | local_irq_disable(); | |
1300 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1301 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1302 | local_irq_enable(); | |
1303 | ||
91c86df5 | 1304 | flush_scheduled_work(); |
018d1c66 | 1305 | |
793b883e SH |
1306 | sky2_phy_reset(hw, port); |
1307 | ||
cd28ab6a SH |
1308 | /* Stop transmitter */ |
1309 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1310 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1311 | ||
1312 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1313 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1314 | |
1315 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1316 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1317 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1318 | ||
1319 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1320 | ||
1321 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1322 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1323 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1324 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1325 | ||
1326 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1327 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1328 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1329 | ||
1330 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1331 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1332 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1333 | ||
1334 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1335 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1336 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1337 | |
1338 | /* Reset the Tx prefetch units */ | |
1339 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1340 | PREF_UNIT_RST_SET); | |
1341 | ||
1342 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1343 | ||
6b1a3aef | 1344 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1345 | |
1346 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1347 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1348 | ||
d571b694 | 1349 | /* turn off LED's */ |
cd28ab6a SH |
1350 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1351 | ||
018d1c66 SH |
1352 | synchronize_irq(hw->pdev->irq); |
1353 | ||
cd28ab6a SH |
1354 | sky2_tx_clean(sky2); |
1355 | sky2_rx_clean(sky2); | |
1356 | ||
1357 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1358 | sky2->rx_le, sky2->rx_le_map); | |
1359 | kfree(sky2->rx_ring); | |
1360 | ||
1361 | pci_free_consistent(hw->pdev, | |
1362 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1363 | sky2->tx_le, sky2->tx_le_map); | |
1364 | kfree(sky2->tx_ring); | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1370 | { | |
793b883e SH |
1371 | if (!hw->copper) |
1372 | return SPEED_1000; | |
1373 | ||
cd28ab6a SH |
1374 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1375 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1376 | ||
1377 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1378 | case PHY_M_PS_SPEED_1000: | |
1379 | return SPEED_1000; | |
1380 | case PHY_M_PS_SPEED_100: | |
1381 | return SPEED_100; | |
1382 | default: | |
1383 | return SPEED_10; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | static void sky2_link_up(struct sky2_port *sky2) | |
1388 | { | |
1389 | struct sky2_hw *hw = sky2->hw; | |
1390 | unsigned port = sky2->port; | |
1391 | u16 reg; | |
1392 | ||
1393 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1394 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1395 | |
1396 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1397 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) | |
1398 | reg |= GM_GPCR_DUP_FULL; | |
1399 | ||
cd28ab6a SH |
1400 | /* enable Rx/Tx */ |
1401 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1402 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1403 | gma_read16(hw, port, GM_GP_CTRL); | |
1404 | ||
1405 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1406 | ||
1407 | netif_carrier_on(sky2->netdev); | |
1408 | netif_wake_queue(sky2->netdev); | |
1409 | ||
1410 | /* Turn on link LED */ | |
793b883e | 1411 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1412 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1413 | ||
793b883e SH |
1414 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1415 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1416 | ||
1417 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1418 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1419 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1420 | SPEED_10 ? 7 : 0) | | |
1421 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1422 | SPEED_100 ? 7 : 0) | | |
1423 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1424 | SPEED_1000 ? 7 : 0)); | |
1425 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1426 | } | |
1427 | ||
cd28ab6a SH |
1428 | if (netif_msg_link(sky2)) |
1429 | printk(KERN_INFO PFX | |
d571b694 | 1430 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1431 | sky2->netdev->name, sky2->speed, |
1432 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1433 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1434 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1435 | } |
1436 | ||
1437 | static void sky2_link_down(struct sky2_port *sky2) | |
1438 | { | |
1439 | struct sky2_hw *hw = sky2->hw; | |
1440 | unsigned port = sky2->port; | |
1441 | u16 reg; | |
1442 | ||
1443 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1444 | ||
1445 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1446 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1447 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1448 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1449 | ||
1450 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1451 | /* restore Asymmetric Pause bit */ | |
1452 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1453 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1454 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1455 | } |
1456 | ||
1457 | sky2_phy_reset(hw, port); | |
1458 | ||
1459 | netif_carrier_off(sky2->netdev); | |
1460 | netif_stop_queue(sky2->netdev); | |
1461 | ||
1462 | /* Turn on link LED */ | |
1463 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1464 | ||
1465 | if (netif_msg_link(sky2)) | |
1466 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1467 | sky2_phy_init(hw, port); | |
1468 | } | |
1469 | ||
793b883e SH |
1470 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1471 | { | |
1472 | struct sky2_hw *hw = sky2->hw; | |
1473 | unsigned port = sky2->port; | |
1474 | u16 lpa; | |
1475 | ||
1476 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1477 | ||
1478 | if (lpa & PHY_M_AN_RF) { | |
1479 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1480 | return -1; | |
1481 | } | |
1482 | ||
1483 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1484 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1485 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1486 | sky2->netdev->name); | |
1487 | return -1; | |
1488 | } | |
1489 | ||
1490 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1491 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1492 | sky2->netdev->name); | |
1493 | return -1; | |
1494 | } | |
1495 | ||
1496 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1497 | ||
1498 | sky2->speed = sky2_phy_speed(hw, aux); | |
1499 | ||
1500 | /* Pause bits are offset (9..8) */ | |
1501 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1502 | aux >>= 6; | |
1503 | ||
1504 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1505 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1506 | ||
1507 | if ((sky2->tx_pause || sky2->rx_pause) | |
1508 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1509 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1510 | else | |
1511 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
cd28ab6a SH |
1515 | |
1516 | /* | |
91c86df5 | 1517 | * Interrupt from PHY are handled outside of interrupt context |
cd28ab6a SH |
1518 | * because accessing phy registers requires spin wait which might |
1519 | * cause excess interrupt latency. | |
1520 | */ | |
91c86df5 | 1521 | static void sky2_phy_task(void *arg) |
cd28ab6a | 1522 | { |
91c86df5 | 1523 | struct sky2_port *sky2 = arg; |
cd28ab6a | 1524 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1525 | u16 istatus, phystat; |
1526 | ||
91c86df5 | 1527 | down(&sky2->phy_sema); |
793b883e SH |
1528 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); |
1529 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1530 | |
1531 | if (netif_msg_intr(sky2)) | |
1532 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1533 | sky2->netdev->name, istatus, phystat); | |
1534 | ||
1535 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1536 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1537 | sky2_link_up(sky2); | |
1538 | goto out; | |
1539 | } | |
cd28ab6a | 1540 | |
793b883e SH |
1541 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1542 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1543 | |
793b883e SH |
1544 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1545 | sky2->duplex = | |
1546 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1547 | |
793b883e SH |
1548 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1549 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1550 | sky2_link_up(sky2); |
793b883e SH |
1551 | else |
1552 | sky2_link_down(sky2); | |
cd28ab6a | 1553 | } |
793b883e | 1554 | out: |
91c86df5 | 1555 | up(&sky2->phy_sema); |
cd28ab6a SH |
1556 | |
1557 | local_irq_disable(); | |
793b883e | 1558 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1559 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1560 | local_irq_enable(); | |
1561 | } | |
1562 | ||
1563 | static void sky2_tx_timeout(struct net_device *dev) | |
1564 | { | |
1565 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1566 | struct sky2_hw *hw = sky2->hw; |
1567 | unsigned txq = txqaddr[sky2->port]; | |
cd28ab6a SH |
1568 | |
1569 | if (netif_msg_timer(sky2)) | |
1570 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1571 | ||
8cc048e3 SH |
1572 | netif_stop_queue(dev); |
1573 | ||
1574 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); | |
1575 | sky2_read32(hw, Q_ADDR(txq, Q_CSR)); | |
1576 | ||
1577 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
cd28ab6a SH |
1578 | |
1579 | sky2_tx_clean(sky2); | |
8cc048e3 SH |
1580 | |
1581 | sky2_qset(hw, txq); | |
1582 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
1583 | ||
1584 | netif_wake_queue(dev); | |
cd28ab6a SH |
1585 | } |
1586 | ||
734d1868 SH |
1587 | |
1588 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) | |
1589 | /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */ | |
1590 | static inline unsigned sky2_buf_size(int mtu) | |
1591 | { | |
1592 | return roundup(mtu + ETH_HLEN + 4, 8); | |
1593 | } | |
1594 | ||
cd28ab6a SH |
1595 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1596 | { | |
6b1a3aef SH |
1597 | struct sky2_port *sky2 = netdev_priv(dev); |
1598 | struct sky2_hw *hw = sky2->hw; | |
1599 | int err; | |
1600 | u16 ctl, mode; | |
cd28ab6a SH |
1601 | |
1602 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1603 | return -EINVAL; | |
1604 | ||
5a5b1ea0 SH |
1605 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1606 | return -EINVAL; | |
1607 | ||
6b1a3aef SH |
1608 | if (!netif_running(dev)) { |
1609 | dev->mtu = new_mtu; | |
1610 | return 0; | |
1611 | } | |
1612 | ||
6b1a3aef SH |
1613 | sky2_write32(hw, B0_IMSK, 0); |
1614 | ||
018d1c66 SH |
1615 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1616 | netif_stop_queue(dev); | |
1617 | netif_poll_disable(hw->dev[0]); | |
1618 | ||
6b1a3aef SH |
1619 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1620 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1621 | sky2_rx_stop(sky2); | |
1622 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1623 | |
1624 | dev->mtu = new_mtu; | |
734d1868 | 1625 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef SH |
1626 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1627 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1628 | ||
1629 | if (dev->mtu > ETH_DATA_LEN) | |
1630 | mode |= GM_SMOD_JUMBO_ENA; | |
1631 | ||
1632 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1633 | |
6b1a3aef | 1634 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1635 | |
6b1a3aef SH |
1636 | err = sky2_rx_start(sky2); |
1637 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1638 | ||
018d1c66 SH |
1639 | netif_poll_disable(hw->dev[0]); |
1640 | netif_wake_queue(dev); | |
6b1a3aef | 1641 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
018d1c66 | 1642 | |
cd28ab6a SH |
1643 | return err; |
1644 | } | |
1645 | ||
1646 | /* | |
1647 | * Receive one packet. | |
1648 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1649 | * For larger packets, get new buffer. |
cd28ab6a | 1650 | */ |
d11c13e7 | 1651 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1652 | u16 length, u32 status) |
1653 | { | |
cd28ab6a | 1654 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1655 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1656 | |
1657 | if (unlikely(netif_msg_rx_status(sky2))) | |
1658 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1659 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1660 | |
793b883e | 1661 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
cd28ab6a | 1662 | |
42eeea01 | 1663 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1664 | goto error; |
1665 | ||
42eeea01 SH |
1666 | if (!(status & GMR_FS_RX_OK)) |
1667 | goto resubmit; | |
1668 | ||
bdb5c58e | 1669 | if (length < copybreak) { |
79e57d32 SH |
1670 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1671 | if (!skb) | |
793b883e SH |
1672 | goto resubmit; |
1673 | ||
79e57d32 | 1674 | skb_reserve(skb, 2); |
793b883e SH |
1675 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1676 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1677 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 SH |
1678 | skb->ip_summed = re->skb->ip_summed; |
1679 | skb->csum = re->skb->csum; | |
793b883e SH |
1680 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1681 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1682 | } else { |
79e57d32 SH |
1683 | struct sk_buff *nskb; |
1684 | ||
734d1868 | 1685 | nskb = dev_alloc_skb(sky2->rx_bufsize); |
793b883e SH |
1686 | if (!nskb) |
1687 | goto resubmit; | |
cd28ab6a | 1688 | |
793b883e | 1689 | skb = re->skb; |
79e57d32 | 1690 | re->skb = nskb; |
793b883e | 1691 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1692 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1693 | prefetch(skb->data); |
cd28ab6a | 1694 | |
793b883e | 1695 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1696 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1697 | } |
cd28ab6a | 1698 | |
79e57d32 | 1699 | skb_put(skb, length); |
793b883e | 1700 | resubmit: |
d11c13e7 | 1701 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1702 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1703 | |
bea86103 SH |
1704 | /* Tell receiver about new buffers. */ |
1705 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
1706 | &sky2->rx_last_put, RX_LE_SIZE); | |
1707 | ||
cd28ab6a SH |
1708 | return skb; |
1709 | ||
1710 | error: | |
1711 | if (netif_msg_rx_err(sky2)) | |
1712 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", | |
1713 | sky2->netdev->name, status, length); | |
793b883e SH |
1714 | |
1715 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1716 | sky2->net_stats.rx_length_errors++; |
1717 | if (status & GMR_FS_FRAGMENT) | |
1718 | sky2->net_stats.rx_frame_errors++; | |
1719 | if (status & GMR_FS_CRC_ERR) | |
1720 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1721 | if (status & GMR_FS_RX_FF_OV) |
1722 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1723 | |
793b883e | 1724 | goto resubmit; |
cd28ab6a SH |
1725 | } |
1726 | ||
2224795d SH |
1727 | /* |
1728 | * Check for transmit complete | |
793b883e | 1729 | */ |
13b97b74 | 1730 | #define TX_NO_STATUS 0xffff |
2224795d | 1731 | |
13b97b74 SH |
1732 | static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last) |
1733 | { | |
1734 | if (last != TX_NO_STATUS) { | |
1735 | struct net_device *dev = hw->dev[port]; | |
1736 | if (dev && netif_running(dev)) { | |
1737 | struct sky2_port *sky2 = netdev_priv(dev); | |
1738 | sky2_tx_complete(sky2, last); | |
1739 | } | |
2224795d | 1740 | } |
cd28ab6a SH |
1741 | } |
1742 | ||
1743 | /* | |
cd28ab6a SH |
1744 | * Both ports share the same status interrupt, therefore there is only |
1745 | * one poll routine. | |
cd28ab6a | 1746 | */ |
d11c13e7 | 1747 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 1748 | { |
d11c13e7 SH |
1749 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
1750 | unsigned int to_do = min(dev0->quota, *budget); | |
cd28ab6a | 1751 | unsigned int work_done = 0; |
793b883e | 1752 | u16 hwidx; |
13b97b74 | 1753 | u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS }; |
cd28ab6a | 1754 | |
793b883e | 1755 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1756 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
af2a58ac | 1757 | rmb(); |
bea86103 | 1758 | |
13210ce5 SH |
1759 | while (hwidx != hw->st_idx) { |
1760 | struct sky2_status_le *le = hw->st_le + hw->st_idx; | |
1761 | struct net_device *dev; | |
d11c13e7 | 1762 | struct sky2_port *sky2; |
cd28ab6a | 1763 | struct sk_buff *skb; |
cd28ab6a SH |
1764 | u32 status; |
1765 | u16 length; | |
13210ce5 | 1766 | u8 op; |
cd28ab6a | 1767 | |
13210ce5 | 1768 | le = hw->st_le + hw->st_idx; |
bea86103 | 1769 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
13210ce5 | 1770 | prefetch(hw->st_le + hw->st_idx); |
bea86103 | 1771 | |
13210ce5 SH |
1772 | BUG_ON(le->link >= 2); |
1773 | dev = hw->dev[le->link]; | |
1774 | if (dev == NULL || !netif_running(dev)) | |
1775 | continue; | |
1776 | ||
1777 | sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1778 | status = le32_to_cpu(le->status); |
1779 | length = le16_to_cpu(le->length); | |
13210ce5 SH |
1780 | op = le->opcode & ~HW_OWNER; |
1781 | le->opcode = 0; | |
cd28ab6a | 1782 | |
13210ce5 | 1783 | switch (op) { |
cd28ab6a | 1784 | case OP_RXSTAT: |
d11c13e7 | 1785 | skb = sky2_receive(sky2, length, status); |
d1f13708 SH |
1786 | if (!skb) |
1787 | break; | |
13210ce5 SH |
1788 | |
1789 | skb->dev = dev; | |
1790 | skb->protocol = eth_type_trans(skb, dev); | |
1791 | dev->last_rx = jiffies; | |
1792 | ||
d1f13708 SH |
1793 | #ifdef SKY2_VLAN_TAG_USED |
1794 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1795 | vlan_hwaccel_receive_skb(skb, | |
1796 | sky2->vlgrp, | |
1797 | be16_to_cpu(sky2->rx_tag)); | |
1798 | } else | |
1799 | #endif | |
cd28ab6a | 1800 | netif_receive_skb(skb); |
13210ce5 SH |
1801 | |
1802 | if (++work_done >= to_do) | |
1803 | goto exit_loop; | |
cd28ab6a SH |
1804 | break; |
1805 | ||
d1f13708 SH |
1806 | #ifdef SKY2_VLAN_TAG_USED |
1807 | case OP_RXVLAN: | |
1808 | sky2->rx_tag = length; | |
1809 | break; | |
1810 | ||
1811 | case OP_RXCHKSVLAN: | |
1812 | sky2->rx_tag = length; | |
1813 | /* fall through */ | |
1814 | #endif | |
cd28ab6a | 1815 | case OP_RXCHKS: |
d11c13e7 SH |
1816 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1817 | skb->ip_summed = CHECKSUM_HW; | |
1818 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1819 | break; |
1820 | ||
1821 | case OP_TXINDEXLE: | |
13b97b74 SH |
1822 | /* TX index reports status for both ports */ |
1823 | tx_done[0] = status & 0xffff; | |
1824 | tx_done[1] = ((status >> 24) & 0xff) | |
1825 | | (u16)(length & 0xf) << 8; | |
cd28ab6a SH |
1826 | break; |
1827 | ||
cd28ab6a SH |
1828 | default: |
1829 | if (net_ratelimit()) | |
793b883e | 1830 | printk(KERN_WARNING PFX |
13210ce5 | 1831 | "unknown status opcode 0x%x\n", op); |
cd28ab6a SH |
1832 | break; |
1833 | } | |
13210ce5 | 1834 | } |
cd28ab6a | 1835 | |
13210ce5 | 1836 | exit_loop: |
3e4b32e1 | 1837 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
793b883e SH |
1838 | mmiowb(); |
1839 | ||
13b97b74 SH |
1840 | sky2_tx_check(hw, 0, tx_done[0]); |
1841 | sky2_tx_check(hw, 1, tx_done[1]); | |
1842 | ||
3e4b32e1 | 1843 | if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) { |
13b97b74 | 1844 | /* need to restart TX timer */ |
cd28ab6a SH |
1845 | if (is_ec_a1(hw)) { |
1846 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1847 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1848 | } | |
1849 | ||
bea86103 | 1850 | netif_rx_complete(dev0); |
cd28ab6a SH |
1851 | hw->intr_mask |= Y2_IS_STAT_BMU; |
1852 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
13210ce5 SH |
1853 | mmiowb(); |
1854 | return 0; | |
1855 | } else { | |
1856 | *budget -= work_done; | |
1857 | dev0->quota -= work_done; | |
1858 | return 1; | |
cd28ab6a | 1859 | } |
cd28ab6a SH |
1860 | } |
1861 | ||
1862 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1863 | { | |
1864 | struct net_device *dev = hw->dev[port]; | |
1865 | ||
1866 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1867 | dev->name, status); | |
1868 | ||
1869 | if (status & Y2_IS_PAR_RD1) { | |
1870 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1871 | dev->name); | |
1872 | /* Clear IRQ */ | |
1873 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1874 | } | |
1875 | ||
1876 | if (status & Y2_IS_PAR_WR1) { | |
1877 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1878 | dev->name); | |
1879 | ||
1880 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1881 | } | |
1882 | ||
1883 | if (status & Y2_IS_PAR_MAC1) { | |
1884 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
1885 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); | |
1886 | } | |
1887 | ||
1888 | if (status & Y2_IS_PAR_RX1) { | |
1889 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
1890 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); | |
1891 | } | |
1892 | ||
1893 | if (status & Y2_IS_TCP_TXA1) { | |
1894 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name); | |
1895 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); | |
1896 | } | |
1897 | } | |
1898 | ||
1899 | static void sky2_hw_intr(struct sky2_hw *hw) | |
1900 | { | |
1901 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
1902 | ||
793b883e | 1903 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 1904 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
1905 | |
1906 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
1907 | u16 pci_err; |
1908 | ||
1909 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
cd28ab6a SH |
1910 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", |
1911 | pci_name(hw->pdev), pci_err); | |
1912 | ||
1913 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1914 | pci_write_config_word(hw->pdev, PCI_STATUS, |
1915 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
1916 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1917 | } | |
1918 | ||
1919 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 1920 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
1921 | u32 pex_err; |
1922 | ||
1923 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 1924 | |
cd28ab6a SH |
1925 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", |
1926 | pci_name(hw->pdev), pex_err); | |
1927 | ||
1928 | /* clear the interrupt */ | |
1929 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1930 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
1931 | 0xffffffffUL); | |
cd28ab6a SH |
1932 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1933 | ||
1934 | if (pex_err & PEX_FATAL_ERRORS) { | |
1935 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
1936 | hwmsk &= ~Y2_IS_PCI_EXP; | |
1937 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
1938 | } | |
1939 | } | |
1940 | ||
1941 | if (status & Y2_HWE_L1_MASK) | |
1942 | sky2_hw_error(hw, 0, status); | |
1943 | status >>= 8; | |
1944 | if (status & Y2_HWE_L1_MASK) | |
1945 | sky2_hw_error(hw, 1, status); | |
1946 | } | |
1947 | ||
1948 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
1949 | { | |
1950 | struct net_device *dev = hw->dev[port]; | |
1951 | struct sky2_port *sky2 = netdev_priv(dev); | |
1952 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
1953 | ||
1954 | if (netif_msg_intr(sky2)) | |
1955 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
1956 | dev->name, status); | |
1957 | ||
1958 | if (status & GM_IS_RX_FF_OR) { | |
1959 | ++sky2->net_stats.rx_fifo_errors; | |
1960 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
1961 | } | |
1962 | ||
1963 | if (status & GM_IS_TX_FF_UR) { | |
1964 | ++sky2->net_stats.tx_fifo_errors; | |
1965 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
1966 | } | |
cd28ab6a SH |
1967 | } |
1968 | ||
1969 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
1970 | { | |
1971 | struct net_device *dev = hw->dev[port]; | |
1972 | struct sky2_port *sky2 = netdev_priv(dev); | |
1973 | ||
1974 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1975 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
91c86df5 | 1976 | schedule_work(&sky2->phy_task); |
cd28ab6a SH |
1977 | } |
1978 | ||
1979 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1980 | { | |
1981 | struct sky2_hw *hw = dev_id; | |
bea86103 | 1982 | struct net_device *dev0 = hw->dev[0]; |
cd28ab6a SH |
1983 | u32 status; |
1984 | ||
1985 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 1986 | if (status == 0 || status == ~0) |
cd28ab6a SH |
1987 | return IRQ_NONE; |
1988 | ||
1989 | if (status & Y2_IS_HW_ERR) | |
1990 | sky2_hw_intr(hw); | |
1991 | ||
793b883e | 1992 | /* Do NAPI for Rx and Tx status */ |
bea86103 | 1993 | if (status & Y2_IS_STAT_BMU) { |
cd28ab6a SH |
1994 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
1995 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
bea86103 | 1996 | |
0a122576 SH |
1997 | if (likely(__netif_rx_schedule_prep(dev0))) { |
1998 | prefetch(&hw->st_le[hw->st_idx]); | |
bea86103 | 1999 | __netif_rx_schedule(dev0); |
0a122576 | 2000 | } |
cd28ab6a SH |
2001 | } |
2002 | ||
793b883e | 2003 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
2004 | sky2_phy_intr(hw, 0); |
2005 | ||
2006 | if (status & Y2_IS_IRQ_PHY2) | |
2007 | sky2_phy_intr(hw, 1); | |
2008 | ||
2009 | if (status & Y2_IS_IRQ_MAC1) | |
2010 | sky2_mac_intr(hw, 0); | |
2011 | ||
2012 | if (status & Y2_IS_IRQ_MAC2) | |
2013 | sky2_mac_intr(hw, 1); | |
2014 | ||
cd28ab6a | 2015 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
2016 | |
2017 | sky2_read32(hw, B0_IMSK); | |
2018 | ||
cd28ab6a SH |
2019 | return IRQ_HANDLED; |
2020 | } | |
2021 | ||
2022 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2023 | static void sky2_netpoll(struct net_device *dev) | |
2024 | { | |
2025 | struct sky2_port *sky2 = netdev_priv(dev); | |
2026 | ||
793b883e | 2027 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2028 | } |
2029 | #endif | |
2030 | ||
2031 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2032 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2033 | { |
793b883e | 2034 | switch (hw->chip_id) { |
cd28ab6a | 2035 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2036 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2037 | return 125; /* 125 Mhz */ |
cd28ab6a | 2038 | case CHIP_ID_YUKON_FE: |
fb17358f | 2039 | return 100; /* 100 Mhz */ |
793b883e | 2040 | default: /* YUKON_XL */ |
fb17358f | 2041 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2042 | } |
2043 | } | |
2044 | ||
fb17358f | 2045 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2046 | { |
fb17358f | 2047 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2048 | } |
2049 | ||
fb17358f | 2050 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2051 | { |
fb17358f | 2052 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2053 | } |
2054 | ||
fb17358f | 2055 | |
cd28ab6a SH |
2056 | static int sky2_reset(struct sky2_hw *hw) |
2057 | { | |
5afa0a9c | 2058 | u32 ctst; |
cd28ab6a SH |
2059 | u16 status; |
2060 | u8 t8, pmd_type; | |
2061 | int i; | |
2062 | ||
2063 | ctst = sky2_read32(hw, B0_CTST); | |
2064 | ||
2065 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2066 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); | |
2067 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2068 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2069 | pci_name(hw->pdev), hw->chip_id); | |
2070 | return -EOPNOTSUPP; | |
2071 | } | |
2072 | ||
793b883e SH |
2073 | /* ring for status responses */ |
2074 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
2075 | &hw->st_dma); | |
2076 | if (!hw->st_le) | |
2077 | return -ENOMEM; | |
2078 | ||
cd28ab6a SH |
2079 | /* disable ASF */ |
2080 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2081 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2082 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2083 | } | |
2084 | ||
2085 | /* do a SW reset */ | |
2086 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2087 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2088 | ||
2089 | /* clear PCI errors, if any */ | |
793b883e | 2090 | pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
cd28ab6a | 2091 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e SH |
2092 | pci_write_config_word(hw->pdev, PCI_STATUS, |
2093 | status | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2094 | |
2095 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2096 | ||
2097 | /* clear any PEX errors */ | |
2098 | if (is_pciex(hw)) { | |
793b883e SH |
2099 | u16 lstat; |
2100 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
2101 | 0xffffffffUL); | |
2102 | pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat); | |
cd28ab6a SH |
2103 | } |
2104 | ||
2105 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2106 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2107 | ||
2108 | hw->ports = 1; | |
2109 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2110 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2111 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2112 | ++hw->ports; | |
2113 | } | |
2114 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
2115 | ||
5afa0a9c | 2116 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2117 | |
2118 | for (i = 0; i < hw->ports; i++) { | |
2119 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2120 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2121 | } | |
2122 | ||
2123 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2124 | ||
793b883e SH |
2125 | /* Clear I2C IRQ noise */ |
2126 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2127 | |
2128 | /* turn off hardware timer (unused) */ | |
2129 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2130 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2131 | |
cd28ab6a SH |
2132 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2133 | ||
69634ee7 SH |
2134 | /* Turn off descriptor polling */ |
2135 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2136 | |
2137 | /* Turn off receive timestamp */ | |
2138 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2139 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2140 | |
2141 | /* enable the Tx Arbiters */ | |
2142 | for (i = 0; i < hw->ports; i++) | |
2143 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2144 | ||
2145 | /* Initialize ram interface */ | |
2146 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2147 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2148 | |
2149 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2150 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2151 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2152 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2153 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2154 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2155 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2156 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2157 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2158 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2159 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2160 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2161 | } | |
2162 | ||
cd28ab6a SH |
2163 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2164 | ||
cd28ab6a SH |
2165 | for (i = 0; i < hw->ports; i++) |
2166 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2167 | |
cd28ab6a SH |
2168 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2169 | hw->st_idx = 0; | |
2170 | ||
2171 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2172 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2173 | ||
2174 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2175 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2176 | |
2177 | /* Set the list last index */ | |
793b883e | 2178 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2179 | |
793b883e | 2180 | /* These status setup values are copied from SysKonnect's driver */ |
cd28ab6a SH |
2181 | if (is_ec_a1(hw)) { |
2182 | /* WA for dev. #4.3 */ | |
793b883e | 2183 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
2184 | |
2185 | /* set Status-FIFO watermark */ | |
2186 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
2187 | ||
2188 | /* set Status-FIFO ISR watermark */ | |
793b883e | 2189 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
69634ee7 | 2190 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000)); |
cd28ab6a | 2191 | } else { |
69634ee7 SH |
2192 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2193 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a SH |
2194 | |
2195 | /* set Status-FIFO ISR watermark */ | |
2196 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
69634ee7 SH |
2197 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); |
2198 | else | |
2199 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2200 | |
69634ee7 SH |
2201 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
2202 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
2203 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); | |
cd28ab6a SH |
2204 | } |
2205 | ||
793b883e | 2206 | /* enable status unit */ |
cd28ab6a SH |
2207 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2208 | ||
2209 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2210 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2211 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2212 | ||
2213 | return 0; | |
2214 | } | |
2215 | ||
2216 | static inline u32 sky2_supported_modes(const struct sky2_hw *hw) | |
2217 | { | |
2218 | u32 modes; | |
2219 | if (hw->copper) { | |
793b883e SH |
2220 | modes = SUPPORTED_10baseT_Half |
2221 | | SUPPORTED_10baseT_Full | |
2222 | | SUPPORTED_100baseT_Half | |
2223 | | SUPPORTED_100baseT_Full | |
2224 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2225 | |
2226 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2227 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2228 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2229 | } else |
2230 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2231 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2232 | return modes; |
2233 | } | |
2234 | ||
793b883e | 2235 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2236 | { |
2237 | struct sky2_port *sky2 = netdev_priv(dev); | |
2238 | struct sky2_hw *hw = sky2->hw; | |
2239 | ||
2240 | ecmd->transceiver = XCVR_INTERNAL; | |
2241 | ecmd->supported = sky2_supported_modes(hw); | |
2242 | ecmd->phy_address = PHY_ADDR_MARV; | |
2243 | if (hw->copper) { | |
2244 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2245 | | SUPPORTED_10baseT_Full |
2246 | | SUPPORTED_100baseT_Half | |
2247 | | SUPPORTED_100baseT_Full | |
2248 | | SUPPORTED_1000baseT_Half | |
2249 | | SUPPORTED_1000baseT_Full | |
2250 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2251 | ecmd->port = PORT_TP; |
2252 | } else | |
2253 | ecmd->port = PORT_FIBRE; | |
2254 | ||
2255 | ecmd->advertising = sky2->advertising; | |
2256 | ecmd->autoneg = sky2->autoneg; | |
2257 | ecmd->speed = sky2->speed; | |
2258 | ecmd->duplex = sky2->duplex; | |
2259 | return 0; | |
2260 | } | |
2261 | ||
2262 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2263 | { | |
2264 | struct sky2_port *sky2 = netdev_priv(dev); | |
2265 | const struct sky2_hw *hw = sky2->hw; | |
2266 | u32 supported = sky2_supported_modes(hw); | |
2267 | ||
2268 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2269 | ecmd->advertising = supported; | |
2270 | sky2->duplex = -1; | |
2271 | sky2->speed = -1; | |
2272 | } else { | |
2273 | u32 setting; | |
2274 | ||
793b883e | 2275 | switch (ecmd->speed) { |
cd28ab6a SH |
2276 | case SPEED_1000: |
2277 | if (ecmd->duplex == DUPLEX_FULL) | |
2278 | setting = SUPPORTED_1000baseT_Full; | |
2279 | else if (ecmd->duplex == DUPLEX_HALF) | |
2280 | setting = SUPPORTED_1000baseT_Half; | |
2281 | else | |
2282 | return -EINVAL; | |
2283 | break; | |
2284 | case SPEED_100: | |
2285 | if (ecmd->duplex == DUPLEX_FULL) | |
2286 | setting = SUPPORTED_100baseT_Full; | |
2287 | else if (ecmd->duplex == DUPLEX_HALF) | |
2288 | setting = SUPPORTED_100baseT_Half; | |
2289 | else | |
2290 | return -EINVAL; | |
2291 | break; | |
2292 | ||
2293 | case SPEED_10: | |
2294 | if (ecmd->duplex == DUPLEX_FULL) | |
2295 | setting = SUPPORTED_10baseT_Full; | |
2296 | else if (ecmd->duplex == DUPLEX_HALF) | |
2297 | setting = SUPPORTED_10baseT_Half; | |
2298 | else | |
2299 | return -EINVAL; | |
2300 | break; | |
2301 | default: | |
2302 | return -EINVAL; | |
2303 | } | |
2304 | ||
2305 | if ((setting & supported) == 0) | |
2306 | return -EINVAL; | |
2307 | ||
2308 | sky2->speed = ecmd->speed; | |
2309 | sky2->duplex = ecmd->duplex; | |
2310 | } | |
2311 | ||
2312 | sky2->autoneg = ecmd->autoneg; | |
2313 | sky2->advertising = ecmd->advertising; | |
2314 | ||
2315 | if (netif_running(dev)) { | |
2316 | sky2_down(dev); | |
2317 | sky2_up(dev); | |
2318 | } | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | static void sky2_get_drvinfo(struct net_device *dev, | |
2324 | struct ethtool_drvinfo *info) | |
2325 | { | |
2326 | struct sky2_port *sky2 = netdev_priv(dev); | |
2327 | ||
2328 | strcpy(info->driver, DRV_NAME); | |
2329 | strcpy(info->version, DRV_VERSION); | |
2330 | strcpy(info->fw_version, "N/A"); | |
2331 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2332 | } | |
2333 | ||
2334 | static const struct sky2_stat { | |
793b883e SH |
2335 | char name[ETH_GSTRING_LEN]; |
2336 | u16 offset; | |
cd28ab6a SH |
2337 | } sky2_stats[] = { |
2338 | { "tx_bytes", GM_TXO_OK_HI }, | |
2339 | { "rx_bytes", GM_RXO_OK_HI }, | |
2340 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2341 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2342 | { "tx_multicast", GM_TXF_MC_OK }, | |
2343 | { "rx_multicast", GM_RXF_MC_OK }, | |
2344 | { "tx_unicast", GM_TXF_UC_OK }, | |
2345 | { "rx_unicast", GM_RXF_UC_OK }, | |
2346 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2347 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2348 | { "collisions", GM_TXF_SNG_COL }, | |
2349 | { "late_collision",GM_TXF_LAT_COL }, | |
2350 | { "aborted", GM_TXF_ABO_COL }, | |
2351 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2352 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2353 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2354 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2355 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2356 | { "rx_runt", GM_RXE_FRAG }, | |
2357 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2358 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2359 | }; | |
2360 | ||
cd28ab6a SH |
2361 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2362 | { | |
2363 | struct sky2_port *sky2 = netdev_priv(dev); | |
2364 | ||
2365 | return sky2->rx_csum; | |
2366 | } | |
2367 | ||
2368 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2369 | { | |
2370 | struct sky2_port *sky2 = netdev_priv(dev); | |
2371 | ||
2372 | sky2->rx_csum = data; | |
793b883e | 2373 | |
cd28ab6a SH |
2374 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2375 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2376 | ||
2377 | return 0; | |
2378 | } | |
2379 | ||
2380 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2381 | { | |
2382 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2383 | return sky2->msg_enable; | |
2384 | } | |
2385 | ||
9a7ae0a9 SH |
2386 | static int sky2_nway_reset(struct net_device *dev) |
2387 | { | |
2388 | struct sky2_port *sky2 = netdev_priv(dev); | |
2389 | struct sky2_hw *hw = sky2->hw; | |
2390 | ||
2391 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2392 | return -EINVAL; | |
2393 | ||
2394 | netif_stop_queue(dev); | |
2395 | ||
91c86df5 | 2396 | down(&sky2->phy_sema); |
9a7ae0a9 SH |
2397 | sky2_phy_reset(hw, sky2->port); |
2398 | sky2_phy_init(hw, sky2->port); | |
91c86df5 | 2399 | up(&sky2->phy_sema); |
9a7ae0a9 SH |
2400 | |
2401 | return 0; | |
2402 | } | |
2403 | ||
793b883e | 2404 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2405 | { |
2406 | struct sky2_hw *hw = sky2->hw; | |
2407 | unsigned port = sky2->port; | |
2408 | int i; | |
2409 | ||
2410 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2411 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2412 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2413 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2414 | |
793b883e | 2415 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2416 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2417 | } | |
2418 | ||
cd28ab6a SH |
2419 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2420 | { | |
2421 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2422 | sky2->msg_enable = value; | |
2423 | } | |
2424 | ||
2425 | static int sky2_get_stats_count(struct net_device *dev) | |
2426 | { | |
2427 | return ARRAY_SIZE(sky2_stats); | |
2428 | } | |
2429 | ||
2430 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2431 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2432 | { |
2433 | struct sky2_port *sky2 = netdev_priv(dev); | |
2434 | ||
793b883e | 2435 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2436 | } |
2437 | ||
793b883e | 2438 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2439 | { |
2440 | int i; | |
2441 | ||
2442 | switch (stringset) { | |
2443 | case ETH_SS_STATS: | |
2444 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2445 | memcpy(data + i * ETH_GSTRING_LEN, | |
2446 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2447 | break; | |
2448 | } | |
2449 | } | |
2450 | ||
2451 | /* Use hardware MIB variables for critical path statistics and | |
2452 | * transmit feedback not reported at interrupt. | |
2453 | * Other errors are accounted for in interrupt handler. | |
2454 | */ | |
2455 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2456 | { | |
2457 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2458 | u64 data[13]; |
cd28ab6a | 2459 | |
793b883e | 2460 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2461 | |
2462 | sky2->net_stats.tx_bytes = data[0]; | |
2463 | sky2->net_stats.rx_bytes = data[1]; | |
2464 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2465 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2466 | sky2->net_stats.multicast = data[5] + data[7]; | |
2467 | sky2->net_stats.collisions = data[10]; | |
2468 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2469 | ||
2470 | return &sky2->net_stats; | |
2471 | } | |
2472 | ||
2473 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2474 | { | |
2475 | struct sky2_port *sky2 = netdev_priv(dev); | |
2476 | struct sockaddr *addr = p; | |
2477 | int err = 0; | |
2478 | ||
2479 | if (!is_valid_ether_addr(addr->sa_data)) | |
2480 | return -EADDRNOTAVAIL; | |
2481 | ||
2482 | sky2_down(dev); | |
2483 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
793b883e | 2484 | memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8, |
cd28ab6a | 2485 | dev->dev_addr, ETH_ALEN); |
793b883e | 2486 | memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8, |
cd28ab6a SH |
2487 | dev->dev_addr, ETH_ALEN); |
2488 | if (dev->flags & IFF_UP) | |
2489 | err = sky2_up(dev); | |
2490 | return err; | |
2491 | } | |
2492 | ||
2493 | static void sky2_set_multicast(struct net_device *dev) | |
2494 | { | |
2495 | struct sky2_port *sky2 = netdev_priv(dev); | |
2496 | struct sky2_hw *hw = sky2->hw; | |
2497 | unsigned port = sky2->port; | |
2498 | struct dev_mc_list *list = dev->mc_list; | |
2499 | u16 reg; | |
2500 | u8 filter[8]; | |
2501 | ||
2502 | memset(filter, 0, sizeof(filter)); | |
2503 | ||
2504 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2505 | reg |= GM_RXCR_UCF_ENA; | |
2506 | ||
d571b694 | 2507 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2508 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2509 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2510 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2511 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2512 | reg &= ~GM_RXCR_MCF_ENA; |
2513 | else { | |
2514 | int i; | |
2515 | reg |= GM_RXCR_MCF_ENA; | |
2516 | ||
2517 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2518 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2519 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2520 | } |
2521 | } | |
2522 | ||
cd28ab6a | 2523 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2524 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2525 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2526 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2527 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2528 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2529 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2530 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2531 | |
2532 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2533 | } | |
2534 | ||
2535 | /* Can have one global because blinking is controlled by | |
2536 | * ethtool and that is always under RTNL mutex | |
2537 | */ | |
91c86df5 | 2538 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2539 | { |
793b883e SH |
2540 | u16 pg; |
2541 | ||
793b883e SH |
2542 | switch (hw->chip_id) { |
2543 | case CHIP_ID_YUKON_XL: | |
2544 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2545 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2546 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2547 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2548 | PHY_M_LEDC_INIT_CTRL(7) | | |
2549 | PHY_M_LEDC_STA1_CTRL(7) | | |
2550 | PHY_M_LEDC_STA0_CTRL(7)) | |
2551 | : 0); | |
2552 | ||
2553 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2554 | break; | |
2555 | ||
2556 | default: | |
2557 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2558 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2559 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2560 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2561 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2562 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2563 | PHY_M_LED_MO_RX(MO_LED_ON) |
2564 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2565 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2566 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2567 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2568 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2569 | ||
793b883e | 2570 | } |
cd28ab6a SH |
2571 | } |
2572 | ||
2573 | /* blink LED's for finding board */ | |
2574 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2575 | { | |
2576 | struct sky2_port *sky2 = netdev_priv(dev); | |
2577 | struct sky2_hw *hw = sky2->hw; | |
2578 | unsigned port = sky2->port; | |
793b883e | 2579 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2580 | long ms; |
91c86df5 | 2581 | int interrupted; |
cd28ab6a SH |
2582 | int onoff = 1; |
2583 | ||
793b883e | 2584 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2585 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2586 | else | |
2587 | ms = data * 1000; | |
2588 | ||
2589 | /* save initial values */ | |
91c86df5 | 2590 | down(&sky2->phy_sema); |
793b883e SH |
2591 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2592 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2593 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2594 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2595 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2596 | } else { | |
2597 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2598 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2599 | } | |
cd28ab6a | 2600 | |
91c86df5 SH |
2601 | interrupted = 0; |
2602 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2603 | sky2_led(hw, port, onoff); |
2604 | onoff = !onoff; | |
2605 | ||
91c86df5 SH |
2606 | up(&sky2->phy_sema); |
2607 | interrupted = msleep_interruptible(250); | |
2608 | down(&sky2->phy_sema); | |
2609 | ||
cd28ab6a SH |
2610 | ms -= 250; |
2611 | } | |
2612 | ||
2613 | /* resume regularly scheduled programming */ | |
793b883e SH |
2614 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2615 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2616 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2617 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2618 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2619 | } else { | |
2620 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2621 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2622 | } | |
91c86df5 | 2623 | up(&sky2->phy_sema); |
cd28ab6a SH |
2624 | |
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | static void sky2_get_pauseparam(struct net_device *dev, | |
2629 | struct ethtool_pauseparam *ecmd) | |
2630 | { | |
2631 | struct sky2_port *sky2 = netdev_priv(dev); | |
2632 | ||
2633 | ecmd->tx_pause = sky2->tx_pause; | |
2634 | ecmd->rx_pause = sky2->rx_pause; | |
2635 | ecmd->autoneg = sky2->autoneg; | |
2636 | } | |
2637 | ||
2638 | static int sky2_set_pauseparam(struct net_device *dev, | |
2639 | struct ethtool_pauseparam *ecmd) | |
2640 | { | |
2641 | struct sky2_port *sky2 = netdev_priv(dev); | |
2642 | int err = 0; | |
2643 | ||
2644 | sky2->autoneg = ecmd->autoneg; | |
2645 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2646 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2647 | ||
2648 | if (netif_running(dev)) { | |
2649 | sky2_down(dev); | |
2650 | err = sky2_up(dev); | |
2651 | } | |
2652 | ||
2653 | return err; | |
2654 | } | |
2655 | ||
2656 | #ifdef CONFIG_PM | |
2657 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2658 | { | |
2659 | struct sky2_port *sky2 = netdev_priv(dev); | |
2660 | ||
2661 | wol->supported = WAKE_MAGIC; | |
2662 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2663 | } | |
2664 | ||
2665 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2666 | { | |
2667 | struct sky2_port *sky2 = netdev_priv(dev); | |
2668 | struct sky2_hw *hw = sky2->hw; | |
2669 | ||
2670 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2671 | return -EOPNOTSUPP; | |
2672 | ||
2673 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2674 | ||
2675 | if (sky2->wol) { | |
2676 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2677 | ||
2678 | sky2_write16(hw, WOL_CTRL_STAT, | |
2679 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2680 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2681 | } else | |
2682 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2683 | ||
2684 | return 0; | |
2685 | } | |
2686 | #endif | |
2687 | ||
fb17358f SH |
2688 | static int sky2_get_coalesce(struct net_device *dev, |
2689 | struct ethtool_coalesce *ecmd) | |
2690 | { | |
2691 | struct sky2_port *sky2 = netdev_priv(dev); | |
2692 | struct sky2_hw *hw = sky2->hw; | |
2693 | ||
2694 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2695 | ecmd->tx_coalesce_usecs = 0; | |
2696 | else { | |
2697 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2698 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2699 | } | |
2700 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2701 | ||
2702 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2703 | ecmd->rx_coalesce_usecs = 0; | |
2704 | else { | |
2705 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2706 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2707 | } | |
2708 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2709 | ||
2710 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2711 | ecmd->rx_coalesce_usecs_irq = 0; | |
2712 | else { | |
2713 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2714 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2715 | } | |
2716 | ||
2717 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2718 | ||
2719 | return 0; | |
2720 | } | |
2721 | ||
2722 | /* Note: this affect both ports */ | |
2723 | static int sky2_set_coalesce(struct net_device *dev, | |
2724 | struct ethtool_coalesce *ecmd) | |
2725 | { | |
2726 | struct sky2_port *sky2 = netdev_priv(dev); | |
2727 | struct sky2_hw *hw = sky2->hw; | |
2728 | const u32 tmin = sky2_clk2us(hw, 1); | |
2729 | const u32 tmax = 5000; | |
2730 | ||
2731 | if (ecmd->tx_coalesce_usecs != 0 && | |
2732 | (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax)) | |
2733 | return -EINVAL; | |
2734 | ||
2735 | if (ecmd->rx_coalesce_usecs != 0 && | |
2736 | (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax)) | |
2737 | return -EINVAL; | |
2738 | ||
2739 | if (ecmd->rx_coalesce_usecs_irq != 0 && | |
2740 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) | |
2741 | return -EINVAL; | |
2742 | ||
2743 | if (ecmd->tx_max_coalesced_frames > 0xffff) | |
2744 | return -EINVAL; | |
2745 | if (ecmd->rx_max_coalesced_frames > 0xff) | |
2746 | return -EINVAL; | |
2747 | if (ecmd->rx_max_coalesced_frames_irq > 0xff) | |
2748 | return -EINVAL; | |
2749 | ||
2750 | if (ecmd->tx_coalesce_usecs == 0) | |
2751 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2752 | else { | |
2753 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2754 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2755 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2756 | } | |
2757 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2758 | ||
2759 | if (ecmd->rx_coalesce_usecs == 0) | |
2760 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2761 | else { | |
2762 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2763 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2764 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2765 | } | |
2766 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2767 | ||
2768 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2769 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2770 | else { | |
2771 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2772 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); | |
2773 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2774 | } | |
2775 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2776 | return 0; | |
2777 | } | |
2778 | ||
793b883e SH |
2779 | static void sky2_get_ringparam(struct net_device *dev, |
2780 | struct ethtool_ringparam *ering) | |
2781 | { | |
2782 | struct sky2_port *sky2 = netdev_priv(dev); | |
2783 | ||
2784 | ering->rx_max_pending = RX_MAX_PENDING; | |
2785 | ering->rx_mini_max_pending = 0; | |
2786 | ering->rx_jumbo_max_pending = 0; | |
2787 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2788 | ||
2789 | ering->rx_pending = sky2->rx_pending; | |
2790 | ering->rx_mini_pending = 0; | |
2791 | ering->rx_jumbo_pending = 0; | |
2792 | ering->tx_pending = sky2->tx_pending; | |
2793 | } | |
2794 | ||
2795 | static int sky2_set_ringparam(struct net_device *dev, | |
2796 | struct ethtool_ringparam *ering) | |
2797 | { | |
2798 | struct sky2_port *sky2 = netdev_priv(dev); | |
2799 | int err = 0; | |
2800 | ||
2801 | if (ering->rx_pending > RX_MAX_PENDING || | |
2802 | ering->rx_pending < 8 || | |
2803 | ering->tx_pending < MAX_SKB_TX_LE || | |
2804 | ering->tx_pending > TX_RING_SIZE - 1) | |
2805 | return -EINVAL; | |
2806 | ||
2807 | if (netif_running(dev)) | |
2808 | sky2_down(dev); | |
2809 | ||
2810 | sky2->rx_pending = ering->rx_pending; | |
2811 | sky2->tx_pending = ering->tx_pending; | |
2812 | ||
2813 | if (netif_running(dev)) | |
2814 | err = sky2_up(dev); | |
2815 | ||
2816 | return err; | |
2817 | } | |
2818 | ||
793b883e SH |
2819 | static int sky2_get_regs_len(struct net_device *dev) |
2820 | { | |
6e4cbb34 | 2821 | return 0x4000; |
793b883e SH |
2822 | } |
2823 | ||
2824 | /* | |
2825 | * Returns copy of control register region | |
6e4cbb34 | 2826 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2827 | */ |
2828 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2829 | void *p) | |
2830 | { | |
2831 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2832 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2833 | |
6e4cbb34 | 2834 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2835 | regs->version = 1; |
6e4cbb34 | 2836 | memset(p, 0, regs->len); |
793b883e | 2837 | |
6e4cbb34 SH |
2838 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2839 | ||
2840 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2841 | io + B3_RI_WTO_R1, | |
2842 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2843 | } |
cd28ab6a SH |
2844 | |
2845 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2846 | .get_settings = sky2_get_settings, |
2847 | .set_settings = sky2_set_settings, | |
2848 | .get_drvinfo = sky2_get_drvinfo, | |
2849 | .get_msglevel = sky2_get_msglevel, | |
2850 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 2851 | .nway_reset = sky2_nway_reset, |
793b883e SH |
2852 | .get_regs_len = sky2_get_regs_len, |
2853 | .get_regs = sky2_get_regs, | |
2854 | .get_link = ethtool_op_get_link, | |
2855 | .get_sg = ethtool_op_get_sg, | |
2856 | .set_sg = ethtool_op_set_sg, | |
2857 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2858 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2859 | .get_tso = ethtool_op_get_tso, | |
2860 | .set_tso = ethtool_op_set_tso, | |
2861 | .get_rx_csum = sky2_get_rx_csum, | |
2862 | .set_rx_csum = sky2_set_rx_csum, | |
2863 | .get_strings = sky2_get_strings, | |
fb17358f SH |
2864 | .get_coalesce = sky2_get_coalesce, |
2865 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
2866 | .get_ringparam = sky2_get_ringparam, |
2867 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2868 | .get_pauseparam = sky2_get_pauseparam, |
2869 | .set_pauseparam = sky2_set_pauseparam, | |
2870 | #ifdef CONFIG_PM | |
793b883e SH |
2871 | .get_wol = sky2_get_wol, |
2872 | .set_wol = sky2_set_wol, | |
cd28ab6a | 2873 | #endif |
793b883e | 2874 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2875 | .get_stats_count = sky2_get_stats_count, |
2876 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 2877 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
2878 | }; |
2879 | ||
2880 | /* Initialize network device */ | |
2881 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2882 | unsigned port, int highmem) | |
2883 | { | |
2884 | struct sky2_port *sky2; | |
2885 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
2886 | ||
2887 | if (!dev) { | |
2888 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
2889 | return NULL; | |
2890 | } | |
2891 | ||
2892 | SET_MODULE_OWNER(dev); | |
2893 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 2894 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
2895 | dev->open = sky2_up; |
2896 | dev->stop = sky2_down; | |
ef743d33 | 2897 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
2898 | dev->hard_start_xmit = sky2_xmit_frame; |
2899 | dev->get_stats = sky2_get_stats; | |
2900 | dev->set_multicast_list = sky2_set_multicast; | |
2901 | dev->set_mac_address = sky2_set_mac_address; | |
2902 | dev->change_mtu = sky2_change_mtu; | |
2903 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
2904 | dev->tx_timeout = sky2_tx_timeout; | |
2905 | dev->watchdog_timeo = TX_WATCHDOG; | |
2906 | if (port == 0) | |
2907 | dev->poll = sky2_poll; | |
2908 | dev->weight = NAPI_WEIGHT; | |
2909 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2910 | dev->poll_controller = sky2_netpoll; | |
2911 | #endif | |
cd28ab6a SH |
2912 | |
2913 | sky2 = netdev_priv(dev); | |
2914 | sky2->netdev = dev; | |
2915 | sky2->hw = hw; | |
2916 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
2917 | ||
2918 | spin_lock_init(&sky2->tx_lock); | |
2919 | /* Auto speed and flow control */ | |
2920 | sky2->autoneg = AUTONEG_ENABLE; | |
2921 | sky2->tx_pause = 0; | |
2922 | sky2->rx_pause = 1; | |
2923 | sky2->duplex = -1; | |
2924 | sky2->speed = -1; | |
2925 | sky2->advertising = sky2_supported_modes(hw); | |
2926 | sky2->rx_csum = 1; | |
91c86df5 SH |
2927 | INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2); |
2928 | init_MUTEX(&sky2->phy_sema); | |
793b883e SH |
2929 | sky2->tx_pending = TX_DEF_PENDING; |
2930 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
734d1868 | 2931 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
2932 | |
2933 | hw->dev[port] = dev; | |
2934 | ||
2935 | sky2->port = port; | |
2936 | ||
5a5b1ea0 SH |
2937 | dev->features |= NETIF_F_LLTX; |
2938 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
2939 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
2940 | if (highmem) |
2941 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 2942 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 2943 | |
d1f13708 SH |
2944 | #ifdef SKY2_VLAN_TAG_USED |
2945 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
2946 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
2947 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
2948 | #endif | |
2949 | ||
cd28ab6a | 2950 | /* read the mac address */ |
793b883e | 2951 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 2952 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
2953 | |
2954 | /* device is off until link detection */ | |
2955 | netif_carrier_off(dev); | |
2956 | netif_stop_queue(dev); | |
2957 | ||
2958 | return dev; | |
2959 | } | |
2960 | ||
2961 | static inline void sky2_show_addr(struct net_device *dev) | |
2962 | { | |
2963 | const struct sky2_port *sky2 = netdev_priv(dev); | |
2964 | ||
2965 | if (netif_msg_probe(sky2)) | |
2966 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
2967 | dev->name, | |
2968 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
2969 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
2970 | } | |
2971 | ||
2972 | static int __devinit sky2_probe(struct pci_dev *pdev, | |
2973 | const struct pci_device_id *ent) | |
2974 | { | |
793b883e | 2975 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 2976 | struct sky2_hw *hw; |
5afa0a9c | 2977 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 2978 | |
793b883e SH |
2979 | err = pci_enable_device(pdev); |
2980 | if (err) { | |
cd28ab6a SH |
2981 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
2982 | pci_name(pdev)); | |
2983 | goto err_out; | |
2984 | } | |
2985 | ||
793b883e SH |
2986 | err = pci_request_regions(pdev, DRV_NAME); |
2987 | if (err) { | |
cd28ab6a SH |
2988 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
2989 | pci_name(pdev)); | |
793b883e | 2990 | goto err_out; |
cd28ab6a SH |
2991 | } |
2992 | ||
2993 | pci_set_master(pdev); | |
2994 | ||
5afa0a9c SH |
2995 | /* Find power-management capability. */ |
2996 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
2997 | if (pm_cap == 0) { | |
2998 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
2999 | "aborting.\n"); | |
3000 | err = -EIO; | |
3001 | goto err_out_free_regions; | |
3002 | } | |
3003 | ||
cd28ab6a SH |
3004 | if (sizeof(dma_addr_t) > sizeof(u32)) { |
3005 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
3006 | if (!err) | |
3007 | using_dac = 1; | |
3008 | } | |
3009 | ||
3010 | if (!using_dac) { | |
3011 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
3012 | if (err) { | |
3013 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3014 | pci_name(pdev)); | |
3015 | goto err_out_free_regions; | |
3016 | } | |
3017 | } | |
cd28ab6a | 3018 | #ifdef __BIG_ENDIAN |
d571b694 | 3019 | /* byte swap descriptors in hardware */ |
cd28ab6a SH |
3020 | { |
3021 | u32 reg; | |
3022 | ||
3023 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3024 | reg |= PCI_REV_DESC; | |
3025 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3026 | } | |
3027 | #endif | |
3028 | ||
3029 | err = -ENOMEM; | |
3030 | hw = kmalloc(sizeof(*hw), GFP_KERNEL); | |
3031 | if (!hw) { | |
3032 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3033 | pci_name(pdev)); | |
3034 | goto err_out_free_regions; | |
3035 | } | |
3036 | ||
3037 | memset(hw, 0, sizeof(*hw)); | |
3038 | hw->pdev = pdev; | |
cd28ab6a SH |
3039 | |
3040 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3041 | if (!hw->regs) { | |
3042 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3043 | pci_name(pdev)); | |
3044 | goto err_out_free_hw; | |
3045 | } | |
5afa0a9c | 3046 | hw->pm_cap = pm_cap; |
cd28ab6a | 3047 | |
cd28ab6a SH |
3048 | err = sky2_reset(hw); |
3049 | if (err) | |
793b883e | 3050 | goto err_out_iounmap; |
cd28ab6a | 3051 | |
5f4f9dc1 SH |
3052 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3053 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3054 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3055 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3056 | |
793b883e SH |
3057 | dev = sky2_init_netdev(hw, 0, using_dac); |
3058 | if (!dev) | |
cd28ab6a SH |
3059 | goto err_out_free_pci; |
3060 | ||
793b883e SH |
3061 | err = register_netdev(dev); |
3062 | if (err) { | |
cd28ab6a SH |
3063 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3064 | pci_name(pdev)); | |
3065 | goto err_out_free_netdev; | |
3066 | } | |
3067 | ||
3068 | sky2_show_addr(dev); | |
3069 | ||
3070 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3071 | if (register_netdev(dev1) == 0) | |
3072 | sky2_show_addr(dev1); | |
3073 | else { | |
3074 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3075 | printk(KERN_WARNING PFX |
3076 | "register of second port failed\n"); | |
cd28ab6a SH |
3077 | hw->dev[1] = NULL; |
3078 | free_netdev(dev1); | |
3079 | } | |
3080 | } | |
3081 | ||
793b883e SH |
3082 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); |
3083 | if (err) { | |
3084 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3085 | pci_name(pdev), pdev->irq); | |
3086 | goto err_out_unregister; | |
3087 | } | |
3088 | ||
3089 | hw->intr_mask = Y2_IS_BASE; | |
3090 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
3091 | ||
3092 | pci_set_drvdata(pdev, hw); | |
3093 | ||
cd28ab6a SH |
3094 | return 0; |
3095 | ||
793b883e SH |
3096 | err_out_unregister: |
3097 | if (dev1) { | |
3098 | unregister_netdev(dev1); | |
3099 | free_netdev(dev1); | |
3100 | } | |
3101 | unregister_netdev(dev); | |
cd28ab6a SH |
3102 | err_out_free_netdev: |
3103 | free_netdev(dev); | |
cd28ab6a | 3104 | err_out_free_pci: |
793b883e | 3105 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3106 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3107 | err_out_iounmap: | |
3108 | iounmap(hw->regs); | |
3109 | err_out_free_hw: | |
3110 | kfree(hw); | |
3111 | err_out_free_regions: | |
3112 | pci_release_regions(pdev); | |
cd28ab6a | 3113 | pci_disable_device(pdev); |
cd28ab6a SH |
3114 | err_out: |
3115 | return err; | |
3116 | } | |
3117 | ||
3118 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3119 | { | |
793b883e | 3120 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3121 | struct net_device *dev0, *dev1; |
3122 | ||
793b883e | 3123 | if (!hw) |
cd28ab6a SH |
3124 | return; |
3125 | ||
cd28ab6a | 3126 | dev0 = hw->dev[0]; |
793b883e SH |
3127 | dev1 = hw->dev[1]; |
3128 | if (dev1) | |
3129 | unregister_netdev(dev1); | |
cd28ab6a SH |
3130 | unregister_netdev(dev0); |
3131 | ||
793b883e | 3132 | sky2_write32(hw, B0_IMSK, 0); |
5afa0a9c | 3133 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3134 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3135 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3136 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3137 | |
3138 | free_irq(pdev->irq, hw); | |
793b883e | 3139 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3140 | pci_release_regions(pdev); |
3141 | pci_disable_device(pdev); | |
793b883e | 3142 | |
cd28ab6a SH |
3143 | if (dev1) |
3144 | free_netdev(dev1); | |
3145 | free_netdev(dev0); | |
3146 | iounmap(hw->regs); | |
3147 | kfree(hw); | |
5afa0a9c | 3148 | |
cd28ab6a SH |
3149 | pci_set_drvdata(pdev, NULL); |
3150 | } | |
3151 | ||
3152 | #ifdef CONFIG_PM | |
3153 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3154 | { | |
793b883e | 3155 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3156 | int i; |
cd28ab6a SH |
3157 | |
3158 | for (i = 0; i < 2; i++) { | |
3159 | struct net_device *dev = hw->dev[i]; | |
3160 | ||
3161 | if (dev) { | |
5afa0a9c SH |
3162 | if (!netif_running(dev)) |
3163 | continue; | |
3164 | ||
3165 | sky2_down(dev); | |
cd28ab6a | 3166 | netif_device_detach(dev); |
cd28ab6a SH |
3167 | } |
3168 | } | |
3169 | ||
5afa0a9c | 3170 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3171 | } |
3172 | ||
3173 | static int sky2_resume(struct pci_dev *pdev) | |
3174 | { | |
793b883e | 3175 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3176 | int i; |
3177 | ||
cd28ab6a SH |
3178 | pci_restore_state(pdev); |
3179 | pci_enable_wake(pdev, PCI_D0, 0); | |
5afa0a9c | 3180 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
3181 | |
3182 | sky2_reset(hw); | |
3183 | ||
3184 | for (i = 0; i < 2; i++) { | |
3185 | struct net_device *dev = hw->dev[i]; | |
3186 | if (dev) { | |
5afa0a9c SH |
3187 | if (netif_running(dev)) { |
3188 | netif_device_attach(dev); | |
cd28ab6a | 3189 | sky2_up(dev); |
5afa0a9c | 3190 | } |
cd28ab6a SH |
3191 | } |
3192 | } | |
3193 | return 0; | |
3194 | } | |
3195 | #endif | |
3196 | ||
3197 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3198 | .name = DRV_NAME, |
3199 | .id_table = sky2_id_table, | |
3200 | .probe = sky2_probe, | |
3201 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3202 | #ifdef CONFIG_PM |
793b883e SH |
3203 | .suspend = sky2_suspend, |
3204 | .resume = sky2_resume, | |
cd28ab6a SH |
3205 | #endif |
3206 | }; | |
3207 | ||
3208 | static int __init sky2_init_module(void) | |
3209 | { | |
50241c4c | 3210 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3211 | } |
3212 | ||
3213 | static void __exit sky2_cleanup_module(void) | |
3214 | { | |
3215 | pci_unregister_driver(&sky2_driver); | |
3216 | } | |
3217 | ||
3218 | module_init(sky2_init_module); | |
3219 | module_exit(sky2_cleanup_module); | |
3220 | ||
3221 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3222 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3223 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3224 | MODULE_VERSION(DRV_VERSION); |