projects / GitHub / LineageOS / android_kernel_samsung_universal7580.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] skge: expand ethtool debug register dump
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
46a60f2d 45#define DRV_VERSION "1.0"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 52#define RX_COPY_THRESHOLD 128
53#define RX_BUF_SIZE 1536
baef58b1
SH		 54#define PHY_RETRIES 1000
55#define ETH_JUMBO_MTU 9000
56#define TX_WATCHDOG (5 * HZ)
57#define NAPI_WEIGHT 64
6abebb53 58#define BLINK_MS 250
baef58b1
SH		 59
60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62MODULE_LICENSE("GPL");
63MODULE_VERSION(DRV_VERSION);
64
65static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69static int debug = -1; /* defaults above */
70module_param(debug, int, 0);
71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 84 { 0 }
85};
86MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port);
96static void yukon_reset(struct skge_hw *hw, int port);
97static void genesis_mac_init(struct skge_hw *hw, int port);
98static void genesis_reset(struct skge_hw *hw, int port);
45bada65 99static void genesis_link_up(struct skge_port *skge);
baef58b1 100
7e676d91 101/* Avoid conditionals by using array */
baef58b1
SH		 102static const int txqaddr[] = { Q_XA1, Q_XA2 };
103static const int rxqaddr[] = { Q_R1, Q_R2 };
104static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 106static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 107
baef58b1
SH		 108static int skge_get_regs_len(struct net_device *dev)
109{
c3f8be96 110 return 0x4000;
baef58b1
SH		 111}
112
113/*
c3f8be96
SH		 114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
baef58b1
SH		 117 */
118static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120{
121 const struct skge_port *skge = netdev_priv(dev);
baef58b1 122 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 123
124 regs->version = 1;
c3f8be96
SH		 125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
127
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 130}
131
132/* Wake on Lan only supported on Yukon chps with rev 1 or above */
133static int wol_supported(const struct skge_hw *hw)
134{
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 137}
138
139static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140{
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145}
146
147static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148{
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
95566065 152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170}
171
31b619c5
SH		 172/* Determine supported/adverised modes based on hardware.
173 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
174 */
175static u32 skge_supported_modes(const struct skge_hw *hw)
176{
177 u32 supported;
178
5e1705dd 179 if (hw->copper) {
31b619c5
SH		 180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201}
baef58b1
SH		 202
203static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205{
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 210 ecmd->supported = skge_supported_modes(hw);
baef58b1 211
5e1705dd 212 if (hw->copper) {
baef58b1
SH		 213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
31b619c5 215 } else
baef58b1 216 ecmd->port = PORT_FIBRE;
baef58b1
SH		 217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223}
224
baef58b1
SH		 225static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226{
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
31b619c5 229 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
baef58b1 235 } else {
31b619c5
SH		 236 u32 setting;
237
2c668514 238 switch (ecmd->speed) {
baef58b1 239 case SPEED_1000:
31b619c5
SH		 240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
baef58b1
SH		 246 break;
247 case SPEED_100:
31b619c5
SH		 248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
baef58b1 256 case SPEED_10:
31b619c5
SH		 257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
baef58b1
SH		 262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
31b619c5
SH		 267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
baef58b1
SH		 273 }
274
275 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 276 skge->advertising = ecmd->advertising;
277
278 if (netif_running(dev)) {
279 skge_down(dev);
280 skge_up(dev);
281 }
282 return (0);
283}
284
285static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287{
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294}
295
296static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300} skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325};
326
327static int skge_get_stats_count(struct net_device *dev)
328{
329 return ARRAY_SIZE(skge_stats);
330}
331
332static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334{
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341}
342
343/* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347static struct net_device_stats *skge_get_stats(struct net_device *dev)
348{
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366}
367
368static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369{
370 int i;
371
95566065 372 switch (stringset) {
baef58b1
SH		 373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379}
380
381static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383{
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395}
396
397static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399{
400 struct skge_port *skge = netdev_priv(dev);
401
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
404 return -EINVAL;
405
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
408
409 if (netif_running(dev)) {
410 skge_down(dev);
411 skge_up(dev);
412 }
413
414 return 0;
415}
416
417static u32 skge_get_msglevel(struct net_device *netdev)
418{
419 struct skge_port *skge = netdev_priv(netdev);
420 return skge->msg_enable;
421}
422
423static void skge_set_msglevel(struct net_device *netdev, u32 value)
424{
425 struct skge_port *skge = netdev_priv(netdev);
426 skge->msg_enable = value;
427}
428
429static int skge_nway_reset(struct net_device *dev)
430{
431 struct skge_port *skge = netdev_priv(dev);
432 struct skge_hw *hw = skge->hw;
433 int port = skge->port;
434
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
436 return -EINVAL;
437
438 spin_lock_bh(&hw->phy_lock);
439 if (hw->chip_id == CHIP_ID_GENESIS) {
440 genesis_reset(hw, port);
441 genesis_mac_init(hw, port);
442 } else {
443 yukon_reset(hw, port);
444 yukon_init(hw, port);
445 }
446 spin_unlock_bh(&hw->phy_lock);
447 return 0;
448}
449
450static int skge_set_sg(struct net_device *dev, u32 data)
451{
452 struct skge_port *skge = netdev_priv(dev);
453 struct skge_hw *hw = skge->hw;
454
455 if (hw->chip_id == CHIP_ID_GENESIS && data)
456 return -EOPNOTSUPP;
457 return ethtool_op_set_sg(dev, data);
458}
459
460static int skge_set_tx_csum(struct net_device *dev, u32 data)
461{
462 struct skge_port *skge = netdev_priv(dev);
463 struct skge_hw *hw = skge->hw;
464
465 if (hw->chip_id == CHIP_ID_GENESIS && data)
466 return -EOPNOTSUPP;
467
468 return ethtool_op_set_tx_csum(dev, data);
469}
470
471static u32 skge_get_rx_csum(struct net_device *dev)
472{
473 struct skge_port *skge = netdev_priv(dev);
474
475 return skge->rx_csum;
476}
477
478/* Only Yukon supports checksum offload. */
479static int skge_set_rx_csum(struct net_device *dev, u32 data)
480{
481 struct skge_port *skge = netdev_priv(dev);
482
483 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
484 return -EOPNOTSUPP;
485
486 skge->rx_csum = data;
487 return 0;
488}
489
baef58b1
SH		 490static void skge_get_pauseparam(struct net_device *dev,
491 struct ethtool_pauseparam *ecmd)
492{
493 struct skge_port *skge = netdev_priv(dev);
494
495 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
496 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
497 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
498 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
499
500 ecmd->autoneg = skge->autoneg;
501}
502
503static int skge_set_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505{
506 struct skge_port *skge = netdev_priv(dev);
507
508 skge->autoneg = ecmd->autoneg;
509 if (ecmd->rx_pause && ecmd->tx_pause)
510 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 511 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 512 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 513 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 514 skge->flow_control = FLOW_MODE_LOC_SEND;
515 else
516 skge->flow_control = FLOW_MODE_NONE;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 skge_up(dev);
521 }
522 return 0;
523}
524
525/* Chip internal frequency for clock calculations */
526static inline u32 hwkhz(const struct skge_hw *hw)
527{
528 if (hw->chip_id == CHIP_ID_GENESIS)
529 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 530 else
531 return 78215; /* or: 78.125 MHz */
532}
533
534/* Chip hz to microseconds */
535static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
536{
537 return (ticks * 1000) / hwkhz(hw);
538}
539
540/* Microseconds to chip hz */
541static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
542{
543 return hwkhz(hw) * usec / 1000;
544}
545
546static int skge_get_coalesce(struct net_device *dev,
547 struct ethtool_coalesce *ecmd)
548{
549 struct skge_port *skge = netdev_priv(dev);
550 struct skge_hw *hw = skge->hw;
551 int port = skge->port;
552
553 ecmd->rx_coalesce_usecs = 0;
554 ecmd->tx_coalesce_usecs = 0;
555
556 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
557 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
558 u32 msk = skge_read32(hw, B2_IRQM_MSK);
559
560 if (msk & rxirqmask[port])
561 ecmd->rx_coalesce_usecs = delay;
562 if (msk & txirqmask[port])
563 ecmd->tx_coalesce_usecs = delay;
564 }
565
566 return 0;
567}
568
569/* Note: interrupt timer is per board, but can turn on/off per port */
570static int skge_set_coalesce(struct net_device *dev,
571 struct ethtool_coalesce *ecmd)
572{
573 struct skge_port *skge = netdev_priv(dev);
574 struct skge_hw *hw = skge->hw;
575 int port = skge->port;
576 u32 msk = skge_read32(hw, B2_IRQM_MSK);
577 u32 delay = 25;
578
579 if (ecmd->rx_coalesce_usecs == 0)
580 msk &= ~rxirqmask[port];
581 else if (ecmd->rx_coalesce_usecs < 25 ||
582 ecmd->rx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= rxirqmask[port];
586 delay = ecmd->rx_coalesce_usecs;
587 }
588
589 if (ecmd->tx_coalesce_usecs == 0)
590 msk &= ~txirqmask[port];
591 else if (ecmd->tx_coalesce_usecs < 25 ||
592 ecmd->tx_coalesce_usecs > 33333)
593 return -EINVAL;
594 else {
595 msk |= txirqmask[port];
596 delay = min(delay, ecmd->rx_coalesce_usecs);
597 }
598
599 skge_write32(hw, B2_IRQM_MSK, msk);
600 if (msk == 0)
601 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
602 else {
603 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
604 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
605 }
606 return 0;
607}
608
6abebb53
SH		 609enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
610static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 611{
6abebb53
SH		 612 struct skge_hw *hw = skge->hw;
613 int port = skge->port;
614
615 spin_lock_bh(&hw->phy_lock);
baef58b1 616 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 617 switch (mode) {
618 case LED_MODE_OFF:
619 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
620 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
621 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
622 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
623 break;
baef58b1 624
6abebb53
SH		 625 case LED_MODE_ON:
626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 628
6abebb53
SH		 629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 631
6abebb53 632 break;
baef58b1 633
6abebb53
SH		 634 case LED_MODE_TST:
635 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
636 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
637 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 638
6abebb53
SH		 639 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
640 break;
641 }
baef58b1 642 } else {
6abebb53
SH		 643 switch (mode) {
644 case LED_MODE_OFF:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
646 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
647 PHY_M_LED_MO_DUP(MO_LED_OFF) |
648 PHY_M_LED_MO_10(MO_LED_OFF) |
649 PHY_M_LED_MO_100(MO_LED_OFF) |
650 PHY_M_LED_MO_1000(MO_LED_OFF) |
651 PHY_M_LED_MO_RX(MO_LED_OFF));
652 break;
653 case LED_MODE_ON:
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
655 PHY_M_LED_PULS_DUR(PULS_170MS) |
656 PHY_M_LED_BLINK_RT(BLINK_84MS) |
657 PHY_M_LEDC_TX_CTRL |
658 PHY_M_LEDC_DP_CTRL);
46a60f2d 659
6abebb53
SH		 660 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
661 PHY_M_LED_MO_RX(MO_LED_OFF) |
662 (skge->speed == SPEED_100 ?
663 PHY_M_LED_MO_100(MO_LED_ON) : 0));
664 break;
665 case LED_MODE_TST:
666 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
667 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
668 PHY_M_LED_MO_DUP(MO_LED_ON) |
669 PHY_M_LED_MO_10(MO_LED_ON) |
670 PHY_M_LED_MO_100(MO_LED_ON) |
671 PHY_M_LED_MO_1000(MO_LED_ON) |
672 PHY_M_LED_MO_RX(MO_LED_ON));
673 }
baef58b1 674 }
4ff6ac05 675 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 676}
677
678/* blink LED's for finding board */
679static int skge_phys_id(struct net_device *dev, u32 data)
680{
681 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 682 unsigned long ms;
683 enum led_mode mode = LED_MODE_TST;
baef58b1 684
95566065 685 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 686 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
687 else
688 ms = data * 1000;
baef58b1 689
6abebb53
SH		 690 while (ms > 0) {
691 skge_led(skge, mode);
692 mode ^= LED_MODE_TST;
baef58b1 693
6abebb53
SH		 694 if (msleep_interruptible(BLINK_MS))
695 break;
696 ms -= BLINK_MS;
697 }
baef58b1 698
6abebb53
SH		 699 /* back to regular LED state */
700 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 701
702 return 0;
703}
704
705static struct ethtool_ops skge_ethtool_ops = {
706 .get_settings = skge_get_settings,
707 .set_settings = skge_set_settings,
708 .get_drvinfo = skge_get_drvinfo,
709 .get_regs_len = skge_get_regs_len,
710 .get_regs = skge_get_regs,
711 .get_wol = skge_get_wol,
712 .set_wol = skge_set_wol,
713 .get_msglevel = skge_get_msglevel,
714 .set_msglevel = skge_set_msglevel,
715 .nway_reset = skge_nway_reset,
716 .get_link = ethtool_op_get_link,
717 .get_ringparam = skge_get_ring_param,
718 .set_ringparam = skge_set_ring_param,
719 .get_pauseparam = skge_get_pauseparam,
720 .set_pauseparam = skge_set_pauseparam,
721 .get_coalesce = skge_get_coalesce,
722 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 723 .get_sg = ethtool_op_get_sg,
724 .set_sg = skge_set_sg,
725 .get_tx_csum = ethtool_op_get_tx_csum,
726 .set_tx_csum = skge_set_tx_csum,
727 .get_rx_csum = skge_get_rx_csum,
728 .set_rx_csum = skge_set_rx_csum,
729 .get_strings = skge_get_strings,
730 .phys_id = skge_phys_id,
731 .get_stats_count = skge_get_stats_count,
732 .get_ethtool_stats = skge_get_ethtool_stats,
733};
734
735/*
736 * Allocate ring elements and chain them together
737 * One-to-one association of board descriptors with ring elements
738 */
739static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
740{
741 struct skge_tx_desc *d;
742 struct skge_element *e;
743 int i;
744
745 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
746 if (!ring->start)
747 return -ENOMEM;
748
749 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
750 e->desc = d;
19a33d4e 751 e->skb = NULL;
baef58b1
SH		 752 if (i == ring->count - 1) {
753 e->next = ring->start;
754 d->next_offset = base;
755 } else {
756 e->next = e + 1;
757 d->next_offset = base + (i+1) * sizeof(*d);
758 }
759 }
760 ring->to_use = ring->to_clean = ring->start;
761
762 return 0;
763}
764
19a33d4e 765static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
baef58b1 766{
19a33d4e 767 struct sk_buff *skb = dev_alloc_skb(size);
baef58b1 768
19a33d4e
SH		 769 if (likely(skb)) {
770 skb->dev = dev;
771 skb_reserve(skb, NET_IP_ALIGN);
baef58b1 772 }
19a33d4e
SH		 773 return skb;
774}
baef58b1 775
19a33d4e
SH		 776/* Allocate and setup a new buffer for receiving */
777static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
778 struct sk_buff *skb, unsigned int bufsize)
779{
780 struct skge_rx_desc *rd = e->desc;
781 u64 map;
baef58b1
SH		 782
783 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
784 PCI_DMA_FROMDEVICE);
785
786 rd->dma_lo = map;
787 rd->dma_hi = map >> 32;
788 e->skb = skb;
789 rd->csum1_start = ETH_HLEN;
790 rd->csum2_start = ETH_HLEN;
791 rd->csum1 = 0;
792 rd->csum2 = 0;
793
794 wmb();
795
796 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
797 pci_unmap_addr_set(e, mapaddr, map);
798 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 799}
800
19a33d4e
SH		 801/* Resume receiving using existing skb,
802 * Note: DMA address is not changed by chip.
803 * MTU not changed while receiver active.
804 */
805static void skge_rx_reuse(struct skge_element *e, unsigned int size)
806{
807 struct skge_rx_desc *rd = e->desc;
808
809 rd->csum2 = 0;
810 rd->csum2_start = ETH_HLEN;
811
812 wmb();
813
814 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
815}
816
817
818/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 819static void skge_rx_clean(struct skge_port *skge)
820{
821 struct skge_hw *hw = skge->hw;
822 struct skge_ring *ring = &skge->rx_ring;
823 struct skge_element *e;
824
19a33d4e
SH		 825 e = ring->start;
826 do {
baef58b1
SH		 827 struct skge_rx_desc *rd = e->desc;
828 rd->control = 0;
19a33d4e
SH		 829 if (e->skb) {
830 pci_unmap_single(hw->pdev,
831 pci_unmap_addr(e, mapaddr),
832 pci_unmap_len(e, maplen),
833 PCI_DMA_FROMDEVICE);
834 dev_kfree_skb(e->skb);
835 e->skb = NULL;
836 }
837 } while ((e = e->next) != ring->start);
baef58b1
SH		 838}
839
19a33d4e 840
baef58b1 841/* Allocate buffers for receive ring
19a33d4e 842 * For receive: to_clean is next received frame.
baef58b1
SH		 843 */
844static int skge_rx_fill(struct skge_port *skge)
845{
846 struct skge_ring *ring = &skge->rx_ring;
847 struct skge_element *e;
19a33d4e 848 unsigned int bufsize = skge->rx_buf_size;
baef58b1 849
19a33d4e
SH		 850 e = ring->start;
851 do {
852 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
baef58b1 853
19a33d4e
SH		 854 if (!skb)
855 return -ENOMEM;
856
857 skge_rx_setup(skge, e, skb, bufsize);
858 } while ( (e = e->next) != ring->start);
baef58b1 859
19a33d4e
SH		 860 ring->to_clean = ring->start;
861 return 0;
baef58b1
SH		 862}
863
864static void skge_link_up(struct skge_port *skge)
865{
46a60f2d 866 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 867 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
868
baef58b1
SH		 869 netif_carrier_on(skge->netdev);
870 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
871 netif_wake_queue(skge->netdev);
872
873 if (netif_msg_link(skge))
874 printk(KERN_INFO PFX
875 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
876 skge->netdev->name, skge->speed,
877 skge->duplex == DUPLEX_FULL ? "full" : "half",
878 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
879 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
880 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
881 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
882 "unknown");
883}
884
885static void skge_link_down(struct skge_port *skge)
886{
54cfb5aa 887 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 888 netif_carrier_off(skge->netdev);
889 netif_stop_queue(skge->netdev);
890
891 if (netif_msg_link(skge))
892 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
893}
894
6b0c1480 895static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 896{
897 int i;
898 u16 v;
899
6b0c1480
SH		 900 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
901 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 902
89bf5f23
SH		 903 /* Need to wait for external PHY */
904 for (i = 0; i < PHY_RETRIES; i++) {
905 udelay(1);
906 if (xm_read16(hw, port, XM_MMU_CMD)
907 & XM_MMU_PHY_RDY)
908 goto ready;
baef58b1
SH		 909 }
910
89bf5f23
SH		 911 printk(KERN_WARNING PFX "%s: phy read timed out\n",
912 hw->dev[port]->name);
913 return 0;
914 ready:
915 v = xm_read16(hw, port, XM_PHY_DATA);
916
baef58b1
SH		 917 return v;
918}
919
6b0c1480 920static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 921{
922 int i;
923
6b0c1480 924 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 925 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 926 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 927 goto ready;
89bf5f23 928 udelay(1);
baef58b1
SH		 929 }
930 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
931 hw->dev[port]->name);
932
933
934 ready:
6b0c1480 935 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 936 for (i = 0; i < PHY_RETRIES; i++) {
937 udelay(1);
6b0c1480 938 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 939 return;
940 }
941 printk(KERN_WARNING PFX "%s: phy write timed out\n",
942 hw->dev[port]->name);
943}
944
945static void genesis_init(struct skge_hw *hw)
946{
947 /* set blink source counter */
948 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
949 skge_write8(hw, B2_BSC_CTRL, BSC_START);
950
951 /* configure mac arbiter */
952 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
953
954 /* configure mac arbiter timeout values */
955 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
956 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
957 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
958 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
959
960 skge_write8(hw, B3_MA_RCINI_RX1, 0);
961 skge_write8(hw, B3_MA_RCINI_RX2, 0);
962 skge_write8(hw, B3_MA_RCINI_TX1, 0);
963 skge_write8(hw, B3_MA_RCINI_TX2, 0);
964
965 /* configure packet arbiter timeout */
966 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
967 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
968 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
969 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
970 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
971}
972
973static void genesis_reset(struct skge_hw *hw, int port)
974{
45bada65 975 const u8 zero[8] = { 0 };
baef58b1 976
46a60f2d
SH		 977 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
978
baef58b1 979 /* reset the statistics module */
6b0c1480
SH		 980 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
981 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
982 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
983 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
984 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 985
89bf5f23
SH		 986 /* disable Broadcom PHY IRQ */
987 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 988
45bada65 989 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 990}
991
992
45bada65
SH		 993/* Convert mode to MII values */
994static const u16 phy_pause_map[] = {
995 [FLOW_MODE_NONE] = 0,
996 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
997 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
998 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
999};
1000
1001
1002/* Check status of Broadcom phy link */
1003static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1004{
45bada65
SH		 1005 struct net_device *dev = hw->dev[port];
1006 struct skge_port *skge = netdev_priv(dev);
1007 u16 status;
1008
1009 /* read twice because of latch */
1010 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1011 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1012
45bada65
SH		 1013 if ((status & PHY_ST_LSYNC) == 0) {
1014 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1015 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1016 xm_write16(hw, port, XM_MMU_CMD, cmd);
1017 /* dummy read to ensure writing */
1018 (void) xm_read16(hw, port, XM_MMU_CMD);
1019
1020 if (netif_carrier_ok(dev))
1021 skge_link_down(skge);
1022 } else {
1023 if (skge->autoneg == AUTONEG_ENABLE &&
1024 (status & PHY_ST_AN_OVER)) {
1025 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1026 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1027
1028 if (lpa & PHY_B_AN_RF) {
1029 printk(KERN_NOTICE PFX "%s: remote fault\n",
1030 dev->name);
1031 return;
1032 }
1033
1034 /* Check Duplex mismatch */
2c668514 1035 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1036 case PHY_B_RES_1000FD:
1037 skge->duplex = DUPLEX_FULL;
1038 break;
1039 case PHY_B_RES_1000HD:
1040 skge->duplex = DUPLEX_HALF;
1041 break;
1042 default:
1043 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1044 dev->name);
1045 return;
1046 }
1047
1048
1049 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1050 switch (aux & PHY_B_AS_PAUSE_MSK) {
1051 case PHY_B_AS_PAUSE_MSK:
1052 skge->flow_control = FLOW_MODE_SYMMETRIC;
1053 break;
1054 case PHY_B_AS_PRR:
1055 skge->flow_control = FLOW_MODE_REM_SEND;
1056 break;
1057 case PHY_B_AS_PRT:
1058 skge->flow_control = FLOW_MODE_LOC_SEND;
1059 break;
1060 default:
1061 skge->flow_control = FLOW_MODE_NONE;
1062 }
1063
1064 skge->speed = SPEED_1000;
1065 }
1066
1067 if (!netif_carrier_ok(dev))
1068 genesis_link_up(skge);
1069 }
1070}
1071
1072/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1073 * Phy on for 100 or 10Mbit operation
1074 */
1075static void bcom_phy_init(struct skge_port *skge, int jumbo)
1076{
1077 struct skge_hw *hw = skge->hw;
1078 int port = skge->port;
baef58b1 1079 int i;
45bada65 1080 u16 id1, r, ext, ctl;
baef58b1
SH		 1081
1082 /* magic workaround patterns for Broadcom */
1083 static const struct {
1084 u16 reg;
1085 u16 val;
1086 } A1hack[] = {
1087 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1088 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1089 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1090 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1091 }, C0hack[] = {
1092 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1093 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1094 };
1095
45bada65
SH		 1096 /* read Id from external PHY (all have the same address) */
1097 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1098
1099 /* Optimize MDIO transfer by suppressing preamble. */
1100 r = xm_read16(hw, port, XM_MMU_CMD);
1101 r |= XM_MMU_NO_PRE;
1102 xm_write16(hw, port, XM_MMU_CMD,r);
1103
2c668514 1104 switch (id1) {
45bada65
SH		 1105 case PHY_BCOM_ID1_C0:
1106 /*
1107 * Workaround BCOM Errata for the C0 type.
1108 * Write magic patterns to reserved registers.
1109 */
1110 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1111 xm_phy_write(hw, port,
1112 C0hack[i].reg, C0hack[i].val);
1113
1114 break;
1115 case PHY_BCOM_ID1_A1:
1116 /*
1117 * Workaround BCOM Errata for the A1 type.
1118 * Write magic patterns to reserved registers.
1119 */
1120 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1121 xm_phy_write(hw, port,
1122 A1hack[i].reg, A1hack[i].val);
1123 break;
1124 }
1125
1126 /*
1127 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1128 * Disable Power Management after reset.
1129 */
1130 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1131 r |= PHY_B_AC_DIS_PM;
1132 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1133
1134 /* Dummy read */
1135 xm_read16(hw, port, XM_ISRC);
1136
1137 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1138 ctl = PHY_CT_SP1000; /* always 1000mbit */
1139
1140 if (skge->autoneg == AUTONEG_ENABLE) {
1141 /*
1142 * Workaround BCOM Errata #1 for the C5 type.
1143 * 1000Base-T Link Acquisition Failure in Slave Mode
1144 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1145 */
1146 u16 adv = PHY_B_1000C_RD;
1147 if (skge->advertising & ADVERTISED_1000baseT_Half)
1148 adv |= PHY_B_1000C_AHD;
1149 if (skge->advertising & ADVERTISED_1000baseT_Full)
1150 adv |= PHY_B_1000C_AFD;
1151 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1152
1153 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1154 } else {
1155 if (skge->duplex == DUPLEX_FULL)
1156 ctl |= PHY_CT_DUP_MD;
1157 /* Force to slave */
1158 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1159 }
1160
1161 /* Set autonegotiation pause parameters */
1162 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1163 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1164
1165 /* Handle Jumbo frames */
1166 if (jumbo) {
1167 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1168 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1169
1170 ext |= PHY_B_PEC_HIGH_LA;
1171
1172 }
1173
1174 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1175 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1176
1177 /* Use link status change interrrupt */
1178 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1179
1180 bcom_check_link(hw, port);
1181}
1182
1183static void genesis_mac_init(struct skge_hw *hw, int port)
1184{
1185 struct net_device *dev = hw->dev[port];
1186 struct skge_port *skge = netdev_priv(dev);
1187 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1188 int i;
1189 u32 r;
1190 const u8 zero[6] = { 0 };
1191
1192 /* Clear MIB counters */
1193 xm_write16(hw, port, XM_STAT_CMD,
1194 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1195 /* Clear two times according to Errata #3 */
1196 xm_write16(hw, port, XM_STAT_CMD,
1197 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1 1198
baef58b1 1199 /* Unreset the XMAC. */
6b0c1480 1200 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1201
1202 /*
1203 * Perform additional initialization for external PHYs,
1204 * namely for the 1000baseTX cards that use the XMAC's
1205 * GMII mode.
1206 */
45bada65 1207 /* Take external Phy out of reset */
89bf5f23
SH		 1208 r = skge_read32(hw, B2_GP_IO);
1209 if (port == 0)
1210 r |= GP_DIR_0|GP_IO_0;
1211 else
1212 r |= GP_DIR_2|GP_IO_2;
1213
1214 skge_write32(hw, B2_GP_IO, r);
1215 skge_read32(hw, B2_GP_IO);
1216
45bada65 1217 /* Enable GMII interfac */
89bf5f23
SH		 1218 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1219
45bada65 1220 bcom_phy_init(skge, jumbo);
89bf5f23 1221
45bada65
SH		 1222 /* Set Station Address */
1223 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1224
45bada65
SH		 1225 /* We don't use match addresses so clear */
1226 for (i = 1; i < 16; i++)
1227 xm_outaddr(hw, port, XM_EXM(i), zero);
1228
1229 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1230 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1231
1232 /* We don't need the FCS appended to the packet. */
1233 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1234 if (jumbo)
1235 r |= XM_RX_BIG_PK_OK;
89bf5f23 1236
45bada65 1237 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1238 /*
45bada65
SH		 1239 * If in manual half duplex mode the other side might be in
1240 * full duplex mode, so ignore if a carrier extension is not seen
1241 * on frames received
89bf5f23 1242 */
45bada65 1243 r |= XM_RX_DIS_CEXT;
baef58b1 1244 }
45bada65 1245 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1246
baef58b1
SH		 1247
1248 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1249 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1250
1251 /*
1252 * Bump up the transmit threshold. This helps hold off transmit
1253 * underruns when we're blasting traffic from both ports at once.
1254 */
1255 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1256
1257 /*
1258 * Enable the reception of all error frames. This is is
1259 * a necessary evil due to the design of the XMAC. The
1260 * XMAC's receive FIFO is only 8K in size, however jumbo
1261 * frames can be up to 9000 bytes in length. When bad
1262 * frame filtering is enabled, the XMAC's RX FIFO operates
1263 * in 'store and forward' mode. For this to work, the
1264 * entire frame has to fit into the FIFO, but that means
1265 * that jumbo frames larger than 8192 bytes will be
1266 * truncated. Disabling all bad frame filtering causes
1267 * the RX FIFO to operate in streaming mode, in which
1268 * case the XMAC will start transfering frames out of the
1269 * RX FIFO as soon as the FIFO threshold is reached.
1270 */
45bada65 1271 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1272
baef58b1
SH		 1273
1274 /*
45bada65
SH		 1275 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1276 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1277 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1278 */
45bada65
SH		 1279 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1280
1281 /*
1282 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1283 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1284 * and 'Octets Tx OK Hi Cnt Ov'.
1285 */
1286 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1287
1288 /* Configure MAC arbiter */
1289 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1290
1291 /* configure timeout values */
1292 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1293 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1294 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1295 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1296
1297 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1298 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1299 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1300 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1301
1302 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1303 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1304 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1305 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1306
1307 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1308 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1309 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1310 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1311
45bada65 1312 if (jumbo) {
baef58b1 1313 /* Enable frame flushing if jumbo frames used */
6b0c1480 1314 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1315 } else {
1316 /* enable timeout timers if normal frames */
1317 skge_write16(hw, B3_PA_CTRL,
45bada65 1318 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1319 }
baef58b1
SH		 1320}
1321
1322static void genesis_stop(struct skge_port *skge)
1323{
1324 struct skge_hw *hw = skge->hw;
1325 int port = skge->port;
89bf5f23 1326 u32 reg;
baef58b1 1327
46a60f2d
SH		 1328 genesis_reset(hw, port);
1329
baef58b1
SH		 1330 /* Clear Tx packet arbiter timeout IRQ */
1331 skge_write16(hw, B3_PA_CTRL,
1332 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1333
1334 /*
1335 * If the transfer stucks at the MAC the STOP command will not
1336 * terminate if we don't flush the XMAC's transmit FIFO !
1337 */
6b0c1480
SH		 1338 xm_write32(hw, port, XM_MODE,
1339 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1340
1341
1342 /* Reset the MAC */
6b0c1480 1343 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1344
1345 /* For external PHYs there must be special handling */
89bf5f23
SH		 1346 reg = skge_read32(hw, B2_GP_IO);
1347 if (port == 0) {
1348 reg |= GP_DIR_0;
1349 reg &= ~GP_IO_0;
1350 } else {
1351 reg |= GP_DIR_2;
1352 reg &= ~GP_IO_2;
baef58b1 1353 }
89bf5f23
SH		 1354 skge_write32(hw, B2_GP_IO, reg);
1355 skge_read32(hw, B2_GP_IO);
baef58b1 1356
6b0c1480
SH		 1357 xm_write16(hw, port, XM_MMU_CMD,
1358 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1359 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1360
6b0c1480 1361 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1362}
1363
1364
1365static void genesis_get_stats(struct skge_port *skge, u64 *data)
1366{
1367 struct skge_hw *hw = skge->hw;
1368 int port = skge->port;
1369 int i;
1370 unsigned long timeout = jiffies + HZ;
1371
6b0c1480 1372 xm_write16(hw, port,
baef58b1
SH		 1373 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1374
1375 /* wait for update to complete */
6b0c1480 1376 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1377 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1378 if (time_after(jiffies, timeout))
1379 break;
1380 udelay(10);
1381 }
1382
1383 /* special case for 64 bit octet counter */
6b0c1480
SH		 1384 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1385 | xm_read32(hw, port, XM_TXO_OK_LO);
1386 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1387 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1388
1389 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1390 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1391}
1392
1393static void genesis_mac_intr(struct skge_hw *hw, int port)
1394{
1395 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1396 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1397
7e676d91
SH		 1398 if (netif_msg_intr(skge))
1399 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1400 skge->netdev->name, status);
baef58b1
SH		 1401
1402 if (status & XM_IS_TXF_UR) {
6b0c1480 1403 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1404 ++skge->net_stats.tx_fifo_errors;
1405 }
1406 if (status & XM_IS_RXF_OV) {
6b0c1480 1407 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1408 ++skge->net_stats.rx_fifo_errors;
1409 }
1410}
1411
6b0c1480 1412static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1413{
1414 int i;
1415
6b0c1480
SH		 1416 gma_write16(hw, port, GM_SMI_DATA, val);
1417 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1418 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1419 for (i = 0; i < PHY_RETRIES; i++) {
1420 udelay(1);
1421
6b0c1480 1422 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1423 break;
1424 }
1425}
1426
6b0c1480 1427static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1428{
1429 int i;
1430
6b0c1480 1431 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1432 GM_SMI_CT_PHY_AD(hw->phy_addr)
1433 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1434
1435 for (i = 0; i < PHY_RETRIES; i++) {
1436 udelay(1);
6b0c1480 1437 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1438 goto ready;
1439 }
1440
1441 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1442 hw->dev[port]->name);
1443 return 0;
1444 ready:
6b0c1480 1445 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1446}
1447
baef58b1
SH		 1448static void genesis_link_up(struct skge_port *skge)
1449{
1450 struct skge_hw *hw = skge->hw;
1451 int port = skge->port;
1452 u16 cmd;
1453 u32 mode, msk;
1454
6b0c1480 1455 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1456
1457 /*
1458 * enabling pause frame reception is required for 1000BT
1459 * because the XMAC is not reset if the link is going down
1460 */
1461 if (skge->flow_control == FLOW_MODE_NONE ||
1462 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1463 /* Disable Pause Frame Reception */
baef58b1
SH		 1464 cmd |= XM_MMU_IGN_PF;
1465 else
1466 /* Enable Pause Frame Reception */
1467 cmd &= ~XM_MMU_IGN_PF;
1468
6b0c1480 1469 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1470
6b0c1480 1471 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1472 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1473 skge->flow_control == FLOW_MODE_LOC_SEND) {
1474 /*
1475 * Configure Pause Frame Generation
1476 * Use internal and external Pause Frame Generation.
1477 * Sending pause frames is edge triggered.
1478 * Send a Pause frame with the maximum pause time if
1479 * internal oder external FIFO full condition occurs.
1480 * Send a zero pause time frame to re-start transmission.
1481 */
1482 /* XM_PAUSE_DA = '010000C28001' (default) */
1483 /* XM_MAC_PTIME = 0xffff (maximum) */
1484 /* remember this value is defined in big endian (!) */
6b0c1480 1485 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1486
1487 mode |= XM_PAUSE_MODE;
6b0c1480 1488 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1489 } else {
1490 /*
1491 * disable pause frame generation is required for 1000BT
1492 * because the XMAC is not reset if the link is going down
1493 */
1494 /* Disable Pause Mode in Mode Register */
1495 mode &= ~XM_PAUSE_MODE;
1496
6b0c1480 1497 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1498 }
1499
6b0c1480 1500 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1501
1502 msk = XM_DEF_MSK;
89bf5f23
SH		 1503 /* disable GP0 interrupt bit for external Phy */
1504 msk |= XM_IS_INP_ASS;
baef58b1 1505
6b0c1480
SH		 1506 xm_write16(hw, port, XM_IMSK, msk);
1507 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1508
1509 /* get MMU Command Reg. */
6b0c1480 1510 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1511 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1512 cmd |= XM_MMU_GMII_FD;
1513
89bf5f23
SH		 1514 /*
1515 * Workaround BCOM Errata (#10523) for all BCom Phys
1516 * Enable Power Management after link up
1517 */
1518 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1519 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1520 & ~PHY_B_AC_DIS_PM);
1521 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1522
1523 /* enable Rx/Tx */
6b0c1480 1524 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1525 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1526 skge_link_up(skge);
1527}
1528
1529
45bada65 1530static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1531{
1532 struct skge_hw *hw = skge->hw;
1533 int port = skge->port;
45bada65
SH		 1534 u16 isrc;
1535
1536 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1537 if (netif_msg_intr(skge))
1538 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1539 skge->netdev->name, isrc);
baef58b1 1540
45bada65
SH		 1541 if (isrc & PHY_B_IS_PSE)
1542 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1543 hw->dev[port]->name);
baef58b1
SH		 1544
1545 /* Workaround BCom Errata:
1546 * enable and disable loopback mode if "NO HCD" occurs.
1547 */
45bada65 1548 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1549 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1550 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1551 ctrl | PHY_CT_LOOP);
6b0c1480 1552 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1553 ctrl & ~PHY_CT_LOOP);
1554 }
1555
45bada65
SH		 1556 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1557 bcom_check_link(hw, port);
baef58b1 1558
baef58b1
SH		 1559}
1560
1561/* Marvell Phy Initailization */
1562static void yukon_init(struct skge_hw *hw, int port)
1563{
1564 struct skge_port *skge = netdev_priv(hw->dev[port]);
1565 u16 ctrl, ct1000, adv;
baef58b1 1566
baef58b1 1567 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1568 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1569
1570 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1571 PHY_M_EC_MAC_S_MSK);
1572 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1573
c506a509 1574 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1575
6b0c1480 1576 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1577 }
1578
6b0c1480 1579 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1580 if (skge->autoneg == AUTONEG_DISABLE)
1581 ctrl &= ~PHY_CT_ANE;
1582
1583 ctrl |= PHY_CT_RESET;
6b0c1480 1584 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1585
1586 ctrl = 0;
1587 ct1000 = 0;
b18f2091 1588 adv = PHY_AN_CSMA;
baef58b1
SH		 1589
1590 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1591 if (hw->copper) {
baef58b1
SH		 1592 if (skge->advertising & ADVERTISED_1000baseT_Full)
1593 ct1000 |= PHY_M_1000C_AFD;
1594 if (skge->advertising & ADVERTISED_1000baseT_Half)
1595 ct1000 |= PHY_M_1000C_AHD;
1596 if (skge->advertising & ADVERTISED_100baseT_Full)
1597 adv |= PHY_M_AN_100_FD;
1598 if (skge->advertising & ADVERTISED_100baseT_Half)
1599 adv |= PHY_M_AN_100_HD;
1600 if (skge->advertising & ADVERTISED_10baseT_Full)
1601 adv |= PHY_M_AN_10_FD;
1602 if (skge->advertising & ADVERTISED_10baseT_Half)
1603 adv |= PHY_M_AN_10_HD;
45bada65 1604 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1605 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1606
45bada65
SH		 1607 /* Set Flow-control capabilities */
1608 adv |= phy_pause_map[skge->flow_control];
1609
baef58b1
SH		 1610 /* Restart Auto-negotiation */
1611 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1612 } else {
1613 /* forced speed/duplex settings */
1614 ct1000 = PHY_M_1000C_MSE;
1615
1616 if (skge->duplex == DUPLEX_FULL)
1617 ctrl |= PHY_CT_DUP_MD;
1618
1619 switch (skge->speed) {
1620 case SPEED_1000:
1621 ctrl |= PHY_CT_SP1000;
1622 break;
1623 case SPEED_100:
1624 ctrl |= PHY_CT_SP100;
1625 break;
1626 }
1627
1628 ctrl |= PHY_CT_RESET;
1629 }
1630
c506a509 1631 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1632
6b0c1480
SH		 1633 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1634 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1635
baef58b1
SH		 1636 /* Enable phy interrupt on autonegotiation complete (or link up) */
1637 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1639 else
4cde06ed 1640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1641}
1642
1643static void yukon_reset(struct skge_hw *hw, int port)
1644{
6b0c1480
SH		 1645 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1646 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1647 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1648 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1649 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1650
6b0c1480
SH		 1651 gma_write16(hw, port, GM_RX_CTRL,
1652 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1653 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1654}
1655
1656static void yukon_mac_init(struct skge_hw *hw, int port)
1657{
1658 struct skge_port *skge = netdev_priv(hw->dev[port]);
1659 int i;
1660 u32 reg;
1661 const u8 *addr = hw->dev[port]->dev_addr;
1662
1663 /* WA code for COMA mode -- set PHY reset */
1664 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1665 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1666 reg = skge_read32(hw, B2_GP_IO);
1667 reg |= GP_DIR_9 | GP_IO_9;
1668 skge_write32(hw, B2_GP_IO, reg);
1669 }
baef58b1
SH		 1670
1671 /* hard reset */
6b0c1480
SH		 1672 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1673 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1674
1675 /* WA code for COMA mode -- clear PHY reset */
1676 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1677 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1678 reg = skge_read32(hw, B2_GP_IO);
1679 reg |= GP_DIR_9;
1680 reg &= ~GP_IO_9;
1681 skge_write32(hw, B2_GP_IO, reg);
1682 }
baef58b1
SH		 1683
1684 /* Set hardware config mode */
1685 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1686 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1687 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1688
1689 /* Clear GMC reset */
6b0c1480
SH		 1690 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1691 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1692 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1693 if (skge->autoneg == AUTONEG_DISABLE) {
1694 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1695 gma_write16(hw, port, GM_GP_CTRL,
1696 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1697
1698 switch (skge->speed) {
1699 case SPEED_1000:
1700 reg |= GM_GPCR_SPEED_1000;
1701 /* fallthru */
1702 case SPEED_100:
1703 reg |= GM_GPCR_SPEED_100;
1704 }
1705
1706 if (skge->duplex == DUPLEX_FULL)
1707 reg |= GM_GPCR_DUP_FULL;
1708 } else
1709 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1710 switch (skge->flow_control) {
1711 case FLOW_MODE_NONE:
6b0c1480 1712 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1713 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1714 break;
1715 case FLOW_MODE_LOC_SEND:
1716 /* disable Rx flow-control */
1717 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1718 }
1719
6b0c1480 1720 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1721 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1722
baef58b1 1723 yukon_init(hw, port);
baef58b1
SH		 1724
1725 /* MIB clear */
6b0c1480
SH		 1726 reg = gma_read16(hw, port, GM_PHY_ADDR);
1727 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1728
1729 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1730 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1731 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1732
1733 /* transmit control */
6b0c1480 1734 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1735
1736 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1737 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1738 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1739
1740 /* transmit flow control */
6b0c1480 1741 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1742
1743 /* transmit parameter */
6b0c1480 1744 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1745 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1746 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1747 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1748
1749 /* serial mode register */
1750 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1751 if (hw->dev[port]->mtu > 1500)
1752 reg |= GM_SMOD_JUMBO_ENA;
1753
6b0c1480 1754 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1755
1756 /* physical address: used for pause frames */
6b0c1480 1757 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1758 /* virtual address for data */
6b0c1480 1759 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1760
1761 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1762 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1763 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1764 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1765
1766 /* Initialize Mac Fifo */
1767
1768 /* Configure Rx MAC FIFO */
6b0c1480 1769 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1770 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1771 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
38231713 1772 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
baef58b1 1773 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1774 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1775 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1776 /*
1777 * because Pause Packet Truncation in GMAC is not working
1778 * we have to increase the Flush Threshold to 64 bytes
1779 * in order to flush pause packets in Rx FIFO on Yukon-1
1780 */
1781 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1782
1783 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1784 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1785 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1786}
1787
1788static void yukon_stop(struct skge_port *skge)
1789{
1790 struct skge_hw *hw = skge->hw;
1791 int port = skge->port;
1792
46a60f2d
SH		 1793 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1794 yukon_reset(hw, port);
baef58b1 1795
6b0c1480
SH		 1796 gma_write16(hw, port, GM_GP_CTRL,
1797 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1798 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1799 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1800
46a60f2d
SH		 1801 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1802 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1803 u32 io = skge_read32(hw, B2_GP_IO);
1804
1805 io |= GP_DIR_9 | GP_IO_9;
1806 skge_write32(hw, B2_GP_IO, io);
1807 skge_read32(hw, B2_GP_IO);
1808 }
1809
baef58b1 1810 /* set GPHY Control reset */
46a60f2d
SH		 1811 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1812 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1813}
1814
1815static void yukon_get_stats(struct skge_port *skge, u64 *data)
1816{
1817 struct skge_hw *hw = skge->hw;
1818 int port = skge->port;
1819 int i;
1820
6b0c1480
SH		 1821 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1822 | gma_read32(hw, port, GM_TXO_OK_LO);
1823 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1824 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1825
1826 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1827 data[i] = gma_read32(hw, port,
baef58b1
SH		 1828 skge_stats[i].gma_offset);
1829}
1830
1831static void yukon_mac_intr(struct skge_hw *hw, int port)
1832{
7e676d91
SH		 1833 struct net_device *dev = hw->dev[port];
1834 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1835 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1836
7e676d91
SH		 1837 if (netif_msg_intr(skge))
1838 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1839 dev->name, status);
1840
baef58b1
SH		 1841 if (status & GM_IS_RX_FF_OR) {
1842 ++skge->net_stats.rx_fifo_errors;
d8a09943 1843 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1844 }
d8a09943 1845
baef58b1
SH		 1846 if (status & GM_IS_TX_FF_UR) {
1847 ++skge->net_stats.tx_fifo_errors;
d8a09943 1848 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1849 }
1850
1851}
1852
1853static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1854{
95566065 1855 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1856 case PHY_M_PS_SPEED_1000:
1857 return SPEED_1000;
1858 case PHY_M_PS_SPEED_100:
1859 return SPEED_100;
1860 default:
1861 return SPEED_10;
1862 }
1863}
1864
1865static void yukon_link_up(struct skge_port *skge)
1866{
1867 struct skge_hw *hw = skge->hw;
1868 int port = skge->port;
1869 u16 reg;
1870
baef58b1 1871 /* Enable Transmit FIFO Underrun */
46a60f2d 1872 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1873
6b0c1480 1874 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1875 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1876 reg |= GM_GPCR_DUP_FULL;
1877
1878 /* enable Rx/Tx */
1879 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1880 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1881
4cde06ed 1882 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1883 skge_link_up(skge);
1884}
1885
1886static void yukon_link_down(struct skge_port *skge)
1887{
1888 struct skge_hw *hw = skge->hw;
1889 int port = skge->port;
d8a09943 1890 u16 ctrl;
baef58b1 1891
6b0c1480 1892 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1893
1894 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1895 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1896 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1897
c506a509 1898 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1899 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1900 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1901 gm_phy_read(hw, port,
baef58b1
SH		 1902 PHY_MARV_AUNE_ADV)
1903 | PHY_M_AN_ASP);
1904
1905 }
1906
1907 yukon_reset(hw, port);
1908 skge_link_down(skge);
1909
1910 yukon_init(hw, port);
1911}
1912
1913static void yukon_phy_intr(struct skge_port *skge)
1914{
1915 struct skge_hw *hw = skge->hw;
1916 int port = skge->port;
1917 const char *reason = NULL;
1918 u16 istatus, phystat;
1919
6b0c1480
SH		 1920 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1921 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1922
1923 if (netif_msg_intr(skge))
1924 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1925 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1926
1927 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1928 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1929 & PHY_M_AN_RF) {
1930 reason = "remote fault";
1931 goto failed;
1932 }
1933
c506a509 1934 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1935 reason = "master/slave fault";
1936 goto failed;
1937 }
1938
1939 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1940 reason = "speed/duplex";
1941 goto failed;
1942 }
1943
1944 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1945 ? DUPLEX_FULL : DUPLEX_HALF;
1946 skge->speed = yukon_speed(hw, phystat);
1947
baef58b1
SH		 1948 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1949 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1950 case PHY_M_PS_PAUSE_MSK:
1951 skge->flow_control = FLOW_MODE_SYMMETRIC;
1952 break;
1953 case PHY_M_PS_RX_P_EN:
1954 skge->flow_control = FLOW_MODE_REM_SEND;
1955 break;
1956 case PHY_M_PS_TX_P_EN:
1957 skge->flow_control = FLOW_MODE_LOC_SEND;
1958 break;
1959 default:
1960 skge->flow_control = FLOW_MODE_NONE;
1961 }
1962
1963 if (skge->flow_control == FLOW_MODE_NONE ||
1964 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1965 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1966 else
6b0c1480 1967 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1968 yukon_link_up(skge);
1969 return;
1970 }
1971
1972 if (istatus & PHY_M_IS_LSP_CHANGE)
1973 skge->speed = yukon_speed(hw, phystat);
1974
1975 if (istatus & PHY_M_IS_DUP_CHANGE)
1976 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1977 if (istatus & PHY_M_IS_LST_CHANGE) {
1978 if (phystat & PHY_M_PS_LINK_UP)
1979 yukon_link_up(skge);
1980 else
1981 yukon_link_down(skge);
1982 }
1983 return;
1984 failed:
1985 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1986 skge->netdev->name, reason);
1987
1988 /* XXX restart autonegotiation? */
1989}
1990
1991static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1992{
1993 u32 end;
1994
1995 start /= 8;
1996 len /= 8;
1997 end = start + len - 1;
1998
1999 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2000 skge_write32(hw, RB_ADDR(q, RB_START), start);
2001 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2002 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2003 skge_write32(hw, RB_ADDR(q, RB_END), end);
2004
2005 if (q == Q_R1 || q == Q_R2) {
2006 /* Set thresholds on receive queue's */
2007 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2008 start + (2*len)/3);
2009 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2010 start + (len/3));
2011 } else {
2012 /* Enable store & forward on Tx queue's because
2013 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2014 */
2015 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2016 }
2017
2018 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2019}
2020
2021/* Setup Bus Memory Interface */
2022static void skge_qset(struct skge_port *skge, u16 q,
2023 const struct skge_element *e)
2024{
2025 struct skge_hw *hw = skge->hw;
2026 u32 watermark = 0x600;
2027 u64 base = skge->dma + (e->desc - skge->mem);
2028
2029 /* optimization to reduce window on 32bit/33mhz */
2030 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2031 watermark /= 2;
2032
2033 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2034 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2035 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2036 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2037}
2038
2039static int skge_up(struct net_device *dev)
2040{
2041 struct skge_port *skge = netdev_priv(dev);
2042 struct skge_hw *hw = skge->hw;
2043 int port = skge->port;
2044 u32 chunk, ram_addr;
2045 size_t rx_size, tx_size;
2046 int err;
2047
2048 if (netif_msg_ifup(skge))
2049 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2050
19a33d4e
SH		 2051 if (dev->mtu > RX_BUF_SIZE)
2052 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2053 else
2054 skge->rx_buf_size = RX_BUF_SIZE;
2055
2056
baef58b1
SH		 2057 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2058 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2059 skge->mem_size = tx_size + rx_size;
2060 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2061 if (!skge->mem)
2062 return -ENOMEM;
2063
2064 memset(skge->mem, 0, skge->mem_size);
2065
2066 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2067 goto free_pci_mem;
2068
19a33d4e
SH		 2069 err = skge_rx_fill(skge);
2070 if (err)
baef58b1
SH		 2071 goto free_rx_ring;
2072
2073 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2074 skge->dma + rx_size)))
2075 goto free_rx_ring;
2076
2077 skge->tx_avail = skge->tx_ring.count - 1;
2078
7e676d91
SH		 2079 /* Enable IRQ from port */
2080 hw->intr_mask |= portirqmask[port];
2081 skge_write32(hw, B0_IMSK, hw->intr_mask);
2082
baef58b1 2083 /* Initialze MAC */
4ff6ac05 2084 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2085 if (hw->chip_id == CHIP_ID_GENESIS)
2086 genesis_mac_init(hw, port);
2087 else
2088 yukon_mac_init(hw, port);
4ff6ac05 2089 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2090
2091 /* Configure RAMbuffers */
981d0377 2092 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2093 ram_addr = hw->ram_offset + 2 * chunk * port;
2094
2095 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2096 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2097
2098 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2099 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2100 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2101
2102 /* Start receiver BMU */
2103 wmb();
2104 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2105 skge_led(skge, LED_MODE_ON);
baef58b1 2106
baef58b1
SH		 2107 return 0;
2108
2109 free_rx_ring:
2110 skge_rx_clean(skge);
2111 kfree(skge->rx_ring.start);
2112 free_pci_mem:
2113 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2114
2115 return err;
2116}
2117
2118static int skge_down(struct net_device *dev)
2119{
2120 struct skge_port *skge = netdev_priv(dev);
2121 struct skge_hw *hw = skge->hw;
2122 int port = skge->port;
2123
2124 if (netif_msg_ifdown(skge))
2125 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2126
2127 netif_stop_queue(dev);
2128
46a60f2d
SH		 2129 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2130 if (hw->chip_id == CHIP_ID_GENESIS)
2131 genesis_stop(skge);
2132 else
2133 yukon_stop(skge);
2134
2135 hw->intr_mask &= ~portirqmask[skge->port];
2136 skge_write32(hw, B0_IMSK, hw->intr_mask);
2137
baef58b1
SH		 2138 /* Stop transmitter */
2139 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2140 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2141 RB_RST_SET|RB_DIS_OP_MD);
2142
baef58b1
SH		 2143
2144 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2145 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2146 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2147
2148 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2149 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2150 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2151
2152 /* Reset PCI FIFO */
2153 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2154 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2155
2156 /* Reset the RAM Buffer async Tx queue */
2157 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2158 /* stop receiver */
2159 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2160 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2161 RB_RST_SET|RB_DIS_OP_MD);
2162 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2163
2164 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2165 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2166 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2167 } else {
6b0c1480
SH		 2168 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2169 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2170 }
2171
6abebb53 2172 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2173
2174 skge_tx_clean(skge);
2175 skge_rx_clean(skge);
2176
2177 kfree(skge->rx_ring.start);
2178 kfree(skge->tx_ring.start);
2179 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2180 return 0;
2181}
2182
2183static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2184{
2185 struct skge_port *skge = netdev_priv(dev);
2186 struct skge_hw *hw = skge->hw;
2187 struct skge_ring *ring = &skge->tx_ring;
2188 struct skge_element *e;
2189 struct skge_tx_desc *td;
2190 int i;
2191 u32 control, len;
2192 u64 map;
2193 unsigned long flags;
2194
2195 skb = skb_padto(skb, ETH_ZLEN);
2196 if (!skb)
2197 return NETDEV_TX_OK;
2198
2199 local_irq_save(flags);
2200 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2201 /* Collision - tell upper layer to requeue */
2202 local_irq_restore(flags);
2203 return NETDEV_TX_LOCKED;
2204 }
baef58b1
SH		 2205
2206 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2207 netif_stop_queue(dev);
2208 spin_unlock_irqrestore(&skge->tx_lock, flags);
2209
2210 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2211 dev->name);
2212 return NETDEV_TX_BUSY;
2213 }
2214
2215 e = ring->to_use;
2216 td = e->desc;
2217 e->skb = skb;
2218 len = skb_headlen(skb);
2219 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2220 pci_unmap_addr_set(e, mapaddr, map);
2221 pci_unmap_len_set(e, maplen, len);
2222
2223 td->dma_lo = map;
2224 td->dma_hi = map >> 32;
2225
2226 if (skb->ip_summed == CHECKSUM_HW) {
2227 const struct iphdr *ip
2228 = (const struct iphdr *) (skb->data + ETH_HLEN);
2229 int offset = skb->h.raw - skb->data;
2230
2231 /* This seems backwards, but it is what the sk98lin
2232 * does. Looks like hardware is wrong?
2233 */
2234 if (ip->protocol == IPPROTO_UDP
981d0377 2235 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2236 control = BMU_TCP_CHECK;
2237 else
2238 control = BMU_UDP_CHECK;
2239
2240 td->csum_offs = 0;
2241 td->csum_start = offset;
2242 td->csum_write = offset + skb->csum;
2243 } else
2244 control = BMU_CHECK;
2245
2246 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2247 control |= BMU_EOF| BMU_IRQ_EOF;
2248 else {
2249 struct skge_tx_desc *tf = td;
2250
2251 control |= BMU_STFWD;
2252 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2253 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2254
2255 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2256 frag->size, PCI_DMA_TODEVICE);
2257
2258 e = e->next;
2259 e->skb = NULL;
2260 tf = e->desc;
2261 tf->dma_lo = map;
2262 tf->dma_hi = (u64) map >> 32;
2263 pci_unmap_addr_set(e, mapaddr, map);
2264 pci_unmap_len_set(e, maplen, frag->size);
2265
2266 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2267 }
2268 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2269 }
2270 /* Make sure all the descriptors written */
2271 wmb();
2272 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2273 wmb();
2274
2275 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2276
2277 if (netif_msg_tx_queued(skge))
0b2d7fea 2278 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2279 dev->name, e - ring->start, skb->len);
2280
2281 ring->to_use = e->next;
2282 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2283 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2284 pr_debug("%s: transmit queue full\n", dev->name);
2285 netif_stop_queue(dev);
2286 }
2287
2288 dev->trans_start = jiffies;
2289 spin_unlock_irqrestore(&skge->tx_lock, flags);
2290
2291 return NETDEV_TX_OK;
2292}
2293
2294static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2295{
19a33d4e 2296 /* This ring element can be skb or fragment */
baef58b1
SH		 2297 if (e->skb) {
2298 pci_unmap_single(hw->pdev,
2299 pci_unmap_addr(e, mapaddr),
2300 pci_unmap_len(e, maplen),
2301 PCI_DMA_TODEVICE);
2302 dev_kfree_skb_any(e->skb);
2303 e->skb = NULL;
2304 } else {
2305 pci_unmap_page(hw->pdev,
2306 pci_unmap_addr(e, mapaddr),
2307 pci_unmap_len(e, maplen),
2308 PCI_DMA_TODEVICE);
2309 }
2310}
2311
2312static void skge_tx_clean(struct skge_port *skge)
2313{
2314 struct skge_ring *ring = &skge->tx_ring;
2315 struct skge_element *e;
2316 unsigned long flags;
2317
2318 spin_lock_irqsave(&skge->tx_lock, flags);
2319 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2320 ++skge->tx_avail;
2321 skge_tx_free(skge->hw, e);
2322 }
2323 ring->to_clean = e;
2324 spin_unlock_irqrestore(&skge->tx_lock, flags);
2325}
2326
2327static void skge_tx_timeout(struct net_device *dev)
2328{
2329 struct skge_port *skge = netdev_priv(dev);
2330
2331 if (netif_msg_timer(skge))
2332 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2333
2334 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2335 skge_tx_clean(skge);
2336}
2337
2338static int skge_change_mtu(struct net_device *dev, int new_mtu)
2339{
2340 int err = 0;
19a33d4e 2341 int running = netif_running(dev);
baef58b1 2342
95566065 2343 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2344 return -EINVAL;
2345
baef58b1 2346
19a33d4e 2347 if (running)
baef58b1 2348 skge_down(dev);
19a33d4e
SH		 2349 dev->mtu = new_mtu;
2350 if (running)
baef58b1 2351 skge_up(dev);
baef58b1
SH		 2352
2353 return err;
2354}
2355
2356static void genesis_set_multicast(struct net_device *dev)
2357{
2358 struct skge_port *skge = netdev_priv(dev);
2359 struct skge_hw *hw = skge->hw;
2360 int port = skge->port;
2361 int i, count = dev->mc_count;
2362 struct dev_mc_list *list = dev->mc_list;
2363 u32 mode;
2364 u8 filter[8];
2365
6b0c1480 2366 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2367 mode |= XM_MD_ENA_HASH;
2368 if (dev->flags & IFF_PROMISC)
2369 mode |= XM_MD_ENA_PROM;
2370 else
2371 mode &= ~XM_MD_ENA_PROM;
2372
2373 if (dev->flags & IFF_ALLMULTI)
2374 memset(filter, 0xff, sizeof(filter));
2375 else {
2376 memset(filter, 0, sizeof(filter));
95566065 2377 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2378 u32 crc, bit;
2379 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2380 bit = ~crc & 0x3f;
baef58b1
SH		 2381 filter[bit/8] |= 1 << (bit%8);
2382 }
2383 }
2384
6b0c1480 2385 xm_write32(hw, port, XM_MODE, mode);
45bada65 2386 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2387}
2388
2389static void yukon_set_multicast(struct net_device *dev)
2390{
2391 struct skge_port *skge = netdev_priv(dev);
2392 struct skge_hw *hw = skge->hw;
2393 int port = skge->port;
2394 struct dev_mc_list *list = dev->mc_list;
2395 u16 reg;
2396 u8 filter[8];
2397
2398 memset(filter, 0, sizeof(filter));
2399
6b0c1480 2400 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2401 reg |= GM_RXCR_UCF_ENA;
2402
2403 if (dev->flags & IFF_PROMISC) /* promiscious */
2404 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2405 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2406 memset(filter, 0xff, sizeof(filter));
2407 else if (dev->mc_count == 0) /* no multicast */
2408 reg &= ~GM_RXCR_MCF_ENA;
2409 else {
2410 int i;
2411 reg |= GM_RXCR_MCF_ENA;
2412
95566065 2413 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2414 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2415 filter[bit/8] |= 1 << (bit%8);
2416 }
2417 }
2418
2419
6b0c1480 2420 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2421 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2422 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2423 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2424 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2425 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2426 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2427 (u16)filter[6] | ((u16)filter[7] << 8));
2428
6b0c1480 2429 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2430}
2431
2432static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2433{
2434 if (hw->chip_id == CHIP_ID_GENESIS)
2435 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2436 else
2437 return (status & GMR_FS_ANY_ERR) ||
2438 (status & GMR_FS_RX_OK) == 0;
2439}
2440
2441static void skge_rx_error(struct skge_port *skge, int slot,
2442 u32 control, u32 status)
2443{
2444 if (netif_msg_rx_err(skge))
2445 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2446 skge->netdev->name, slot, control, status);
2447
19a33d4e 2448 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
baef58b1 2449 skge->net_stats.rx_length_errors++;
19a33d4e
SH		 2450 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2451 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2452 skge->net_stats.rx_length_errors++;
2453 if (status & XMR_FS_FRA_ERR)
2454 skge->net_stats.rx_frame_errors++;
2455 if (status & XMR_FS_FCS_ERR)
2456 skge->net_stats.rx_crc_errors++;
2457 } else {
2458 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2459 skge->net_stats.rx_length_errors++;
2460 if (status & GMR_FS_FRAGMENT)
2461 skge->net_stats.rx_frame_errors++;
2462 if (status & GMR_FS_CRC_ERR)
2463 skge->net_stats.rx_crc_errors++;
2464 }
2465}
2466
2467/* Get receive buffer from descriptor.
2468 * Handles copy of small buffers and reallocation failures
2469 */
2470static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2471 struct skge_element *e,
2472 unsigned int len)
2473{
2474 struct sk_buff *nskb, *skb;
2475
2476 if (len < RX_COPY_THRESHOLD) {
2477 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2478 if (unlikely(!nskb))
2479 return NULL;
2480
2481 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2482 pci_unmap_addr(e, mapaddr),
2483 len, PCI_DMA_FROMDEVICE);
2484 memcpy(nskb->data, e->skb->data, len);
2485 pci_dma_sync_single_for_device(skge->hw->pdev,
2486 pci_unmap_addr(e, mapaddr),
2487 len, PCI_DMA_FROMDEVICE);
2488
2489 if (skge->rx_csum) {
2490 struct skge_rx_desc *rd = e->desc;
2491 nskb->csum = le16_to_cpu(rd->csum2);
2492 nskb->ip_summed = CHECKSUM_HW;
baef58b1 2493 }
19a33d4e
SH		 2494 skge_rx_reuse(e, skge->rx_buf_size);
2495 return nskb;
2496 } else {
2497 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2498 if (unlikely(!nskb))
2499 return NULL;
2500
2501 pci_unmap_single(skge->hw->pdev,
2502 pci_unmap_addr(e, mapaddr),
2503 pci_unmap_len(e, maplen),
2504 PCI_DMA_FROMDEVICE);
2505 skb = e->skb;
2506 if (skge->rx_csum) {
2507 struct skge_rx_desc *rd = e->desc;
2508 skb->csum = le16_to_cpu(rd->csum2);
2509 skb->ip_summed = CHECKSUM_HW;
2510 }
2511
2512 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2513 return skb;
baef58b1
SH		 2514 }
2515}
2516
19a33d4e 2517
baef58b1
SH		 2518static int skge_poll(struct net_device *dev, int *budget)
2519{
2520 struct skge_port *skge = netdev_priv(dev);
2521 struct skge_hw *hw = skge->hw;
2522 struct skge_ring *ring = &skge->rx_ring;
2523 struct skge_element *e;
2524 unsigned int to_do = min(dev->quota, *budget);
2525 unsigned int work_done = 0;
7e676d91 2526
19a33d4e 2527 for (e = ring->to_clean; work_done < to_do; e = e->next) {
baef58b1 2528 struct skge_rx_desc *rd = e->desc;
19a33d4e 2529 struct sk_buff *skb;
baef58b1
SH		 2530 u32 control, len, status;
2531
2532 rmb();
2533 control = rd->control;
2534 if (control & BMU_OWN)
2535 break;
2536
2537 len = control & BMU_BBC;
baef58b1 2538 status = rd->status;
19a33d4e
SH		 2539
2540 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2541 || bad_phy_status(hw, status))) {
baef58b1 2542 skge_rx_error(skge, e - ring->start, control, status);
19a33d4e 2543 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2544 continue;
2545 }
2546
2547 if (netif_msg_rx_status(skge))
0b2d7fea 2548 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2549 dev->name, e - ring->start, rd->status, len);
2550
19a33d4e
SH		 2551 skb = skge_rx_get(skge, e, len);
2552 if (likely(skb)) {
2553 skb_put(skb, len);
2554 skb->protocol = eth_type_trans(skb, dev);
baef58b1 2555
19a33d4e
SH		 2556 dev->last_rx = jiffies;
2557 netif_receive_skb(skb);
baef58b1 2558
19a33d4e
SH		 2559 ++work_done;
2560 } else
2561 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2562 }
2563 ring->to_clean = e;
2564
baef58b1
SH		 2565 /* restart receiver */
2566 wmb();
2567 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2568 CSR_START | CSR_IRQ_CL_F);
2569
19a33d4e
SH		 2570 *budget -= work_done;
2571 dev->quota -= work_done;
2572
2573 if (work_done >= to_do)
2574 return 1; /* not done */
baef58b1 2575
19a33d4e
SH		 2576 local_irq_disable();
2577 __netif_rx_complete(dev);
2578 hw->intr_mask |= portirqmask[skge->port];
2579 skge_write32(hw, B0_IMSK, hw->intr_mask);
2580 local_irq_enable();
2581 return 0;
baef58b1
SH		 2582}
2583
2584static inline void skge_tx_intr(struct net_device *dev)
2585{
2586 struct skge_port *skge = netdev_priv(dev);
2587 struct skge_hw *hw = skge->hw;
2588 struct skge_ring *ring = &skge->tx_ring;
2589 struct skge_element *e;
2590
2591 spin_lock(&skge->tx_lock);
95566065 2592 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2593 struct skge_tx_desc *td = e->desc;
2594 u32 control;
2595
2596 rmb();
2597 control = td->control;
2598 if (control & BMU_OWN)
2599 break;
2600
2601 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2602 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2603 dev->name, e - ring->start, td->status);
2604
2605 skge_tx_free(hw, e);
2606 e->skb = NULL;
2607 ++skge->tx_avail;
2608 }
2609 ring->to_clean = e;
2610 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2611
2612 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2613 netif_wake_queue(dev);
2614
2615 spin_unlock(&skge->tx_lock);
2616}
2617
f6620cab
SH		 2618/* Parity errors seem to happen when Genesis is connected to a switch
2619 * with no other ports present. Heartbeat error??
2620 */
baef58b1
SH		 2621static void skge_mac_parity(struct skge_hw *hw, int port)
2622{
f6620cab
SH		 2623 struct net_device *dev = hw->dev[port];
2624
2625 if (dev) {
2626 struct skge_port *skge = netdev_priv(dev);
2627 ++skge->net_stats.tx_heartbeat_errors;
2628 }
baef58b1
SH		 2629
2630 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2631 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2632 MFF_CLR_PERR);
2633 else
2634 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2635 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2636 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2637 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2638}
2639
2640static void skge_pci_clear(struct skge_hw *hw)
2641{
2642 u16 status;
2643
467b3417 2644 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2645 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2646 pci_write_config_word(hw->pdev, PCI_STATUS,
2647 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2648 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2649}
2650
2651static void skge_mac_intr(struct skge_hw *hw, int port)
2652{
95566065 2653 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2654 genesis_mac_intr(hw, port);
2655 else
2656 yukon_mac_intr(hw, port);
2657}
2658
2659/* Handle device specific framing and timeout interrupts */
2660static void skge_error_irq(struct skge_hw *hw)
2661{
2662 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2663
2664 if (hw->chip_id == CHIP_ID_GENESIS) {
2665 /* clear xmac errors */
2666 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2667 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2668 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2669 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2670 } else {
2671 /* Timestamp (unused) overflow */
2672 if (hwstatus & IS_IRQ_TIST_OV)
2673 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2674 }
2675
2676 if (hwstatus & IS_RAM_RD_PAR) {
2677 printk(KERN_ERR PFX "Ram read data parity error\n");
2678 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2679 }
2680
2681 if (hwstatus & IS_RAM_WR_PAR) {
2682 printk(KERN_ERR PFX "Ram write data parity error\n");
2683 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2684 }
2685
2686 if (hwstatus & IS_M1_PAR_ERR)
2687 skge_mac_parity(hw, 0);
2688
2689 if (hwstatus & IS_M2_PAR_ERR)
2690 skge_mac_parity(hw, 1);
2691
2692 if (hwstatus & IS_R1_PAR_ERR)
2693 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2694
2695 if (hwstatus & IS_R2_PAR_ERR)
2696 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2697
2698 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2699 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2700 hwstatus);
2701
2702 skge_pci_clear(hw);
2703
050ec18a 2704 /* if error still set then just ignore it */
baef58b1
SH		 2705 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2706 if (hwstatus & IS_IRQ_STAT) {
050ec18a 2707 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
baef58b1
SH		 2708 hwstatus);
2709 hw->intr_mask &= ~IS_HW_ERR;
2710 }
2711 }
2712}
2713
2714/*
2715 * Interrrupt from PHY are handled in tasklet (soft irq)
2716 * because accessing phy registers requires spin wait which might
2717 * cause excess interrupt latency.
2718 */
2719static void skge_extirq(unsigned long data)
2720{
2721 struct skge_hw *hw = (struct skge_hw *) data;
2722 int port;
2723
2724 spin_lock(&hw->phy_lock);
2725 for (port = 0; port < 2; port++) {
2726 struct net_device *dev = hw->dev[port];
2727
2728 if (dev && netif_running(dev)) {
2729 struct skge_port *skge = netdev_priv(dev);
2730
2731 if (hw->chip_id != CHIP_ID_GENESIS)
2732 yukon_phy_intr(skge);
89bf5f23 2733 else
45bada65 2734 bcom_phy_intr(skge);
baef58b1
SH		 2735 }
2736 }
2737 spin_unlock(&hw->phy_lock);
2738
2739 local_irq_disable();
2740 hw->intr_mask |= IS_EXT_REG;
2741 skge_write32(hw, B0_IMSK, hw->intr_mask);
2742 local_irq_enable();
2743}
2744
2745static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2746{
2747 struct skge_hw *hw = dev_id;
2748 u32 status = skge_read32(hw, B0_SP_ISRC);
2749
2750 if (status == 0 || status == ~0) /* hotplug or shared irq */
2751 return IRQ_NONE;
2752
2753 status &= hw->intr_mask;
7e676d91 2754 if (status & IS_R1_F) {
baef58b1 2755 hw->intr_mask &= ~IS_R1_F;
7e676d91 2756 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2757 }
2758
7e676d91 2759 if (status & IS_R2_F) {
baef58b1 2760 hw->intr_mask &= ~IS_R2_F;
7e676d91 2761 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2762 }
2763
2764 if (status & IS_XA1_F)
2765 skge_tx_intr(hw->dev[0]);
2766
2767 if (status & IS_XA2_F)
2768 skge_tx_intr(hw->dev[1]);
2769
d25f5a67
SH		 2770 if (status & IS_PA_TO_RX1) {
2771 struct skge_port *skge = netdev_priv(hw->dev[0]);
2772 ++skge->net_stats.rx_over_errors;
2773 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2774 }
2775
2776 if (status & IS_PA_TO_RX2) {
2777 struct skge_port *skge = netdev_priv(hw->dev[1]);
2778 ++skge->net_stats.rx_over_errors;
2779 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2780 }
2781
2782 if (status & IS_PA_TO_TX1)
2783 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2784
2785 if (status & IS_PA_TO_TX2)
2786 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2787
baef58b1
SH		 2788 if (status & IS_MAC1)
2789 skge_mac_intr(hw, 0);
95566065 2790
baef58b1
SH		 2791 if (status & IS_MAC2)
2792 skge_mac_intr(hw, 1);
2793
2794 if (status & IS_HW_ERR)
2795 skge_error_irq(hw);
2796
2797 if (status & IS_EXT_REG) {
2798 hw->intr_mask &= ~IS_EXT_REG;
2799 tasklet_schedule(&hw->ext_tasklet);
2800 }
2801
7e676d91 2802 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2803
2804 return IRQ_HANDLED;
2805}
2806
2807#ifdef CONFIG_NET_POLL_CONTROLLER
2808static void skge_netpoll(struct net_device *dev)
2809{
2810 struct skge_port *skge = netdev_priv(dev);
2811
2812 disable_irq(dev->irq);
2813 skge_intr(dev->irq, skge->hw, NULL);
2814 enable_irq(dev->irq);
2815}
2816#endif
2817
2818static int skge_set_mac_address(struct net_device *dev, void *p)
2819{
2820 struct skge_port *skge = netdev_priv(dev);
2821 struct sockaddr *addr = p;
2822 int err = 0;
2823
2824 if (!is_valid_ether_addr(addr->sa_data))
2825 return -EADDRNOTAVAIL;
2826
2827 skge_down(dev);
2828 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2829 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2830 dev->dev_addr, ETH_ALEN);
2831 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2832 dev->dev_addr, ETH_ALEN);
2833 if (dev->flags & IFF_UP)
2834 err = skge_up(dev);
2835 return err;
2836}
2837
2838static const struct {
2839 u8 id;
2840 const char *name;
2841} skge_chips[] = {
2842 { CHIP_ID_GENESIS, "Genesis" },
2843 { CHIP_ID_YUKON, "Yukon" },
2844 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2845 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2846};
2847
2848static const char *skge_board_name(const struct skge_hw *hw)
2849{
2850 int i;
2851 static char buf[16];
2852
2853 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2854 if (skge_chips[i].id == hw->chip_id)
2855 return skge_chips[i].name;
2856
2857 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2858 return buf;
2859}
2860
2861
2862/*
2863 * Setup the board data structure, but don't bring up
2864 * the port(s)
2865 */
2866static int skge_reset(struct skge_hw *hw)
2867{
2868 u16 ctst;
5e1705dd 2869 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 2870 int i;
baef58b1
SH		 2871
2872 ctst = skge_read16(hw, B0_CTST);
2873
2874 /* do a SW reset */
2875 skge_write8(hw, B0_CTST, CS_RST_SET);
2876 skge_write8(hw, B0_CTST, CS_RST_CLR);
2877
2878 /* clear PCI errors, if any */
2879 skge_pci_clear(hw);
2880
2881 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2882
2883 /* restore CLK_RUN bits (for Yukon-Lite) */
2884 skge_write16(hw, B0_CTST,
2885 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2886
2887 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 2888 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2889 pmd_type = skge_read8(hw, B2_PMD_TYP);
2890 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 2891
95566065 2892 switch (hw->chip_id) {
baef58b1 2893 case CHIP_ID_GENESIS:
5e1705dd 2894 switch (phy_type) {
baef58b1
SH		 2895 case SK_PHY_BCOM:
2896 hw->phy_addr = PHY_ADDR_BCOM;
2897 break;
2898 default:
2899 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 2900 pci_name(hw->pdev), phy_type);
baef58b1
SH		 2901 return -EOPNOTSUPP;
2902 }
2903 break;
2904
2905 case CHIP_ID_YUKON:
2906 case CHIP_ID_YUKON_LITE:
2907 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 2908 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2909 hw->copper = 1;
baef58b1
SH		 2910
2911 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 2912 break;
2913
2914 default:
2915 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2916 pci_name(hw->pdev), hw->chip_id);
2917 return -EOPNOTSUPP;
2918 }
2919
981d0377
SH		 2920 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2921 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2922 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2923
2924 /* read the adapters RAM size */
2925 t8 = skge_read8(hw, B2_E_0);
2926 if (hw->chip_id == CHIP_ID_GENESIS) {
2927 if (t8 == 3) {
2928 /* special case: 4 x 64k x 36, offset = 0x80000 */
2929 hw->ram_size = 0x100000;
2930 hw->ram_offset = 0x80000;
2931 } else
2932 hw->ram_size = t8 * 512;
2933 }
2934 else if (t8 == 0)
2935 hw->ram_size = 0x20000;
2936 else
2937 hw->ram_size = t8 * 4096;
2938
050ec18a 2939 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 2940 if (hw->chip_id == CHIP_ID_GENESIS)
2941 genesis_init(hw);
2942 else {
2943 /* switch power to VCC (WA for VAUX problem) */
2944 skge_write8(hw, B0_POWER_CTRL,
2945 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
050ec18a
SH		 2946 /* avoid boards with stuck Hardware error bits */
2947 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2948 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2949 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2950 hw->intr_mask &= ~IS_HW_ERR;
2951 }
2952
981d0377 2953 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2954 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2955 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2956 }
2957 }
2958
2959 /* turn off hardware timer (unused) */
2960 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2961 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2962 skge_write8(hw, B0_LED, LED_STAT_ON);
2963
2964 /* enable the Tx Arbiters */
981d0377 2965 for (i = 0; i < hw->ports; i++)
6b0c1480 2966 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2967
2968 /* Initialize ram interface */
2969 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2970
2971 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2972 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2973 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2974 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2975 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2976 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2977 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2978 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2979 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2980 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2981 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2982 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2983
2984 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2985
2986 /* Set interrupt moderation for Transmit only
2987 * Receive interrupts avoided by NAPI
2988 */
2989 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2990 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2991 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2992
baef58b1
SH		 2993 skge_write32(hw, B0_IMSK, hw->intr_mask);
2994
baef58b1 2995 spin_lock_bh(&hw->phy_lock);
981d0377 2996 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 2997 if (hw->chip_id == CHIP_ID_GENESIS)
2998 genesis_reset(hw, i);
2999 else
3000 yukon_reset(hw, i);
3001 }
3002 spin_unlock_bh(&hw->phy_lock);
3003
3004 return 0;
3005}
3006
3007/* Initialize network device */
981d0377
SH		 3008static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3009 int highmem)
baef58b1
SH		 3010{
3011 struct skge_port *skge;
3012 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3013
3014 if (!dev) {
3015 printk(KERN_ERR "skge etherdev alloc failed");
3016 return NULL;
3017 }
3018
3019 SET_MODULE_OWNER(dev);
3020 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3021 dev->open = skge_up;
3022 dev->stop = skge_down;
3023 dev->hard_start_xmit = skge_xmit_frame;
3024 dev->get_stats = skge_get_stats;
3025 if (hw->chip_id == CHIP_ID_GENESIS)
3026 dev->set_multicast_list = genesis_set_multicast;
3027 else
3028 dev->set_multicast_list = yukon_set_multicast;
3029
3030 dev->set_mac_address = skge_set_mac_address;
3031 dev->change_mtu = skge_change_mtu;
3032 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3033 dev->tx_timeout = skge_tx_timeout;
3034 dev->watchdog_timeo = TX_WATCHDOG;
3035 dev->poll = skge_poll;
3036 dev->weight = NAPI_WEIGHT;
3037#ifdef CONFIG_NET_POLL_CONTROLLER
3038 dev->poll_controller = skge_netpoll;
3039#endif
3040 dev->irq = hw->pdev->irq;
3041 dev->features = NETIF_F_LLTX;
981d0377
SH		 3042 if (highmem)
3043 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3044
3045 skge = netdev_priv(dev);
3046 skge->netdev = dev;
3047 skge->hw = hw;
3048 skge->msg_enable = netif_msg_init(debug, default_msg);
3049 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3050 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3051
3052 /* Auto speed and flow control */
3053 skge->autoneg = AUTONEG_ENABLE;
3054 skge->flow_control = FLOW_MODE_SYMMETRIC;
3055 skge->duplex = -1;
3056 skge->speed = -1;
31b619c5 3057 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3058
3059 hw->dev[port] = dev;
3060
3061 skge->port = port;
3062
3063 spin_lock_init(&skge->tx_lock);
3064
baef58b1
SH		 3065 if (hw->chip_id != CHIP_ID_GENESIS) {
3066 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3067 skge->rx_csum = 1;
3068 }
3069
3070 /* read the mac address */
3071 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3072
3073 /* device is off until link detection */
3074 netif_carrier_off(dev);
3075 netif_stop_queue(dev);
3076
3077 return dev;
3078}
3079
3080static void __devinit skge_show_addr(struct net_device *dev)
3081{
3082 const struct skge_port *skge = netdev_priv(dev);
3083
3084 if (netif_msg_probe(skge))
3085 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3086 dev->name,
3087 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3088 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3089}
3090
3091static int __devinit skge_probe(struct pci_dev *pdev,
3092 const struct pci_device_id *ent)
3093{
3094 struct net_device *dev, *dev1;
3095 struct skge_hw *hw;
3096 int err, using_dac = 0;
3097
3098 if ((err = pci_enable_device(pdev))) {
3099 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3100 pci_name(pdev));
3101 goto err_out;
3102 }
3103
3104 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3105 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3106 pci_name(pdev));
3107 goto err_out_disable_pdev;
3108 }
3109
3110 pci_set_master(pdev);
3111
3112 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3113 using_dac = 1;
3114 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3115 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3116 pci_name(pdev));
3117 goto err_out_free_regions;
3118 }
3119
3120#ifdef __BIG_ENDIAN
3121 /* byte swap decriptors in hardware */
3122 {
3123 u32 reg;
3124
3125 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3126 reg |= PCI_REV_DESC;
3127 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3128 }
3129#endif
3130
3131 err = -ENOMEM;
3132 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3133 if (!hw) {
3134 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3135 pci_name(pdev));
3136 goto err_out_free_regions;
3137 }
3138
3139 memset(hw, 0, sizeof(*hw));
3140 hw->pdev = pdev;
3141 spin_lock_init(&hw->phy_lock);
3142 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3143
3144 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3145 if (!hw->regs) {
3146 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3147 pci_name(pdev));
3148 goto err_out_free_hw;
3149 }
3150
3151 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3152 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3153 pci_name(pdev), pdev->irq);
3154 goto err_out_iounmap;
3155 }
3156 pci_set_drvdata(pdev, hw);
3157
3158 err = skge_reset(hw);
3159 if (err)
3160 goto err_out_free_irq;
3161
3162 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3163 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3164 skge_board_name(hw), hw->chip_rev);
baef58b1 3165
981d0377 3166 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3167 goto err_out_led_off;
3168
baef58b1
SH		 3169 if ((err = register_netdev(dev))) {
3170 printk(KERN_ERR PFX "%s: cannot register net device\n",
3171 pci_name(pdev));
3172 goto err_out_free_netdev;
3173 }
3174
3175 skge_show_addr(dev);
3176
981d0377 3177 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3178 if (register_netdev(dev1) == 0)
3179 skge_show_addr(dev1);
3180 else {
3181 /* Failure to register second port need not be fatal */
3182 printk(KERN_WARNING PFX "register of second port failed\n");
3183 hw->dev[1] = NULL;
3184 free_netdev(dev1);
3185 }
3186 }
3187
3188 return 0;
3189
3190err_out_free_netdev:
3191 free_netdev(dev);
3192err_out_led_off:
3193 skge_write16(hw, B0_LED, LED_STAT_OFF);
3194err_out_free_irq:
3195 free_irq(pdev->irq, hw);
3196err_out_iounmap:
3197 iounmap(hw->regs);
3198err_out_free_hw:
3199 kfree(hw);
3200err_out_free_regions:
3201 pci_release_regions(pdev);
3202err_out_disable_pdev:
3203 pci_disable_device(pdev);
3204 pci_set_drvdata(pdev, NULL);
3205err_out:
3206 return err;
3207}
3208
3209static void __devexit skge_remove(struct pci_dev *pdev)
3210{
3211 struct skge_hw *hw = pci_get_drvdata(pdev);
3212 struct net_device *dev0, *dev1;
3213
95566065 3214 if (!hw)
baef58b1
SH		 3215 return;
3216
3217 if ((dev1 = hw->dev[1]))
3218 unregister_netdev(dev1);
3219 dev0 = hw->dev[0];
3220 unregister_netdev(dev0);
3221
46a60f2d
SH		 3222 skge_write32(hw, B0_IMSK, 0);
3223 skge_write16(hw, B0_LED, LED_STAT_OFF);
3224 skge_pci_clear(hw);
3225 skge_write8(hw, B0_CTST, CS_RST_SET);
3226
baef58b1
SH		 3227 tasklet_kill(&hw->ext_tasklet);
3228
3229 free_irq(pdev->irq, hw);
3230 pci_release_regions(pdev);
3231 pci_disable_device(pdev);
3232 if (dev1)
3233 free_netdev(dev1);
3234 free_netdev(dev0);
46a60f2d 3235
baef58b1
SH		 3236 iounmap(hw->regs);
3237 kfree(hw);
3238 pci_set_drvdata(pdev, NULL);
3239}
3240
3241#ifdef CONFIG_PM
2a569579 3242static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3243{
3244 struct skge_hw *hw = pci_get_drvdata(pdev);
3245 int i, wol = 0;
3246
95566065 3247 for (i = 0; i < 2; i++) {
baef58b1
SH		 3248 struct net_device *dev = hw->dev[i];
3249
3250 if (dev) {
3251 struct skge_port *skge = netdev_priv(dev);
3252 if (netif_running(dev)) {
3253 netif_carrier_off(dev);
46a60f2d
SH		 3254 if (skge->wol)
3255 netif_stop_queue(dev);
3256 else
3257 skge_down(dev);
baef58b1
SH		 3258 }
3259 netif_device_detach(dev);
3260 wol |= skge->wol;
3261 }
3262 }
3263
3264 pci_save_state(pdev);
2a569579 3265 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3266 pci_disable_device(pdev);
3267 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3268
3269 return 0;
3270}
3271
3272static int skge_resume(struct pci_dev *pdev)
3273{
3274 struct skge_hw *hw = pci_get_drvdata(pdev);
3275 int i;
3276
3277 pci_set_power_state(pdev, PCI_D0);
3278 pci_restore_state(pdev);
3279 pci_enable_wake(pdev, PCI_D0, 0);
3280
3281 skge_reset(hw);
3282
95566065 3283 for (i = 0; i < 2; i++) {
baef58b1
SH		 3284 struct net_device *dev = hw->dev[i];
3285 if (dev) {
3286 netif_device_attach(dev);
95566065 3287 if (netif_running(dev))
baef58b1
SH		 3288 skge_up(dev);
3289 }
3290 }
3291 return 0;
3292}
3293#endif
3294
3295static struct pci_driver skge_driver = {
3296 .name = DRV_NAME,
3297 .id_table = skge_id_table,
3298 .probe = skge_probe,
3299 .remove = __devexit_p(skge_remove),
3300#ifdef CONFIG_PM
3301 .suspend = skge_suspend,
3302 .resume = skge_resume,
3303#endif
3304};
3305
3306static int __init skge_init_module(void)
3307{
3308 return pci_module_init(&skge_driver);
3309}
3310
3311static void __exit skge_cleanup_module(void)
3312{
3313 pci_unregister_driver(&skge_driver);
3314}
3315
3316module_init(skge_init_module);
3317module_exit(skge_cleanup_module);