Commit | Line | Data |
---|---|---|
baef58b1 SH |
1 | /* |
2 | * New driver for Marvell Yukon chipset and SysKonnect Gigabit | |
3 | * Ethernet adapters. Based on earlier sk98lin, e100 and | |
4 | * FreeBSD if_sk drivers. | |
5 | * | |
6 | * This driver intentionally does not support all the features | |
7 | * of the original driver such as link fail-over and link management because | |
8 | * those should be done at higher levels. | |
9 | * | |
10 | * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
27 | #include <linux/config.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/moduleparam.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <asm/irq.h> | |
40 | ||
41 | #include "skge.h" | |
42 | ||
43 | #define DRV_NAME "skge" | |
44 | #define DRV_VERSION "0.6" | |
45 | #define PFX DRV_NAME " " | |
46 | ||
47 | #define DEFAULT_TX_RING_SIZE 128 | |
48 | #define DEFAULT_RX_RING_SIZE 512 | |
49 | #define MAX_TX_RING_SIZE 1024 | |
50 | #define MAX_RX_RING_SIZE 4096 | |
51 | #define PHY_RETRIES 1000 | |
52 | #define ETH_JUMBO_MTU 9000 | |
53 | #define TX_WATCHDOG (5 * HZ) | |
54 | #define NAPI_WEIGHT 64 | |
55 | #define BLINK_HZ (HZ/4) | |
56 | #define LINK_POLL_HZ (HZ/10) | |
57 | ||
58 | MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); | |
59 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
60 | MODULE_LICENSE("GPL"); | |
61 | MODULE_VERSION(DRV_VERSION); | |
62 | ||
63 | static const u32 default_msg | |
64 | = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK | |
65 | | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN; | |
66 | ||
67 | static int debug = -1; /* defaults above */ | |
68 | module_param(debug, int, 0); | |
69 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
70 | ||
71 | static const struct pci_device_id skge_id_table[] = { | |
72 | { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940, | |
73 | PCI_ANY_ID, PCI_ANY_ID }, | |
74 | { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B, | |
75 | PCI_ANY_ID, PCI_ANY_ID }, | |
76 | { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE, | |
77 | PCI_ANY_ID, PCI_ANY_ID }, | |
78 | { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU, | |
79 | PCI_ANY_ID, PCI_ANY_ID }, | |
80 | { PCI_VENDOR_ID_SYSKONNECT, 0x9E00, /* SK-9Exx */ | |
81 | PCI_ANY_ID, PCI_ANY_ID }, | |
82 | { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T, | |
83 | PCI_ANY_ID, PCI_ANY_ID }, | |
84 | { PCI_VENDOR_ID_MARVELL, 0x4320, /* Gigabit Ethernet Controller */ | |
85 | PCI_ANY_ID, PCI_ANY_ID }, | |
86 | { PCI_VENDOR_ID_MARVELL, 0x5005, /* Marvell (11ab), Belkin */ | |
87 | PCI_ANY_ID, PCI_ANY_ID }, | |
88 | { PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD, | |
89 | PCI_ANY_ID, PCI_ANY_ID }, | |
90 | { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032, | |
91 | PCI_ANY_ID, PCI_ANY_ID }, | |
92 | { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064, | |
93 | PCI_ANY_ID, PCI_ANY_ID }, | |
94 | { 0 } | |
95 | }; | |
96 | MODULE_DEVICE_TABLE(pci, skge_id_table); | |
97 | ||
98 | static int skge_up(struct net_device *dev); | |
99 | static int skge_down(struct net_device *dev); | |
100 | static void skge_tx_clean(struct skge_port *skge); | |
101 | static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
102 | static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
103 | static void genesis_get_stats(struct skge_port *skge, u64 *data); | |
104 | static void yukon_get_stats(struct skge_port *skge, u64 *data); | |
105 | static void yukon_init(struct skge_hw *hw, int port); | |
106 | static void yukon_reset(struct skge_hw *hw, int port); | |
107 | static void genesis_mac_init(struct skge_hw *hw, int port); | |
108 | static void genesis_reset(struct skge_hw *hw, int port); | |
109 | ||
110 | static const int txqaddr[] = { Q_XA1, Q_XA2 }; | |
111 | static const int rxqaddr[] = { Q_R1, Q_R2 }; | |
112 | static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; | |
113 | static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; | |
114 | ||
115 | /* Don't need to look at whole 16K. | |
116 | * last interesting register is descriptor poll timer. | |
117 | */ | |
118 | #define SKGE_REGS_LEN (29*128) | |
119 | ||
120 | static int skge_get_regs_len(struct net_device *dev) | |
121 | { | |
122 | return SKGE_REGS_LEN; | |
123 | } | |
124 | ||
125 | /* | |
126 | * Returns copy of control register region | |
127 | * I/O region is divided into banks and certain regions are unreadable | |
128 | */ | |
129 | static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
130 | void *p) | |
131 | { | |
132 | const struct skge_port *skge = netdev_priv(dev); | |
133 | unsigned long offs; | |
134 | const void __iomem *io = skge->hw->regs; | |
135 | static const unsigned long bankmap | |
136 | = (1<<0) | (1<<2) | (1<<8) | (1<<9) | |
137 | | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16) | |
138 | | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23) | |
139 | | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28); | |
140 | ||
141 | regs->version = 1; | |
142 | for (offs = 0; offs < regs->len; offs += 128) { | |
143 | u32 len = min_t(u32, 128, regs->len - offs); | |
144 | ||
145 | if (bankmap & (1<<(offs/128))) | |
146 | memcpy_fromio(p + offs, io + offs, len); | |
147 | else | |
148 | memset(p + offs, 0, len); | |
149 | } | |
150 | } | |
151 | ||
152 | /* Wake on Lan only supported on Yukon chps with rev 1 or above */ | |
153 | static int wol_supported(const struct skge_hw *hw) | |
154 | { | |
155 | return !((hw->chip_id == CHIP_ID_GENESIS || | |
156 | (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0))); | |
157 | } | |
158 | ||
159 | static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
160 | { | |
161 | struct skge_port *skge = netdev_priv(dev); | |
162 | ||
163 | wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0; | |
164 | wol->wolopts = skge->wol ? WAKE_MAGIC : 0; | |
165 | } | |
166 | ||
167 | static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
168 | { | |
169 | struct skge_port *skge = netdev_priv(dev); | |
170 | struct skge_hw *hw = skge->hw; | |
171 | ||
172 | if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
173 | return -EOPNOTSUPP; | |
174 | ||
175 | if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw)) | |
176 | return -EOPNOTSUPP; | |
177 | ||
178 | skge->wol = wol->wolopts == WAKE_MAGIC; | |
179 | ||
180 | if (skge->wol) { | |
181 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
182 | ||
183 | skge_write16(hw, WOL_CTRL_STAT, | |
184 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
185 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
186 | } else | |
187 | skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | ||
193 | static int skge_get_settings(struct net_device *dev, | |
194 | struct ethtool_cmd *ecmd) | |
195 | { | |
196 | struct skge_port *skge = netdev_priv(dev); | |
197 | struct skge_hw *hw = skge->hw; | |
198 | ||
199 | ecmd->transceiver = XCVR_INTERNAL; | |
200 | ||
201 | if (iscopper(hw)) { | |
202 | if (hw->chip_id == CHIP_ID_GENESIS) | |
203 | ecmd->supported = SUPPORTED_1000baseT_Full | |
204 | | SUPPORTED_1000baseT_Half | |
205 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
206 | else { | |
207 | ecmd->supported = SUPPORTED_10baseT_Half | |
208 | | SUPPORTED_10baseT_Full | |
209 | | SUPPORTED_100baseT_Half | |
210 | | SUPPORTED_100baseT_Full | |
211 | | SUPPORTED_1000baseT_Half | |
212 | | SUPPORTED_1000baseT_Full | |
213 | | SUPPORTED_Autoneg| SUPPORTED_TP; | |
214 | ||
215 | if (hw->chip_id == CHIP_ID_YUKON) | |
216 | ecmd->supported &= ~SUPPORTED_1000baseT_Half; | |
217 | ||
218 | else if (hw->chip_id == CHIP_ID_YUKON_FE) | |
219 | ecmd->supported &= ~(SUPPORTED_1000baseT_Half | |
220 | | SUPPORTED_1000baseT_Full); | |
221 | } | |
222 | ||
223 | ecmd->port = PORT_TP; | |
224 | ecmd->phy_address = hw->phy_addr; | |
225 | } else { | |
226 | ecmd->supported = SUPPORTED_1000baseT_Full | |
227 | | SUPPORTED_FIBRE | |
228 | | SUPPORTED_Autoneg; | |
229 | ||
230 | ecmd->port = PORT_FIBRE; | |
231 | } | |
232 | ||
233 | ecmd->advertising = skge->advertising; | |
234 | ecmd->autoneg = skge->autoneg; | |
235 | ecmd->speed = skge->speed; | |
236 | ecmd->duplex = skge->duplex; | |
237 | return 0; | |
238 | } | |
239 | ||
240 | static u32 skge_modes(const struct skge_hw *hw) | |
241 | { | |
242 | u32 modes = ADVERTISED_Autoneg | |
243 | | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half | |
244 | | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half | |
245 | | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half; | |
246 | ||
247 | if (iscopper(hw)) { | |
248 | modes |= ADVERTISED_TP; | |
249 | switch(hw->chip_id) { | |
250 | case CHIP_ID_GENESIS: | |
251 | modes &= ~(ADVERTISED_100baseT_Full | |
252 | | ADVERTISED_100baseT_Half | |
253 | | ADVERTISED_10baseT_Full | |
254 | | ADVERTISED_10baseT_Half); | |
255 | break; | |
256 | ||
257 | case CHIP_ID_YUKON: | |
258 | modes &= ~ADVERTISED_1000baseT_Half; | |
259 | break; | |
260 | ||
261 | case CHIP_ID_YUKON_FE: | |
262 | modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); | |
263 | break; | |
264 | } | |
265 | } else { | |
266 | modes |= ADVERTISED_FIBRE; | |
267 | modes &= ~ADVERTISED_1000baseT_Half; | |
268 | } | |
269 | return modes; | |
270 | } | |
271 | ||
272 | static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
273 | { | |
274 | struct skge_port *skge = netdev_priv(dev); | |
275 | const struct skge_hw *hw = skge->hw; | |
276 | ||
277 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
278 | if (ecmd->advertising & skge_modes(hw)) | |
279 | return -EINVAL; | |
280 | } else { | |
281 | switch(ecmd->speed) { | |
282 | case SPEED_1000: | |
283 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
284 | return -EINVAL; | |
285 | break; | |
286 | case SPEED_100: | |
287 | case SPEED_10: | |
288 | if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS) | |
289 | return -EINVAL; | |
290 | break; | |
291 | default: | |
292 | return -EINVAL; | |
293 | } | |
294 | } | |
295 | ||
296 | skge->autoneg = ecmd->autoneg; | |
297 | skge->speed = ecmd->speed; | |
298 | skge->duplex = ecmd->duplex; | |
299 | skge->advertising = ecmd->advertising; | |
300 | ||
301 | if (netif_running(dev)) { | |
302 | skge_down(dev); | |
303 | skge_up(dev); | |
304 | } | |
305 | return (0); | |
306 | } | |
307 | ||
308 | static void skge_get_drvinfo(struct net_device *dev, | |
309 | struct ethtool_drvinfo *info) | |
310 | { | |
311 | struct skge_port *skge = netdev_priv(dev); | |
312 | ||
313 | strcpy(info->driver, DRV_NAME); | |
314 | strcpy(info->version, DRV_VERSION); | |
315 | strcpy(info->fw_version, "N/A"); | |
316 | strcpy(info->bus_info, pci_name(skge->hw->pdev)); | |
317 | } | |
318 | ||
319 | static const struct skge_stat { | |
320 | char name[ETH_GSTRING_LEN]; | |
321 | u16 xmac_offset; | |
322 | u16 gma_offset; | |
323 | } skge_stats[] = { | |
324 | { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, | |
325 | { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, | |
326 | ||
327 | { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, | |
328 | { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, | |
329 | { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, | |
330 | { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, | |
331 | { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, | |
332 | { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, | |
333 | { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, | |
334 | { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, | |
335 | ||
336 | { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, | |
337 | { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, | |
338 | { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, | |
339 | { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, | |
340 | { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, | |
341 | { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, | |
342 | ||
343 | { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
344 | { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, | |
345 | { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, | |
346 | { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
347 | { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, | |
348 | }; | |
349 | ||
350 | static int skge_get_stats_count(struct net_device *dev) | |
351 | { | |
352 | return ARRAY_SIZE(skge_stats); | |
353 | } | |
354 | ||
355 | static void skge_get_ethtool_stats(struct net_device *dev, | |
356 | struct ethtool_stats *stats, u64 *data) | |
357 | { | |
358 | struct skge_port *skge = netdev_priv(dev); | |
359 | ||
360 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
361 | genesis_get_stats(skge, data); | |
362 | else | |
363 | yukon_get_stats(skge, data); | |
364 | } | |
365 | ||
366 | /* Use hardware MIB variables for critical path statistics and | |
367 | * transmit feedback not reported at interrupt. | |
368 | * Other errors are accounted for in interrupt handler. | |
369 | */ | |
370 | static struct net_device_stats *skge_get_stats(struct net_device *dev) | |
371 | { | |
372 | struct skge_port *skge = netdev_priv(dev); | |
373 | u64 data[ARRAY_SIZE(skge_stats)]; | |
374 | ||
375 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
376 | genesis_get_stats(skge, data); | |
377 | else | |
378 | yukon_get_stats(skge, data); | |
379 | ||
380 | skge->net_stats.tx_bytes = data[0]; | |
381 | skge->net_stats.rx_bytes = data[1]; | |
382 | skge->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
383 | skge->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
384 | skge->net_stats.multicast = data[5] + data[7]; | |
385 | skge->net_stats.collisions = data[10]; | |
386 | skge->net_stats.tx_aborted_errors = data[12]; | |
387 | ||
388 | return &skge->net_stats; | |
389 | } | |
390 | ||
391 | static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
392 | { | |
393 | int i; | |
394 | ||
395 | switch(stringset) { | |
396 | case ETH_SS_STATS: | |
397 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | |
398 | memcpy(data + i * ETH_GSTRING_LEN, | |
399 | skge_stats[i].name, ETH_GSTRING_LEN); | |
400 | break; | |
401 | } | |
402 | } | |
403 | ||
404 | static void skge_get_ring_param(struct net_device *dev, | |
405 | struct ethtool_ringparam *p) | |
406 | { | |
407 | struct skge_port *skge = netdev_priv(dev); | |
408 | ||
409 | p->rx_max_pending = MAX_RX_RING_SIZE; | |
410 | p->tx_max_pending = MAX_TX_RING_SIZE; | |
411 | p->rx_mini_max_pending = 0; | |
412 | p->rx_jumbo_max_pending = 0; | |
413 | ||
414 | p->rx_pending = skge->rx_ring.count; | |
415 | p->tx_pending = skge->tx_ring.count; | |
416 | p->rx_mini_pending = 0; | |
417 | p->rx_jumbo_pending = 0; | |
418 | } | |
419 | ||
420 | static int skge_set_ring_param(struct net_device *dev, | |
421 | struct ethtool_ringparam *p) | |
422 | { | |
423 | struct skge_port *skge = netdev_priv(dev); | |
424 | ||
425 | if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || | |
426 | p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE) | |
427 | return -EINVAL; | |
428 | ||
429 | skge->rx_ring.count = p->rx_pending; | |
430 | skge->tx_ring.count = p->tx_pending; | |
431 | ||
432 | if (netif_running(dev)) { | |
433 | skge_down(dev); | |
434 | skge_up(dev); | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static u32 skge_get_msglevel(struct net_device *netdev) | |
441 | { | |
442 | struct skge_port *skge = netdev_priv(netdev); | |
443 | return skge->msg_enable; | |
444 | } | |
445 | ||
446 | static void skge_set_msglevel(struct net_device *netdev, u32 value) | |
447 | { | |
448 | struct skge_port *skge = netdev_priv(netdev); | |
449 | skge->msg_enable = value; | |
450 | } | |
451 | ||
452 | static int skge_nway_reset(struct net_device *dev) | |
453 | { | |
454 | struct skge_port *skge = netdev_priv(dev); | |
455 | struct skge_hw *hw = skge->hw; | |
456 | int port = skge->port; | |
457 | ||
458 | if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) | |
459 | return -EINVAL; | |
460 | ||
461 | spin_lock_bh(&hw->phy_lock); | |
462 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
463 | genesis_reset(hw, port); | |
464 | genesis_mac_init(hw, port); | |
465 | } else { | |
466 | yukon_reset(hw, port); | |
467 | yukon_init(hw, port); | |
468 | } | |
469 | spin_unlock_bh(&hw->phy_lock); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int skge_set_sg(struct net_device *dev, u32 data) | |
474 | { | |
475 | struct skge_port *skge = netdev_priv(dev); | |
476 | struct skge_hw *hw = skge->hw; | |
477 | ||
478 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
479 | return -EOPNOTSUPP; | |
480 | return ethtool_op_set_sg(dev, data); | |
481 | } | |
482 | ||
483 | static int skge_set_tx_csum(struct net_device *dev, u32 data) | |
484 | { | |
485 | struct skge_port *skge = netdev_priv(dev); | |
486 | struct skge_hw *hw = skge->hw; | |
487 | ||
488 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
489 | return -EOPNOTSUPP; | |
490 | ||
491 | return ethtool_op_set_tx_csum(dev, data); | |
492 | } | |
493 | ||
494 | static u32 skge_get_rx_csum(struct net_device *dev) | |
495 | { | |
496 | struct skge_port *skge = netdev_priv(dev); | |
497 | ||
498 | return skge->rx_csum; | |
499 | } | |
500 | ||
501 | /* Only Yukon supports checksum offload. */ | |
502 | static int skge_set_rx_csum(struct net_device *dev, u32 data) | |
503 | { | |
504 | struct skge_port *skge = netdev_priv(dev); | |
505 | ||
506 | if (skge->hw->chip_id == CHIP_ID_GENESIS && data) | |
507 | return -EOPNOTSUPP; | |
508 | ||
509 | skge->rx_csum = data; | |
510 | return 0; | |
511 | } | |
512 | ||
513 | /* Only Yukon II supports TSO (not implemented yet) */ | |
514 | static int skge_set_tso(struct net_device *dev, u32 data) | |
515 | { | |
516 | if (data) | |
517 | return -EOPNOTSUPP; | |
518 | return 0; | |
519 | } | |
520 | ||
521 | static void skge_get_pauseparam(struct net_device *dev, | |
522 | struct ethtool_pauseparam *ecmd) | |
523 | { | |
524 | struct skge_port *skge = netdev_priv(dev); | |
525 | ||
526 | ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND) | |
527 | || (skge->flow_control == FLOW_MODE_SYMMETRIC); | |
528 | ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND) | |
529 | || (skge->flow_control == FLOW_MODE_SYMMETRIC); | |
530 | ||
531 | ecmd->autoneg = skge->autoneg; | |
532 | } | |
533 | ||
534 | static int skge_set_pauseparam(struct net_device *dev, | |
535 | struct ethtool_pauseparam *ecmd) | |
536 | { | |
537 | struct skge_port *skge = netdev_priv(dev); | |
538 | ||
539 | skge->autoneg = ecmd->autoneg; | |
540 | if (ecmd->rx_pause && ecmd->tx_pause) | |
541 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
542 | else if(ecmd->rx_pause && !ecmd->tx_pause) | |
543 | skge->flow_control = FLOW_MODE_REM_SEND; | |
544 | else if(!ecmd->rx_pause && ecmd->tx_pause) | |
545 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
546 | else | |
547 | skge->flow_control = FLOW_MODE_NONE; | |
548 | ||
549 | if (netif_running(dev)) { | |
550 | skge_down(dev); | |
551 | skge_up(dev); | |
552 | } | |
553 | return 0; | |
554 | } | |
555 | ||
556 | /* Chip internal frequency for clock calculations */ | |
557 | static inline u32 hwkhz(const struct skge_hw *hw) | |
558 | { | |
559 | if (hw->chip_id == CHIP_ID_GENESIS) | |
560 | return 53215; /* or: 53.125 MHz */ | |
561 | else if (hw->chip_id == CHIP_ID_YUKON_EC) | |
562 | return 125000; /* or: 125.000 MHz */ | |
563 | else | |
564 | return 78215; /* or: 78.125 MHz */ | |
565 | } | |
566 | ||
567 | /* Chip hz to microseconds */ | |
568 | static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) | |
569 | { | |
570 | return (ticks * 1000) / hwkhz(hw); | |
571 | } | |
572 | ||
573 | /* Microseconds to chip hz */ | |
574 | static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) | |
575 | { | |
576 | return hwkhz(hw) * usec / 1000; | |
577 | } | |
578 | ||
579 | static int skge_get_coalesce(struct net_device *dev, | |
580 | struct ethtool_coalesce *ecmd) | |
581 | { | |
582 | struct skge_port *skge = netdev_priv(dev); | |
583 | struct skge_hw *hw = skge->hw; | |
584 | int port = skge->port; | |
585 | ||
586 | ecmd->rx_coalesce_usecs = 0; | |
587 | ecmd->tx_coalesce_usecs = 0; | |
588 | ||
589 | if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { | |
590 | u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); | |
591 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
592 | ||
593 | if (msk & rxirqmask[port]) | |
594 | ecmd->rx_coalesce_usecs = delay; | |
595 | if (msk & txirqmask[port]) | |
596 | ecmd->tx_coalesce_usecs = delay; | |
597 | } | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* Note: interrupt timer is per board, but can turn on/off per port */ | |
603 | static int skge_set_coalesce(struct net_device *dev, | |
604 | struct ethtool_coalesce *ecmd) | |
605 | { | |
606 | struct skge_port *skge = netdev_priv(dev); | |
607 | struct skge_hw *hw = skge->hw; | |
608 | int port = skge->port; | |
609 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
610 | u32 delay = 25; | |
611 | ||
612 | if (ecmd->rx_coalesce_usecs == 0) | |
613 | msk &= ~rxirqmask[port]; | |
614 | else if (ecmd->rx_coalesce_usecs < 25 || | |
615 | ecmd->rx_coalesce_usecs > 33333) | |
616 | return -EINVAL; | |
617 | else { | |
618 | msk |= rxirqmask[port]; | |
619 | delay = ecmd->rx_coalesce_usecs; | |
620 | } | |
621 | ||
622 | if (ecmd->tx_coalesce_usecs == 0) | |
623 | msk &= ~txirqmask[port]; | |
624 | else if (ecmd->tx_coalesce_usecs < 25 || | |
625 | ecmd->tx_coalesce_usecs > 33333) | |
626 | return -EINVAL; | |
627 | else { | |
628 | msk |= txirqmask[port]; | |
629 | delay = min(delay, ecmd->rx_coalesce_usecs); | |
630 | } | |
631 | ||
632 | skge_write32(hw, B2_IRQM_MSK, msk); | |
633 | if (msk == 0) | |
634 | skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); | |
635 | else { | |
636 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); | |
637 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
638 | } | |
639 | return 0; | |
640 | } | |
641 | ||
642 | static void skge_led_on(struct skge_hw *hw, int port) | |
643 | { | |
644 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
645 | skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); | |
646 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
647 | ||
648 | skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON); | |
649 | skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100); | |
650 | skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); | |
651 | ||
652 | switch (hw->phy_type) { | |
653 | case SK_PHY_BCOM: | |
654 | skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, | |
655 | PHY_B_PEC_LED_ON); | |
656 | break; | |
657 | case SK_PHY_LONE: | |
658 | skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG, | |
659 | 0x0800); | |
660 | break; | |
661 | default: | |
662 | skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON); | |
663 | skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100); | |
664 | skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START); | |
665 | } | |
666 | } else { | |
667 | skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
668 | skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
669 | PHY_M_LED_MO_DUP(MO_LED_ON) | | |
670 | PHY_M_LED_MO_10(MO_LED_ON) | | |
671 | PHY_M_LED_MO_100(MO_LED_ON) | | |
672 | PHY_M_LED_MO_1000(MO_LED_ON) | | |
673 | PHY_M_LED_MO_RX(MO_LED_ON)); | |
674 | } | |
675 | } | |
676 | ||
677 | static void skge_led_off(struct skge_hw *hw, int port) | |
678 | { | |
679 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
680 | skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF); | |
681 | skge_write8(hw, B0_LED, LED_STAT_OFF); | |
682 | ||
683 | skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0); | |
684 | skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF); | |
685 | ||
686 | switch (hw->phy_type) { | |
687 | case SK_PHY_BCOM: | |
688 | skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, | |
689 | PHY_B_PEC_LED_OFF); | |
690 | break; | |
691 | case SK_PHY_LONE: | |
692 | skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG, | |
693 | PHY_L_LC_LEDT); | |
694 | break; | |
695 | default: | |
696 | skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0); | |
697 | skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF); | |
698 | } | |
699 | } else { | |
700 | skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
701 | skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
702 | PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
703 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
704 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
705 | PHY_M_LED_MO_1000(MO_LED_OFF) | | |
706 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
707 | } | |
708 | } | |
709 | ||
710 | static void skge_blink_timer(unsigned long data) | |
711 | { | |
712 | struct skge_port *skge = (struct skge_port *) data; | |
713 | struct skge_hw *hw = skge->hw; | |
714 | unsigned long flags; | |
715 | ||
716 | spin_lock_irqsave(&hw->phy_lock, flags); | |
717 | if (skge->blink_on) | |
718 | skge_led_on(hw, skge->port); | |
719 | else | |
720 | skge_led_off(hw, skge->port); | |
721 | spin_unlock_irqrestore(&hw->phy_lock, flags); | |
722 | ||
723 | skge->blink_on = !skge->blink_on; | |
724 | mod_timer(&skge->led_blink, jiffies + BLINK_HZ); | |
725 | } | |
726 | ||
727 | /* blink LED's for finding board */ | |
728 | static int skge_phys_id(struct net_device *dev, u32 data) | |
729 | { | |
730 | struct skge_port *skge = netdev_priv(dev); | |
731 | ||
732 | if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) | |
733 | data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); | |
734 | ||
735 | /* start blinking */ | |
736 | skge->blink_on = 1; | |
737 | mod_timer(&skge->led_blink, jiffies+1); | |
738 | ||
739 | msleep_interruptible(data * 1000); | |
740 | del_timer_sync(&skge->led_blink); | |
741 | ||
742 | skge_led_off(skge->hw, skge->port); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static struct ethtool_ops skge_ethtool_ops = { | |
748 | .get_settings = skge_get_settings, | |
749 | .set_settings = skge_set_settings, | |
750 | .get_drvinfo = skge_get_drvinfo, | |
751 | .get_regs_len = skge_get_regs_len, | |
752 | .get_regs = skge_get_regs, | |
753 | .get_wol = skge_get_wol, | |
754 | .set_wol = skge_set_wol, | |
755 | .get_msglevel = skge_get_msglevel, | |
756 | .set_msglevel = skge_set_msglevel, | |
757 | .nway_reset = skge_nway_reset, | |
758 | .get_link = ethtool_op_get_link, | |
759 | .get_ringparam = skge_get_ring_param, | |
760 | .set_ringparam = skge_set_ring_param, | |
761 | .get_pauseparam = skge_get_pauseparam, | |
762 | .set_pauseparam = skge_set_pauseparam, | |
763 | .get_coalesce = skge_get_coalesce, | |
764 | .set_coalesce = skge_set_coalesce, | |
765 | .get_tso = ethtool_op_get_tso, | |
766 | .set_tso = skge_set_tso, | |
767 | .get_sg = ethtool_op_get_sg, | |
768 | .set_sg = skge_set_sg, | |
769 | .get_tx_csum = ethtool_op_get_tx_csum, | |
770 | .set_tx_csum = skge_set_tx_csum, | |
771 | .get_rx_csum = skge_get_rx_csum, | |
772 | .set_rx_csum = skge_set_rx_csum, | |
773 | .get_strings = skge_get_strings, | |
774 | .phys_id = skge_phys_id, | |
775 | .get_stats_count = skge_get_stats_count, | |
776 | .get_ethtool_stats = skge_get_ethtool_stats, | |
777 | }; | |
778 | ||
779 | /* | |
780 | * Allocate ring elements and chain them together | |
781 | * One-to-one association of board descriptors with ring elements | |
782 | */ | |
783 | static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base) | |
784 | { | |
785 | struct skge_tx_desc *d; | |
786 | struct skge_element *e; | |
787 | int i; | |
788 | ||
789 | ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL); | |
790 | if (!ring->start) | |
791 | return -ENOMEM; | |
792 | ||
793 | for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { | |
794 | e->desc = d; | |
795 | if (i == ring->count - 1) { | |
796 | e->next = ring->start; | |
797 | d->next_offset = base; | |
798 | } else { | |
799 | e->next = e + 1; | |
800 | d->next_offset = base + (i+1) * sizeof(*d); | |
801 | } | |
802 | } | |
803 | ring->to_use = ring->to_clean = ring->start; | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | /* Setup buffer for receiving */ | |
809 | static inline int skge_rx_alloc(struct skge_port *skge, | |
810 | struct skge_element *e) | |
811 | { | |
812 | unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */ | |
813 | struct skge_rx_desc *rd = e->desc; | |
814 | struct sk_buff *skb; | |
815 | u64 map; | |
816 | ||
817 | skb = dev_alloc_skb(bufsize + NET_IP_ALIGN); | |
818 | if (unlikely(!skb)) { | |
819 | printk(KERN_DEBUG PFX "%s: out of memory for receive\n", | |
820 | skge->netdev->name); | |
821 | return -ENOMEM; | |
822 | } | |
823 | ||
824 | skb->dev = skge->netdev; | |
825 | skb_reserve(skb, NET_IP_ALIGN); | |
826 | ||
827 | map = pci_map_single(skge->hw->pdev, skb->data, bufsize, | |
828 | PCI_DMA_FROMDEVICE); | |
829 | ||
830 | rd->dma_lo = map; | |
831 | rd->dma_hi = map >> 32; | |
832 | e->skb = skb; | |
833 | rd->csum1_start = ETH_HLEN; | |
834 | rd->csum2_start = ETH_HLEN; | |
835 | rd->csum1 = 0; | |
836 | rd->csum2 = 0; | |
837 | ||
838 | wmb(); | |
839 | ||
840 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; | |
841 | pci_unmap_addr_set(e, mapaddr, map); | |
842 | pci_unmap_len_set(e, maplen, bufsize); | |
843 | return 0; | |
844 | } | |
845 | ||
846 | /* Free all unused buffers in receive ring, assumes receiver stopped */ | |
847 | static void skge_rx_clean(struct skge_port *skge) | |
848 | { | |
849 | struct skge_hw *hw = skge->hw; | |
850 | struct skge_ring *ring = &skge->rx_ring; | |
851 | struct skge_element *e; | |
852 | ||
853 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { | |
854 | struct skge_rx_desc *rd = e->desc; | |
855 | rd->control = 0; | |
856 | ||
857 | pci_unmap_single(hw->pdev, | |
858 | pci_unmap_addr(e, mapaddr), | |
859 | pci_unmap_len(e, maplen), | |
860 | PCI_DMA_FROMDEVICE); | |
861 | dev_kfree_skb(e->skb); | |
862 | e->skb = NULL; | |
863 | } | |
864 | ring->to_clean = e; | |
865 | } | |
866 | ||
867 | /* Allocate buffers for receive ring | |
868 | * For receive: to_use is refill location | |
869 | * to_clean is next received frame. | |
870 | * | |
871 | * if (to_use == to_clean) | |
872 | * then ring all frames in ring need buffers | |
873 | * if (to_use->next == to_clean) | |
874 | * then ring all frames in ring have buffers | |
875 | */ | |
876 | static int skge_rx_fill(struct skge_port *skge) | |
877 | { | |
878 | struct skge_ring *ring = &skge->rx_ring; | |
879 | struct skge_element *e; | |
880 | int ret = 0; | |
881 | ||
882 | for (e = ring->to_use; e->next != ring->to_clean; e = e->next) { | |
883 | if (skge_rx_alloc(skge, e)) { | |
884 | ret = 1; | |
885 | break; | |
886 | } | |
887 | ||
888 | } | |
889 | ring->to_use = e; | |
890 | ||
891 | return ret; | |
892 | } | |
893 | ||
894 | static void skge_link_up(struct skge_port *skge) | |
895 | { | |
896 | netif_carrier_on(skge->netdev); | |
897 | if (skge->tx_avail > MAX_SKB_FRAGS + 1) | |
898 | netif_wake_queue(skge->netdev); | |
899 | ||
900 | if (netif_msg_link(skge)) | |
901 | printk(KERN_INFO PFX | |
902 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", | |
903 | skge->netdev->name, skge->speed, | |
904 | skge->duplex == DUPLEX_FULL ? "full" : "half", | |
905 | (skge->flow_control == FLOW_MODE_NONE) ? "none" : | |
906 | (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" : | |
907 | (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" : | |
908 | (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" : | |
909 | "unknown"); | |
910 | } | |
911 | ||
912 | static void skge_link_down(struct skge_port *skge) | |
913 | { | |
914 | netif_carrier_off(skge->netdev); | |
915 | netif_stop_queue(skge->netdev); | |
916 | ||
917 | if (netif_msg_link(skge)) | |
918 | printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); | |
919 | } | |
920 | ||
921 | static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
922 | { | |
923 | int i; | |
924 | u16 v; | |
925 | ||
926 | skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); | |
927 | v = skge_xm_read16(hw, port, XM_PHY_DATA); | |
928 | if (hw->phy_type != SK_PHY_XMAC) { | |
929 | for (i = 0; i < PHY_RETRIES; i++) { | |
930 | udelay(1); | |
931 | if (skge_xm_read16(hw, port, XM_MMU_CMD) | |
932 | & XM_MMU_PHY_RDY) | |
933 | goto ready; | |
934 | } | |
935 | ||
936 | printk(KERN_WARNING PFX "%s: phy read timed out\n", | |
937 | hw->dev[port]->name); | |
938 | return 0; | |
939 | ready: | |
940 | v = skge_xm_read16(hw, port, XM_PHY_DATA); | |
941 | } | |
942 | ||
943 | return v; | |
944 | } | |
945 | ||
946 | static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) | |
947 | { | |
948 | int i; | |
949 | ||
950 | skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); | |
951 | for (i = 0; i < PHY_RETRIES; i++) { | |
952 | if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
953 | goto ready; | |
954 | cpu_relax(); | |
955 | } | |
956 | printk(KERN_WARNING PFX "%s: phy write failed to come ready\n", | |
957 | hw->dev[port]->name); | |
958 | ||
959 | ||
960 | ready: | |
961 | skge_xm_write16(hw, port, XM_PHY_DATA, val); | |
962 | for (i = 0; i < PHY_RETRIES; i++) { | |
963 | udelay(1); | |
964 | if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
965 | return; | |
966 | } | |
967 | printk(KERN_WARNING PFX "%s: phy write timed out\n", | |
968 | hw->dev[port]->name); | |
969 | } | |
970 | ||
971 | static void genesis_init(struct skge_hw *hw) | |
972 | { | |
973 | /* set blink source counter */ | |
974 | skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); | |
975 | skge_write8(hw, B2_BSC_CTRL, BSC_START); | |
976 | ||
977 | /* configure mac arbiter */ | |
978 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
979 | ||
980 | /* configure mac arbiter timeout values */ | |
981 | skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); | |
982 | skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); | |
983 | skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); | |
984 | skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); | |
985 | ||
986 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
987 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
988 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
989 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
990 | ||
991 | /* configure packet arbiter timeout */ | |
992 | skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); | |
993 | skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); | |
994 | skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); | |
995 | skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); | |
996 | skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); | |
997 | } | |
998 | ||
999 | static void genesis_reset(struct skge_hw *hw, int port) | |
1000 | { | |
1001 | int i; | |
1002 | u64 zero = 0; | |
1003 | ||
1004 | /* reset the statistics module */ | |
1005 | skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); | |
1006 | skge_xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | |
1007 | skge_xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ | |
1008 | skge_xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ | |
1009 | skge_xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ | |
1010 | ||
1011 | /* disable all PHY IRQs */ | |
1012 | if (hw->phy_type == SK_PHY_BCOM) | |
1013 | skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); | |
1014 | ||
1015 | skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero); | |
1016 | for (i = 0; i < 15; i++) | |
1017 | skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero); | |
1018 | skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero); | |
1019 | } | |
1020 | ||
1021 | ||
1022 | static void genesis_mac_init(struct skge_hw *hw, int port) | |
1023 | { | |
1024 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1025 | int i; | |
1026 | u32 r; | |
1027 | u16 id1; | |
1028 | u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5; | |
1029 | ||
1030 | /* magic workaround patterns for Broadcom */ | |
1031 | static const struct { | |
1032 | u16 reg; | |
1033 | u16 val; | |
1034 | } A1hack[] = { | |
1035 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, | |
1036 | { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, | |
1037 | { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, | |
1038 | { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, | |
1039 | }, C0hack[] = { | |
1040 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, | |
1041 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | |
1042 | }; | |
1043 | ||
1044 | ||
1045 | /* initialize Rx, Tx and Link LED */ | |
1046 | skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON); | |
1047 | skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); | |
1048 | ||
1049 | skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START); | |
1050 | skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START); | |
1051 | ||
1052 | /* Unreset the XMAC. */ | |
1053 | skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); | |
1054 | ||
1055 | /* | |
1056 | * Perform additional initialization for external PHYs, | |
1057 | * namely for the 1000baseTX cards that use the XMAC's | |
1058 | * GMII mode. | |
1059 | */ | |
1060 | spin_lock_bh(&hw->phy_lock); | |
1061 | if (hw->phy_type != SK_PHY_XMAC) { | |
1062 | /* Take PHY out of reset. */ | |
1063 | r = skge_read32(hw, B2_GP_IO); | |
1064 | if (port == 0) | |
1065 | r |= GP_DIR_0|GP_IO_0; | |
1066 | else | |
1067 | r |= GP_DIR_2|GP_IO_2; | |
1068 | ||
1069 | skge_write32(hw, B2_GP_IO, r); | |
1070 | skge_read32(hw, B2_GP_IO); | |
1071 | ||
1072 | /* Enable GMII mode on the XMAC. */ | |
1073 | skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); | |
1074 | ||
1075 | id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1); | |
1076 | ||
1077 | /* Optimize MDIO transfer by suppressing preamble. */ | |
1078 | skge_xm_write16(hw, port, XM_MMU_CMD, | |
1079 | skge_xm_read16(hw, port, XM_MMU_CMD) | |
1080 | | XM_MMU_NO_PRE); | |
1081 | ||
1082 | if (id1 == PHY_BCOM_ID1_C0) { | |
1083 | /* | |
1084 | * Workaround BCOM Errata for the C0 type. | |
1085 | * Write magic patterns to reserved registers. | |
1086 | */ | |
1087 | for (i = 0; i < ARRAY_SIZE(C0hack); i++) | |
1088 | skge_xm_phy_write(hw, port, | |
1089 | C0hack[i].reg, C0hack[i].val); | |
1090 | ||
1091 | } else if (id1 == PHY_BCOM_ID1_A1) { | |
1092 | /* | |
1093 | * Workaround BCOM Errata for the A1 type. | |
1094 | * Write magic patterns to reserved registers. | |
1095 | */ | |
1096 | for (i = 0; i < ARRAY_SIZE(A1hack); i++) | |
1097 | skge_xm_phy_write(hw, port, | |
1098 | A1hack[i].reg, A1hack[i].val); | |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * Workaround BCOM Errata (#10523) for all BCom PHYs. | |
1103 | * Disable Power Management after reset. | |
1104 | */ | |
1105 | r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); | |
1106 | skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM); | |
1107 | } | |
1108 | ||
1109 | /* Dummy read */ | |
1110 | skge_xm_read16(hw, port, XM_ISRC); | |
1111 | ||
1112 | r = skge_xm_read32(hw, port, XM_MODE); | |
1113 | skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA); | |
1114 | ||
1115 | /* We don't need the FCS appended to the packet. */ | |
1116 | r = skge_xm_read16(hw, port, XM_RX_CMD); | |
1117 | skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS); | |
1118 | ||
1119 | /* We want short frames padded to 60 bytes. */ | |
1120 | r = skge_xm_read16(hw, port, XM_TX_CMD); | |
1121 | skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD); | |
1122 | ||
1123 | /* | |
1124 | * Enable the reception of all error frames. This is is | |
1125 | * a necessary evil due to the design of the XMAC. The | |
1126 | * XMAC's receive FIFO is only 8K in size, however jumbo | |
1127 | * frames can be up to 9000 bytes in length. When bad | |
1128 | * frame filtering is enabled, the XMAC's RX FIFO operates | |
1129 | * in 'store and forward' mode. For this to work, the | |
1130 | * entire frame has to fit into the FIFO, but that means | |
1131 | * that jumbo frames larger than 8192 bytes will be | |
1132 | * truncated. Disabling all bad frame filtering causes | |
1133 | * the RX FIFO to operate in streaming mode, in which | |
1134 | * case the XMAC will start transfering frames out of the | |
1135 | * RX FIFO as soon as the FIFO threshold is reached. | |
1136 | */ | |
1137 | r = skge_xm_read32(hw, port, XM_MODE); | |
1138 | skge_xm_write32(hw, port, XM_MODE, | |
1139 | XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT| | |
1140 | XM_MD_RX_ERR|XM_MD_RX_IRLE); | |
1141 | ||
1142 | skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr); | |
1143 | skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr); | |
1144 | ||
1145 | /* | |
1146 | * Bump up the transmit threshold. This helps hold off transmit | |
1147 | * underruns when we're blasting traffic from both ports at once. | |
1148 | */ | |
1149 | skge_xm_write16(hw, port, XM_TX_THR, 512); | |
1150 | ||
1151 | /* Configure MAC arbiter */ | |
1152 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1153 | ||
1154 | /* configure timeout values */ | |
1155 | skge_write8(hw, B3_MA_TOINI_RX1, 72); | |
1156 | skge_write8(hw, B3_MA_TOINI_RX2, 72); | |
1157 | skge_write8(hw, B3_MA_TOINI_TX1, 72); | |
1158 | skge_write8(hw, B3_MA_TOINI_TX2, 72); | |
1159 | ||
1160 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1161 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1162 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1163 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1164 | ||
1165 | /* Configure Rx MAC FIFO */ | |
1166 | skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); | |
1167 | skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); | |
1168 | skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); | |
1169 | ||
1170 | /* Configure Tx MAC FIFO */ | |
1171 | skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); | |
1172 | skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); | |
1173 | skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); | |
1174 | ||
1175 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
1176 | /* Enable frame flushing if jumbo frames used */ | |
1177 | skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); | |
1178 | } else { | |
1179 | /* enable timeout timers if normal frames */ | |
1180 | skge_write16(hw, B3_PA_CTRL, | |
1181 | port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); | |
1182 | } | |
1183 | ||
1184 | ||
1185 | r = skge_xm_read16(hw, port, XM_RX_CMD); | |
1186 | if (hw->dev[port]->mtu > ETH_DATA_LEN) | |
1187 | skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK); | |
1188 | else | |
1189 | skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK)); | |
1190 | ||
1191 | switch (hw->phy_type) { | |
1192 | case SK_PHY_XMAC: | |
1193 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1194 | ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD; | |
1195 | ||
1196 | switch (skge->flow_control) { | |
1197 | case FLOW_MODE_NONE: | |
1198 | ctrl1 |= PHY_X_P_NO_PAUSE; | |
1199 | break; | |
1200 | case FLOW_MODE_LOC_SEND: | |
1201 | ctrl1 |= PHY_X_P_ASYM_MD; | |
1202 | break; | |
1203 | case FLOW_MODE_SYMMETRIC: | |
1204 | ctrl1 |= PHY_X_P_SYM_MD; | |
1205 | break; | |
1206 | case FLOW_MODE_REM_SEND: | |
1207 | ctrl1 |= PHY_X_P_BOTH_MD; | |
1208 | break; | |
1209 | } | |
1210 | ||
1211 | skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1); | |
1212 | ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG; | |
1213 | } else { | |
1214 | ctrl2 = 0; | |
1215 | if (skge->duplex == DUPLEX_FULL) | |
1216 | ctrl2 |= PHY_CT_DUP_MD; | |
1217 | } | |
1218 | ||
1219 | skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2); | |
1220 | break; | |
1221 | ||
1222 | case SK_PHY_BCOM: | |
1223 | ctrl1 = PHY_CT_SP1000; | |
1224 | ctrl2 = 0; | |
1225 | ctrl3 = PHY_SEL_TYPE; | |
1226 | ctrl4 = PHY_B_PEC_EN_LTR; | |
1227 | ctrl5 = PHY_B_AC_TX_TST; | |
1228 | ||
1229 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1230 | /* | |
1231 | * Workaround BCOM Errata #1 for the C5 type. | |
1232 | * 1000Base-T Link Acquisition Failure in Slave Mode | |
1233 | * Set Repeater/DTE bit 10 of the 1000Base-T Control Register | |
1234 | */ | |
1235 | ctrl2 |= PHY_B_1000C_RD; | |
1236 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1237 | ctrl2 |= PHY_B_1000C_AHD; | |
1238 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1239 | ctrl2 |= PHY_B_1000C_AFD; | |
1240 | ||
1241 | /* Set Flow-control capabilities */ | |
1242 | switch (skge->flow_control) { | |
1243 | case FLOW_MODE_NONE: | |
1244 | ctrl3 |= PHY_B_P_NO_PAUSE; | |
1245 | break; | |
1246 | case FLOW_MODE_LOC_SEND: | |
1247 | ctrl3 |= PHY_B_P_ASYM_MD; | |
1248 | break; | |
1249 | case FLOW_MODE_SYMMETRIC: | |
1250 | ctrl3 |= PHY_B_P_SYM_MD; | |
1251 | break; | |
1252 | case FLOW_MODE_REM_SEND: | |
1253 | ctrl3 |= PHY_B_P_BOTH_MD; | |
1254 | break; | |
1255 | } | |
1256 | ||
1257 | /* Restart Auto-negotiation */ | |
1258 | ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1259 | } else { | |
1260 | if (skge->duplex == DUPLEX_FULL) | |
1261 | ctrl1 |= PHY_CT_DUP_MD; | |
1262 | ||
1263 | ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */ | |
1264 | } | |
1265 | ||
1266 | skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2); | |
1267 | skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3); | |
1268 | ||
1269 | if (skge->netdev->mtu > ETH_DATA_LEN) { | |
1270 | ctrl4 |= PHY_B_PEC_HIGH_LA; | |
1271 | ctrl5 |= PHY_B_AC_LONG_PACK; | |
1272 | ||
1273 | skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5); | |
1274 | } | |
1275 | ||
1276 | skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4); | |
1277 | skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1); | |
1278 | break; | |
1279 | } | |
1280 | spin_unlock_bh(&hw->phy_lock); | |
1281 | ||
1282 | /* Clear MIB counters */ | |
1283 | skge_xm_write16(hw, port, XM_STAT_CMD, | |
1284 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1285 | /* Clear two times according to Errata #3 */ | |
1286 | skge_xm_write16(hw, port, XM_STAT_CMD, | |
1287 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1288 | ||
1289 | /* Start polling for link status */ | |
1290 | mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); | |
1291 | } | |
1292 | ||
1293 | static void genesis_stop(struct skge_port *skge) | |
1294 | { | |
1295 | struct skge_hw *hw = skge->hw; | |
1296 | int port = skge->port; | |
1297 | ||
1298 | /* Clear Tx packet arbiter timeout IRQ */ | |
1299 | skge_write16(hw, B3_PA_CTRL, | |
1300 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | |
1301 | ||
1302 | /* | |
1303 | * If the transfer stucks at the MAC the STOP command will not | |
1304 | * terminate if we don't flush the XMAC's transmit FIFO ! | |
1305 | */ | |
1306 | skge_xm_write32(hw, port, XM_MODE, | |
1307 | skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF); | |
1308 | ||
1309 | ||
1310 | /* Reset the MAC */ | |
1311 | skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); | |
1312 | ||
1313 | /* For external PHYs there must be special handling */ | |
1314 | if (hw->phy_type != SK_PHY_XMAC) { | |
1315 | u32 reg = skge_read32(hw, B2_GP_IO); | |
1316 | ||
1317 | if (port == 0) { | |
1318 | reg |= GP_DIR_0; | |
1319 | reg &= ~GP_IO_0; | |
1320 | } else { | |
1321 | reg |= GP_DIR_2; | |
1322 | reg &= ~GP_IO_2; | |
1323 | } | |
1324 | skge_write32(hw, B2_GP_IO, reg); | |
1325 | skge_read32(hw, B2_GP_IO); | |
1326 | } | |
1327 | ||
1328 | skge_xm_write16(hw, port, XM_MMU_CMD, | |
1329 | skge_xm_read16(hw, port, XM_MMU_CMD) | |
1330 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); | |
1331 | ||
1332 | skge_xm_read16(hw, port, XM_MMU_CMD); | |
1333 | } | |
1334 | ||
1335 | ||
1336 | static void genesis_get_stats(struct skge_port *skge, u64 *data) | |
1337 | { | |
1338 | struct skge_hw *hw = skge->hw; | |
1339 | int port = skge->port; | |
1340 | int i; | |
1341 | unsigned long timeout = jiffies + HZ; | |
1342 | ||
1343 | skge_xm_write16(hw, port, | |
1344 | XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); | |
1345 | ||
1346 | /* wait for update to complete */ | |
1347 | while (skge_xm_read16(hw, port, XM_STAT_CMD) | |
1348 | & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { | |
1349 | if (time_after(jiffies, timeout)) | |
1350 | break; | |
1351 | udelay(10); | |
1352 | } | |
1353 | ||
1354 | /* special case for 64 bit octet counter */ | |
1355 | data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32 | |
1356 | | skge_xm_read32(hw, port, XM_TXO_OK_LO); | |
1357 | data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32 | |
1358 | | skge_xm_read32(hw, port, XM_RXO_OK_LO); | |
1359 | ||
1360 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
1361 | data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset); | |
1362 | } | |
1363 | ||
1364 | static void genesis_mac_intr(struct skge_hw *hw, int port) | |
1365 | { | |
1366 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1367 | u16 status = skge_xm_read16(hw, port, XM_ISRC); | |
1368 | ||
1369 | pr_debug("genesis_intr status %x\n", status); | |
1370 | if (hw->phy_type == SK_PHY_XMAC) { | |
1371 | /* LInk down, start polling for state change */ | |
1372 | if (status & XM_IS_INP_ASS) { | |
1373 | skge_xm_write16(hw, port, XM_IMSK, | |
1374 | skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS); | |
1375 | mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); | |
1376 | } | |
1377 | else if (status & XM_IS_AND) | |
1378 | mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); | |
1379 | } | |
1380 | ||
1381 | if (status & XM_IS_TXF_UR) { | |
1382 | skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF); | |
1383 | ++skge->net_stats.tx_fifo_errors; | |
1384 | } | |
1385 | if (status & XM_IS_RXF_OV) { | |
1386 | skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF); | |
1387 | ++skge->net_stats.rx_fifo_errors; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) | |
1392 | { | |
1393 | int i; | |
1394 | ||
1395 | skge_gma_write16(hw, port, GM_SMI_DATA, val); | |
1396 | skge_gma_write16(hw, port, GM_SMI_CTRL, | |
1397 | GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); | |
1398 | for (i = 0; i < PHY_RETRIES; i++) { | |
1399 | udelay(1); | |
1400 | ||
1401 | if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) | |
1402 | break; | |
1403 | } | |
1404 | } | |
1405 | ||
1406 | static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1407 | { | |
1408 | int i; | |
1409 | ||
1410 | skge_gma_write16(hw, port, GM_SMI_CTRL, | |
1411 | GM_SMI_CT_PHY_AD(hw->phy_addr) | |
1412 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); | |
1413 | ||
1414 | for (i = 0; i < PHY_RETRIES; i++) { | |
1415 | udelay(1); | |
1416 | if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) | |
1417 | goto ready; | |
1418 | } | |
1419 | ||
1420 | printk(KERN_WARNING PFX "%s: phy read timeout\n", | |
1421 | hw->dev[port]->name); | |
1422 | return 0; | |
1423 | ready: | |
1424 | return skge_gma_read16(hw, port, GM_SMI_DATA); | |
1425 | } | |
1426 | ||
1427 | static void genesis_link_down(struct skge_port *skge) | |
1428 | { | |
1429 | struct skge_hw *hw = skge->hw; | |
1430 | int port = skge->port; | |
1431 | ||
1432 | pr_debug("genesis_link_down\n"); | |
1433 | ||
1434 | skge_xm_write16(hw, port, XM_MMU_CMD, | |
1435 | skge_xm_read16(hw, port, XM_MMU_CMD) | |
1436 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); | |
1437 | ||
1438 | /* dummy read to ensure writing */ | |
1439 | (void) skge_xm_read16(hw, port, XM_MMU_CMD); | |
1440 | ||
1441 | skge_link_down(skge); | |
1442 | } | |
1443 | ||
1444 | static void genesis_link_up(struct skge_port *skge) | |
1445 | { | |
1446 | struct skge_hw *hw = skge->hw; | |
1447 | int port = skge->port; | |
1448 | u16 cmd; | |
1449 | u32 mode, msk; | |
1450 | ||
1451 | pr_debug("genesis_link_up\n"); | |
1452 | cmd = skge_xm_read16(hw, port, XM_MMU_CMD); | |
1453 | ||
1454 | /* | |
1455 | * enabling pause frame reception is required for 1000BT | |
1456 | * because the XMAC is not reset if the link is going down | |
1457 | */ | |
1458 | if (skge->flow_control == FLOW_MODE_NONE || | |
1459 | skge->flow_control == FLOW_MODE_LOC_SEND) | |
1460 | cmd |= XM_MMU_IGN_PF; | |
1461 | else | |
1462 | /* Enable Pause Frame Reception */ | |
1463 | cmd &= ~XM_MMU_IGN_PF; | |
1464 | ||
1465 | skge_xm_write16(hw, port, XM_MMU_CMD, cmd); | |
1466 | ||
1467 | mode = skge_xm_read32(hw, port, XM_MODE); | |
1468 | if (skge->flow_control == FLOW_MODE_SYMMETRIC || | |
1469 | skge->flow_control == FLOW_MODE_LOC_SEND) { | |
1470 | /* | |
1471 | * Configure Pause Frame Generation | |
1472 | * Use internal and external Pause Frame Generation. | |
1473 | * Sending pause frames is edge triggered. | |
1474 | * Send a Pause frame with the maximum pause time if | |
1475 | * internal oder external FIFO full condition occurs. | |
1476 | * Send a zero pause time frame to re-start transmission. | |
1477 | */ | |
1478 | /* XM_PAUSE_DA = '010000C28001' (default) */ | |
1479 | /* XM_MAC_PTIME = 0xffff (maximum) */ | |
1480 | /* remember this value is defined in big endian (!) */ | |
1481 | skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff); | |
1482 | ||
1483 | mode |= XM_PAUSE_MODE; | |
1484 | skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); | |
1485 | } else { | |
1486 | /* | |
1487 | * disable pause frame generation is required for 1000BT | |
1488 | * because the XMAC is not reset if the link is going down | |
1489 | */ | |
1490 | /* Disable Pause Mode in Mode Register */ | |
1491 | mode &= ~XM_PAUSE_MODE; | |
1492 | ||
1493 | skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); | |
1494 | } | |
1495 | ||
1496 | skge_xm_write32(hw, port, XM_MODE, mode); | |
1497 | ||
1498 | msk = XM_DEF_MSK; | |
1499 | if (hw->phy_type != SK_PHY_XMAC) | |
1500 | msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */ | |
1501 | ||
1502 | skge_xm_write16(hw, port, XM_IMSK, msk); | |
1503 | skge_xm_read16(hw, port, XM_ISRC); | |
1504 | ||
1505 | /* get MMU Command Reg. */ | |
1506 | cmd = skge_xm_read16(hw, port, XM_MMU_CMD); | |
1507 | if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) | |
1508 | cmd |= XM_MMU_GMII_FD; | |
1509 | ||
1510 | if (hw->phy_type == SK_PHY_BCOM) { | |
1511 | /* | |
1512 | * Workaround BCOM Errata (#10523) for all BCom Phys | |
1513 | * Enable Power Management after link up | |
1514 | */ | |
1515 | skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1516 | skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) | |
1517 | & ~PHY_B_AC_DIS_PM); | |
1518 | skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK, | |
1519 | PHY_B_DEF_MSK); | |
1520 | } | |
1521 | ||
1522 | /* enable Rx/Tx */ | |
1523 | skge_xm_write16(hw, port, XM_MMU_CMD, | |
1524 | cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); | |
1525 | skge_link_up(skge); | |
1526 | } | |
1527 | ||
1528 | ||
1529 | static void genesis_bcom_intr(struct skge_port *skge) | |
1530 | { | |
1531 | struct skge_hw *hw = skge->hw; | |
1532 | int port = skge->port; | |
1533 | u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT); | |
1534 | ||
1535 | pr_debug("genesis_bcom intr stat=%x\n", stat); | |
1536 | ||
1537 | /* Workaround BCom Errata: | |
1538 | * enable and disable loopback mode if "NO HCD" occurs. | |
1539 | */ | |
1540 | if (stat & PHY_B_IS_NO_HDCL) { | |
1541 | u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL); | |
1542 | skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
1543 | ctrl | PHY_CT_LOOP); | |
1544 | skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
1545 | ctrl & ~PHY_CT_LOOP); | |
1546 | } | |
1547 | ||
1548 | stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT); | |
1549 | if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) { | |
1550 | u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); | |
1551 | if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev)) | |
1552 | genesis_link_down(skge); | |
1553 | ||
1554 | else if (stat & PHY_B_IS_LST_CHANGE) { | |
1555 | if (aux & PHY_B_AS_AN_C) { | |
1556 | switch (aux & PHY_B_AS_AN_RES_MSK) { | |
1557 | case PHY_B_RES_1000FD: | |
1558 | skge->duplex = DUPLEX_FULL; | |
1559 | break; | |
1560 | case PHY_B_RES_1000HD: | |
1561 | skge->duplex = DUPLEX_HALF; | |
1562 | break; | |
1563 | } | |
1564 | ||
1565 | switch (aux & PHY_B_AS_PAUSE_MSK) { | |
1566 | case PHY_B_AS_PAUSE_MSK: | |
1567 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
1568 | break; | |
1569 | case PHY_B_AS_PRR: | |
1570 | skge->flow_control = FLOW_MODE_REM_SEND; | |
1571 | break; | |
1572 | case PHY_B_AS_PRT: | |
1573 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
1574 | break; | |
1575 | default: | |
1576 | skge->flow_control = FLOW_MODE_NONE; | |
1577 | } | |
1578 | skge->speed = SPEED_1000; | |
1579 | } | |
1580 | genesis_link_up(skge); | |
1581 | } | |
1582 | else | |
1583 | mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); | |
1584 | } | |
1585 | } | |
1586 | ||
1587 | /* Perodic poll of phy status to check for link transistion */ | |
1588 | static void skge_link_timer(unsigned long __arg) | |
1589 | { | |
1590 | struct skge_port *skge = (struct skge_port *) __arg; | |
1591 | struct skge_hw *hw = skge->hw; | |
1592 | int port = skge->port; | |
1593 | ||
1594 | if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev)) | |
1595 | return; | |
1596 | ||
1597 | spin_lock_bh(&hw->phy_lock); | |
1598 | if (hw->phy_type == SK_PHY_BCOM) | |
1599 | genesis_bcom_intr(skge); | |
1600 | else { | |
1601 | int i; | |
1602 | for (i = 0; i < 3; i++) | |
1603 | if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS) | |
1604 | break; | |
1605 | ||
1606 | if (i == 3) | |
1607 | mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ); | |
1608 | else | |
1609 | genesis_link_up(skge); | |
1610 | } | |
1611 | spin_unlock_bh(&hw->phy_lock); | |
1612 | } | |
1613 | ||
1614 | /* Marvell Phy Initailization */ | |
1615 | static void yukon_init(struct skge_hw *hw, int port) | |
1616 | { | |
1617 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1618 | u16 ctrl, ct1000, adv; | |
1619 | u16 ledctrl, ledover; | |
1620 | ||
1621 | pr_debug("yukon_init\n"); | |
1622 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1623 | u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); | |
1624 | ||
1625 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
1626 | PHY_M_EC_MAC_S_MSK); | |
1627 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); | |
1628 | ||
1629 | /* on PHY 88E1111 there is a change for downshift control */ | |
1630 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
1631 | ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA; | |
1632 | else | |
1633 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); | |
1634 | ||
1635 | skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
1636 | } | |
1637 | ||
1638 | ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL); | |
1639 | if (skge->autoneg == AUTONEG_DISABLE) | |
1640 | ctrl &= ~PHY_CT_ANE; | |
1641 | ||
1642 | ctrl |= PHY_CT_RESET; | |
1643 | skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
1644 | ||
1645 | ctrl = 0; | |
1646 | ct1000 = 0; | |
1647 | adv = PHY_SEL_TYPE; | |
1648 | ||
1649 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1650 | if (iscopper(hw)) { | |
1651 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1652 | ct1000 |= PHY_M_1000C_AFD; | |
1653 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1654 | ct1000 |= PHY_M_1000C_AHD; | |
1655 | if (skge->advertising & ADVERTISED_100baseT_Full) | |
1656 | adv |= PHY_M_AN_100_FD; | |
1657 | if (skge->advertising & ADVERTISED_100baseT_Half) | |
1658 | adv |= PHY_M_AN_100_HD; | |
1659 | if (skge->advertising & ADVERTISED_10baseT_Full) | |
1660 | adv |= PHY_M_AN_10_FD; | |
1661 | if (skge->advertising & ADVERTISED_10baseT_Half) | |
1662 | adv |= PHY_M_AN_10_HD; | |
1663 | ||
1664 | /* Set Flow-control capabilities */ | |
1665 | switch (skge->flow_control) { | |
1666 | case FLOW_MODE_NONE: | |
1667 | adv |= PHY_B_P_NO_PAUSE; | |
1668 | break; | |
1669 | case FLOW_MODE_LOC_SEND: | |
1670 | adv |= PHY_B_P_ASYM_MD; | |
1671 | break; | |
1672 | case FLOW_MODE_SYMMETRIC: | |
1673 | adv |= PHY_B_P_SYM_MD; | |
1674 | break; | |
1675 | case FLOW_MODE_REM_SEND: | |
1676 | adv |= PHY_B_P_BOTH_MD; | |
1677 | break; | |
1678 | } | |
1679 | } else { /* special defines for FIBER (88E1011S only) */ | |
1680 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; | |
1681 | ||
1682 | /* Set Flow-control capabilities */ | |
1683 | switch (skge->flow_control) { | |
1684 | case FLOW_MODE_NONE: | |
1685 | adv |= PHY_M_P_NO_PAUSE_X; | |
1686 | break; | |
1687 | case FLOW_MODE_LOC_SEND: | |
1688 | adv |= PHY_M_P_ASYM_MD_X; | |
1689 | break; | |
1690 | case FLOW_MODE_SYMMETRIC: | |
1691 | adv |= PHY_M_P_SYM_MD_X; | |
1692 | break; | |
1693 | case FLOW_MODE_REM_SEND: | |
1694 | adv |= PHY_M_P_BOTH_MD_X; | |
1695 | break; | |
1696 | } | |
1697 | } | |
1698 | /* Restart Auto-negotiation */ | |
1699 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1700 | } else { | |
1701 | /* forced speed/duplex settings */ | |
1702 | ct1000 = PHY_M_1000C_MSE; | |
1703 | ||
1704 | if (skge->duplex == DUPLEX_FULL) | |
1705 | ctrl |= PHY_CT_DUP_MD; | |
1706 | ||
1707 | switch (skge->speed) { | |
1708 | case SPEED_1000: | |
1709 | ctrl |= PHY_CT_SP1000; | |
1710 | break; | |
1711 | case SPEED_100: | |
1712 | ctrl |= PHY_CT_SP100; | |
1713 | break; | |
1714 | } | |
1715 | ||
1716 | ctrl |= PHY_CT_RESET; | |
1717 | } | |
1718 | ||
1719 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
1720 | skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
1721 | ||
1722 | skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
1723 | skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
1724 | ||
1725 | /* Setup Phy LED's */ | |
1726 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
1727 | ledover = 0; | |
1728 | ||
1729 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
1730 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
1731 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
1732 | ||
1733 | skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, | |
1734 | ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR) | |
1735 | ||
1736 | & ~PHY_M_FELP_LED1_MSK) | |
1737 | | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL))); | |
1738 | } else { | |
1739 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
1740 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
1741 | ||
1742 | /* turn off the Rx LED (LED_RX) */ | |
1743 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
1744 | } | |
1745 | ||
1746 | /* disable blink mode (LED_DUPLEX) on collisions */ | |
1747 | ctrl |= PHY_M_LEDC_DP_CTRL; | |
1748 | skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
1749 | ||
1750 | if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) { | |
1751 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
1752 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
1753 | } | |
1754 | ||
1755 | if (ledover) | |
1756 | skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
1757 | ||
1758 | /* Enable phy interrupt on autonegotiation complete (or link up) */ | |
1759 | if (skge->autoneg == AUTONEG_ENABLE) | |
1760 | skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
1761 | else | |
1762 | skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1763 | } | |
1764 | ||
1765 | static void yukon_reset(struct skge_hw *hw, int port) | |
1766 | { | |
1767 | skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ | |
1768 | skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ | |
1769 | skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
1770 | skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
1771 | skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
1772 | ||
1773 | skge_gma_write16(hw, port, GM_RX_CTRL, | |
1774 | skge_gma_read16(hw, port, GM_RX_CTRL) | |
1775 | | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); | |
1776 | } | |
1777 | ||
1778 | static void yukon_mac_init(struct skge_hw *hw, int port) | |
1779 | { | |
1780 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1781 | int i; | |
1782 | u32 reg; | |
1783 | const u8 *addr = hw->dev[port]->dev_addr; | |
1784 | ||
1785 | /* WA code for COMA mode -- set PHY reset */ | |
1786 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
1787 | chip_rev(hw) == CHIP_REV_YU_LITE_A3) | |
1788 | skge_write32(hw, B2_GP_IO, | |
1789 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); | |
1790 | ||
1791 | /* hard reset */ | |
1792 | skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1793 | skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET); | |
1794 | ||
1795 | /* WA code for COMA mode -- clear PHY reset */ | |
1796 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
1797 | chip_rev(hw) == CHIP_REV_YU_LITE_A3) | |
1798 | skge_write32(hw, B2_GP_IO, | |
1799 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9) | |
1800 | & ~GP_IO_9); | |
1801 | ||
1802 | /* Set hardware config mode */ | |
1803 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | |
1804 | GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; | |
1805 | reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; | |
1806 | ||
1807 | /* Clear GMC reset */ | |
1808 | skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET); | |
1809 | skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); | |
1810 | skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); | |
1811 | if (skge->autoneg == AUTONEG_DISABLE) { | |
1812 | reg = GM_GPCR_AU_ALL_DIS; | |
1813 | skge_gma_write16(hw, port, GM_GP_CTRL, | |
1814 | skge_gma_read16(hw, port, GM_GP_CTRL) | reg); | |
1815 | ||
1816 | switch (skge->speed) { | |
1817 | case SPEED_1000: | |
1818 | reg |= GM_GPCR_SPEED_1000; | |
1819 | /* fallthru */ | |
1820 | case SPEED_100: | |
1821 | reg |= GM_GPCR_SPEED_100; | |
1822 | } | |
1823 | ||
1824 | if (skge->duplex == DUPLEX_FULL) | |
1825 | reg |= GM_GPCR_DUP_FULL; | |
1826 | } else | |
1827 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
1828 | switch (skge->flow_control) { | |
1829 | case FLOW_MODE_NONE: | |
1830 | skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1831 | reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
1832 | break; | |
1833 | case FLOW_MODE_LOC_SEND: | |
1834 | /* disable Rx flow-control */ | |
1835 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
1836 | } | |
1837 | ||
1838 | skge_gma_write16(hw, port, GM_GP_CTRL, reg); | |
1839 | skge_read16(hw, GMAC_IRQ_SRC); | |
1840 | ||
1841 | spin_lock_bh(&hw->phy_lock); | |
1842 | yukon_init(hw, port); | |
1843 | spin_unlock_bh(&hw->phy_lock); | |
1844 | ||
1845 | /* MIB clear */ | |
1846 | reg = skge_gma_read16(hw, port, GM_PHY_ADDR); | |
1847 | skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
1848 | ||
1849 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
1850 | skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); | |
1851 | skge_gma_write16(hw, port, GM_PHY_ADDR, reg); | |
1852 | ||
1853 | /* transmit control */ | |
1854 | skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
1855 | ||
1856 | /* receive control reg: unicast + multicast + no FCS */ | |
1857 | skge_gma_write16(hw, port, GM_RX_CTRL, | |
1858 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); | |
1859 | ||
1860 | /* transmit flow control */ | |
1861 | skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
1862 | ||
1863 | /* transmit parameter */ | |
1864 | skge_gma_write16(hw, port, GM_TX_PARAM, | |
1865 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
1866 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
1867 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); | |
1868 | ||
1869 | /* serial mode register */ | |
1870 | reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1871 | if (hw->dev[port]->mtu > 1500) | |
1872 | reg |= GM_SMOD_JUMBO_ENA; | |
1873 | ||
1874 | skge_gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
1875 | ||
1876 | /* physical address: used for pause frames */ | |
1877 | skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
1878 | /* virtual address for data */ | |
1879 | skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
1880 | ||
1881 | /* enable interrupt mask for counter overflows */ | |
1882 | skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0); | |
1883 | skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
1884 | skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
1885 | ||
1886 | /* Initialize Mac Fifo */ | |
1887 | ||
1888 | /* Configure Rx MAC FIFO */ | |
1889 | skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); | |
1890 | reg = GMF_OPER_ON | GMF_RX_F_FL_ON; | |
1891 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
1892 | chip_rev(hw) == CHIP_REV_YU_LITE_A3) | |
1893 | reg &= ~GMF_RX_F_FL_ON; | |
1894 | skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
1895 | skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg); | |
1896 | skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
1897 | ||
1898 | /* Configure Tx MAC FIFO */ | |
1899 | skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
1900 | skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
1901 | } | |
1902 | ||
1903 | static void yukon_stop(struct skge_port *skge) | |
1904 | { | |
1905 | struct skge_hw *hw = skge->hw; | |
1906 | int port = skge->port; | |
1907 | ||
1908 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
1909 | chip_rev(hw) == CHIP_REV_YU_LITE_A3) { | |
1910 | skge_write32(hw, B2_GP_IO, | |
1911 | skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); | |
1912 | } | |
1913 | ||
1914 | skge_gma_write16(hw, port, GM_GP_CTRL, | |
1915 | skge_gma_read16(hw, port, GM_GP_CTRL) | |
1916 | & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA)); | |
1917 | skge_gma_read16(hw, port, GM_GP_CTRL); | |
1918 | ||
1919 | /* set GPHY Control reset */ | |
1920 | skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET); | |
1921 | skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET); | |
1922 | } | |
1923 | ||
1924 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | |
1925 | { | |
1926 | struct skge_hw *hw = skge->hw; | |
1927 | int port = skge->port; | |
1928 | int i; | |
1929 | ||
1930 | data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
1931 | | skge_gma_read32(hw, port, GM_TXO_OK_LO); | |
1932 | data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32 | |
1933 | | skge_gma_read32(hw, port, GM_RXO_OK_LO); | |
1934 | ||
1935 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
1936 | data[i] = skge_gma_read32(hw, port, | |
1937 | skge_stats[i].gma_offset); | |
1938 | } | |
1939 | ||
1940 | static void yukon_mac_intr(struct skge_hw *hw, int port) | |
1941 | { | |
1942 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1943 | u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC)); | |
1944 | ||
1945 | pr_debug("yukon_intr status %x\n", status); | |
1946 | if (status & GM_IS_RX_FF_OR) { | |
1947 | ++skge->net_stats.rx_fifo_errors; | |
1948 | skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO); | |
1949 | } | |
1950 | if (status & GM_IS_TX_FF_UR) { | |
1951 | ++skge->net_stats.tx_fifo_errors; | |
1952 | skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU); | |
1953 | } | |
1954 | ||
1955 | } | |
1956 | ||
1957 | static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |
1958 | { | |
1959 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1960 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1961 | ||
1962 | switch(aux & PHY_M_PS_SPEED_MSK) { | |
1963 | case PHY_M_PS_SPEED_1000: | |
1964 | return SPEED_1000; | |
1965 | case PHY_M_PS_SPEED_100: | |
1966 | return SPEED_100; | |
1967 | default: | |
1968 | return SPEED_10; | |
1969 | } | |
1970 | } | |
1971 | ||
1972 | static void yukon_link_up(struct skge_port *skge) | |
1973 | { | |
1974 | struct skge_hw *hw = skge->hw; | |
1975 | int port = skge->port; | |
1976 | u16 reg; | |
1977 | ||
1978 | pr_debug("yukon_link_up\n"); | |
1979 | ||
1980 | /* Enable Transmit FIFO Underrun */ | |
1981 | skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK); | |
1982 | ||
1983 | reg = skge_gma_read16(hw, port, GM_GP_CTRL); | |
1984 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) | |
1985 | reg |= GM_GPCR_DUP_FULL; | |
1986 | ||
1987 | /* enable Rx/Tx */ | |
1988 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1989 | skge_gma_write16(hw, port, GM_GP_CTRL, reg); | |
1990 | ||
1991 | skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1992 | skge_link_up(skge); | |
1993 | } | |
1994 | ||
1995 | static void yukon_link_down(struct skge_port *skge) | |
1996 | { | |
1997 | struct skge_hw *hw = skge->hw; | |
1998 | int port = skge->port; | |
1999 | ||
2000 | pr_debug("yukon_link_down\n"); | |
2001 | skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
2002 | skge_gm_phy_write(hw, port, GM_GP_CTRL, | |
2003 | skge_gm_phy_read(hw, port, GM_GP_CTRL) | |
2004 | & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); | |
2005 | ||
2006 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
2007 | skge->flow_control == FLOW_MODE_REM_SEND) { | |
2008 | /* restore Asymmetric Pause bit */ | |
2009 | skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
2010 | skge_gm_phy_read(hw, port, | |
2011 | PHY_MARV_AUNE_ADV) | |
2012 | | PHY_M_AN_ASP); | |
2013 | ||
2014 | } | |
2015 | ||
2016 | yukon_reset(hw, port); | |
2017 | skge_link_down(skge); | |
2018 | ||
2019 | yukon_init(hw, port); | |
2020 | } | |
2021 | ||
2022 | static void yukon_phy_intr(struct skge_port *skge) | |
2023 | { | |
2024 | struct skge_hw *hw = skge->hw; | |
2025 | int port = skge->port; | |
2026 | const char *reason = NULL; | |
2027 | u16 istatus, phystat; | |
2028 | ||
2029 | istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
2030 | phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
2031 | pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat); | |
2032 | ||
2033 | if (istatus & PHY_M_IS_AN_COMPL) { | |
2034 | if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP) | |
2035 | & PHY_M_AN_RF) { | |
2036 | reason = "remote fault"; | |
2037 | goto failed; | |
2038 | } | |
2039 | ||
2040 | if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC) | |
2041 | && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT) | |
2042 | & PHY_B_1000S_MSF)) { | |
2043 | reason = "master/slave fault"; | |
2044 | goto failed; | |
2045 | } | |
2046 | ||
2047 | if (!(phystat & PHY_M_PS_SPDUP_RES)) { | |
2048 | reason = "speed/duplex"; | |
2049 | goto failed; | |
2050 | } | |
2051 | ||
2052 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) | |
2053 | ? DUPLEX_FULL : DUPLEX_HALF; | |
2054 | skge->speed = yukon_speed(hw, phystat); | |
2055 | ||
2056 | /* Tx & Rx Pause Enabled bits are at 9..8 */ | |
2057 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
2058 | phystat >>= 6; | |
2059 | ||
2060 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ | |
2061 | switch (phystat & PHY_M_PS_PAUSE_MSK) { | |
2062 | case PHY_M_PS_PAUSE_MSK: | |
2063 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
2064 | break; | |
2065 | case PHY_M_PS_RX_P_EN: | |
2066 | skge->flow_control = FLOW_MODE_REM_SEND; | |
2067 | break; | |
2068 | case PHY_M_PS_TX_P_EN: | |
2069 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
2070 | break; | |
2071 | default: | |
2072 | skge->flow_control = FLOW_MODE_NONE; | |
2073 | } | |
2074 | ||
2075 | if (skge->flow_control == FLOW_MODE_NONE || | |
2076 | (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) | |
2077 | skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
2078 | else | |
2079 | skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
2080 | yukon_link_up(skge); | |
2081 | return; | |
2082 | } | |
2083 | ||
2084 | if (istatus & PHY_M_IS_LSP_CHANGE) | |
2085 | skge->speed = yukon_speed(hw, phystat); | |
2086 | ||
2087 | if (istatus & PHY_M_IS_DUP_CHANGE) | |
2088 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
2089 | if (istatus & PHY_M_IS_LST_CHANGE) { | |
2090 | if (phystat & PHY_M_PS_LINK_UP) | |
2091 | yukon_link_up(skge); | |
2092 | else | |
2093 | yukon_link_down(skge); | |
2094 | } | |
2095 | return; | |
2096 | failed: | |
2097 | printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n", | |
2098 | skge->netdev->name, reason); | |
2099 | ||
2100 | /* XXX restart autonegotiation? */ | |
2101 | } | |
2102 | ||
2103 | static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) | |
2104 | { | |
2105 | u32 end; | |
2106 | ||
2107 | start /= 8; | |
2108 | len /= 8; | |
2109 | end = start + len - 1; | |
2110 | ||
2111 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); | |
2112 | skge_write32(hw, RB_ADDR(q, RB_START), start); | |
2113 | skge_write32(hw, RB_ADDR(q, RB_WP), start); | |
2114 | skge_write32(hw, RB_ADDR(q, RB_RP), start); | |
2115 | skge_write32(hw, RB_ADDR(q, RB_END), end); | |
2116 | ||
2117 | if (q == Q_R1 || q == Q_R2) { | |
2118 | /* Set thresholds on receive queue's */ | |
2119 | skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), | |
2120 | start + (2*len)/3); | |
2121 | skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), | |
2122 | start + (len/3)); | |
2123 | } else { | |
2124 | /* Enable store & forward on Tx queue's because | |
2125 | * Tx FIFO is only 4K on Genesis and 1K on Yukon | |
2126 | */ | |
2127 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
2128 | } | |
2129 | ||
2130 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
2131 | } | |
2132 | ||
2133 | /* Setup Bus Memory Interface */ | |
2134 | static void skge_qset(struct skge_port *skge, u16 q, | |
2135 | const struct skge_element *e) | |
2136 | { | |
2137 | struct skge_hw *hw = skge->hw; | |
2138 | u32 watermark = 0x600; | |
2139 | u64 base = skge->dma + (e->desc - skge->mem); | |
2140 | ||
2141 | /* optimization to reduce window on 32bit/33mhz */ | |
2142 | if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) | |
2143 | watermark /= 2; | |
2144 | ||
2145 | skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); | |
2146 | skge_write32(hw, Q_ADDR(q, Q_F), watermark); | |
2147 | skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); | |
2148 | skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); | |
2149 | } | |
2150 | ||
2151 | static int skge_up(struct net_device *dev) | |
2152 | { | |
2153 | struct skge_port *skge = netdev_priv(dev); | |
2154 | struct skge_hw *hw = skge->hw; | |
2155 | int port = skge->port; | |
2156 | u32 chunk, ram_addr; | |
2157 | size_t rx_size, tx_size; | |
2158 | int err; | |
2159 | ||
2160 | if (netif_msg_ifup(skge)) | |
2161 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
2162 | ||
2163 | rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); | |
2164 | tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); | |
2165 | skge->mem_size = tx_size + rx_size; | |
2166 | skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); | |
2167 | if (!skge->mem) | |
2168 | return -ENOMEM; | |
2169 | ||
2170 | memset(skge->mem, 0, skge->mem_size); | |
2171 | ||
2172 | if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma))) | |
2173 | goto free_pci_mem; | |
2174 | ||
2175 | if (skge_rx_fill(skge)) | |
2176 | goto free_rx_ring; | |
2177 | ||
2178 | if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, | |
2179 | skge->dma + rx_size))) | |
2180 | goto free_rx_ring; | |
2181 | ||
2182 | skge->tx_avail = skge->tx_ring.count - 1; | |
2183 | ||
2184 | /* Initialze MAC */ | |
2185 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2186 | genesis_mac_init(hw, port); | |
2187 | else | |
2188 | yukon_mac_init(hw, port); | |
2189 | ||
2190 | /* Configure RAMbuffers */ | |
2191 | chunk = hw->ram_size / (isdualport(hw) ? 4 : 2); | |
2192 | ram_addr = hw->ram_offset + 2 * chunk * port; | |
2193 | ||
2194 | skge_ramset(hw, rxqaddr[port], ram_addr, chunk); | |
2195 | skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); | |
2196 | ||
2197 | BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); | |
2198 | skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); | |
2199 | skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); | |
2200 | ||
2201 | /* Start receiver BMU */ | |
2202 | wmb(); | |
2203 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | |
2204 | ||
2205 | pr_debug("skge_up completed\n"); | |
2206 | return 0; | |
2207 | ||
2208 | free_rx_ring: | |
2209 | skge_rx_clean(skge); | |
2210 | kfree(skge->rx_ring.start); | |
2211 | free_pci_mem: | |
2212 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
2213 | ||
2214 | return err; | |
2215 | } | |
2216 | ||
2217 | static int skge_down(struct net_device *dev) | |
2218 | { | |
2219 | struct skge_port *skge = netdev_priv(dev); | |
2220 | struct skge_hw *hw = skge->hw; | |
2221 | int port = skge->port; | |
2222 | ||
2223 | if (netif_msg_ifdown(skge)) | |
2224 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
2225 | ||
2226 | netif_stop_queue(dev); | |
2227 | ||
2228 | del_timer_sync(&skge->led_blink); | |
2229 | del_timer_sync(&skge->link_check); | |
2230 | ||
2231 | /* Stop transmitter */ | |
2232 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | |
2233 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
2234 | RB_RST_SET|RB_DIS_OP_MD); | |
2235 | ||
2236 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2237 | genesis_stop(skge); | |
2238 | else | |
2239 | yukon_stop(skge); | |
2240 | ||
2241 | /* Disable Force Sync bit and Enable Alloc bit */ | |
2242 | skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL), | |
2243 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
2244 | ||
2245 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
2246 | skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L); | |
2247 | skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L); | |
2248 | ||
2249 | /* Reset PCI FIFO */ | |
2250 | skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); | |
2251 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2252 | ||
2253 | /* Reset the RAM Buffer async Tx queue */ | |
2254 | skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); | |
2255 | /* stop receiver */ | |
2256 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); | |
2257 | skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), | |
2258 | RB_RST_SET|RB_DIS_OP_MD); | |
2259 | skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); | |
2260 | ||
2261 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
2262 | skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET); | |
2263 | skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET); | |
2264 | skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP); | |
2265 | skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP); | |
2266 | } else { | |
2267 | skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
2268 | skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
2269 | } | |
2270 | ||
2271 | /* turn off led's */ | |
2272 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
2273 | ||
2274 | skge_tx_clean(skge); | |
2275 | skge_rx_clean(skge); | |
2276 | ||
2277 | kfree(skge->rx_ring.start); | |
2278 | kfree(skge->tx_ring.start); | |
2279 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |
2284 | { | |
2285 | struct skge_port *skge = netdev_priv(dev); | |
2286 | struct skge_hw *hw = skge->hw; | |
2287 | struct skge_ring *ring = &skge->tx_ring; | |
2288 | struct skge_element *e; | |
2289 | struct skge_tx_desc *td; | |
2290 | int i; | |
2291 | u32 control, len; | |
2292 | u64 map; | |
2293 | unsigned long flags; | |
2294 | ||
2295 | skb = skb_padto(skb, ETH_ZLEN); | |
2296 | if (!skb) | |
2297 | return NETDEV_TX_OK; | |
2298 | ||
2299 | local_irq_save(flags); | |
2300 | if (!spin_trylock(&skge->tx_lock)) { | |
2301 | /* Collision - tell upper layer to requeue */ | |
2302 | local_irq_restore(flags); | |
2303 | return NETDEV_TX_LOCKED; | |
2304 | } | |
2305 | ||
2306 | if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) { | |
2307 | netif_stop_queue(dev); | |
2308 | spin_unlock_irqrestore(&skge->tx_lock, flags); | |
2309 | ||
2310 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
2311 | dev->name); | |
2312 | return NETDEV_TX_BUSY; | |
2313 | } | |
2314 | ||
2315 | e = ring->to_use; | |
2316 | td = e->desc; | |
2317 | e->skb = skb; | |
2318 | len = skb_headlen(skb); | |
2319 | map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2320 | pci_unmap_addr_set(e, mapaddr, map); | |
2321 | pci_unmap_len_set(e, maplen, len); | |
2322 | ||
2323 | td->dma_lo = map; | |
2324 | td->dma_hi = map >> 32; | |
2325 | ||
2326 | if (skb->ip_summed == CHECKSUM_HW) { | |
2327 | const struct iphdr *ip | |
2328 | = (const struct iphdr *) (skb->data + ETH_HLEN); | |
2329 | int offset = skb->h.raw - skb->data; | |
2330 | ||
2331 | /* This seems backwards, but it is what the sk98lin | |
2332 | * does. Looks like hardware is wrong? | |
2333 | */ | |
2334 | if (ip->protocol == IPPROTO_UDP | |
2335 | && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON) | |
2336 | control = BMU_TCP_CHECK; | |
2337 | else | |
2338 | control = BMU_UDP_CHECK; | |
2339 | ||
2340 | td->csum_offs = 0; | |
2341 | td->csum_start = offset; | |
2342 | td->csum_write = offset + skb->csum; | |
2343 | } else | |
2344 | control = BMU_CHECK; | |
2345 | ||
2346 | if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ | |
2347 | control |= BMU_EOF| BMU_IRQ_EOF; | |
2348 | else { | |
2349 | struct skge_tx_desc *tf = td; | |
2350 | ||
2351 | control |= BMU_STFWD; | |
2352 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2353 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2354 | ||
2355 | map = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
2356 | frag->size, PCI_DMA_TODEVICE); | |
2357 | ||
2358 | e = e->next; | |
2359 | e->skb = NULL; | |
2360 | tf = e->desc; | |
2361 | tf->dma_lo = map; | |
2362 | tf->dma_hi = (u64) map >> 32; | |
2363 | pci_unmap_addr_set(e, mapaddr, map); | |
2364 | pci_unmap_len_set(e, maplen, frag->size); | |
2365 | ||
2366 | tf->control = BMU_OWN | BMU_SW | control | frag->size; | |
2367 | } | |
2368 | tf->control |= BMU_EOF | BMU_IRQ_EOF; | |
2369 | } | |
2370 | /* Make sure all the descriptors written */ | |
2371 | wmb(); | |
2372 | td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; | |
2373 | wmb(); | |
2374 | ||
2375 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); | |
2376 | ||
2377 | if (netif_msg_tx_queued(skge)) | |
2378 | printk(KERN_DEBUG "%s: tx queued, slot %d, len %d\n", | |
2379 | dev->name, e - ring->start, skb->len); | |
2380 | ||
2381 | ring->to_use = e->next; | |
2382 | skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1; | |
2383 | if (skge->tx_avail <= MAX_SKB_FRAGS + 1) { | |
2384 | pr_debug("%s: transmit queue full\n", dev->name); | |
2385 | netif_stop_queue(dev); | |
2386 | } | |
2387 | ||
2388 | dev->trans_start = jiffies; | |
2389 | spin_unlock_irqrestore(&skge->tx_lock, flags); | |
2390 | ||
2391 | return NETDEV_TX_OK; | |
2392 | } | |
2393 | ||
2394 | static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e) | |
2395 | { | |
2396 | if (e->skb) { | |
2397 | pci_unmap_single(hw->pdev, | |
2398 | pci_unmap_addr(e, mapaddr), | |
2399 | pci_unmap_len(e, maplen), | |
2400 | PCI_DMA_TODEVICE); | |
2401 | dev_kfree_skb_any(e->skb); | |
2402 | e->skb = NULL; | |
2403 | } else { | |
2404 | pci_unmap_page(hw->pdev, | |
2405 | pci_unmap_addr(e, mapaddr), | |
2406 | pci_unmap_len(e, maplen), | |
2407 | PCI_DMA_TODEVICE); | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | static void skge_tx_clean(struct skge_port *skge) | |
2412 | { | |
2413 | struct skge_ring *ring = &skge->tx_ring; | |
2414 | struct skge_element *e; | |
2415 | unsigned long flags; | |
2416 | ||
2417 | spin_lock_irqsave(&skge->tx_lock, flags); | |
2418 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { | |
2419 | ++skge->tx_avail; | |
2420 | skge_tx_free(skge->hw, e); | |
2421 | } | |
2422 | ring->to_clean = e; | |
2423 | spin_unlock_irqrestore(&skge->tx_lock, flags); | |
2424 | } | |
2425 | ||
2426 | static void skge_tx_timeout(struct net_device *dev) | |
2427 | { | |
2428 | struct skge_port *skge = netdev_priv(dev); | |
2429 | ||
2430 | if (netif_msg_timer(skge)) | |
2431 | printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); | |
2432 | ||
2433 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); | |
2434 | skge_tx_clean(skge); | |
2435 | } | |
2436 | ||
2437 | static int skge_change_mtu(struct net_device *dev, int new_mtu) | |
2438 | { | |
2439 | int err = 0; | |
2440 | ||
2441 | if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
2442 | return -EINVAL; | |
2443 | ||
2444 | dev->mtu = new_mtu; | |
2445 | ||
2446 | if (netif_running(dev)) { | |
2447 | skge_down(dev); | |
2448 | skge_up(dev); | |
2449 | } | |
2450 | ||
2451 | return err; | |
2452 | } | |
2453 | ||
2454 | static void genesis_set_multicast(struct net_device *dev) | |
2455 | { | |
2456 | struct skge_port *skge = netdev_priv(dev); | |
2457 | struct skge_hw *hw = skge->hw; | |
2458 | int port = skge->port; | |
2459 | int i, count = dev->mc_count; | |
2460 | struct dev_mc_list *list = dev->mc_list; | |
2461 | u32 mode; | |
2462 | u8 filter[8]; | |
2463 | ||
2464 | mode = skge_xm_read32(hw, port, XM_MODE); | |
2465 | mode |= XM_MD_ENA_HASH; | |
2466 | if (dev->flags & IFF_PROMISC) | |
2467 | mode |= XM_MD_ENA_PROM; | |
2468 | else | |
2469 | mode &= ~XM_MD_ENA_PROM; | |
2470 | ||
2471 | if (dev->flags & IFF_ALLMULTI) | |
2472 | memset(filter, 0xff, sizeof(filter)); | |
2473 | else { | |
2474 | memset(filter, 0, sizeof(filter)); | |
2475 | for(i = 0; list && i < count; i++, list = list->next) { | |
2476 | u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN); | |
2477 | u8 bit = 63 - (crc & 63); | |
2478 | ||
2479 | filter[bit/8] |= 1 << (bit%8); | |
2480 | } | |
2481 | } | |
2482 | ||
2483 | skge_xm_outhash(hw, port, XM_HSM, filter); | |
2484 | ||
2485 | skge_xm_write32(hw, port, XM_MODE, mode); | |
2486 | } | |
2487 | ||
2488 | static void yukon_set_multicast(struct net_device *dev) | |
2489 | { | |
2490 | struct skge_port *skge = netdev_priv(dev); | |
2491 | struct skge_hw *hw = skge->hw; | |
2492 | int port = skge->port; | |
2493 | struct dev_mc_list *list = dev->mc_list; | |
2494 | u16 reg; | |
2495 | u8 filter[8]; | |
2496 | ||
2497 | memset(filter, 0, sizeof(filter)); | |
2498 | ||
2499 | reg = skge_gma_read16(hw, port, GM_RX_CTRL); | |
2500 | reg |= GM_RXCR_UCF_ENA; | |
2501 | ||
2502 | if (dev->flags & IFF_PROMISC) /* promiscious */ | |
2503 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); | |
2504 | else if (dev->flags & IFF_ALLMULTI) /* all multicast */ | |
2505 | memset(filter, 0xff, sizeof(filter)); | |
2506 | else if (dev->mc_count == 0) /* no multicast */ | |
2507 | reg &= ~GM_RXCR_MCF_ENA; | |
2508 | else { | |
2509 | int i; | |
2510 | reg |= GM_RXCR_MCF_ENA; | |
2511 | ||
2512 | for(i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2513 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
2514 | filter[bit/8] |= 1 << (bit%8); | |
2515 | } | |
2516 | } | |
2517 | ||
2518 | ||
2519 | skge_gma_write16(hw, port, GM_MC_ADDR_H1, | |
2520 | (u16)filter[0] | ((u16)filter[1] << 8)); | |
2521 | skge_gma_write16(hw, port, GM_MC_ADDR_H2, | |
2522 | (u16)filter[2] | ((u16)filter[3] << 8)); | |
2523 | skge_gma_write16(hw, port, GM_MC_ADDR_H3, | |
2524 | (u16)filter[4] | ((u16)filter[5] << 8)); | |
2525 | skge_gma_write16(hw, port, GM_MC_ADDR_H4, | |
2526 | (u16)filter[6] | ((u16)filter[7] << 8)); | |
2527 | ||
2528 | skge_gma_write16(hw, port, GM_RX_CTRL, reg); | |
2529 | } | |
2530 | ||
2531 | static inline int bad_phy_status(const struct skge_hw *hw, u32 status) | |
2532 | { | |
2533 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2534 | return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; | |
2535 | else | |
2536 | return (status & GMR_FS_ANY_ERR) || | |
2537 | (status & GMR_FS_RX_OK) == 0; | |
2538 | } | |
2539 | ||
2540 | static void skge_rx_error(struct skge_port *skge, int slot, | |
2541 | u32 control, u32 status) | |
2542 | { | |
2543 | if (netif_msg_rx_err(skge)) | |
2544 | printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n", | |
2545 | skge->netdev->name, slot, control, status); | |
2546 | ||
2547 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF) | |
2548 | || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN) | |
2549 | skge->net_stats.rx_length_errors++; | |
2550 | else { | |
2551 | if (skge->hw->chip_id == CHIP_ID_GENESIS) { | |
2552 | if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) | |
2553 | skge->net_stats.rx_length_errors++; | |
2554 | if (status & XMR_FS_FRA_ERR) | |
2555 | skge->net_stats.rx_frame_errors++; | |
2556 | if (status & XMR_FS_FCS_ERR) | |
2557 | skge->net_stats.rx_crc_errors++; | |
2558 | } else { | |
2559 | if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) | |
2560 | skge->net_stats.rx_length_errors++; | |
2561 | if (status & GMR_FS_FRAGMENT) | |
2562 | skge->net_stats.rx_frame_errors++; | |
2563 | if (status & GMR_FS_CRC_ERR) | |
2564 | skge->net_stats.rx_crc_errors++; | |
2565 | } | |
2566 | } | |
2567 | } | |
2568 | ||
2569 | static int skge_poll(struct net_device *dev, int *budget) | |
2570 | { | |
2571 | struct skge_port *skge = netdev_priv(dev); | |
2572 | struct skge_hw *hw = skge->hw; | |
2573 | struct skge_ring *ring = &skge->rx_ring; | |
2574 | struct skge_element *e; | |
2575 | unsigned int to_do = min(dev->quota, *budget); | |
2576 | unsigned int work_done = 0; | |
2577 | int done; | |
2578 | static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 }; | |
2579 | ||
2580 | for (e = ring->to_clean; e != ring->to_use && work_done < to_do; | |
2581 | e = e->next) { | |
2582 | struct skge_rx_desc *rd = e->desc; | |
2583 | struct sk_buff *skb = e->skb; | |
2584 | u32 control, len, status; | |
2585 | ||
2586 | rmb(); | |
2587 | control = rd->control; | |
2588 | if (control & BMU_OWN) | |
2589 | break; | |
2590 | ||
2591 | len = control & BMU_BBC; | |
2592 | e->skb = NULL; | |
2593 | ||
2594 | pci_unmap_single(hw->pdev, | |
2595 | pci_unmap_addr(e, mapaddr), | |
2596 | pci_unmap_len(e, maplen), | |
2597 | PCI_DMA_FROMDEVICE); | |
2598 | ||
2599 | status = rd->status; | |
2600 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF) | |
2601 | || len > dev->mtu + VLAN_ETH_HLEN | |
2602 | || bad_phy_status(hw, status)) { | |
2603 | skge_rx_error(skge, e - ring->start, control, status); | |
2604 | dev_kfree_skb(skb); | |
2605 | continue; | |
2606 | } | |
2607 | ||
2608 | if (netif_msg_rx_status(skge)) | |
2609 | printk(KERN_DEBUG PFX "%s: rx slot %d status 0x%x len %d\n", | |
2610 | dev->name, e - ring->start, rd->status, len); | |
2611 | ||
2612 | skb_put(skb, len); | |
2613 | skb->protocol = eth_type_trans(skb, dev); | |
2614 | ||
2615 | if (skge->rx_csum) { | |
2616 | skb->csum = le16_to_cpu(rd->csum2); | |
2617 | skb->ip_summed = CHECKSUM_HW; | |
2618 | } | |
2619 | ||
2620 | dev->last_rx = jiffies; | |
2621 | netif_receive_skb(skb); | |
2622 | ||
2623 | ++work_done; | |
2624 | } | |
2625 | ring->to_clean = e; | |
2626 | ||
2627 | *budget -= work_done; | |
2628 | dev->quota -= work_done; | |
2629 | done = work_done < to_do; | |
2630 | ||
2631 | if (skge_rx_fill(skge)) | |
2632 | done = 0; | |
2633 | ||
2634 | /* restart receiver */ | |
2635 | wmb(); | |
2636 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), | |
2637 | CSR_START | CSR_IRQ_CL_F); | |
2638 | ||
2639 | if (done) { | |
2640 | local_irq_disable(); | |
2641 | hw->intr_mask |= irqmask[skge->port]; | |
2642 | /* Order is important since data can get interrupted */ | |
2643 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2644 | __netif_rx_complete(dev); | |
2645 | local_irq_enable(); | |
2646 | } | |
2647 | ||
2648 | return !done; | |
2649 | } | |
2650 | ||
2651 | static inline void skge_tx_intr(struct net_device *dev) | |
2652 | { | |
2653 | struct skge_port *skge = netdev_priv(dev); | |
2654 | struct skge_hw *hw = skge->hw; | |
2655 | struct skge_ring *ring = &skge->tx_ring; | |
2656 | struct skge_element *e; | |
2657 | ||
2658 | spin_lock(&skge->tx_lock); | |
2659 | for(e = ring->to_clean; e != ring->to_use; e = e->next) { | |
2660 | struct skge_tx_desc *td = e->desc; | |
2661 | u32 control; | |
2662 | ||
2663 | rmb(); | |
2664 | control = td->control; | |
2665 | if (control & BMU_OWN) | |
2666 | break; | |
2667 | ||
2668 | if (unlikely(netif_msg_tx_done(skge))) | |
2669 | printk(KERN_DEBUG PFX "%s: tx done slot %d status 0x%x\n", | |
2670 | dev->name, e - ring->start, td->status); | |
2671 | ||
2672 | skge_tx_free(hw, e); | |
2673 | e->skb = NULL; | |
2674 | ++skge->tx_avail; | |
2675 | } | |
2676 | ring->to_clean = e; | |
2677 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); | |
2678 | ||
2679 | if (skge->tx_avail > MAX_SKB_FRAGS + 1) | |
2680 | netif_wake_queue(dev); | |
2681 | ||
2682 | spin_unlock(&skge->tx_lock); | |
2683 | } | |
2684 | ||
2685 | static void skge_mac_parity(struct skge_hw *hw, int port) | |
2686 | { | |
2687 | printk(KERN_ERR PFX "%s: mac data parity error\n", | |
2688 | hw->dev[port] ? hw->dev[port]->name | |
2689 | : (port == 0 ? "(port A)": "(port B")); | |
2690 | ||
2691 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2692 | skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), | |
2693 | MFF_CLR_PERR); | |
2694 | else | |
2695 | /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ | |
2696 | skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), | |
2697 | (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0) | |
2698 | ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); | |
2699 | } | |
2700 | ||
2701 | static void skge_pci_clear(struct skge_hw *hw) | |
2702 | { | |
2703 | u16 status; | |
2704 | ||
2705 | status = skge_read16(hw, SKGEPCI_REG(PCI_STATUS)); | |
2706 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
2707 | skge_write16(hw, SKGEPCI_REG(PCI_STATUS), | |
2708 | status | PCI_STATUS_ERROR_BITS); | |
2709 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2710 | } | |
2711 | ||
2712 | static void skge_mac_intr(struct skge_hw *hw, int port) | |
2713 | { | |
2714 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2715 | genesis_mac_intr(hw, port); | |
2716 | else | |
2717 | yukon_mac_intr(hw, port); | |
2718 | } | |
2719 | ||
2720 | /* Handle device specific framing and timeout interrupts */ | |
2721 | static void skge_error_irq(struct skge_hw *hw) | |
2722 | { | |
2723 | u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); | |
2724 | ||
2725 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
2726 | /* clear xmac errors */ | |
2727 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | |
2728 | skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT); | |
2729 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) | |
2730 | skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT); | |
2731 | } else { | |
2732 | /* Timestamp (unused) overflow */ | |
2733 | if (hwstatus & IS_IRQ_TIST_OV) | |
2734 | skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); | |
2735 | ||
2736 | if (hwstatus & IS_IRQ_SENSOR) { | |
2737 | /* no sensors on 32-bit Yukon */ | |
2738 | if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) { | |
2739 | printk(KERN_ERR PFX "ignoring bogus sensor interrups\n"); | |
2740 | skge_write32(hw, B0_HWE_IMSK, | |
2741 | IS_ERR_MSK & ~IS_IRQ_SENSOR); | |
2742 | } else | |
2743 | printk(KERN_WARNING PFX "sensor interrupt\n"); | |
2744 | } | |
2745 | ||
2746 | ||
2747 | } | |
2748 | ||
2749 | if (hwstatus & IS_RAM_RD_PAR) { | |
2750 | printk(KERN_ERR PFX "Ram read data parity error\n"); | |
2751 | skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); | |
2752 | } | |
2753 | ||
2754 | if (hwstatus & IS_RAM_WR_PAR) { | |
2755 | printk(KERN_ERR PFX "Ram write data parity error\n"); | |
2756 | skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); | |
2757 | } | |
2758 | ||
2759 | if (hwstatus & IS_M1_PAR_ERR) | |
2760 | skge_mac_parity(hw, 0); | |
2761 | ||
2762 | if (hwstatus & IS_M2_PAR_ERR) | |
2763 | skge_mac_parity(hw, 1); | |
2764 | ||
2765 | if (hwstatus & IS_R1_PAR_ERR) | |
2766 | skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); | |
2767 | ||
2768 | if (hwstatus & IS_R2_PAR_ERR) | |
2769 | skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); | |
2770 | ||
2771 | if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { | |
2772 | printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n", | |
2773 | hwstatus); | |
2774 | ||
2775 | skge_pci_clear(hw); | |
2776 | ||
2777 | hwstatus = skge_read32(hw, B0_HWE_ISRC); | |
2778 | if (hwstatus & IS_IRQ_STAT) { | |
2779 | printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n", | |
2780 | hwstatus); | |
2781 | hw->intr_mask &= ~IS_HW_ERR; | |
2782 | } | |
2783 | } | |
2784 | } | |
2785 | ||
2786 | /* | |
2787 | * Interrrupt from PHY are handled in tasklet (soft irq) | |
2788 | * because accessing phy registers requires spin wait which might | |
2789 | * cause excess interrupt latency. | |
2790 | */ | |
2791 | static void skge_extirq(unsigned long data) | |
2792 | { | |
2793 | struct skge_hw *hw = (struct skge_hw *) data; | |
2794 | int port; | |
2795 | ||
2796 | spin_lock(&hw->phy_lock); | |
2797 | for (port = 0; port < 2; port++) { | |
2798 | struct net_device *dev = hw->dev[port]; | |
2799 | ||
2800 | if (dev && netif_running(dev)) { | |
2801 | struct skge_port *skge = netdev_priv(dev); | |
2802 | ||
2803 | if (hw->chip_id != CHIP_ID_GENESIS) | |
2804 | yukon_phy_intr(skge); | |
2805 | else if (hw->phy_type == SK_PHY_BCOM) | |
2806 | genesis_bcom_intr(skge); | |
2807 | } | |
2808 | } | |
2809 | spin_unlock(&hw->phy_lock); | |
2810 | ||
2811 | local_irq_disable(); | |
2812 | hw->intr_mask |= IS_EXT_REG; | |
2813 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2814 | local_irq_enable(); | |
2815 | } | |
2816 | ||
2817 | static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2818 | { | |
2819 | struct skge_hw *hw = dev_id; | |
2820 | u32 status = skge_read32(hw, B0_SP_ISRC); | |
2821 | ||
2822 | if (status == 0 || status == ~0) /* hotplug or shared irq */ | |
2823 | return IRQ_NONE; | |
2824 | ||
2825 | status &= hw->intr_mask; | |
2826 | ||
2827 | if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) { | |
2828 | status &= ~IS_R1_F; | |
2829 | hw->intr_mask &= ~IS_R1_F; | |
2830 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2831 | __netif_rx_schedule(hw->dev[0]); | |
2832 | } | |
2833 | ||
2834 | if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) { | |
2835 | status &= ~IS_R2_F; | |
2836 | hw->intr_mask &= ~IS_R2_F; | |
2837 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2838 | __netif_rx_schedule(hw->dev[1]); | |
2839 | } | |
2840 | ||
2841 | if (status & IS_XA1_F) | |
2842 | skge_tx_intr(hw->dev[0]); | |
2843 | ||
2844 | if (status & IS_XA2_F) | |
2845 | skge_tx_intr(hw->dev[1]); | |
2846 | ||
2847 | if (status & IS_MAC1) | |
2848 | skge_mac_intr(hw, 0); | |
2849 | ||
2850 | if (status & IS_MAC2) | |
2851 | skge_mac_intr(hw, 1); | |
2852 | ||
2853 | if (status & IS_HW_ERR) | |
2854 | skge_error_irq(hw); | |
2855 | ||
2856 | if (status & IS_EXT_REG) { | |
2857 | hw->intr_mask &= ~IS_EXT_REG; | |
2858 | tasklet_schedule(&hw->ext_tasklet); | |
2859 | } | |
2860 | ||
2861 | if (status) | |
2862 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
2863 | ||
2864 | return IRQ_HANDLED; | |
2865 | } | |
2866 | ||
2867 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2868 | static void skge_netpoll(struct net_device *dev) | |
2869 | { | |
2870 | struct skge_port *skge = netdev_priv(dev); | |
2871 | ||
2872 | disable_irq(dev->irq); | |
2873 | skge_intr(dev->irq, skge->hw, NULL); | |
2874 | enable_irq(dev->irq); | |
2875 | } | |
2876 | #endif | |
2877 | ||
2878 | static int skge_set_mac_address(struct net_device *dev, void *p) | |
2879 | { | |
2880 | struct skge_port *skge = netdev_priv(dev); | |
2881 | struct sockaddr *addr = p; | |
2882 | int err = 0; | |
2883 | ||
2884 | if (!is_valid_ether_addr(addr->sa_data)) | |
2885 | return -EADDRNOTAVAIL; | |
2886 | ||
2887 | skge_down(dev); | |
2888 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
2889 | memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8, | |
2890 | dev->dev_addr, ETH_ALEN); | |
2891 | memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8, | |
2892 | dev->dev_addr, ETH_ALEN); | |
2893 | if (dev->flags & IFF_UP) | |
2894 | err = skge_up(dev); | |
2895 | return err; | |
2896 | } | |
2897 | ||
2898 | static const struct { | |
2899 | u8 id; | |
2900 | const char *name; | |
2901 | } skge_chips[] = { | |
2902 | { CHIP_ID_GENESIS, "Genesis" }, | |
2903 | { CHIP_ID_YUKON, "Yukon" }, | |
2904 | { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, | |
2905 | { CHIP_ID_YUKON_LP, "Yukon-LP"}, | |
2906 | { CHIP_ID_YUKON_XL, "Yukon-2 XL"}, | |
2907 | { CHIP_ID_YUKON_EC, "YUKON-2 EC"}, | |
2908 | { CHIP_ID_YUKON_FE, "YUKON-2 FE"}, | |
2909 | }; | |
2910 | ||
2911 | static const char *skge_board_name(const struct skge_hw *hw) | |
2912 | { | |
2913 | int i; | |
2914 | static char buf[16]; | |
2915 | ||
2916 | for (i = 0; i < ARRAY_SIZE(skge_chips); i++) | |
2917 | if (skge_chips[i].id == hw->chip_id) | |
2918 | return skge_chips[i].name; | |
2919 | ||
2920 | snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); | |
2921 | return buf; | |
2922 | } | |
2923 | ||
2924 | ||
2925 | /* | |
2926 | * Setup the board data structure, but don't bring up | |
2927 | * the port(s) | |
2928 | */ | |
2929 | static int skge_reset(struct skge_hw *hw) | |
2930 | { | |
2931 | u16 ctst; | |
2932 | u8 t8; | |
2933 | int i, ports; | |
2934 | ||
2935 | ctst = skge_read16(hw, B0_CTST); | |
2936 | ||
2937 | /* do a SW reset */ | |
2938 | skge_write8(hw, B0_CTST, CS_RST_SET); | |
2939 | skge_write8(hw, B0_CTST, CS_RST_CLR); | |
2940 | ||
2941 | /* clear PCI errors, if any */ | |
2942 | skge_pci_clear(hw); | |
2943 | ||
2944 | skge_write8(hw, B0_CTST, CS_MRST_CLR); | |
2945 | ||
2946 | /* restore CLK_RUN bits (for Yukon-Lite) */ | |
2947 | skge_write16(hw, B0_CTST, | |
2948 | ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); | |
2949 | ||
2950 | hw->chip_id = skge_read8(hw, B2_CHIP_ID); | |
2951 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; | |
2952 | hw->pmd_type = skge_read8(hw, B2_PMD_TYP); | |
2953 | ||
2954 | switch(hw->chip_id) { | |
2955 | case CHIP_ID_GENESIS: | |
2956 | switch (hw->phy_type) { | |
2957 | case SK_PHY_XMAC: | |
2958 | hw->phy_addr = PHY_ADDR_XMAC; | |
2959 | break; | |
2960 | case SK_PHY_BCOM: | |
2961 | hw->phy_addr = PHY_ADDR_BCOM; | |
2962 | break; | |
2963 | default: | |
2964 | printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n", | |
2965 | pci_name(hw->pdev), hw->phy_type); | |
2966 | return -EOPNOTSUPP; | |
2967 | } | |
2968 | break; | |
2969 | ||
2970 | case CHIP_ID_YUKON: | |
2971 | case CHIP_ID_YUKON_LITE: | |
2972 | case CHIP_ID_YUKON_LP: | |
2973 | if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S') | |
2974 | hw->phy_type = SK_PHY_MARV_COPPER; | |
2975 | ||
2976 | hw->phy_addr = PHY_ADDR_MARV; | |
2977 | if (!iscopper(hw)) | |
2978 | hw->phy_type = SK_PHY_MARV_FIBER; | |
2979 | ||
2980 | break; | |
2981 | ||
2982 | default: | |
2983 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2984 | pci_name(hw->pdev), hw->chip_id); | |
2985 | return -EOPNOTSUPP; | |
2986 | } | |
2987 | ||
2988 | hw->mac_cfg = skge_read8(hw, B2_MAC_CFG); | |
2989 | ports = isdualport(hw) ? 2 : 1; | |
2990 | ||
2991 | /* read the adapters RAM size */ | |
2992 | t8 = skge_read8(hw, B2_E_0); | |
2993 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
2994 | if (t8 == 3) { | |
2995 | /* special case: 4 x 64k x 36, offset = 0x80000 */ | |
2996 | hw->ram_size = 0x100000; | |
2997 | hw->ram_offset = 0x80000; | |
2998 | } else | |
2999 | hw->ram_size = t8 * 512; | |
3000 | } | |
3001 | else if (t8 == 0) | |
3002 | hw->ram_size = 0x20000; | |
3003 | else | |
3004 | hw->ram_size = t8 * 4096; | |
3005 | ||
3006 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3007 | genesis_init(hw); | |
3008 | else { | |
3009 | /* switch power to VCC (WA for VAUX problem) */ | |
3010 | skge_write8(hw, B0_POWER_CTRL, | |
3011 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
3012 | for (i = 0; i < ports; i++) { | |
3013 | skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
3014 | skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
3015 | } | |
3016 | } | |
3017 | ||
3018 | /* turn off hardware timer (unused) */ | |
3019 | skge_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3020 | skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
3021 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
3022 | ||
3023 | /* enable the Tx Arbiters */ | |
3024 | for (i = 0; i < ports; i++) | |
3025 | skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
3026 | ||
3027 | /* Initialize ram interface */ | |
3028 | skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); | |
3029 | ||
3030 | skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); | |
3031 | skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); | |
3032 | skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); | |
3033 | skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); | |
3034 | skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); | |
3035 | skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); | |
3036 | skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); | |
3037 | skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); | |
3038 | skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); | |
3039 | skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); | |
3040 | skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); | |
3041 | skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); | |
3042 | ||
3043 | skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); | |
3044 | ||
3045 | /* Set interrupt moderation for Transmit only | |
3046 | * Receive interrupts avoided by NAPI | |
3047 | */ | |
3048 | skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); | |
3049 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); | |
3050 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
3051 | ||
3052 | hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1; | |
3053 | if (isdualport(hw)) | |
3054 | hw->intr_mask |= IS_PORT_2; | |
3055 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
3056 | ||
3057 | if (hw->chip_id != CHIP_ID_GENESIS) | |
3058 | skge_write8(hw, GMAC_IRQ_MSK, 0); | |
3059 | ||
3060 | spin_lock_bh(&hw->phy_lock); | |
3061 | for (i = 0; i < ports; i++) { | |
3062 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3063 | genesis_reset(hw, i); | |
3064 | else | |
3065 | yukon_reset(hw, i); | |
3066 | } | |
3067 | spin_unlock_bh(&hw->phy_lock); | |
3068 | ||
3069 | return 0; | |
3070 | } | |
3071 | ||
3072 | /* Initialize network device */ | |
3073 | static struct net_device *skge_devinit(struct skge_hw *hw, int port) | |
3074 | { | |
3075 | struct skge_port *skge; | |
3076 | struct net_device *dev = alloc_etherdev(sizeof(*skge)); | |
3077 | ||
3078 | if (!dev) { | |
3079 | printk(KERN_ERR "skge etherdev alloc failed"); | |
3080 | return NULL; | |
3081 | } | |
3082 | ||
3083 | SET_MODULE_OWNER(dev); | |
3084 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
3085 | dev->open = skge_up; | |
3086 | dev->stop = skge_down; | |
3087 | dev->hard_start_xmit = skge_xmit_frame; | |
3088 | dev->get_stats = skge_get_stats; | |
3089 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3090 | dev->set_multicast_list = genesis_set_multicast; | |
3091 | else | |
3092 | dev->set_multicast_list = yukon_set_multicast; | |
3093 | ||
3094 | dev->set_mac_address = skge_set_mac_address; | |
3095 | dev->change_mtu = skge_change_mtu; | |
3096 | SET_ETHTOOL_OPS(dev, &skge_ethtool_ops); | |
3097 | dev->tx_timeout = skge_tx_timeout; | |
3098 | dev->watchdog_timeo = TX_WATCHDOG; | |
3099 | dev->poll = skge_poll; | |
3100 | dev->weight = NAPI_WEIGHT; | |
3101 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3102 | dev->poll_controller = skge_netpoll; | |
3103 | #endif | |
3104 | dev->irq = hw->pdev->irq; | |
3105 | dev->features = NETIF_F_LLTX; | |
3106 | ||
3107 | skge = netdev_priv(dev); | |
3108 | skge->netdev = dev; | |
3109 | skge->hw = hw; | |
3110 | skge->msg_enable = netif_msg_init(debug, default_msg); | |
3111 | skge->tx_ring.count = DEFAULT_TX_RING_SIZE; | |
3112 | skge->rx_ring.count = DEFAULT_RX_RING_SIZE; | |
3113 | ||
3114 | /* Auto speed and flow control */ | |
3115 | skge->autoneg = AUTONEG_ENABLE; | |
3116 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
3117 | skge->duplex = -1; | |
3118 | skge->speed = -1; | |
3119 | skge->advertising = skge_modes(hw); | |
3120 | ||
3121 | hw->dev[port] = dev; | |
3122 | ||
3123 | skge->port = port; | |
3124 | ||
3125 | spin_lock_init(&skge->tx_lock); | |
3126 | ||
3127 | init_timer(&skge->link_check); | |
3128 | skge->link_check.function = skge_link_timer; | |
3129 | skge->link_check.data = (unsigned long) skge; | |
3130 | ||
3131 | init_timer(&skge->led_blink); | |
3132 | skge->led_blink.function = skge_blink_timer; | |
3133 | skge->led_blink.data = (unsigned long) skge; | |
3134 | ||
3135 | if (hw->chip_id != CHIP_ID_GENESIS) { | |
3136 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
3137 | skge->rx_csum = 1; | |
3138 | } | |
3139 | ||
3140 | /* read the mac address */ | |
3141 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); | |
3142 | ||
3143 | /* device is off until link detection */ | |
3144 | netif_carrier_off(dev); | |
3145 | netif_stop_queue(dev); | |
3146 | ||
3147 | return dev; | |
3148 | } | |
3149 | ||
3150 | static void __devinit skge_show_addr(struct net_device *dev) | |
3151 | { | |
3152 | const struct skge_port *skge = netdev_priv(dev); | |
3153 | ||
3154 | if (netif_msg_probe(skge)) | |
3155 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3156 | dev->name, | |
3157 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3158 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3159 | } | |
3160 | ||
3161 | static int __devinit skge_probe(struct pci_dev *pdev, | |
3162 | const struct pci_device_id *ent) | |
3163 | { | |
3164 | struct net_device *dev, *dev1; | |
3165 | struct skge_hw *hw; | |
3166 | int err, using_dac = 0; | |
3167 | ||
3168 | if ((err = pci_enable_device(pdev))) { | |
3169 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", | |
3170 | pci_name(pdev)); | |
3171 | goto err_out; | |
3172 | } | |
3173 | ||
3174 | if ((err = pci_request_regions(pdev, DRV_NAME))) { | |
3175 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", | |
3176 | pci_name(pdev)); | |
3177 | goto err_out_disable_pdev; | |
3178 | } | |
3179 | ||
3180 | pci_set_master(pdev); | |
3181 | ||
3182 | if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) | |
3183 | using_dac = 1; | |
3184 | else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { | |
3185 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3186 | pci_name(pdev)); | |
3187 | goto err_out_free_regions; | |
3188 | } | |
3189 | ||
3190 | #ifdef __BIG_ENDIAN | |
3191 | /* byte swap decriptors in hardware */ | |
3192 | { | |
3193 | u32 reg; | |
3194 | ||
3195 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3196 | reg |= PCI_REV_DESC; | |
3197 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3198 | } | |
3199 | #endif | |
3200 | ||
3201 | err = -ENOMEM; | |
3202 | hw = kmalloc(sizeof(*hw), GFP_KERNEL); | |
3203 | if (!hw) { | |
3204 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3205 | pci_name(pdev)); | |
3206 | goto err_out_free_regions; | |
3207 | } | |
3208 | ||
3209 | memset(hw, 0, sizeof(*hw)); | |
3210 | hw->pdev = pdev; | |
3211 | spin_lock_init(&hw->phy_lock); | |
3212 | tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw); | |
3213 | ||
3214 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3215 | if (!hw->regs) { | |
3216 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3217 | pci_name(pdev)); | |
3218 | goto err_out_free_hw; | |
3219 | } | |
3220 | ||
3221 | if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) { | |
3222 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3223 | pci_name(pdev), pdev->irq); | |
3224 | goto err_out_iounmap; | |
3225 | } | |
3226 | pci_set_drvdata(pdev, hw); | |
3227 | ||
3228 | err = skge_reset(hw); | |
3229 | if (err) | |
3230 | goto err_out_free_irq; | |
3231 | ||
3232 | printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n", | |
3233 | pci_resource_start(pdev, 0), pdev->irq, | |
3234 | skge_board_name(hw), chip_rev(hw)); | |
3235 | ||
3236 | if ((dev = skge_devinit(hw, 0)) == NULL) | |
3237 | goto err_out_led_off; | |
3238 | ||
3239 | if (using_dac) | |
3240 | dev->features |= NETIF_F_HIGHDMA; | |
3241 | ||
3242 | if ((err = register_netdev(dev))) { | |
3243 | printk(KERN_ERR PFX "%s: cannot register net device\n", | |
3244 | pci_name(pdev)); | |
3245 | goto err_out_free_netdev; | |
3246 | } | |
3247 | ||
3248 | skge_show_addr(dev); | |
3249 | ||
3250 | if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) { | |
3251 | if (using_dac) | |
3252 | dev1->features |= NETIF_F_HIGHDMA; | |
3253 | ||
3254 | if (register_netdev(dev1) == 0) | |
3255 | skge_show_addr(dev1); | |
3256 | else { | |
3257 | /* Failure to register second port need not be fatal */ | |
3258 | printk(KERN_WARNING PFX "register of second port failed\n"); | |
3259 | hw->dev[1] = NULL; | |
3260 | free_netdev(dev1); | |
3261 | } | |
3262 | } | |
3263 | ||
3264 | return 0; | |
3265 | ||
3266 | err_out_free_netdev: | |
3267 | free_netdev(dev); | |
3268 | err_out_led_off: | |
3269 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
3270 | err_out_free_irq: | |
3271 | free_irq(pdev->irq, hw); | |
3272 | err_out_iounmap: | |
3273 | iounmap(hw->regs); | |
3274 | err_out_free_hw: | |
3275 | kfree(hw); | |
3276 | err_out_free_regions: | |
3277 | pci_release_regions(pdev); | |
3278 | err_out_disable_pdev: | |
3279 | pci_disable_device(pdev); | |
3280 | pci_set_drvdata(pdev, NULL); | |
3281 | err_out: | |
3282 | return err; | |
3283 | } | |
3284 | ||
3285 | static void __devexit skge_remove(struct pci_dev *pdev) | |
3286 | { | |
3287 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3288 | struct net_device *dev0, *dev1; | |
3289 | ||
3290 | if(!hw) | |
3291 | return; | |
3292 | ||
3293 | if ((dev1 = hw->dev[1])) | |
3294 | unregister_netdev(dev1); | |
3295 | dev0 = hw->dev[0]; | |
3296 | unregister_netdev(dev0); | |
3297 | ||
3298 | tasklet_kill(&hw->ext_tasklet); | |
3299 | ||
3300 | free_irq(pdev->irq, hw); | |
3301 | pci_release_regions(pdev); | |
3302 | pci_disable_device(pdev); | |
3303 | if (dev1) | |
3304 | free_netdev(dev1); | |
3305 | free_netdev(dev0); | |
3306 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
3307 | iounmap(hw->regs); | |
3308 | kfree(hw); | |
3309 | pci_set_drvdata(pdev, NULL); | |
3310 | } | |
3311 | ||
3312 | #ifdef CONFIG_PM | |
3313 | static int skge_suspend(struct pci_dev *pdev, u32 state) | |
3314 | { | |
3315 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3316 | int i, wol = 0; | |
3317 | ||
3318 | for(i = 0; i < 2; i++) { | |
3319 | struct net_device *dev = hw->dev[i]; | |
3320 | ||
3321 | if (dev) { | |
3322 | struct skge_port *skge = netdev_priv(dev); | |
3323 | if (netif_running(dev)) { | |
3324 | netif_carrier_off(dev); | |
3325 | skge_down(dev); | |
3326 | } | |
3327 | netif_device_detach(dev); | |
3328 | wol |= skge->wol; | |
3329 | } | |
3330 | } | |
3331 | ||
3332 | pci_save_state(pdev); | |
3333 | pci_enable_wake(pdev, state, wol); | |
3334 | pci_disable_device(pdev); | |
3335 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3336 | ||
3337 | return 0; | |
3338 | } | |
3339 | ||
3340 | static int skge_resume(struct pci_dev *pdev) | |
3341 | { | |
3342 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3343 | int i; | |
3344 | ||
3345 | pci_set_power_state(pdev, PCI_D0); | |
3346 | pci_restore_state(pdev); | |
3347 | pci_enable_wake(pdev, PCI_D0, 0); | |
3348 | ||
3349 | skge_reset(hw); | |
3350 | ||
3351 | for(i = 0; i < 2; i++) { | |
3352 | struct net_device *dev = hw->dev[i]; | |
3353 | if (dev) { | |
3354 | netif_device_attach(dev); | |
3355 | if(netif_running(dev)) | |
3356 | skge_up(dev); | |
3357 | } | |
3358 | } | |
3359 | return 0; | |
3360 | } | |
3361 | #endif | |
3362 | ||
3363 | static struct pci_driver skge_driver = { | |
3364 | .name = DRV_NAME, | |
3365 | .id_table = skge_id_table, | |
3366 | .probe = skge_probe, | |
3367 | .remove = __devexit_p(skge_remove), | |
3368 | #ifdef CONFIG_PM | |
3369 | .suspend = skge_suspend, | |
3370 | .resume = skge_resume, | |
3371 | #endif | |
3372 | }; | |
3373 | ||
3374 | static int __init skge_init_module(void) | |
3375 | { | |
3376 | return pci_module_init(&skge_driver); | |
3377 | } | |
3378 | ||
3379 | static void __exit skge_cleanup_module(void) | |
3380 | { | |
3381 | pci_unregister_driver(&skge_driver); | |
3382 | } | |
3383 | ||
3384 | module_init(skge_init_module); | |
3385 | module_exit(skge_cleanup_module); |