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[PATCH] skge: dont use dev_alloc_skb for rx buffs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
2cd8e5d3 41#include <linux/mii.h>
baef58b1
SH		 42#include <asm/irq.h>
43
44#include "skge.h"
45
46#define DRV_NAME "skge"
9362860f 47#define DRV_VERSION "1.4"
baef58b1
SH		 48#define PFX DRV_NAME " "
49
50#define DEFAULT_TX_RING_SIZE 128
51#define DEFAULT_RX_RING_SIZE 512
52#define MAX_TX_RING_SIZE 1024
53#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 54#define RX_COPY_THRESHOLD 128
55#define RX_BUF_SIZE 1536
baef58b1
SH		 56#define PHY_RETRIES 1000
57#define ETH_JUMBO_MTU 9000
58#define TX_WATCHDOG (5 * HZ)
59#define NAPI_WEIGHT 64
6abebb53 60#define BLINK_MS 250
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
83 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 84 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 85 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 86 { 0 }
87};
88MODULE_DEVICE_TABLE(pci, skge_id_table);
89
90static int skge_up(struct net_device *dev);
91static int skge_down(struct net_device *dev);
ee294dcd 92static void skge_phy_reset(struct skge_port *skge);
baef58b1 93static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 94static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 96static void genesis_get_stats(struct skge_port *skge, u64 *data);
97static void yukon_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_init(struct skge_hw *hw, int port);
baef58b1 99static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 100static void genesis_link_up(struct skge_port *skge);
baef58b1 101
7e676d91 102/* Avoid conditionals by using array */
baef58b1
SH		 103static const int txqaddr[] = { Q_XA1, Q_XA2 };
104static const int rxqaddr[] = { Q_R1, Q_R2 };
105static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107
baef58b1
SH		 108static int skge_get_regs_len(struct net_device *dev)
109{
c3f8be96 110 return 0x4000;
baef58b1
SH		 111}
112
113/*
c3f8be96
SH		 114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
baef58b1
SH		 117 */
118static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120{
121 const struct skge_port *skge = netdev_priv(dev);
baef58b1 122 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 123
124 regs->version = 1;
c3f8be96
SH		 125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 127
c3f8be96
SH		 128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 130}
131
8f3f8193 132/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 133static int wol_supported(const struct skge_hw *hw)
134{
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 137}
138
139static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140{
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145}
146
147static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148{
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
95566065 152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170}
171
8f3f8193
SH		 172/* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 174 */
175static u32 skge_supported_modes(const struct skge_hw *hw)
176{
177 u32 supported;
178
5e1705dd 179 if (hw->copper) {
31b619c5
SH		 180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201}
baef58b1
SH		 202
203static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205{
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 210 ecmd->supported = skge_supported_modes(hw);
baef58b1 211
5e1705dd 212 if (hw->copper) {
baef58b1
SH		 213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
31b619c5 215 } else
baef58b1 216 ecmd->port = PORT_FIBRE;
baef58b1
SH		 217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223}
224
baef58b1
SH		 225static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226{
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
31b619c5 229 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
baef58b1 235 } else {
31b619c5
SH		 236 u32 setting;
237
2c668514 238 switch (ecmd->speed) {
baef58b1 239 case SPEED_1000:
31b619c5
SH		 240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
baef58b1
SH		 246 break;
247 case SPEED_100:
31b619c5
SH		 248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
baef58b1 256 case SPEED_10:
31b619c5
SH		 257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
baef58b1
SH		 262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
31b619c5
SH		 267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
baef58b1
SH		 273 }
274
275 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 276 skge->advertising = ecmd->advertising;
277
ee294dcd
SH		 278 if (netif_running(dev))
279 skge_phy_reset(skge);
280
baef58b1
SH		 281 return (0);
282}
283
284static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286{
287 struct skge_port *skge = netdev_priv(dev);
288
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
293}
294
295static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
297 u16 xmac_offset;
298 u16 gma_offset;
299} skge_stats[] = {
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
302
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
311
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
318
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
324};
325
326static int skge_get_stats_count(struct net_device *dev)
327{
328 return ARRAY_SIZE(skge_stats);
329}
330
331static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
333{
334 struct skge_port *skge = netdev_priv(dev);
335
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
338 else
339 yukon_get_stats(skge, data);
340}
341
342/* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
345 */
346static struct net_device_stats *skge_get_stats(struct net_device *dev)
347{
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
350
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
353 else
354 yukon_get_stats(skge, data);
355
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
363
364 return &skge->net_stats;
365}
366
367static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
368{
369 int i;
370
95566065 371 switch (stringset) {
baef58b1
SH		 372 case ETH_SS_STATS:
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
376 break;
377 }
378}
379
380static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
382{
383 struct skge_port *skge = netdev_priv(dev);
384
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
389
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
394}
395
396static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
398{
399 struct skge_port *skge = netdev_priv(dev);
3b8bb472 400 int err;
baef58b1
SH		 401
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
404 return -EINVAL;
405
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
408
409 if (netif_running(dev)) {
410 skge_down(dev);
3b8bb472
SH		 411 err = skge_up(dev);
412 if (err)
413 dev_close(dev);
baef58b1
SH		 414 }
415
416 return 0;
417}
418
419static u32 skge_get_msglevel(struct net_device *netdev)
420{
421 struct skge_port *skge = netdev_priv(netdev);
422 return skge->msg_enable;
423}
424
425static void skge_set_msglevel(struct net_device *netdev, u32 value)
426{
427 struct skge_port *skge = netdev_priv(netdev);
428 skge->msg_enable = value;
429}
430
431static int skge_nway_reset(struct net_device *dev)
432{
433 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 434
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
436 return -EINVAL;
437
ee294dcd 438 skge_phy_reset(skge);
baef58b1
SH		 439 return 0;
440}
441
442static int skge_set_sg(struct net_device *dev, u32 data)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446
447 if (hw->chip_id == CHIP_ID_GENESIS && data)
448 return -EOPNOTSUPP;
449 return ethtool_op_set_sg(dev, data);
450}
451
452static int skge_set_tx_csum(struct net_device *dev, u32 data)
453{
454 struct skge_port *skge = netdev_priv(dev);
455 struct skge_hw *hw = skge->hw;
456
457 if (hw->chip_id == CHIP_ID_GENESIS && data)
458 return -EOPNOTSUPP;
459
460 return ethtool_op_set_tx_csum(dev, data);
461}
462
463static u32 skge_get_rx_csum(struct net_device *dev)
464{
465 struct skge_port *skge = netdev_priv(dev);
466
467 return skge->rx_csum;
468}
469
470/* Only Yukon supports checksum offload. */
471static int skge_set_rx_csum(struct net_device *dev, u32 data)
472{
473 struct skge_port *skge = netdev_priv(dev);
474
475 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
476 return -EOPNOTSUPP;
477
478 skge->rx_csum = data;
479 return 0;
480}
481
baef58b1
SH		 482static void skge_get_pauseparam(struct net_device *dev,
483 struct ethtool_pauseparam *ecmd)
484{
485 struct skge_port *skge = netdev_priv(dev);
486
487 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
488 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
491
492 ecmd->autoneg = skge->autoneg;
493}
494
495static int skge_set_pauseparam(struct net_device *dev,
496 struct ethtool_pauseparam *ecmd)
497{
498 struct skge_port *skge = netdev_priv(dev);
499
500 skge->autoneg = ecmd->autoneg;
501 if (ecmd->rx_pause && ecmd->tx_pause)
502 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 503 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 504 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 505 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 506 skge->flow_control = FLOW_MODE_LOC_SEND;
507 else
508 skge->flow_control = FLOW_MODE_NONE;
509
e8df8554
SH		 510 if (netif_running(dev))
511 skge_phy_reset(skge);
baef58b1
SH		 512 return 0;
513}
514
515/* Chip internal frequency for clock calculations */
516static inline u32 hwkhz(const struct skge_hw *hw)
517{
518 if (hw->chip_id == CHIP_ID_GENESIS)
519 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 520 else
521 return 78215; /* or: 78.125 MHz */
522}
523
8f3f8193 524/* Chip HZ to microseconds */
baef58b1
SH		 525static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
526{
527 return (ticks * 1000) / hwkhz(hw);
528}
529
8f3f8193 530/* Microseconds to chip HZ */
baef58b1
SH		 531static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
532{
533 return hwkhz(hw) * usec / 1000;
534}
535
536static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
538{
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
542
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
545
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
549
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
554 }
555
556 return 0;
557}
558
559/* Note: interrupt timer is per board, but can turn on/off per port */
560static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
567 u32 delay = 25;
568
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
573 return -EINVAL;
574 else {
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
577 }
578
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
587 }
588
589 skge_write32(hw, B2_IRQM_MSK, msk);
590 if (msk == 0)
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
592 else {
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
595 }
596 return 0;
597}
598
6abebb53
SH		 599enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 601{
6abebb53
SH		 602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
604
605 spin_lock_bh(&hw->phy_lock);
baef58b1 606 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 607 switch (mode) {
608 case LED_MODE_OFF:
609 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
610 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
611 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
612 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
613 break;
baef58b1 614
6abebb53
SH		 615 case LED_MODE_ON:
616 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 618
6abebb53
SH		 619 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
620 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 621
6abebb53 622 break;
baef58b1 623
6abebb53
SH		 624 case LED_MODE_TST:
625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 628
6abebb53
SH		 629 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
630 break;
631 }
baef58b1 632 } else {
6abebb53
SH		 633 switch (mode) {
634 case LED_MODE_OFF:
635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
637 PHY_M_LED_MO_DUP(MO_LED_OFF) |
638 PHY_M_LED_MO_10(MO_LED_OFF) |
639 PHY_M_LED_MO_100(MO_LED_OFF) |
640 PHY_M_LED_MO_1000(MO_LED_OFF) |
641 PHY_M_LED_MO_RX(MO_LED_OFF));
642 break;
643 case LED_MODE_ON:
644 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
645 PHY_M_LED_PULS_DUR(PULS_170MS) |
646 PHY_M_LED_BLINK_RT(BLINK_84MS) |
647 PHY_M_LEDC_TX_CTRL |
648 PHY_M_LEDC_DP_CTRL);
46a60f2d 649
6abebb53
SH		 650 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
651 PHY_M_LED_MO_RX(MO_LED_OFF) |
652 (skge->speed == SPEED_100 ?
653 PHY_M_LED_MO_100(MO_LED_ON) : 0));
654 break;
655 case LED_MODE_TST:
656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
657 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
658 PHY_M_LED_MO_DUP(MO_LED_ON) |
659 PHY_M_LED_MO_10(MO_LED_ON) |
660 PHY_M_LED_MO_100(MO_LED_ON) |
661 PHY_M_LED_MO_1000(MO_LED_ON) |
662 PHY_M_LED_MO_RX(MO_LED_ON));
663 }
baef58b1 664 }
4ff6ac05 665 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 666}
667
668/* blink LED's for finding board */
669static int skge_phys_id(struct net_device *dev, u32 data)
670{
671 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 672 unsigned long ms;
673 enum led_mode mode = LED_MODE_TST;
baef58b1 674
95566065 675 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 676 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
677 else
678 ms = data * 1000;
baef58b1 679
6abebb53
SH		 680 while (ms > 0) {
681 skge_led(skge, mode);
682 mode ^= LED_MODE_TST;
baef58b1 683
6abebb53
SH		 684 if (msleep_interruptible(BLINK_MS))
685 break;
686 ms -= BLINK_MS;
687 }
baef58b1 688
6abebb53
SH		 689 /* back to regular LED state */
690 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 691
692 return 0;
693}
694
695static struct ethtool_ops skge_ethtool_ops = {
696 .get_settings = skge_get_settings,
697 .set_settings = skge_set_settings,
698 .get_drvinfo = skge_get_drvinfo,
699 .get_regs_len = skge_get_regs_len,
700 .get_regs = skge_get_regs,
701 .get_wol = skge_get_wol,
702 .set_wol = skge_set_wol,
703 .get_msglevel = skge_get_msglevel,
704 .set_msglevel = skge_set_msglevel,
705 .nway_reset = skge_nway_reset,
706 .get_link = ethtool_op_get_link,
707 .get_ringparam = skge_get_ring_param,
708 .set_ringparam = skge_set_ring_param,
709 .get_pauseparam = skge_get_pauseparam,
710 .set_pauseparam = skge_set_pauseparam,
711 .get_coalesce = skge_get_coalesce,
712 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 713 .get_sg = ethtool_op_get_sg,
714 .set_sg = skge_set_sg,
715 .get_tx_csum = ethtool_op_get_tx_csum,
716 .set_tx_csum = skge_set_tx_csum,
717 .get_rx_csum = skge_get_rx_csum,
718 .set_rx_csum = skge_set_rx_csum,
719 .get_strings = skge_get_strings,
720 .phys_id = skge_phys_id,
721 .get_stats_count = skge_get_stats_count,
722 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 723 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 724};
725
726/*
727 * Allocate ring elements and chain them together
728 * One-to-one association of board descriptors with ring elements
729 */
c3da1447 730static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 731{
732 struct skge_tx_desc *d;
733 struct skge_element *e;
734 int i;
735
ff7907ae 736 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 737 if (!ring->start)
738 return -ENOMEM;
739
740 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
741 e->desc = d;
742 if (i == ring->count - 1) {
743 e->next = ring->start;
744 d->next_offset = base;
745 } else {
746 e->next = e + 1;
747 d->next_offset = base + (i+1) * sizeof(*d);
748 }
749 }
750 ring->to_use = ring->to_clean = ring->start;
751
752 return 0;
753}
754
19a33d4e
SH		 755/* Allocate and setup a new buffer for receiving */
756static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
757 struct sk_buff *skb, unsigned int bufsize)
758{
759 struct skge_rx_desc *rd = e->desc;
760 u64 map;
baef58b1
SH		 761
762 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
763 PCI_DMA_FROMDEVICE);
764
765 rd->dma_lo = map;
766 rd->dma_hi = map >> 32;
767 e->skb = skb;
768 rd->csum1_start = ETH_HLEN;
769 rd->csum2_start = ETH_HLEN;
770 rd->csum1 = 0;
771 rd->csum2 = 0;
772
773 wmb();
774
775 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
776 pci_unmap_addr_set(e, mapaddr, map);
777 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 778}
779
19a33d4e
SH		 780/* Resume receiving using existing skb,
781 * Note: DMA address is not changed by chip.
782 * MTU not changed while receiver active.
783 */
784static void skge_rx_reuse(struct skge_element *e, unsigned int size)
785{
786 struct skge_rx_desc *rd = e->desc;
787
788 rd->csum2 = 0;
789 rd->csum2_start = ETH_HLEN;
790
791 wmb();
792
793 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
794}
795
796
797/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 798static void skge_rx_clean(struct skge_port *skge)
799{
800 struct skge_hw *hw = skge->hw;
801 struct skge_ring *ring = &skge->rx_ring;
802 struct skge_element *e;
803
19a33d4e
SH		 804 e = ring->start;
805 do {
baef58b1
SH		 806 struct skge_rx_desc *rd = e->desc;
807 rd->control = 0;
19a33d4e
SH		 808 if (e->skb) {
809 pci_unmap_single(hw->pdev,
810 pci_unmap_addr(e, mapaddr),
811 pci_unmap_len(e, maplen),
812 PCI_DMA_FROMDEVICE);
813 dev_kfree_skb(e->skb);
814 e->skb = NULL;
815 }
816 } while ((e = e->next) != ring->start);
baef58b1
SH		 817}
818
19a33d4e 819
baef58b1 820/* Allocate buffers for receive ring
19a33d4e 821 * For receive: to_clean is next received frame.
baef58b1
SH		 822 */
823static int skge_rx_fill(struct skge_port *skge)
824{
825 struct skge_ring *ring = &skge->rx_ring;
826 struct skge_element *e;
baef58b1 827
19a33d4e
SH		 828 e = ring->start;
829 do {
383181ac 830 struct sk_buff *skb;
baef58b1 831
b5d56ddc 832 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL);
19a33d4e
SH		 833 if (!skb)
834 return -ENOMEM;
835
383181ac
SH		 836 skb_reserve(skb, NET_IP_ALIGN);
837 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 838 } while ( (e = e->next) != ring->start);
baef58b1 839
19a33d4e
SH		 840 ring->to_clean = ring->start;
841 return 0;
baef58b1
SH		 842}
843
844static void skge_link_up(struct skge_port *skge)
845{
46a60f2d 846 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 847 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
848
baef58b1
SH		 849 netif_carrier_on(skge->netdev);
850 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
851 netif_wake_queue(skge->netdev);
852
853 if (netif_msg_link(skge))
854 printk(KERN_INFO PFX
855 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
856 skge->netdev->name, skge->speed,
857 skge->duplex == DUPLEX_FULL ? "full" : "half",
858 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
859 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
860 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
861 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
862 "unknown");
863}
864
865static void skge_link_down(struct skge_port *skge)
866{
54cfb5aa 867 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 868 netif_carrier_off(skge->netdev);
869 netif_stop_queue(skge->netdev);
870
871 if (netif_msg_link(skge))
872 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
873}
874
2cd8e5d3 875static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 876{
877 int i;
baef58b1 878
6b0c1480 879 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 880 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 881
89bf5f23 882 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 883 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 884 goto ready;
0781191c 885 udelay(1);
baef58b1
SH		 886 }
887
2cd8e5d3 888 return -ETIMEDOUT;
89bf5f23 889 ready:
2cd8e5d3 890 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 891
2cd8e5d3
SH		 892 return 0;
893}
894
895static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
896{
897 u16 v = 0;
898 if (__xm_phy_read(hw, port, reg, &v))
899 printk(KERN_WARNING PFX "%s: phy read timed out\n",
900 hw->dev[port]->name);
baef58b1
SH		 901 return v;
902}
903
2cd8e5d3 904static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 905{
906 int i;
907
6b0c1480 908 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 909 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 910 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 911 goto ready;
89bf5f23 912 udelay(1);
baef58b1 913 }
2cd8e5d3 914 return -EIO;
baef58b1
SH		 915
916 ready:
6b0c1480 917 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 918 for (i = 0; i < PHY_RETRIES; i++) {
919 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
920 return 0;
921 udelay(1);
922 }
923 return -ETIMEDOUT;
baef58b1
SH		 924}
925
926static void genesis_init(struct skge_hw *hw)
927{
928 /* set blink source counter */
929 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
930 skge_write8(hw, B2_BSC_CTRL, BSC_START);
931
932 /* configure mac arbiter */
933 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
934
935 /* configure mac arbiter timeout values */
936 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
940
941 skge_write8(hw, B3_MA_RCINI_RX1, 0);
942 skge_write8(hw, B3_MA_RCINI_RX2, 0);
943 skge_write8(hw, B3_MA_RCINI_TX1, 0);
944 skge_write8(hw, B3_MA_RCINI_TX2, 0);
945
946 /* configure packet arbiter timeout */
947 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
948 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
952}
953
954static void genesis_reset(struct skge_hw *hw, int port)
955{
45bada65 956 const u8 zero[8] = { 0 };
baef58b1 957
46a60f2d
SH		 958 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
959
baef58b1 960 /* reset the statistics module */
6b0c1480
SH		 961 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
962 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
963 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
964 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
965 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 966
89bf5f23
SH		 967 /* disable Broadcom PHY IRQ */
968 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 969
45bada65 970 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 971}
972
973
45bada65
SH		 974/* Convert mode to MII values */
975static const u16 phy_pause_map[] = {
976 [FLOW_MODE_NONE] = 0,
977 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
978 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
979 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
980};
981
982
983/* Check status of Broadcom phy link */
984static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 985{
45bada65
SH		 986 struct net_device *dev = hw->dev[port];
987 struct skge_port *skge = netdev_priv(dev);
988 u16 status;
989
990 /* read twice because of latch */
991 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
992 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
993
45bada65
SH		 994 if ((status & PHY_ST_LSYNC) == 0) {
995 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
996 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
997 xm_write16(hw, port, XM_MMU_CMD, cmd);
998 /* dummy read to ensure writing */
999 (void) xm_read16(hw, port, XM_MMU_CMD);
1000
1001 if (netif_carrier_ok(dev))
1002 skge_link_down(skge);
1003 } else {
1004 if (skge->autoneg == AUTONEG_ENABLE &&
1005 (status & PHY_ST_AN_OVER)) {
1006 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1007 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1008
1009 if (lpa & PHY_B_AN_RF) {
1010 printk(KERN_NOTICE PFX "%s: remote fault\n",
1011 dev->name);
1012 return;
1013 }
1014
1015 /* Check Duplex mismatch */
2c668514 1016 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1017 case PHY_B_RES_1000FD:
1018 skge->duplex = DUPLEX_FULL;
1019 break;
1020 case PHY_B_RES_1000HD:
1021 skge->duplex = DUPLEX_HALF;
1022 break;
1023 default:
1024 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1025 dev->name);
1026 return;
1027 }
1028
1029
1030 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1031 switch (aux & PHY_B_AS_PAUSE_MSK) {
1032 case PHY_B_AS_PAUSE_MSK:
1033 skge->flow_control = FLOW_MODE_SYMMETRIC;
1034 break;
1035 case PHY_B_AS_PRR:
1036 skge->flow_control = FLOW_MODE_REM_SEND;
1037 break;
1038 case PHY_B_AS_PRT:
1039 skge->flow_control = FLOW_MODE_LOC_SEND;
1040 break;
1041 default:
1042 skge->flow_control = FLOW_MODE_NONE;
1043 }
1044
1045 skge->speed = SPEED_1000;
1046 }
1047
1048 if (!netif_carrier_ok(dev))
1049 genesis_link_up(skge);
1050 }
1051}
1052
1053/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1054 * Phy on for 100 or 10Mbit operation
1055 */
1056static void bcom_phy_init(struct skge_port *skge, int jumbo)
1057{
1058 struct skge_hw *hw = skge->hw;
1059 int port = skge->port;
baef58b1 1060 int i;
45bada65 1061 u16 id1, r, ext, ctl;
baef58b1
SH		 1062
1063 /* magic workaround patterns for Broadcom */
1064 static const struct {
1065 u16 reg;
1066 u16 val;
1067 } A1hack[] = {
1068 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1069 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1070 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1071 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1072 }, C0hack[] = {
1073 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1074 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1075 };
1076
45bada65
SH		 1077 /* read Id from external PHY (all have the same address) */
1078 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1079
1080 /* Optimize MDIO transfer by suppressing preamble. */
1081 r = xm_read16(hw, port, XM_MMU_CMD);
1082 r |= XM_MMU_NO_PRE;
1083 xm_write16(hw, port, XM_MMU_CMD,r);
1084
2c668514 1085 switch (id1) {
45bada65
SH		 1086 case PHY_BCOM_ID1_C0:
1087 /*
1088 * Workaround BCOM Errata for the C0 type.
1089 * Write magic patterns to reserved registers.
1090 */
1091 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1092 xm_phy_write(hw, port,
1093 C0hack[i].reg, C0hack[i].val);
1094
1095 break;
1096 case PHY_BCOM_ID1_A1:
1097 /*
1098 * Workaround BCOM Errata for the A1 type.
1099 * Write magic patterns to reserved registers.
1100 */
1101 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1102 xm_phy_write(hw, port,
1103 A1hack[i].reg, A1hack[i].val);
1104 break;
1105 }
1106
1107 /*
1108 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1109 * Disable Power Management after reset.
1110 */
1111 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1112 r |= PHY_B_AC_DIS_PM;
1113 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1114
1115 /* Dummy read */
1116 xm_read16(hw, port, XM_ISRC);
1117
1118 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1119 ctl = PHY_CT_SP1000; /* always 1000mbit */
1120
1121 if (skge->autoneg == AUTONEG_ENABLE) {
1122 /*
1123 * Workaround BCOM Errata #1 for the C5 type.
1124 * 1000Base-T Link Acquisition Failure in Slave Mode
1125 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1126 */
1127 u16 adv = PHY_B_1000C_RD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Half)
1129 adv |= PHY_B_1000C_AHD;
1130 if (skge->advertising & ADVERTISED_1000baseT_Full)
1131 adv |= PHY_B_1000C_AFD;
1132 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1133
1134 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1135 } else {
1136 if (skge->duplex == DUPLEX_FULL)
1137 ctl |= PHY_CT_DUP_MD;
1138 /* Force to slave */
1139 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1140 }
1141
1142 /* Set autonegotiation pause parameters */
1143 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1144 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1145
1146 /* Handle Jumbo frames */
1147 if (jumbo) {
1148 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1149 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1150
1151 ext |= PHY_B_PEC_HIGH_LA;
1152
1153 }
1154
1155 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1156 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1157
8f3f8193 1158 /* Use link status change interrupt */
45bada65
SH		 1159 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1160
1161 bcom_check_link(hw, port);
1162}
1163
1164static void genesis_mac_init(struct skge_hw *hw, int port)
1165{
1166 struct net_device *dev = hw->dev[port];
1167 struct skge_port *skge = netdev_priv(dev);
1168 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1169 int i;
1170 u32 r;
1171 const u8 zero[6] = { 0 };
1172
0781191c
SH		 1173 for (i = 0; i < 10; i++) {
1174 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1175 MFF_SET_MAC_RST);
1176 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1177 goto reset_ok;
1178 udelay(1);
1179 }
baef58b1 1180
0781191c
SH		 1181 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1182
1183 reset_ok:
baef58b1 1184 /* Unreset the XMAC. */
6b0c1480 1185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1186
1187 /*
1188 * Perform additional initialization for external PHYs,
1189 * namely for the 1000baseTX cards that use the XMAC's
1190 * GMII mode.
1191 */
45bada65 1192 /* Take external Phy out of reset */
89bf5f23
SH		 1193 r = skge_read32(hw, B2_GP_IO);
1194 if (port == 0)
1195 r |= GP_DIR_0|GP_IO_0;
1196 else
1197 r |= GP_DIR_2|GP_IO_2;
1198
1199 skge_write32(hw, B2_GP_IO, r);
0781191c 1200
89bf5f23 1201
8f3f8193 1202 /* Enable GMII interface */
89bf5f23
SH		 1203 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1204
45bada65 1205 bcom_phy_init(skge, jumbo);
89bf5f23 1206
45bada65
SH		 1207 /* Set Station Address */
1208 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1209
45bada65
SH		 1210 /* We don't use match addresses so clear */
1211 for (i = 1; i < 16; i++)
1212 xm_outaddr(hw, port, XM_EXM(i), zero);
1213
0781191c
SH		 1214 /* Clear MIB counters */
1215 xm_write16(hw, port, XM_STAT_CMD,
1216 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1217 /* Clear two times according to Errata #3 */
1218 xm_write16(hw, port, XM_STAT_CMD,
1219 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1220
45bada65
SH		 1221 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1222 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1223
1224 /* We don't need the FCS appended to the packet. */
1225 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1226 if (jumbo)
1227 r |= XM_RX_BIG_PK_OK;
89bf5f23 1228
45bada65 1229 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1230 /*
45bada65
SH		 1231 * If in manual half duplex mode the other side might be in
1232 * full duplex mode, so ignore if a carrier extension is not seen
1233 * on frames received
89bf5f23 1234 */
45bada65 1235 r |= XM_RX_DIS_CEXT;
baef58b1 1236 }
45bada65 1237 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1238
baef58b1
SH		 1239
1240 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1241 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1242
1243 /*
1244 * Bump up the transmit threshold. This helps hold off transmit
1245 * underruns when we're blasting traffic from both ports at once.
1246 */
1247 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1248
1249 /*
1250 * Enable the reception of all error frames. This is is
1251 * a necessary evil due to the design of the XMAC. The
1252 * XMAC's receive FIFO is only 8K in size, however jumbo
1253 * frames can be up to 9000 bytes in length. When bad
1254 * frame filtering is enabled, the XMAC's RX FIFO operates
1255 * in 'store and forward' mode. For this to work, the
1256 * entire frame has to fit into the FIFO, but that means
1257 * that jumbo frames larger than 8192 bytes will be
1258 * truncated. Disabling all bad frame filtering causes
1259 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1260 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1261 * RX FIFO as soon as the FIFO threshold is reached.
1262 */
45bada65 1263 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1264
baef58b1
SH		 1265
1266 /*
45bada65
SH		 1267 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1268 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1269 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1270 */
45bada65
SH		 1271 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1272
1273 /*
1274 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1275 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1276 * and 'Octets Tx OK Hi Cnt Ov'.
1277 */
1278 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1279
1280 /* Configure MAC arbiter */
1281 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1282
1283 /* configure timeout values */
1284 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1288
1289 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1293
1294 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1296 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1297 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1298
1299 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1301 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1302 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1303
45bada65 1304 if (jumbo) {
baef58b1 1305 /* Enable frame flushing if jumbo frames used */
6b0c1480 1306 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1307 } else {
1308 /* enable timeout timers if normal frames */
1309 skge_write16(hw, B3_PA_CTRL,
45bada65 1310 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1311 }
baef58b1
SH		 1312}
1313
1314static void genesis_stop(struct skge_port *skge)
1315{
1316 struct skge_hw *hw = skge->hw;
1317 int port = skge->port;
89bf5f23 1318 u32 reg;
baef58b1 1319
46a60f2d
SH		 1320 genesis_reset(hw, port);
1321
baef58b1
SH		 1322 /* Clear Tx packet arbiter timeout IRQ */
1323 skge_write16(hw, B3_PA_CTRL,
1324 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1325
1326 /*
8f3f8193 1327 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1328 * terminate if we don't flush the XMAC's transmit FIFO !
1329 */
6b0c1480
SH		 1330 xm_write32(hw, port, XM_MODE,
1331 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1332
1333
1334 /* Reset the MAC */
6b0c1480 1335 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1336
1337 /* For external PHYs there must be special handling */
89bf5f23
SH		 1338 reg = skge_read32(hw, B2_GP_IO);
1339 if (port == 0) {
1340 reg |= GP_DIR_0;
1341 reg &= ~GP_IO_0;
1342 } else {
1343 reg |= GP_DIR_2;
1344 reg &= ~GP_IO_2;
baef58b1 1345 }
89bf5f23
SH		 1346 skge_write32(hw, B2_GP_IO, reg);
1347 skge_read32(hw, B2_GP_IO);
baef58b1 1348
6b0c1480
SH		 1349 xm_write16(hw, port, XM_MMU_CMD,
1350 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1351 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1352
6b0c1480 1353 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1354}
1355
1356
1357static void genesis_get_stats(struct skge_port *skge, u64 *data)
1358{
1359 struct skge_hw *hw = skge->hw;
1360 int port = skge->port;
1361 int i;
1362 unsigned long timeout = jiffies + HZ;
1363
6b0c1480 1364 xm_write16(hw, port,
baef58b1
SH		 1365 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1366
1367 /* wait for update to complete */
6b0c1480 1368 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1369 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1370 if (time_after(jiffies, timeout))
1371 break;
1372 udelay(10);
1373 }
1374
1375 /* special case for 64 bit octet counter */
6b0c1480
SH		 1376 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_TXO_OK_LO);
1378 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1379 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1380
1381 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1382 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1383}
1384
1385static void genesis_mac_intr(struct skge_hw *hw, int port)
1386{
1387 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1388 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1389
7e676d91
SH		 1390 if (netif_msg_intr(skge))
1391 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1392 skge->netdev->name, status);
baef58b1
SH		 1393
1394 if (status & XM_IS_TXF_UR) {
6b0c1480 1395 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1396 ++skge->net_stats.tx_fifo_errors;
1397 }
1398 if (status & XM_IS_RXF_OV) {
6b0c1480 1399 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1400 ++skge->net_stats.rx_fifo_errors;
1401 }
1402}
1403
baef58b1
SH		 1404static void genesis_link_up(struct skge_port *skge)
1405{
1406 struct skge_hw *hw = skge->hw;
1407 int port = skge->port;
1408 u16 cmd;
1409 u32 mode, msk;
1410
6b0c1480 1411 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1412
1413 /*
1414 * enabling pause frame reception is required for 1000BT
1415 * because the XMAC is not reset if the link is going down
1416 */
1417 if (skge->flow_control == FLOW_MODE_NONE ||
1418 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1419 /* Disable Pause Frame Reception */
baef58b1
SH		 1420 cmd |= XM_MMU_IGN_PF;
1421 else
1422 /* Enable Pause Frame Reception */
1423 cmd &= ~XM_MMU_IGN_PF;
1424
6b0c1480 1425 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1426
6b0c1480 1427 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1428 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1429 skge->flow_control == FLOW_MODE_LOC_SEND) {
1430 /*
1431 * Configure Pause Frame Generation
1432 * Use internal and external Pause Frame Generation.
1433 * Sending pause frames is edge triggered.
1434 * Send a Pause frame with the maximum pause time if
1435 * internal oder external FIFO full condition occurs.
1436 * Send a zero pause time frame to re-start transmission.
1437 */
1438 /* XM_PAUSE_DA = '010000C28001' (default) */
1439 /* XM_MAC_PTIME = 0xffff (maximum) */
1440 /* remember this value is defined in big endian (!) */
6b0c1480 1441 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1442
1443 mode |= XM_PAUSE_MODE;
6b0c1480 1444 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1445 } else {
1446 /*
1447 * disable pause frame generation is required for 1000BT
1448 * because the XMAC is not reset if the link is going down
1449 */
1450 /* Disable Pause Mode in Mode Register */
1451 mode &= ~XM_PAUSE_MODE;
1452
6b0c1480 1453 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1454 }
1455
6b0c1480 1456 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1457
1458 msk = XM_DEF_MSK;
89bf5f23
SH		 1459 /* disable GP0 interrupt bit for external Phy */
1460 msk |= XM_IS_INP_ASS;
baef58b1 1461
6b0c1480
SH		 1462 xm_write16(hw, port, XM_IMSK, msk);
1463 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1464
1465 /* get MMU Command Reg. */
6b0c1480 1466 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1467 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1468 cmd |= XM_MMU_GMII_FD;
1469
89bf5f23
SH		 1470 /*
1471 * Workaround BCOM Errata (#10523) for all BCom Phys
1472 * Enable Power Management after link up
1473 */
1474 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1475 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1476 & ~PHY_B_AC_DIS_PM);
1477 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1478
1479 /* enable Rx/Tx */
6b0c1480 1480 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1481 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1482 skge_link_up(skge);
1483}
1484
1485
45bada65 1486static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1487{
1488 struct skge_hw *hw = skge->hw;
1489 int port = skge->port;
45bada65
SH		 1490 u16 isrc;
1491
1492 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1493 if (netif_msg_intr(skge))
1494 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1495 skge->netdev->name, isrc);
baef58b1 1496
45bada65
SH		 1497 if (isrc & PHY_B_IS_PSE)
1498 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1499 hw->dev[port]->name);
baef58b1
SH		 1500
1501 /* Workaround BCom Errata:
1502 * enable and disable loopback mode if "NO HCD" occurs.
1503 */
45bada65 1504 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1505 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1506 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1507 ctrl | PHY_CT_LOOP);
6b0c1480 1508 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1509 ctrl & ~PHY_CT_LOOP);
1510 }
1511
45bada65
SH		 1512 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1513 bcom_check_link(hw, port);
baef58b1 1514
baef58b1
SH		 1515}
1516
2cd8e5d3
SH		 1517static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1518{
1519 int i;
1520
1521 gma_write16(hw, port, GM_SMI_DATA, val);
1522 gma_write16(hw, port, GM_SMI_CTRL,
1523 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1524 for (i = 0; i < PHY_RETRIES; i++) {
1525 udelay(1);
1526
1527 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1528 return 0;
1529 }
1530
1531 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1532 hw->dev[port]->name);
1533 return -EIO;
1534}
1535
1536static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1537{
1538 int i;
1539
1540 gma_write16(hw, port, GM_SMI_CTRL,
1541 GM_SMI_CT_PHY_AD(hw->phy_addr)
1542 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1543
1544 for (i = 0; i < PHY_RETRIES; i++) {
1545 udelay(1);
1546 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1547 goto ready;
1548 }
1549
1550 return -ETIMEDOUT;
1551 ready:
1552 *val = gma_read16(hw, port, GM_SMI_DATA);
1553 return 0;
1554}
1555
1556static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1557{
1558 u16 v = 0;
1559 if (__gm_phy_read(hw, port, reg, &v))
1560 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1561 hw->dev[port]->name);
1562 return v;
1563}
1564
8f3f8193 1565/* Marvell Phy Initialization */
baef58b1
SH		 1566static void yukon_init(struct skge_hw *hw, int port)
1567{
1568 struct skge_port *skge = netdev_priv(hw->dev[port]);
1569 u16 ctrl, ct1000, adv;
baef58b1 1570
baef58b1 1571 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1572 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1573
1574 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1575 PHY_M_EC_MAC_S_MSK);
1576 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1577
c506a509 1578 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1579
6b0c1480 1580 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1581 }
1582
6b0c1480 1583 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1584 if (skge->autoneg == AUTONEG_DISABLE)
1585 ctrl &= ~PHY_CT_ANE;
1586
1587 ctrl |= PHY_CT_RESET;
6b0c1480 1588 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1589
1590 ctrl = 0;
1591 ct1000 = 0;
b18f2091 1592 adv = PHY_AN_CSMA;
baef58b1
SH		 1593
1594 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1595 if (hw->copper) {
baef58b1
SH		 1596 if (skge->advertising & ADVERTISED_1000baseT_Full)
1597 ct1000 |= PHY_M_1000C_AFD;
1598 if (skge->advertising & ADVERTISED_1000baseT_Half)
1599 ct1000 |= PHY_M_1000C_AHD;
1600 if (skge->advertising & ADVERTISED_100baseT_Full)
1601 adv |= PHY_M_AN_100_FD;
1602 if (skge->advertising & ADVERTISED_100baseT_Half)
1603 adv |= PHY_M_AN_100_HD;
1604 if (skge->advertising & ADVERTISED_10baseT_Full)
1605 adv |= PHY_M_AN_10_FD;
1606 if (skge->advertising & ADVERTISED_10baseT_Half)
1607 adv |= PHY_M_AN_10_HD;
45bada65 1608 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1609 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1610
45bada65
SH		 1611 /* Set Flow-control capabilities */
1612 adv |= phy_pause_map[skge->flow_control];
1613
baef58b1
SH		 1614 /* Restart Auto-negotiation */
1615 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1616 } else {
1617 /* forced speed/duplex settings */
1618 ct1000 = PHY_M_1000C_MSE;
1619
1620 if (skge->duplex == DUPLEX_FULL)
1621 ctrl |= PHY_CT_DUP_MD;
1622
1623 switch (skge->speed) {
1624 case SPEED_1000:
1625 ctrl |= PHY_CT_SP1000;
1626 break;
1627 case SPEED_100:
1628 ctrl |= PHY_CT_SP100;
1629 break;
1630 }
1631
1632 ctrl |= PHY_CT_RESET;
1633 }
1634
c506a509 1635 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1636
6b0c1480
SH		 1637 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1638 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1639
baef58b1
SH		 1640 /* Enable phy interrupt on autonegotiation complete (or link up) */
1641 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1642 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1643 else
4cde06ed 1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1645}
1646
1647static void yukon_reset(struct skge_hw *hw, int port)
1648{
6b0c1480
SH		 1649 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1650 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1651 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1652 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1654
6b0c1480
SH		 1655 gma_write16(hw, port, GM_RX_CTRL,
1656 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1657 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1658}
1659
c8868611
SH		 1660/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1661static int is_yukon_lite_a0(struct skge_hw *hw)
1662{
1663 u32 reg;
1664 int ret;
1665
1666 if (hw->chip_id != CHIP_ID_YUKON)
1667 return 0;
1668
1669 reg = skge_read32(hw, B2_FAR);
1670 skge_write8(hw, B2_FAR + 3, 0xff);
1671 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1672 skge_write32(hw, B2_FAR, reg);
1673 return ret;
1674}
1675
baef58b1
SH		 1676static void yukon_mac_init(struct skge_hw *hw, int port)
1677{
1678 struct skge_port *skge = netdev_priv(hw->dev[port]);
1679 int i;
1680 u32 reg;
1681 const u8 *addr = hw->dev[port]->dev_addr;
1682
1683 /* WA code for COMA mode -- set PHY reset */
1684 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1685 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1686 reg = skge_read32(hw, B2_GP_IO);
1687 reg |= GP_DIR_9 | GP_IO_9;
1688 skge_write32(hw, B2_GP_IO, reg);
1689 }
baef58b1
SH		 1690
1691 /* hard reset */
6b0c1480
SH		 1692 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1693 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1694
1695 /* WA code for COMA mode -- clear PHY reset */
1696 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1697 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1698 reg = skge_read32(hw, B2_GP_IO);
1699 reg |= GP_DIR_9;
1700 reg &= ~GP_IO_9;
1701 skge_write32(hw, B2_GP_IO, reg);
1702 }
baef58b1
SH		 1703
1704 /* Set hardware config mode */
1705 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1706 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1707 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1708
1709 /* Clear GMC reset */
6b0c1480
SH		 1710 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1712 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1713
baef58b1
SH		 1714 if (skge->autoneg == AUTONEG_DISABLE) {
1715 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1716 gma_write16(hw, port, GM_GP_CTRL,
1717 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1718
1719 switch (skge->speed) {
1720 case SPEED_1000:
564f9abb 1721 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1722 reg |= GM_GPCR_SPEED_1000;
564f9abb 1723 break;
baef58b1 1724 case SPEED_100:
564f9abb 1725 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1726 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1727 break;
1728 case SPEED_10:
1729 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1730 break;
baef58b1
SH		 1731 }
1732
1733 if (skge->duplex == DUPLEX_FULL)
1734 reg |= GM_GPCR_DUP_FULL;
1735 } else
1736 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1737
baef58b1
SH		 1738 switch (skge->flow_control) {
1739 case FLOW_MODE_NONE:
6b0c1480 1740 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1741 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1742 break;
1743 case FLOW_MODE_LOC_SEND:
1744 /* disable Rx flow-control */
1745 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1746 }
1747
6b0c1480 1748 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1749 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1750
baef58b1 1751 yukon_init(hw, port);
baef58b1
SH		 1752
1753 /* MIB clear */
6b0c1480
SH		 1754 reg = gma_read16(hw, port, GM_PHY_ADDR);
1755 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1756
1757 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1758 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1759 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1760
1761 /* transmit control */
6b0c1480 1762 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1763
1764 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1765 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1766 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1767
1768 /* transmit flow control */
6b0c1480 1769 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1770
1771 /* transmit parameter */
6b0c1480 1772 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1773 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1774 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1775 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1776
1777 /* serial mode register */
1778 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1779 if (hw->dev[port]->mtu > 1500)
1780 reg |= GM_SMOD_JUMBO_ENA;
1781
6b0c1480 1782 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1783
1784 /* physical address: used for pause frames */
6b0c1480 1785 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1786 /* virtual address for data */
6b0c1480 1787 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1788
1789 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1790 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1791 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1793
1794 /* Initialize Mac Fifo */
1795
1796 /* Configure Rx MAC FIFO */
6b0c1480 1797 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1798 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1799
1800 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1801 if (is_yukon_lite_a0(hw))
baef58b1 1802 reg &= ~GMF_RX_F_FL_ON;
c8868611 1803
6b0c1480
SH		 1804 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1805 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1806 /*
1807 * because Pause Packet Truncation in GMAC is not working
1808 * we have to increase the Flush Threshold to 64 bytes
1809 * in order to flush pause packets in Rx FIFO on Yukon-1
1810 */
1811 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1812
1813 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1814 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1815 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1816}
1817
355ec572
SH		 1818/* Go into power down mode */
1819static void yukon_suspend(struct skge_hw *hw, int port)
1820{
1821 u16 ctrl;
1822
1823 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1824 ctrl |= PHY_M_PC_POL_R_DIS;
1825 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1826
1827 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1828 ctrl |= PHY_CT_RESET;
1829 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1830
1831 /* switch IEEE compatible power down mode on */
1832 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1833 ctrl |= PHY_CT_PDOWN;
1834 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1835}
1836
baef58b1
SH		 1837static void yukon_stop(struct skge_port *skge)
1838{
1839 struct skge_hw *hw = skge->hw;
1840 int port = skge->port;
1841
46a60f2d
SH		 1842 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1843 yukon_reset(hw, port);
baef58b1 1844
6b0c1480
SH		 1845 gma_write16(hw, port, GM_GP_CTRL,
1846 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1847 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1848 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1849
355ec572 1850 yukon_suspend(hw, port);
46a60f2d 1851
baef58b1 1852 /* set GPHY Control reset */
46a60f2d
SH		 1853 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1854 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1855}
1856
1857static void yukon_get_stats(struct skge_port *skge, u64 *data)
1858{
1859 struct skge_hw *hw = skge->hw;
1860 int port = skge->port;
1861 int i;
1862
6b0c1480
SH		 1863 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1864 | gma_read32(hw, port, GM_TXO_OK_LO);
1865 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1866 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1867
1868 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1869 data[i] = gma_read32(hw, port,
baef58b1
SH		 1870 skge_stats[i].gma_offset);
1871}
1872
1873static void yukon_mac_intr(struct skge_hw *hw, int port)
1874{
7e676d91
SH		 1875 struct net_device *dev = hw->dev[port];
1876 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1877 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1878
7e676d91
SH		 1879 if (netif_msg_intr(skge))
1880 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1881 dev->name, status);
1882
baef58b1
SH		 1883 if (status & GM_IS_RX_FF_OR) {
1884 ++skge->net_stats.rx_fifo_errors;
d8a09943 1885 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1886 }
d8a09943 1887
baef58b1
SH		 1888 if (status & GM_IS_TX_FF_UR) {
1889 ++skge->net_stats.tx_fifo_errors;
d8a09943 1890 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1891 }
1892
1893}
1894
1895static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1896{
95566065 1897 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1898 case PHY_M_PS_SPEED_1000:
1899 return SPEED_1000;
1900 case PHY_M_PS_SPEED_100:
1901 return SPEED_100;
1902 default:
1903 return SPEED_10;
1904 }
1905}
1906
1907static void yukon_link_up(struct skge_port *skge)
1908{
1909 struct skge_hw *hw = skge->hw;
1910 int port = skge->port;
1911 u16 reg;
1912
baef58b1 1913 /* Enable Transmit FIFO Underrun */
46a60f2d 1914 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1915
6b0c1480 1916 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1917 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1918 reg |= GM_GPCR_DUP_FULL;
1919
1920 /* enable Rx/Tx */
1921 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1922 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1923
4cde06ed 1924 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1925 skge_link_up(skge);
1926}
1927
1928static void yukon_link_down(struct skge_port *skge)
1929{
1930 struct skge_hw *hw = skge->hw;
1931 int port = skge->port;
d8a09943 1932 u16 ctrl;
baef58b1 1933
6b0c1480 1934 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1935
1936 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1937 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1938 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1939
c506a509 1940 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1941 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1942 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1943 gm_phy_read(hw, port,
baef58b1
SH		 1944 PHY_MARV_AUNE_ADV)
1945 | PHY_M_AN_ASP);
1946
1947 }
1948
1949 yukon_reset(hw, port);
1950 skge_link_down(skge);
1951
1952 yukon_init(hw, port);
1953}
1954
1955static void yukon_phy_intr(struct skge_port *skge)
1956{
1957 struct skge_hw *hw = skge->hw;
1958 int port = skge->port;
1959 const char *reason = NULL;
1960 u16 istatus, phystat;
1961
6b0c1480
SH		 1962 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1963 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1964
1965 if (netif_msg_intr(skge))
1966 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1967 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1968
1969 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1970 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1971 & PHY_M_AN_RF) {
1972 reason = "remote fault";
1973 goto failed;
1974 }
1975
c506a509 1976 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1977 reason = "master/slave fault";
1978 goto failed;
1979 }
1980
1981 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1982 reason = "speed/duplex";
1983 goto failed;
1984 }
1985
1986 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1987 ? DUPLEX_FULL : DUPLEX_HALF;
1988 skge->speed = yukon_speed(hw, phystat);
1989
baef58b1
SH		 1990 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1991 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1992 case PHY_M_PS_PAUSE_MSK:
1993 skge->flow_control = FLOW_MODE_SYMMETRIC;
1994 break;
1995 case PHY_M_PS_RX_P_EN:
1996 skge->flow_control = FLOW_MODE_REM_SEND;
1997 break;
1998 case PHY_M_PS_TX_P_EN:
1999 skge->flow_control = FLOW_MODE_LOC_SEND;
2000 break;
2001 default:
2002 skge->flow_control = FLOW_MODE_NONE;
2003 }
2004
2005 if (skge->flow_control == FLOW_MODE_NONE ||
2006 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2007 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2008 else
6b0c1480 2009 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2010 yukon_link_up(skge);
2011 return;
2012 }
2013
2014 if (istatus & PHY_M_IS_LSP_CHANGE)
2015 skge->speed = yukon_speed(hw, phystat);
2016
2017 if (istatus & PHY_M_IS_DUP_CHANGE)
2018 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2019 if (istatus & PHY_M_IS_LST_CHANGE) {
2020 if (phystat & PHY_M_PS_LINK_UP)
2021 yukon_link_up(skge);
2022 else
2023 yukon_link_down(skge);
2024 }
2025 return;
2026 failed:
2027 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2028 skge->netdev->name, reason);
2029
2030 /* XXX restart autonegotiation? */
2031}
2032
ee294dcd
SH		 2033static void skge_phy_reset(struct skge_port *skge)
2034{
2035 struct skge_hw *hw = skge->hw;
2036 int port = skge->port;
2037
2038 netif_stop_queue(skge->netdev);
2039 netif_carrier_off(skge->netdev);
2040
2041 spin_lock_bh(&hw->phy_lock);
2042 if (hw->chip_id == CHIP_ID_GENESIS) {
2043 genesis_reset(hw, port);
2044 genesis_mac_init(hw, port);
2045 } else {
2046 yukon_reset(hw, port);
2047 yukon_init(hw, port);
2048 }
2049 spin_unlock_bh(&hw->phy_lock);
2050}
2051
2cd8e5d3
SH		 2052/* Basic MII support */
2053static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054{
2055 struct mii_ioctl_data *data = if_mii(ifr);
2056 struct skge_port *skge = netdev_priv(dev);
2057 struct skge_hw *hw = skge->hw;
2058 int err = -EOPNOTSUPP;
2059
2060 if (!netif_running(dev))
2061 return -ENODEV; /* Phy still in reset */
2062
2063 switch(cmd) {
2064 case SIOCGMIIPHY:
2065 data->phy_id = hw->phy_addr;
2066
2067 /* fallthru */
2068 case SIOCGMIIREG: {
2069 u16 val = 0;
2070 spin_lock_bh(&hw->phy_lock);
2071 if (hw->chip_id == CHIP_ID_GENESIS)
2072 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2073 else
2074 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2075 spin_unlock_bh(&hw->phy_lock);
2076 data->val_out = val;
2077 break;
2078 }
2079
2080 case SIOCSMIIREG:
2081 if (!capable(CAP_NET_ADMIN))
2082 return -EPERM;
2083
2084 spin_lock_bh(&hw->phy_lock);
2085 if (hw->chip_id == CHIP_ID_GENESIS)
2086 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2087 data->val_in);
2088 else
2089 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2090 data->val_in);
2091 spin_unlock_bh(&hw->phy_lock);
2092 break;
2093 }
2094 return err;
2095}
2096
baef58b1
SH		 2097static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2098{
2099 u32 end;
2100
2101 start /= 8;
2102 len /= 8;
2103 end = start + len - 1;
2104
2105 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2106 skge_write32(hw, RB_ADDR(q, RB_START), start);
2107 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2108 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_END), end);
2110
2111 if (q == Q_R1 || q == Q_R2) {
2112 /* Set thresholds on receive queue's */
2113 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2114 start + (2*len)/3);
2115 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2116 start + (len/3));
2117 } else {
2118 /* Enable store & forward on Tx queue's because
2119 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2120 */
2121 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2122 }
2123
2124 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2125}
2126
2127/* Setup Bus Memory Interface */
2128static void skge_qset(struct skge_port *skge, u16 q,
2129 const struct skge_element *e)
2130{
2131 struct skge_hw *hw = skge->hw;
2132 u32 watermark = 0x600;
2133 u64 base = skge->dma + (e->desc - skge->mem);
2134
2135 /* optimization to reduce window on 32bit/33mhz */
2136 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2137 watermark /= 2;
2138
2139 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2140 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2141 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2142 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2143}
2144
2145static int skge_up(struct net_device *dev)
2146{
2147 struct skge_port *skge = netdev_priv(dev);
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 u32 chunk, ram_addr;
2151 size_t rx_size, tx_size;
2152 int err;
2153
2154 if (netif_msg_ifup(skge))
2155 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2156
19a33d4e 2157 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2158 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2159 else
2160 skge->rx_buf_size = RX_BUF_SIZE;
2161
2162
baef58b1
SH		 2163 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2164 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2165 skge->mem_size = tx_size + rx_size;
2166 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2167 if (!skge->mem)
2168 return -ENOMEM;
2169
c3da1447
SH		 2170 BUG_ON(skge->dma & 7);
2171
2172 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2173 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2174 err = -EINVAL;
2175 goto free_pci_mem;
2176 }
2177
baef58b1
SH		 2178 memset(skge->mem, 0, skge->mem_size);
2179
203babb6
SH		 2180 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2181 if (err)
baef58b1
SH		 2182 goto free_pci_mem;
2183
19a33d4e
SH		 2184 err = skge_rx_fill(skge);
2185 if (err)
baef58b1
SH		 2186 goto free_rx_ring;
2187
203babb6
SH		 2188 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2189 skge->dma + rx_size);
2190 if (err)
baef58b1
SH		 2191 goto free_rx_ring;
2192
2193 skge->tx_avail = skge->tx_ring.count - 1;
2194
8f3f8193 2195 /* Initialize MAC */
4ff6ac05 2196 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2197 if (hw->chip_id == CHIP_ID_GENESIS)
2198 genesis_mac_init(hw, port);
2199 else
2200 yukon_mac_init(hw, port);
4ff6ac05 2201 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2202
2203 /* Configure RAMbuffers */
981d0377 2204 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2205 ram_addr = hw->ram_offset + 2 * chunk * port;
2206
2207 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2208 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2209
2210 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2211 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2212 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2213
2214 /* Start receiver BMU */
2215 wmb();
2216 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2217 skge_led(skge, LED_MODE_ON);
baef58b1 2218
baef58b1
SH		 2219 return 0;
2220
2221 free_rx_ring:
2222 skge_rx_clean(skge);
2223 kfree(skge->rx_ring.start);
2224 free_pci_mem:
2225 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2226 skge->mem = NULL;
baef58b1
SH		 2227
2228 return err;
2229}
2230
2231static int skge_down(struct net_device *dev)
2232{
2233 struct skge_port *skge = netdev_priv(dev);
2234 struct skge_hw *hw = skge->hw;
2235 int port = skge->port;
2236
7731a4ea
SH		 2237 if (skge->mem == NULL)
2238 return 0;
2239
baef58b1
SH		 2240 if (netif_msg_ifdown(skge))
2241 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2242
2243 netif_stop_queue(dev);
2244
46a60f2d
SH		 2245 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2246 if (hw->chip_id == CHIP_ID_GENESIS)
2247 genesis_stop(skge);
2248 else
2249 yukon_stop(skge);
2250
baef58b1
SH		 2251 /* Stop transmitter */
2252 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2253 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2254 RB_RST_SET|RB_DIS_OP_MD);
2255
baef58b1
SH		 2256
2257 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2258 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2259 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2260
2261 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2262 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2263 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2264
2265 /* Reset PCI FIFO */
2266 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2267 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2268
2269 /* Reset the RAM Buffer async Tx queue */
2270 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2271 /* stop receiver */
2272 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2273 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2274 RB_RST_SET|RB_DIS_OP_MD);
2275 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2276
2277 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2278 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2279 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2280 } else {
6b0c1480
SH		 2281 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2282 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2283 }
2284
6abebb53 2285 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2286
2287 skge_tx_clean(skge);
2288 skge_rx_clean(skge);
2289
2290 kfree(skge->rx_ring.start);
2291 kfree(skge->tx_ring.start);
2292 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2293 skge->mem = NULL;
baef58b1
SH		 2294 return 0;
2295}
2296
2297static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2298{
2299 struct skge_port *skge = netdev_priv(dev);
2300 struct skge_hw *hw = skge->hw;
2301 struct skge_ring *ring = &skge->tx_ring;
2302 struct skge_element *e;
2303 struct skge_tx_desc *td;
2304 int i;
2305 u32 control, len;
2306 u64 map;
baef58b1
SH		 2307
2308 skb = skb_padto(skb, ETH_ZLEN);
2309 if (!skb)
2310 return NETDEV_TX_OK;
2311
baef58b1 2312 if (!spin_trylock(&skge->tx_lock)) {
203babb6
SH		 2313 /* Collision - tell upper layer to requeue */
2314 return NETDEV_TX_LOCKED;
2315 }
baef58b1
SH		 2316
2317 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
98684a9d 2318 if (!netif_queue_stopped(dev)) {
ee1c8191 2319 netif_stop_queue(dev);
baef58b1 2320
ee1c8191
SH		 2321 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2322 dev->name);
2323 }
00a6cae2 2324 spin_unlock(&skge->tx_lock);
baef58b1
SH		 2325 return NETDEV_TX_BUSY;
2326 }
2327
2328 e = ring->to_use;
2329 td = e->desc;
2330 e->skb = skb;
2331 len = skb_headlen(skb);
2332 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2333 pci_unmap_addr_set(e, mapaddr, map);
2334 pci_unmap_len_set(e, maplen, len);
2335
2336 td->dma_lo = map;
2337 td->dma_hi = map >> 32;
2338
2339 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2340 int offset = skb->h.raw - skb->data;
2341
2342 /* This seems backwards, but it is what the sk98lin
2343 * does. Looks like hardware is wrong?
2344 */
ea182d4a 2345 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2346 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2347 control = BMU_TCP_CHECK;
2348 else
2349 control = BMU_UDP_CHECK;
2350
2351 td->csum_offs = 0;
2352 td->csum_start = offset;
2353 td->csum_write = offset + skb->csum;
2354 } else
2355 control = BMU_CHECK;
2356
2357 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2358 control |= BMU_EOF| BMU_IRQ_EOF;
2359 else {
2360 struct skge_tx_desc *tf = td;
2361
2362 control |= BMU_STFWD;
2363 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2364 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2365
2366 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2367 frag->size, PCI_DMA_TODEVICE);
2368
2369 e = e->next;
2370 e->skb = NULL;
2371 tf = e->desc;
2372 tf->dma_lo = map;
2373 tf->dma_hi = (u64) map >> 32;
2374 pci_unmap_addr_set(e, mapaddr, map);
2375 pci_unmap_len_set(e, maplen, frag->size);
2376
2377 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2378 }
2379 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2380 }
2381 /* Make sure all the descriptors written */
2382 wmb();
2383 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2384 wmb();
2385
2386 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2387
2388 if (netif_msg_tx_queued(skge))
0b2d7fea 2389 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2390 dev->name, e - ring->start, skb->len);
2391
2392 ring->to_use = e->next;
2393 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2394 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2395 pr_debug("%s: transmit queue full\n", dev->name);
2396 netif_stop_queue(dev);
2397 }
2398
c68ce71a 2399 mmiowb();
00a6cae2 2400 spin_unlock(&skge->tx_lock);
baef58b1 2401
c68ce71a
SH		 2402 dev->trans_start = jiffies;
2403
baef58b1
SH		 2404 return NETDEV_TX_OK;
2405}
2406
2407static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2408{
19a33d4e 2409 /* This ring element can be skb or fragment */
baef58b1
SH		 2410 if (e->skb) {
2411 pci_unmap_single(hw->pdev,
2412 pci_unmap_addr(e, mapaddr),
2413 pci_unmap_len(e, maplen),
2414 PCI_DMA_TODEVICE);
00a6cae2 2415 dev_kfree_skb(e->skb);
baef58b1
SH		 2416 e->skb = NULL;
2417 } else {
2418 pci_unmap_page(hw->pdev,
2419 pci_unmap_addr(e, mapaddr),
2420 pci_unmap_len(e, maplen),
2421 PCI_DMA_TODEVICE);
2422 }
2423}
2424
2425static void skge_tx_clean(struct skge_port *skge)
2426{
2427 struct skge_ring *ring = &skge->tx_ring;
2428 struct skge_element *e;
baef58b1 2429
00a6cae2 2430 spin_lock_bh(&skge->tx_lock);
baef58b1
SH		 2431 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2432 ++skge->tx_avail;
2433 skge_tx_free(skge->hw, e);
2434 }
2435 ring->to_clean = e;
00a6cae2 2436 spin_unlock_bh(&skge->tx_lock);
baef58b1
SH		 2437}
2438
2439static void skge_tx_timeout(struct net_device *dev)
2440{
2441 struct skge_port *skge = netdev_priv(dev);
2442
2443 if (netif_msg_timer(skge))
2444 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2445
2446 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2447 skge_tx_clean(skge);
2448}
2449
2450static int skge_change_mtu(struct net_device *dev, int new_mtu)
2451{
7731a4ea 2452 int err;
baef58b1 2453
95566065 2454 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2455 return -EINVAL;
2456
7731a4ea
SH		 2457 if (!netif_running(dev)) {
2458 dev->mtu = new_mtu;
2459 return 0;
2460 }
2461
2462 skge_down(dev);
baef58b1 2463
19a33d4e 2464 dev->mtu = new_mtu;
7731a4ea
SH		 2465
2466 err = skge_up(dev);
2467 if (err)
2468 dev_close(dev);
baef58b1
SH		 2469
2470 return err;
2471}
2472
2473static void genesis_set_multicast(struct net_device *dev)
2474{
2475 struct skge_port *skge = netdev_priv(dev);
2476 struct skge_hw *hw = skge->hw;
2477 int port = skge->port;
2478 int i, count = dev->mc_count;
2479 struct dev_mc_list *list = dev->mc_list;
2480 u32 mode;
2481 u8 filter[8];
2482
6b0c1480 2483 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2484 mode |= XM_MD_ENA_HASH;
2485 if (dev->flags & IFF_PROMISC)
2486 mode |= XM_MD_ENA_PROM;
2487 else
2488 mode &= ~XM_MD_ENA_PROM;
2489
2490 if (dev->flags & IFF_ALLMULTI)
2491 memset(filter, 0xff, sizeof(filter));
2492 else {
2493 memset(filter, 0, sizeof(filter));
95566065 2494 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2495 u32 crc, bit;
2496 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2497 bit = ~crc & 0x3f;
baef58b1
SH		 2498 filter[bit/8] |= 1 << (bit%8);
2499 }
2500 }
2501
6b0c1480 2502 xm_write32(hw, port, XM_MODE, mode);
45bada65 2503 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2504}
2505
2506static void yukon_set_multicast(struct net_device *dev)
2507{
2508 struct skge_port *skge = netdev_priv(dev);
2509 struct skge_hw *hw = skge->hw;
2510 int port = skge->port;
2511 struct dev_mc_list *list = dev->mc_list;
2512 u16 reg;
2513 u8 filter[8];
2514
2515 memset(filter, 0, sizeof(filter));
2516
6b0c1480 2517 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2518 reg |= GM_RXCR_UCF_ENA;
2519
8f3f8193 2520 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2521 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2522 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2523 memset(filter, 0xff, sizeof(filter));
2524 else if (dev->mc_count == 0) /* no multicast */
2525 reg &= ~GM_RXCR_MCF_ENA;
2526 else {
2527 int i;
2528 reg |= GM_RXCR_MCF_ENA;
2529
95566065 2530 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2531 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2532 filter[bit/8] |= 1 << (bit%8);
2533 }
2534 }
2535
2536
6b0c1480 2537 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2538 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2539 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2540 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2541 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2542 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2543 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2544 (u16)filter[6] | ((u16)filter[7] << 8));
2545
6b0c1480 2546 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2547}
2548
383181ac
SH		 2549static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2550{
2551 if (hw->chip_id == CHIP_ID_GENESIS)
2552 return status >> XMR_FS_LEN_SHIFT;
2553 else
2554 return status >> GMR_FS_LEN_SHIFT;
2555}
2556
baef58b1
SH		 2557static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2558{
2559 if (hw->chip_id == CHIP_ID_GENESIS)
2560 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2561 else
2562 return (status & GMR_FS_ANY_ERR) ||
2563 (status & GMR_FS_RX_OK) == 0;
2564}
2565
19a33d4e
SH		 2566
2567/* Get receive buffer from descriptor.
2568 * Handles copy of small buffers and reallocation failures
2569 */
2570static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2571 struct skge_element *e,
383181ac 2572 u32 control, u32 status, u16 csum)
19a33d4e 2573{
383181ac
SH		 2574 struct sk_buff *skb;
2575 u16 len = control & BMU_BBC;
2576
2577 if (unlikely(netif_msg_rx_status(skge)))
2578 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2579 skge->netdev->name, e - skge->rx_ring.start,
2580 status, len);
2581
2582 if (len > skge->rx_buf_size)
2583 goto error;
2584
2585 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2586 goto error;
2587
2588 if (bad_phy_status(skge->hw, status))
2589 goto error;
2590
2591 if (phy_length(skge->hw, status) != len)
2592 goto error;
19a33d4e
SH		 2593
2594 if (len < RX_COPY_THRESHOLD) {
b5d56ddc 2595 skb = alloc_skb(len + 2, GFP_ATOMIC);
383181ac
SH		 2596 if (!skb)
2597 goto resubmit;
19a33d4e 2598
383181ac 2599 skb_reserve(skb, 2);
19a33d4e
SH		 2600 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2601 pci_unmap_addr(e, mapaddr),
2602 len, PCI_DMA_FROMDEVICE);
383181ac 2603 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2604 pci_dma_sync_single_for_device(skge->hw->pdev,
2605 pci_unmap_addr(e, mapaddr),
2606 len, PCI_DMA_FROMDEVICE);
19a33d4e 2607 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2608 } else {
383181ac 2609 struct sk_buff *nskb;
b5d56ddc 2610 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC);
383181ac
SH		 2611 if (!nskb)
2612 goto resubmit;
19a33d4e 2613
901ccefb 2614 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2615 pci_unmap_single(skge->hw->pdev,
2616 pci_unmap_addr(e, mapaddr),
2617 pci_unmap_len(e, maplen),
2618 PCI_DMA_FROMDEVICE);
2619 skb = e->skb;
383181ac 2620 prefetch(skb->data);
19a33d4e 2621 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2622 }
383181ac
SH		 2623
2624 skb_put(skb, len);
2625 skb->dev = skge->netdev;
2626 if (skge->rx_csum) {
2627 skb->csum = csum;
2628 skb->ip_summed = CHECKSUM_HW;
2629 }
2630
2631 skb->protocol = eth_type_trans(skb, skge->netdev);
2632
2633 return skb;
2634error:
2635
2636 if (netif_msg_rx_err(skge))
2637 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2638 skge->netdev->name, e - skge->rx_ring.start,
2639 control, status);
2640
2641 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2642 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2643 skge->net_stats.rx_length_errors++;
2644 if (status & XMR_FS_FRA_ERR)
2645 skge->net_stats.rx_frame_errors++;
2646 if (status & XMR_FS_FCS_ERR)
2647 skge->net_stats.rx_crc_errors++;
2648 } else {
2649 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2650 skge->net_stats.rx_length_errors++;
2651 if (status & GMR_FS_FRAGMENT)
2652 skge->net_stats.rx_frame_errors++;
2653 if (status & GMR_FS_CRC_ERR)
2654 skge->net_stats.rx_crc_errors++;
2655 }
2656
2657resubmit:
2658 skge_rx_reuse(e, skge->rx_buf_size);
2659 return NULL;
baef58b1
SH		 2660}
2661
00a6cae2
SH		 2662static void skge_tx_done(struct skge_port *skge)
2663{
2664 struct skge_ring *ring = &skge->tx_ring;
2665 struct skge_element *e;
2666
2667 spin_lock(&skge->tx_lock);
2668 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2669 struct skge_tx_desc *td = e->desc;
2670 u32 control;
2671
2672 rmb();
2673 control = td->control;
2674 if (control & BMU_OWN)
2675 break;
2676
2677 if (unlikely(netif_msg_tx_done(skge)))
2678 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2679 skge->netdev->name, e - ring->start, td->status);
2680
2681 skge_tx_free(skge->hw, e);
2682 e->skb = NULL;
2683 ++skge->tx_avail;
2684 }
2685 ring->to_clean = e;
2686 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2687
2688 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2689 netif_wake_queue(skge->netdev);
2690
2691 spin_unlock(&skge->tx_lock);
2692}
19a33d4e 2693
baef58b1
SH		 2694static int skge_poll(struct net_device *dev, int *budget)
2695{
2696 struct skge_port *skge = netdev_priv(dev);
2697 struct skge_hw *hw = skge->hw;
2698 struct skge_ring *ring = &skge->rx_ring;
2699 struct skge_element *e;
00a6cae2
SH		 2700 int to_do = min(dev->quota, *budget);
2701 int work_done = 0;
2702
2703 skge_tx_done(skge);
7e676d91 2704
1631aef1 2705 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2706 struct skge_rx_desc *rd = e->desc;
19a33d4e 2707 struct sk_buff *skb;
383181ac 2708 u32 control;
baef58b1
SH		 2709
2710 rmb();
2711 control = rd->control;
2712 if (control & BMU_OWN)
2713 break;
2714
203babb6
SH		 2715 skb = skge_rx_get(skge, e, control, rd->status,
2716 le16_to_cpu(rd->csum2));
19a33d4e 2717 if (likely(skb)) {
19a33d4e
SH		 2718 dev->last_rx = jiffies;
2719 netif_receive_skb(skb);
baef58b1 2720
19a33d4e
SH		 2721 ++work_done;
2722 } else
2723 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2724 }
2725 ring->to_clean = e;
2726
baef58b1
SH		 2727 /* restart receiver */
2728 wmb();
a9cdab86 2729 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2730
19a33d4e
SH		 2731 *budget -= work_done;
2732 dev->quota -= work_done;
2733
2734 if (work_done >= to_do)
2735 return 1; /* not done */
baef58b1 2736
cfc3ed79 2737 netif_rx_complete(dev);
c68ce71a
SH		 2738 mmiowb();
2739
cfc3ed79 2740 hw->intr_mask |= skge->port == 0 ? (IS_R1_F|IS_XA1_F) : (IS_R2_F|IS_XA2_F);
80dd857d 2741 skge_write32(hw, B0_IMSK, hw->intr_mask);
1631aef1 2742
19a33d4e 2743 return 0;
baef58b1
SH		 2744}
2745
f6620cab
SH		 2746/* Parity errors seem to happen when Genesis is connected to a switch
2747 * with no other ports present. Heartbeat error??
2748 */
baef58b1
SH		 2749static void skge_mac_parity(struct skge_hw *hw, int port)
2750{
f6620cab
SH		 2751 struct net_device *dev = hw->dev[port];
2752
2753 if (dev) {
2754 struct skge_port *skge = netdev_priv(dev);
2755 ++skge->net_stats.tx_heartbeat_errors;
2756 }
baef58b1
SH		 2757
2758 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2759 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2760 MFF_CLR_PERR);
2761 else
2762 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2763 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2764 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2765 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2766}
2767
baef58b1
SH		 2768static void skge_mac_intr(struct skge_hw *hw, int port)
2769{
95566065 2770 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2771 genesis_mac_intr(hw, port);
2772 else
2773 yukon_mac_intr(hw, port);
2774}
2775
2776/* Handle device specific framing and timeout interrupts */
2777static void skge_error_irq(struct skge_hw *hw)
2778{
2779 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2780
2781 if (hw->chip_id == CHIP_ID_GENESIS) {
2782 /* clear xmac errors */
2783 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2784 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2785 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2786 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2787 } else {
2788 /* Timestamp (unused) overflow */
2789 if (hwstatus & IS_IRQ_TIST_OV)
2790 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2791 }
2792
2793 if (hwstatus & IS_RAM_RD_PAR) {
2794 printk(KERN_ERR PFX "Ram read data parity error\n");
2795 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2796 }
2797
2798 if (hwstatus & IS_RAM_WR_PAR) {
2799 printk(KERN_ERR PFX "Ram write data parity error\n");
2800 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2801 }
2802
2803 if (hwstatus & IS_M1_PAR_ERR)
2804 skge_mac_parity(hw, 0);
2805
2806 if (hwstatus & IS_M2_PAR_ERR)
2807 skge_mac_parity(hw, 1);
2808
b9d64acc
SH		 2809 if (hwstatus & IS_R1_PAR_ERR) {
2810 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2811 hw->dev[0]->name);
baef58b1 2812 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 2813 }
baef58b1 2814
b9d64acc
SH		 2815 if (hwstatus & IS_R2_PAR_ERR) {
2816 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2817 hw->dev[1]->name);
baef58b1 2818 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 2819 }
baef58b1
SH		 2820
2821 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 2822 u16 pci_status, pci_cmd;
2823
2824 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2825 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 2826
b9d64acc
SH		 2827 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2828 pci_name(hw->pdev), pci_cmd, pci_status);
2829
2830 /* Write the error bits back to clear them. */
2831 pci_status &= PCI_STATUS_ERROR_BITS;
2832 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2833 pci_write_config_word(hw->pdev, PCI_COMMAND,
2834 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2835 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2836 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 2837
050ec18a 2838 /* if error still set then just ignore it */
baef58b1
SH		 2839 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2840 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 2841 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 2842 hw->intr_mask &= ~IS_HW_ERR;
2843 }
2844 }
2845}
2846
2847/*
8f3f8193 2848 * Interrupt from PHY are handled in tasklet (soft irq)
baef58b1
SH		 2849 * because accessing phy registers requires spin wait which might
2850 * cause excess interrupt latency.
2851 */
2852static void skge_extirq(unsigned long data)
2853{
2854 struct skge_hw *hw = (struct skge_hw *) data;
2855 int port;
2856
2857 spin_lock(&hw->phy_lock);
cfc3ed79 2858 for (port = 0; port < hw->ports; port++) {
baef58b1 2859 struct net_device *dev = hw->dev[port];
cfc3ed79 2860 struct skge_port *skge = netdev_priv(dev);
baef58b1 2861
cfc3ed79 2862 if (netif_running(dev)) {
baef58b1
SH		 2863 if (hw->chip_id != CHIP_ID_GENESIS)
2864 yukon_phy_intr(skge);
89bf5f23 2865 else
45bada65 2866 bcom_phy_intr(skge);
baef58b1
SH		 2867 }
2868 }
2869 spin_unlock(&hw->phy_lock);
2870
baef58b1
SH		 2871 hw->intr_mask |= IS_EXT_REG;
2872 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2873}
2874
2875static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2876{
2877 struct skge_hw *hw = dev_id;
cfc3ed79 2878 u32 status;
baef58b1 2879
cfc3ed79
SH		 2880 /* Reading this register masks IRQ */
2881 status = skge_read32(hw, B0_SP_ISRC);
2882 if (status == 0)
baef58b1
SH		 2883 return IRQ_NONE;
2884
cfc3ed79
SH		 2885 if (status & IS_EXT_REG) {
2886 hw->intr_mask &= ~IS_EXT_REG;
2887 tasklet_schedule(&hw->ext_tasklet);
2888 }
2889
00a6cae2 2890 if (status & (IS_R1_F|IS_XA1_F)) {
a9cdab86 2891 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2892 hw->intr_mask &= ~(IS_R1_F|IS_XA1_F);
a9cdab86 2893 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2894 }
2895
00a6cae2 2896 if (status & (IS_R2_F|IS_XA2_F)) {
a9cdab86 2897 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2898 hw->intr_mask &= ~(IS_R2_F|IS_XA2_F);
a9cdab86 2899 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2900 }
2901
cfc3ed79
SH		 2902 if (likely((status & hw->intr_mask) == 0))
2903 return IRQ_HANDLED;
2904
d25f5a67
SH		 2905 if (status & IS_PA_TO_RX1) {
2906 struct skge_port *skge = netdev_priv(hw->dev[0]);
2907 ++skge->net_stats.rx_over_errors;
2908 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2909 }
2910
2911 if (status & IS_PA_TO_RX2) {
2912 struct skge_port *skge = netdev_priv(hw->dev[1]);
2913 ++skge->net_stats.rx_over_errors;
2914 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2915 }
2916
2917 if (status & IS_PA_TO_TX1)
2918 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2919
2920 if (status & IS_PA_TO_TX2)
2921 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2922
baef58b1
SH		 2923 if (status & IS_MAC1)
2924 skge_mac_intr(hw, 0);
95566065 2925
baef58b1
SH		 2926 if (status & IS_MAC2)
2927 skge_mac_intr(hw, 1);
2928
2929 if (status & IS_HW_ERR)
2930 skge_error_irq(hw);
2931
7e676d91 2932 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2933
2934 return IRQ_HANDLED;
2935}
2936
2937#ifdef CONFIG_NET_POLL_CONTROLLER
2938static void skge_netpoll(struct net_device *dev)
2939{
2940 struct skge_port *skge = netdev_priv(dev);
2941
2942 disable_irq(dev->irq);
2943 skge_intr(dev->irq, skge->hw, NULL);
2944 enable_irq(dev->irq);
2945}
2946#endif
2947
2948static int skge_set_mac_address(struct net_device *dev, void *p)
2949{
2950 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2951 struct skge_hw *hw = skge->hw;
2952 unsigned port = skge->port;
2953 const struct sockaddr *addr = p;
baef58b1
SH		 2954
2955 if (!is_valid_ether_addr(addr->sa_data))
2956 return -EADDRNOTAVAIL;
2957
c2681dd8 2958 spin_lock_bh(&hw->phy_lock);
baef58b1 2959 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2960 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2961 dev->dev_addr, ETH_ALEN);
c2681dd8 2962 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2963 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2964
2965 if (hw->chip_id == CHIP_ID_GENESIS)
2966 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2967 else {
2968 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2969 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2970 }
2971 spin_unlock_bh(&hw->phy_lock);
2972
2973 return 0;
baef58b1
SH		 2974}
2975
2976static const struct {
2977 u8 id;
2978 const char *name;
2979} skge_chips[] = {
2980 { CHIP_ID_GENESIS, "Genesis" },
2981 { CHIP_ID_YUKON, "Yukon" },
2982 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2983 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2984};
2985
2986static const char *skge_board_name(const struct skge_hw *hw)
2987{
2988 int i;
2989 static char buf[16];
2990
2991 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2992 if (skge_chips[i].id == hw->chip_id)
2993 return skge_chips[i].name;
2994
2995 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2996 return buf;
2997}
2998
2999
3000/*
3001 * Setup the board data structure, but don't bring up
3002 * the port(s)
3003 */
3004static int skge_reset(struct skge_hw *hw)
3005{
adba9e23 3006 u32 reg;
b9d64acc 3007 u16 ctst, pci_status;
5e1705dd 3008 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 3009 int i;
baef58b1
SH		 3010
3011 ctst = skge_read16(hw, B0_CTST);
3012
3013 /* do a SW reset */
3014 skge_write8(hw, B0_CTST, CS_RST_SET);
3015 skge_write8(hw, B0_CTST, CS_RST_CLR);
3016
3017 /* clear PCI errors, if any */
b9d64acc
SH		 3018 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3019 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3020
b9d64acc
SH		 3021 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3022 pci_write_config_word(hw->pdev, PCI_STATUS,
3023 pci_status | PCI_STATUS_ERROR_BITS);
3024 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3025 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3026
3027 /* restore CLK_RUN bits (for Yukon-Lite) */
3028 skge_write16(hw, B0_CTST,
3029 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3030
3031 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 3032 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3033 pmd_type = skge_read8(hw, B2_PMD_TYP);
3034 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3035
95566065 3036 switch (hw->chip_id) {
baef58b1 3037 case CHIP_ID_GENESIS:
5e1705dd 3038 switch (phy_type) {
baef58b1
SH		 3039 case SK_PHY_BCOM:
3040 hw->phy_addr = PHY_ADDR_BCOM;
3041 break;
3042 default:
3043 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3044 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3045 return -EOPNOTSUPP;
3046 }
3047 break;
3048
3049 case CHIP_ID_YUKON:
3050 case CHIP_ID_YUKON_LITE:
3051 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3052 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3053 hw->copper = 1;
baef58b1
SH		 3054
3055 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3056 break;
3057
3058 default:
3059 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3060 pci_name(hw->pdev), hw->chip_id);
3061 return -EOPNOTSUPP;
3062 }
3063
981d0377
SH		 3064 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3065 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3066 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3067
3068 /* read the adapters RAM size */
3069 t8 = skge_read8(hw, B2_E_0);
3070 if (hw->chip_id == CHIP_ID_GENESIS) {
3071 if (t8 == 3) {
3072 /* special case: 4 x 64k x 36, offset = 0x80000 */
3073 hw->ram_size = 0x100000;
3074 hw->ram_offset = 0x80000;
3075 } else
3076 hw->ram_size = t8 * 512;
3077 }
3078 else if (t8 == 0)
3079 hw->ram_size = 0x20000;
3080 else
3081 hw->ram_size = t8 * 4096;
3082
cfc3ed79
SH		 3083 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3084 if (hw->ports > 1)
3085 hw->intr_mask |= IS_PORT_2;
3086
baef58b1
SH		 3087 if (hw->chip_id == CHIP_ID_GENESIS)
3088 genesis_init(hw);
3089 else {
3090 /* switch power to VCC (WA for VAUX problem) */
3091 skge_write8(hw, B0_POWER_CTRL,
3092 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3093
050ec18a
SH		 3094 /* avoid boards with stuck Hardware error bits */
3095 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3096 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3097 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3098 hw->intr_mask &= ~IS_HW_ERR;
3099 }
3100
adba9e23
SH		 3101 /* Clear PHY COMA */
3102 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3103 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3104 reg &= ~PCI_PHY_COMA;
3105 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3106 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3107
3108
981d0377 3109 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3110 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3111 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3112 }
3113 }
3114
3115 /* turn off hardware timer (unused) */
3116 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3117 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3118 skge_write8(hw, B0_LED, LED_STAT_ON);
3119
3120 /* enable the Tx Arbiters */
981d0377 3121 for (i = 0; i < hw->ports; i++)
6b0c1480 3122 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3123
3124 /* Initialize ram interface */
3125 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3126
3127 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3128 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3129 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3130 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3131 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3132 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3133 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3134 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3135 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3136 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3137 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3138 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3139
3140 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3141
3142 /* Set interrupt moderation for Transmit only
3143 * Receive interrupts avoided by NAPI
3144 */
3145 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3146 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3147 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3148
baef58b1
SH		 3149 skge_write32(hw, B0_IMSK, hw->intr_mask);
3150
baef58b1 3151 spin_lock_bh(&hw->phy_lock);
981d0377 3152 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3153 if (hw->chip_id == CHIP_ID_GENESIS)
3154 genesis_reset(hw, i);
3155 else
3156 yukon_reset(hw, i);
3157 }
3158 spin_unlock_bh(&hw->phy_lock);
3159
3160 return 0;
3161}
3162
3163/* Initialize network device */
981d0377
SH		 3164static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3165 int highmem)
baef58b1
SH		 3166{
3167 struct skge_port *skge;
3168 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3169
3170 if (!dev) {
3171 printk(KERN_ERR "skge etherdev alloc failed");
3172 return NULL;
3173 }
3174
3175 SET_MODULE_OWNER(dev);
3176 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3177 dev->open = skge_up;
3178 dev->stop = skge_down;
2cd8e5d3 3179 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3180 dev->hard_start_xmit = skge_xmit_frame;
3181 dev->get_stats = skge_get_stats;
3182 if (hw->chip_id == CHIP_ID_GENESIS)
3183 dev->set_multicast_list = genesis_set_multicast;
3184 else
3185 dev->set_multicast_list = yukon_set_multicast;
3186
3187 dev->set_mac_address = skge_set_mac_address;
3188 dev->change_mtu = skge_change_mtu;
3189 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3190 dev->tx_timeout = skge_tx_timeout;
3191 dev->watchdog_timeo = TX_WATCHDOG;
3192 dev->poll = skge_poll;
3193 dev->weight = NAPI_WEIGHT;
3194#ifdef CONFIG_NET_POLL_CONTROLLER
3195 dev->poll_controller = skge_netpoll;
3196#endif
3197 dev->irq = hw->pdev->irq;
3198 dev->features = NETIF_F_LLTX;
981d0377
SH		 3199 if (highmem)
3200 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3201
3202 skge = netdev_priv(dev);
3203 skge->netdev = dev;
3204 skge->hw = hw;
3205 skge->msg_enable = netif_msg_init(debug, default_msg);
3206 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3207 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3208
3209 /* Auto speed and flow control */
3210 skge->autoneg = AUTONEG_ENABLE;
3211 skge->flow_control = FLOW_MODE_SYMMETRIC;
3212 skge->duplex = -1;
3213 skge->speed = -1;
31b619c5 3214 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3215
3216 hw->dev[port] = dev;
3217
3218 skge->port = port;
3219
3220 spin_lock_init(&skge->tx_lock);
3221
baef58b1
SH		 3222 if (hw->chip_id != CHIP_ID_GENESIS) {
3223 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3224 skge->rx_csum = 1;
3225 }
3226
3227 /* read the mac address */
3228 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3229 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3230
3231 /* device is off until link detection */
3232 netif_carrier_off(dev);
3233 netif_stop_queue(dev);
3234
3235 return dev;
3236}
3237
3238static void __devinit skge_show_addr(struct net_device *dev)
3239{
3240 const struct skge_port *skge = netdev_priv(dev);
3241
3242 if (netif_msg_probe(skge))
3243 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3244 dev->name,
3245 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3246 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3247}
3248
3249static int __devinit skge_probe(struct pci_dev *pdev,
3250 const struct pci_device_id *ent)
3251{
3252 struct net_device *dev, *dev1;
3253 struct skge_hw *hw;
3254 int err, using_dac = 0;
3255
203babb6
SH		 3256 err = pci_enable_device(pdev);
3257 if (err) {
baef58b1
SH		 3258 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3259 pci_name(pdev));
3260 goto err_out;
3261 }
3262
203babb6
SH		 3263 err = pci_request_regions(pdev, DRV_NAME);
3264 if (err) {
baef58b1
SH		 3265 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3266 pci_name(pdev));
3267 goto err_out_disable_pdev;
3268 }
3269
3270 pci_set_master(pdev);
3271
93aea718 3272 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3273 using_dac = 1;
77783a78 3274 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3275 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3276 using_dac = 0;
3277 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3278 }
3279
3280 if (err) {
3281 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3282 pci_name(pdev));
3283 goto err_out_free_regions;
baef58b1
SH		 3284 }
3285
3286#ifdef __BIG_ENDIAN
8f3f8193 3287 /* byte swap descriptors in hardware */
baef58b1
SH		 3288 {
3289 u32 reg;
3290
3291 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3292 reg |= PCI_REV_DESC;
3293 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3294 }
3295#endif
3296
3297 err = -ENOMEM;
7e863061 3298 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3299 if (!hw) {
3300 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3301 pci_name(pdev));
3302 goto err_out_free_regions;
3303 }
3304
baef58b1
SH		 3305 hw->pdev = pdev;
3306 spin_lock_init(&hw->phy_lock);
3307 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3308
3309 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3310 if (!hw->regs) {
3311 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3312 pci_name(pdev));
3313 goto err_out_free_hw;
3314 }
3315
203babb6
SH		 3316 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3317 if (err) {
baef58b1
SH		 3318 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3319 pci_name(pdev), pdev->irq);
3320 goto err_out_iounmap;
3321 }
3322 pci_set_drvdata(pdev, hw);
3323
3324 err = skge_reset(hw);
3325 if (err)
3326 goto err_out_free_irq;
3327
d7eaee08 3328 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3329 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3330 skge_board_name(hw), hw->chip_rev);
baef58b1 3331
981d0377 3332 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3333 goto err_out_led_off;
3334
203babb6
SH		 3335 err = register_netdev(dev);
3336 if (err) {
baef58b1
SH		 3337 printk(KERN_ERR PFX "%s: cannot register net device\n",
3338 pci_name(pdev));
3339 goto err_out_free_netdev;
3340 }
3341
3342 skge_show_addr(dev);
3343
981d0377 3344 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3345 if (register_netdev(dev1) == 0)
3346 skge_show_addr(dev1);
3347 else {
3348 /* Failure to register second port need not be fatal */
3349 printk(KERN_WARNING PFX "register of second port failed\n");
3350 hw->dev[1] = NULL;
3351 free_netdev(dev1);
3352 }
3353 }
3354
3355 return 0;
3356
3357err_out_free_netdev:
3358 free_netdev(dev);
3359err_out_led_off:
3360 skge_write16(hw, B0_LED, LED_STAT_OFF);
3361err_out_free_irq:
3362 free_irq(pdev->irq, hw);
3363err_out_iounmap:
3364 iounmap(hw->regs);
3365err_out_free_hw:
3366 kfree(hw);
3367err_out_free_regions:
3368 pci_release_regions(pdev);
3369err_out_disable_pdev:
3370 pci_disable_device(pdev);
3371 pci_set_drvdata(pdev, NULL);
3372err_out:
3373 return err;
3374}
3375
3376static void __devexit skge_remove(struct pci_dev *pdev)
3377{
3378 struct skge_hw *hw = pci_get_drvdata(pdev);
3379 struct net_device *dev0, *dev1;
3380
95566065 3381 if (!hw)
baef58b1
SH		 3382 return;
3383
3384 if ((dev1 = hw->dev[1]))
3385 unregister_netdev(dev1);
3386 dev0 = hw->dev[0];
3387 unregister_netdev(dev0);
3388
46a60f2d
SH		 3389 skge_write32(hw, B0_IMSK, 0);
3390 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3391 skge_write8(hw, B0_CTST, CS_RST_SET);
3392
baef58b1
SH		 3393 tasklet_kill(&hw->ext_tasklet);
3394
3395 free_irq(pdev->irq, hw);
3396 pci_release_regions(pdev);
3397 pci_disable_device(pdev);
3398 if (dev1)
3399 free_netdev(dev1);
3400 free_netdev(dev0);
46a60f2d 3401
baef58b1
SH		 3402 iounmap(hw->regs);
3403 kfree(hw);
3404 pci_set_drvdata(pdev, NULL);
3405}
3406
3407#ifdef CONFIG_PM
2a569579 3408static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3409{
3410 struct skge_hw *hw = pci_get_drvdata(pdev);
3411 int i, wol = 0;
3412
95566065 3413 for (i = 0; i < 2; i++) {
baef58b1
SH		 3414 struct net_device *dev = hw->dev[i];
3415
3416 if (dev) {
3417 struct skge_port *skge = netdev_priv(dev);
3418 if (netif_running(dev)) {
3419 netif_carrier_off(dev);
46a60f2d
SH		 3420 if (skge->wol)
3421 netif_stop_queue(dev);
3422 else
3423 skge_down(dev);
baef58b1
SH		 3424 }
3425 netif_device_detach(dev);
3426 wol |= skge->wol;
3427 }
3428 }
3429
3430 pci_save_state(pdev);
2a569579 3431 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3432 pci_disable_device(pdev);
3433 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3434
3435 return 0;
3436}
3437
3438static int skge_resume(struct pci_dev *pdev)
3439{
3440 struct skge_hw *hw = pci_get_drvdata(pdev);
3441 int i;
3442
3443 pci_set_power_state(pdev, PCI_D0);
3444 pci_restore_state(pdev);
3445 pci_enable_wake(pdev, PCI_D0, 0);
3446
3447 skge_reset(hw);
3448
95566065 3449 for (i = 0; i < 2; i++) {
baef58b1
SH		 3450 struct net_device *dev = hw->dev[i];
3451 if (dev) {
3452 netif_device_attach(dev);
edd702e8
SH		 3453 if (netif_running(dev) && skge_up(dev))
3454 dev_close(dev);
baef58b1
SH		 3455 }
3456 }
3457 return 0;
3458}
3459#endif
3460
3461static struct pci_driver skge_driver = {
3462 .name = DRV_NAME,
3463 .id_table = skge_id_table,
3464 .probe = skge_probe,
3465 .remove = __devexit_p(skge_remove),
3466#ifdef CONFIG_PM
3467 .suspend = skge_suspend,
3468 .resume = skge_resume,
3469#endif
3470};
3471
3472static int __init skge_init_module(void)
3473{
3474 return pci_module_init(&skge_driver);
3475}
3476
3477static void __exit skge_cleanup_module(void)
3478{
3479 pci_unregister_driver(&skge_driver);
3480}
3481
3482module_init(skge_init_module);
3483module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)