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[PATCH] skge: remove SK-9EE support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
747802ab 45#define DRV_VERSION "0.7"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 52#define RX_COPY_THRESHOLD 128
53#define RX_BUF_SIZE 1536
baef58b1
SH		 54#define PHY_RETRIES 1000
55#define ETH_JUMBO_MTU 9000
56#define TX_WATCHDOG (5 * HZ)
57#define NAPI_WEIGHT 64
58#define BLINK_HZ (HZ/4)
baef58b1
SH		 59
60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62MODULE_LICENSE("GPL");
63MODULE_VERSION(DRV_VERSION);
64
65static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69static int debug = -1; /* defaults above */
70module_param(debug, int, 0);
71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 84 { 0 }
85};
86MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port);
96static void yukon_reset(struct skge_hw *hw, int port);
97static void genesis_mac_init(struct skge_hw *hw, int port);
98static void genesis_reset(struct skge_hw *hw, int port);
45bada65 99static void genesis_link_up(struct skge_port *skge);
baef58b1 100
7e676d91 101/* Avoid conditionals by using array */
baef58b1
SH		 102static const int txqaddr[] = { Q_XA1, Q_XA2 };
103static const int rxqaddr[] = { Q_R1, Q_R2 };
104static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 106static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1
SH		 107
108/* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111#define SKGE_REGS_LEN (29*128)
112
113static int skge_get_regs_len(struct net_device *dev)
114{
115 return SKGE_REGS_LEN;
116}
117
118/*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124{
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143}
144
145/* Wake on Lan only supported on Yukon chps with rev 1 or above */
146static int wol_supported(const struct skge_hw *hw)
147{
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 150}
151
152static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153{
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158}
159
160static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161{
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
95566065 165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183}
184
31b619c5
SH		 185/* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188static u32 skge_supported_modes(const struct skge_hw *hw)
189{
190 u32 supported;
191
192 if (iscopper(hw)) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214}
baef58b1
SH		 215
216static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218{
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 223 ecmd->supported = skge_supported_modes(hw);
baef58b1
SH		 224
225 if (iscopper(hw)) {
baef58b1
SH		 226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
31b619c5 228 } else
baef58b1 229 ecmd->port = PORT_FIBRE;
baef58b1
SH		 230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236}
237
baef58b1
SH		 238static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239{
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
31b619c5 242 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
baef58b1 248 } else {
31b619c5
SH		 249 u32 setting;
250
251 switch(ecmd->speed) {
baef58b1 252 case SPEED_1000:
31b619c5
SH		 253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
baef58b1
SH		 259 break;
260 case SPEED_100:
31b619c5
SH		 261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
baef58b1 269 case SPEED_10:
31b619c5
SH		 270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
baef58b1
SH		 275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
31b619c5
SH		 280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
baef58b1
SH		 286 }
287
288 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296}
297
298static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300{
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307}
308
309static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313} skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338};
339
340static int skge_get_stats_count(struct net_device *dev)
341{
342 return ARRAY_SIZE(skge_stats);
343}
344
345static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347{
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354}
355
356/* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360static struct net_device_stats *skge_get_stats(struct net_device *dev)
361{
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379}
380
381static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382{
383 int i;
384
95566065 385 switch (stringset) {
baef58b1
SH		 386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392}
393
394static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396{
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408}
409
410static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412{
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428}
429
430static u32 skge_get_msglevel(struct net_device *netdev)
431{
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434}
435
436static void skge_set_msglevel(struct net_device *netdev, u32 value)
437{
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440}
441
442static int skge_nway_reset(struct net_device *dev)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461}
462
463static int skge_set_sg(struct net_device *dev, u32 data)
464{
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471}
472
473static int skge_set_tx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482}
483
484static u32 skge_get_rx_csum(struct net_device *dev)
485{
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489}
490
491/* Only Yukon supports checksum offload. */
492static int skge_set_rx_csum(struct net_device *dev, u32 data)
493{
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501}
502
baef58b1
SH		 503static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505{
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514}
515
516static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518{
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 524 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 525 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 526 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536}
537
538/* Chip internal frequency for clock calculations */
539static inline u32 hwkhz(const struct skge_hw *hw)
540{
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 543 else
544 return 78215; /* or: 78.125 MHz */
545}
546
547/* Chip hz to microseconds */
548static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549{
550 return (ticks * 1000) / hwkhz(hw);
551}
552
553/* Microseconds to chip hz */
554static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555{
556 return hwkhz(hw) * usec / 1000;
557}
558
559static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561{
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580}
581
582/* Note: interrupt timer is per board, but can turn on/off per port */
583static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585{
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620}
621
622static void skge_led_on(struct skge_hw *hw, int port)
623{
624 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 625 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 626 skge_write8(hw, B0_LED, LED_STAT_ON);
627
6b0c1480
SH		 628 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
629 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
630 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 631
89bf5f23
SH		 632 /* For Broadcom Phy only */
633 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
baef58b1 634 } else {
6b0c1480
SH		 635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 637 PHY_M_LED_MO_DUP(MO_LED_ON) |
638 PHY_M_LED_MO_10(MO_LED_ON) |
639 PHY_M_LED_MO_100(MO_LED_ON) |
640 PHY_M_LED_MO_1000(MO_LED_ON) |
641 PHY_M_LED_MO_RX(MO_LED_ON));
642 }
643}
644
645static void skge_led_off(struct skge_hw *hw, int port)
646{
647 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 648 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 649 skge_write8(hw, B0_LED, LED_STAT_OFF);
650
6b0c1480
SH		 651 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
652 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1 653
89bf5f23
SH		 654 /* Broadcom only */
655 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
baef58b1 656 } else {
6b0c1480
SH		 657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 659 PHY_M_LED_MO_DUP(MO_LED_OFF) |
660 PHY_M_LED_MO_10(MO_LED_OFF) |
661 PHY_M_LED_MO_100(MO_LED_OFF) |
662 PHY_M_LED_MO_1000(MO_LED_OFF) |
663 PHY_M_LED_MO_RX(MO_LED_OFF));
664 }
665}
666
667static void skge_blink_timer(unsigned long data)
668{
669 struct skge_port *skge = (struct skge_port *) data;
670 struct skge_hw *hw = skge->hw;
671 unsigned long flags;
672
673 spin_lock_irqsave(&hw->phy_lock, flags);
674 if (skge->blink_on)
675 skge_led_on(hw, skge->port);
676 else
677 skge_led_off(hw, skge->port);
678 spin_unlock_irqrestore(&hw->phy_lock, flags);
679
680 skge->blink_on = !skge->blink_on;
681 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
682}
683
684/* blink LED's for finding board */
685static int skge_phys_id(struct net_device *dev, u32 data)
686{
687 struct skge_port *skge = netdev_priv(dev);
688
95566065 689 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 690 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
691
692 /* start blinking */
693 skge->blink_on = 1;
694 mod_timer(&skge->led_blink, jiffies+1);
695
696 msleep_interruptible(data * 1000);
697 del_timer_sync(&skge->led_blink);
698
699 skge_led_off(skge->hw, skge->port);
700
701 return 0;
702}
703
704static struct ethtool_ops skge_ethtool_ops = {
705 .get_settings = skge_get_settings,
706 .set_settings = skge_set_settings,
707 .get_drvinfo = skge_get_drvinfo,
708 .get_regs_len = skge_get_regs_len,
709 .get_regs = skge_get_regs,
710 .get_wol = skge_get_wol,
711 .set_wol = skge_set_wol,
712 .get_msglevel = skge_get_msglevel,
713 .set_msglevel = skge_set_msglevel,
714 .nway_reset = skge_nway_reset,
715 .get_link = ethtool_op_get_link,
716 .get_ringparam = skge_get_ring_param,
717 .set_ringparam = skge_set_ring_param,
718 .get_pauseparam = skge_get_pauseparam,
719 .set_pauseparam = skge_set_pauseparam,
720 .get_coalesce = skge_get_coalesce,
721 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 722 .get_sg = ethtool_op_get_sg,
723 .set_sg = skge_set_sg,
724 .get_tx_csum = ethtool_op_get_tx_csum,
725 .set_tx_csum = skge_set_tx_csum,
726 .get_rx_csum = skge_get_rx_csum,
727 .set_rx_csum = skge_set_rx_csum,
728 .get_strings = skge_get_strings,
729 .phys_id = skge_phys_id,
730 .get_stats_count = skge_get_stats_count,
731 .get_ethtool_stats = skge_get_ethtool_stats,
732};
733
734/*
735 * Allocate ring elements and chain them together
736 * One-to-one association of board descriptors with ring elements
737 */
738static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
739{
740 struct skge_tx_desc *d;
741 struct skge_element *e;
742 int i;
743
744 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
745 if (!ring->start)
746 return -ENOMEM;
747
748 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
749 e->desc = d;
19a33d4e 750 e->skb = NULL;
baef58b1
SH		 751 if (i == ring->count - 1) {
752 e->next = ring->start;
753 d->next_offset = base;
754 } else {
755 e->next = e + 1;
756 d->next_offset = base + (i+1) * sizeof(*d);
757 }
758 }
759 ring->to_use = ring->to_clean = ring->start;
760
761 return 0;
762}
763
19a33d4e 764static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
baef58b1 765{
19a33d4e 766 struct sk_buff *skb = dev_alloc_skb(size);
baef58b1 767
19a33d4e
SH		 768 if (likely(skb)) {
769 skb->dev = dev;
770 skb_reserve(skb, NET_IP_ALIGN);
baef58b1 771 }
19a33d4e
SH		 772 return skb;
773}
baef58b1 774
19a33d4e
SH		 775/* Allocate and setup a new buffer for receiving */
776static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
777 struct sk_buff *skb, unsigned int bufsize)
778{
779 struct skge_rx_desc *rd = e->desc;
780 u64 map;
baef58b1
SH		 781
782 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
783 PCI_DMA_FROMDEVICE);
784
785 rd->dma_lo = map;
786 rd->dma_hi = map >> 32;
787 e->skb = skb;
788 rd->csum1_start = ETH_HLEN;
789 rd->csum2_start = ETH_HLEN;
790 rd->csum1 = 0;
791 rd->csum2 = 0;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
796 pci_unmap_addr_set(e, mapaddr, map);
797 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 798}
799
19a33d4e
SH		 800/* Resume receiving using existing skb,
801 * Note: DMA address is not changed by chip.
802 * MTU not changed while receiver active.
803 */
804static void skge_rx_reuse(struct skge_element *e, unsigned int size)
805{
806 struct skge_rx_desc *rd = e->desc;
807
808 rd->csum2 = 0;
809 rd->csum2_start = ETH_HLEN;
810
811 wmb();
812
813 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
814}
815
816
817/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 818static void skge_rx_clean(struct skge_port *skge)
819{
820 struct skge_hw *hw = skge->hw;
821 struct skge_ring *ring = &skge->rx_ring;
822 struct skge_element *e;
823
19a33d4e
SH		 824 e = ring->start;
825 do {
baef58b1
SH		 826 struct skge_rx_desc *rd = e->desc;
827 rd->control = 0;
19a33d4e
SH		 828 if (e->skb) {
829 pci_unmap_single(hw->pdev,
830 pci_unmap_addr(e, mapaddr),
831 pci_unmap_len(e, maplen),
832 PCI_DMA_FROMDEVICE);
833 dev_kfree_skb(e->skb);
834 e->skb = NULL;
835 }
836 } while ((e = e->next) != ring->start);
baef58b1
SH		 837}
838
19a33d4e 839
baef58b1 840/* Allocate buffers for receive ring
19a33d4e 841 * For receive: to_clean is next received frame.
baef58b1
SH		 842 */
843static int skge_rx_fill(struct skge_port *skge)
844{
845 struct skge_ring *ring = &skge->rx_ring;
846 struct skge_element *e;
19a33d4e 847 unsigned int bufsize = skge->rx_buf_size;
baef58b1 848
19a33d4e
SH		 849 e = ring->start;
850 do {
851 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
baef58b1 852
19a33d4e
SH		 853 if (!skb)
854 return -ENOMEM;
855
856 skge_rx_setup(skge, e, skb, bufsize);
857 } while ( (e = e->next) != ring->start);
baef58b1 858
19a33d4e
SH		 859 ring->to_clean = ring->start;
860 return 0;
baef58b1
SH		 861}
862
863static void skge_link_up(struct skge_port *skge)
864{
865 netif_carrier_on(skge->netdev);
866 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
867 netif_wake_queue(skge->netdev);
868
869 if (netif_msg_link(skge))
870 printk(KERN_INFO PFX
871 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
872 skge->netdev->name, skge->speed,
873 skge->duplex == DUPLEX_FULL ? "full" : "half",
874 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
875 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
876 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
877 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
878 "unknown");
879}
880
881static void skge_link_down(struct skge_port *skge)
882{
883 netif_carrier_off(skge->netdev);
884 netif_stop_queue(skge->netdev);
885
886 if (netif_msg_link(skge))
887 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
888}
889
6b0c1480 890static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 891{
892 int i;
893 u16 v;
894
6b0c1480
SH		 895 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
896 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 897
89bf5f23
SH		 898 /* Need to wait for external PHY */
899 for (i = 0; i < PHY_RETRIES; i++) {
900 udelay(1);
901 if (xm_read16(hw, port, XM_MMU_CMD)
902 & XM_MMU_PHY_RDY)
903 goto ready;
baef58b1
SH		 904 }
905
89bf5f23
SH		 906 printk(KERN_WARNING PFX "%s: phy read timed out\n",
907 hw->dev[port]->name);
908 return 0;
909 ready:
910 v = xm_read16(hw, port, XM_PHY_DATA);
911
baef58b1
SH		 912 return v;
913}
914
6b0c1480 915static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 916{
917 int i;
918
6b0c1480 919 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 920 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 921 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 922 goto ready;
89bf5f23 923 udelay(1);
baef58b1
SH		 924 }
925 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
926 hw->dev[port]->name);
927
928
929 ready:
6b0c1480 930 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 931 for (i = 0; i < PHY_RETRIES; i++) {
932 udelay(1);
6b0c1480 933 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 934 return;
935 }
936 printk(KERN_WARNING PFX "%s: phy write timed out\n",
937 hw->dev[port]->name);
938}
939
940static void genesis_init(struct skge_hw *hw)
941{
942 /* set blink source counter */
943 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
944 skge_write8(hw, B2_BSC_CTRL, BSC_START);
945
946 /* configure mac arbiter */
947 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
948
949 /* configure mac arbiter timeout values */
950 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
951 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
952 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
953 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
954
955 skge_write8(hw, B3_MA_RCINI_RX1, 0);
956 skge_write8(hw, B3_MA_RCINI_RX2, 0);
957 skge_write8(hw, B3_MA_RCINI_TX1, 0);
958 skge_write8(hw, B3_MA_RCINI_TX2, 0);
959
960 /* configure packet arbiter timeout */
961 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
962 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
963 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
964 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
965 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
966}
967
968static void genesis_reset(struct skge_hw *hw, int port)
969{
45bada65 970 const u8 zero[8] = { 0 };
baef58b1
SH		 971
972 /* reset the statistics module */
6b0c1480
SH		 973 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
974 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
975 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
976 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
977 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 978
89bf5f23
SH		 979 /* disable Broadcom PHY IRQ */
980 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 981
45bada65 982 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 983}
984
985
45bada65
SH		 986/* Convert mode to MII values */
987static const u16 phy_pause_map[] = {
988 [FLOW_MODE_NONE] = 0,
989 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
990 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
991 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
992};
993
994
995/* Check status of Broadcom phy link */
996static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 997{
45bada65
SH		 998 struct net_device *dev = hw->dev[port];
999 struct skge_port *skge = netdev_priv(dev);
1000 u16 status;
1001
1002 /* read twice because of latch */
1003 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1004 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1005
1006 pr_debug("bcom_check_link status=0x%x\n", status);
1007
1008 if ((status & PHY_ST_LSYNC) == 0) {
1009 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1010 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1011 xm_write16(hw, port, XM_MMU_CMD, cmd);
1012 /* dummy read to ensure writing */
1013 (void) xm_read16(hw, port, XM_MMU_CMD);
1014
1015 if (netif_carrier_ok(dev))
1016 skge_link_down(skge);
1017 } else {
1018 if (skge->autoneg == AUTONEG_ENABLE &&
1019 (status & PHY_ST_AN_OVER)) {
1020 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1021 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1022
1023 if (lpa & PHY_B_AN_RF) {
1024 printk(KERN_NOTICE PFX "%s: remote fault\n",
1025 dev->name);
1026 return;
1027 }
1028
1029 /* Check Duplex mismatch */
1030 switch(aux & PHY_B_AS_AN_RES_MSK) {
1031 case PHY_B_RES_1000FD:
1032 skge->duplex = DUPLEX_FULL;
1033 break;
1034 case PHY_B_RES_1000HD:
1035 skge->duplex = DUPLEX_HALF;
1036 break;
1037 default:
1038 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1039 dev->name);
1040 return;
1041 }
1042
1043
1044 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1045 switch (aux & PHY_B_AS_PAUSE_MSK) {
1046 case PHY_B_AS_PAUSE_MSK:
1047 skge->flow_control = FLOW_MODE_SYMMETRIC;
1048 break;
1049 case PHY_B_AS_PRR:
1050 skge->flow_control = FLOW_MODE_REM_SEND;
1051 break;
1052 case PHY_B_AS_PRT:
1053 skge->flow_control = FLOW_MODE_LOC_SEND;
1054 break;
1055 default:
1056 skge->flow_control = FLOW_MODE_NONE;
1057 }
1058
1059 skge->speed = SPEED_1000;
1060 }
1061
1062 if (!netif_carrier_ok(dev))
1063 genesis_link_up(skge);
1064 }
1065}
1066
1067/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1068 * Phy on for 100 or 10Mbit operation
1069 */
1070static void bcom_phy_init(struct skge_port *skge, int jumbo)
1071{
1072 struct skge_hw *hw = skge->hw;
1073 int port = skge->port;
baef58b1 1074 int i;
45bada65 1075 u16 id1, r, ext, ctl;
baef58b1
SH		 1076
1077 /* magic workaround patterns for Broadcom */
1078 static const struct {
1079 u16 reg;
1080 u16 val;
1081 } A1hack[] = {
1082 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1083 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1084 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1085 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1086 }, C0hack[] = {
1087 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1088 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1089 };
1090
45bada65
SH		 1091 pr_debug("bcom_phy_init\n");
1092
1093 /* read Id from external PHY (all have the same address) */
1094 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1095
1096 /* Optimize MDIO transfer by suppressing preamble. */
1097 r = xm_read16(hw, port, XM_MMU_CMD);
1098 r |= XM_MMU_NO_PRE;
1099 xm_write16(hw, port, XM_MMU_CMD,r);
1100
1101 switch(id1) {
1102 case PHY_BCOM_ID1_C0:
1103 /*
1104 * Workaround BCOM Errata for the C0 type.
1105 * Write magic patterns to reserved registers.
1106 */
1107 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1108 xm_phy_write(hw, port,
1109 C0hack[i].reg, C0hack[i].val);
1110
1111 break;
1112 case PHY_BCOM_ID1_A1:
1113 /*
1114 * Workaround BCOM Errata for the A1 type.
1115 * Write magic patterns to reserved registers.
1116 */
1117 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1118 xm_phy_write(hw, port,
1119 A1hack[i].reg, A1hack[i].val);
1120 break;
1121 }
1122
1123 /*
1124 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1125 * Disable Power Management after reset.
1126 */
1127 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1128 r |= PHY_B_AC_DIS_PM;
1129 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1130
1131 /* Dummy read */
1132 xm_read16(hw, port, XM_ISRC);
1133
1134 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1135 ctl = PHY_CT_SP1000; /* always 1000mbit */
1136
1137 if (skge->autoneg == AUTONEG_ENABLE) {
1138 /*
1139 * Workaround BCOM Errata #1 for the C5 type.
1140 * 1000Base-T Link Acquisition Failure in Slave Mode
1141 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1142 */
1143 u16 adv = PHY_B_1000C_RD;
1144 if (skge->advertising & ADVERTISED_1000baseT_Half)
1145 adv |= PHY_B_1000C_AHD;
1146 if (skge->advertising & ADVERTISED_1000baseT_Full)
1147 adv |= PHY_B_1000C_AFD;
1148 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1149
1150 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1151 } else {
1152 if (skge->duplex == DUPLEX_FULL)
1153 ctl |= PHY_CT_DUP_MD;
1154 /* Force to slave */
1155 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1156 }
1157
1158 /* Set autonegotiation pause parameters */
1159 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1160 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1161
1162 /* Handle Jumbo frames */
1163 if (jumbo) {
1164 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1165 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1166
1167 ext |= PHY_B_PEC_HIGH_LA;
1168
1169 }
1170
1171 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1172 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1173
1174 /* Use link status change interrrupt */
1175 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1176
1177 bcom_check_link(hw, port);
1178}
1179
1180static void genesis_mac_init(struct skge_hw *hw, int port)
1181{
1182 struct net_device *dev = hw->dev[port];
1183 struct skge_port *skge = netdev_priv(dev);
1184 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1185 int i;
1186 u32 r;
1187 const u8 zero[6] = { 0 };
1188
1189 /* Clear MIB counters */
1190 xm_write16(hw, port, XM_STAT_CMD,
1191 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1192 /* Clear two times according to Errata #3 */
1193 xm_write16(hw, port, XM_STAT_CMD,
1194 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1
SH		 1195
1196 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1197 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1198 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1199
6b0c1480
SH		 1200 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1201 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1202
1203 /* Unreset the XMAC. */
6b0c1480 1204 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1205
1206 /*
1207 * Perform additional initialization for external PHYs,
1208 * namely for the 1000baseTX cards that use the XMAC's
1209 * GMII mode.
1210 */
1211 spin_lock_bh(&hw->phy_lock);
45bada65 1212 /* Take external Phy out of reset */
89bf5f23
SH		 1213 r = skge_read32(hw, B2_GP_IO);
1214 if (port == 0)
1215 r |= GP_DIR_0|GP_IO_0;
1216 else
1217 r |= GP_DIR_2|GP_IO_2;
1218
1219 skge_write32(hw, B2_GP_IO, r);
1220 skge_read32(hw, B2_GP_IO);
45bada65 1221 spin_unlock_bh(&hw->phy_lock);
89bf5f23 1222
45bada65 1223 /* Enable GMII interfac */
89bf5f23
SH		 1224 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1225
45bada65 1226 bcom_phy_init(skge, jumbo);
89bf5f23 1227
45bada65
SH		 1228 /* Set Station Address */
1229 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1230
45bada65
SH		 1231 /* We don't use match addresses so clear */
1232 for (i = 1; i < 16; i++)
1233 xm_outaddr(hw, port, XM_EXM(i), zero);
1234
1235 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1236 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1237
1238 /* We don't need the FCS appended to the packet. */
1239 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1240 if (jumbo)
1241 r |= XM_RX_BIG_PK_OK;
89bf5f23 1242
45bada65 1243 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1244 /*
45bada65
SH		 1245 * If in manual half duplex mode the other side might be in
1246 * full duplex mode, so ignore if a carrier extension is not seen
1247 * on frames received
89bf5f23 1248 */
45bada65 1249 r |= XM_RX_DIS_CEXT;
baef58b1 1250 }
45bada65 1251 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1252
baef58b1
SH		 1253
1254 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1255 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1256
1257 /*
1258 * Bump up the transmit threshold. This helps hold off transmit
1259 * underruns when we're blasting traffic from both ports at once.
1260 */
1261 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1262
1263 /*
1264 * Enable the reception of all error frames. This is is
1265 * a necessary evil due to the design of the XMAC. The
1266 * XMAC's receive FIFO is only 8K in size, however jumbo
1267 * frames can be up to 9000 bytes in length. When bad
1268 * frame filtering is enabled, the XMAC's RX FIFO operates
1269 * in 'store and forward' mode. For this to work, the
1270 * entire frame has to fit into the FIFO, but that means
1271 * that jumbo frames larger than 8192 bytes will be
1272 * truncated. Disabling all bad frame filtering causes
1273 * the RX FIFO to operate in streaming mode, in which
1274 * case the XMAC will start transfering frames out of the
1275 * RX FIFO as soon as the FIFO threshold is reached.
1276 */
45bada65 1277 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1278
baef58b1
SH		 1279
1280 /*
45bada65
SH		 1281 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1282 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1283 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1284 */
45bada65
SH		 1285 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1286
1287 /*
1288 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1289 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1290 * and 'Octets Tx OK Hi Cnt Ov'.
1291 */
1292 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1293
1294 /* Configure MAC arbiter */
1295 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1296
1297 /* configure timeout values */
1298 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1299 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1300 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1301 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1302
1303 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1304 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1305 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1306 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1307
1308 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1309 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1310 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1311 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1312
1313 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1314 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1315 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1316 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1317
45bada65 1318 if (jumbo) {
baef58b1 1319 /* Enable frame flushing if jumbo frames used */
6b0c1480 1320 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1321 } else {
1322 /* enable timeout timers if normal frames */
1323 skge_write16(hw, B3_PA_CTRL,
45bada65 1324 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1325 }
baef58b1
SH		 1326}
1327
1328static void genesis_stop(struct skge_port *skge)
1329{
1330 struct skge_hw *hw = skge->hw;
1331 int port = skge->port;
89bf5f23 1332 u32 reg;
baef58b1
SH		 1333
1334 /* Clear Tx packet arbiter timeout IRQ */
1335 skge_write16(hw, B3_PA_CTRL,
1336 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1337
1338 /*
1339 * If the transfer stucks at the MAC the STOP command will not
1340 * terminate if we don't flush the XMAC's transmit FIFO !
1341 */
6b0c1480
SH		 1342 xm_write32(hw, port, XM_MODE,
1343 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1344
1345
1346 /* Reset the MAC */
6b0c1480 1347 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1348
1349 /* For external PHYs there must be special handling */
89bf5f23
SH		 1350 reg = skge_read32(hw, B2_GP_IO);
1351 if (port == 0) {
1352 reg |= GP_DIR_0;
1353 reg &= ~GP_IO_0;
1354 } else {
1355 reg |= GP_DIR_2;
1356 reg &= ~GP_IO_2;
baef58b1 1357 }
89bf5f23
SH		 1358 skge_write32(hw, B2_GP_IO, reg);
1359 skge_read32(hw, B2_GP_IO);
baef58b1 1360
6b0c1480
SH		 1361 xm_write16(hw, port, XM_MMU_CMD,
1362 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1363 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1364
6b0c1480 1365 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1366}
1367
1368
1369static void genesis_get_stats(struct skge_port *skge, u64 *data)
1370{
1371 struct skge_hw *hw = skge->hw;
1372 int port = skge->port;
1373 int i;
1374 unsigned long timeout = jiffies + HZ;
1375
6b0c1480 1376 xm_write16(hw, port,
baef58b1
SH		 1377 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1378
1379 /* wait for update to complete */
6b0c1480 1380 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1381 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1382 if (time_after(jiffies, timeout))
1383 break;
1384 udelay(10);
1385 }
1386
1387 /* special case for 64 bit octet counter */
6b0c1480
SH		 1388 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1389 | xm_read32(hw, port, XM_TXO_OK_LO);
1390 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1391 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1392
1393 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1394 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1395}
1396
1397static void genesis_mac_intr(struct skge_hw *hw, int port)
1398{
1399 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1400 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1401
7e676d91
SH		 1402 if (netif_msg_intr(skge))
1403 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1404 skge->netdev->name, status);
baef58b1
SH		 1405
1406 if (status & XM_IS_TXF_UR) {
6b0c1480 1407 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1408 ++skge->net_stats.tx_fifo_errors;
1409 }
1410 if (status & XM_IS_RXF_OV) {
6b0c1480 1411 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1412 ++skge->net_stats.rx_fifo_errors;
1413 }
1414}
1415
6b0c1480 1416static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1417{
1418 int i;
1419
6b0c1480
SH		 1420 gma_write16(hw, port, GM_SMI_DATA, val);
1421 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1422 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1423 for (i = 0; i < PHY_RETRIES; i++) {
1424 udelay(1);
1425
6b0c1480 1426 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1427 break;
1428 }
1429}
1430
6b0c1480 1431static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1432{
1433 int i;
1434
6b0c1480 1435 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1436 GM_SMI_CT_PHY_AD(hw->phy_addr)
1437 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1438
1439 for (i = 0; i < PHY_RETRIES; i++) {
1440 udelay(1);
6b0c1480 1441 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1442 goto ready;
1443 }
1444
1445 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1446 hw->dev[port]->name);
1447 return 0;
1448 ready:
6b0c1480 1449 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1450}
1451
baef58b1
SH		 1452static void genesis_link_up(struct skge_port *skge)
1453{
1454 struct skge_hw *hw = skge->hw;
1455 int port = skge->port;
1456 u16 cmd;
1457 u32 mode, msk;
1458
1459 pr_debug("genesis_link_up\n");
6b0c1480 1460 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1461
1462 /*
1463 * enabling pause frame reception is required for 1000BT
1464 * because the XMAC is not reset if the link is going down
1465 */
1466 if (skge->flow_control == FLOW_MODE_NONE ||
1467 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1468 /* Disable Pause Frame Reception */
baef58b1
SH		 1469 cmd |= XM_MMU_IGN_PF;
1470 else
1471 /* Enable Pause Frame Reception */
1472 cmd &= ~XM_MMU_IGN_PF;
1473
6b0c1480 1474 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1475
6b0c1480 1476 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1477 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1478 skge->flow_control == FLOW_MODE_LOC_SEND) {
1479 /*
1480 * Configure Pause Frame Generation
1481 * Use internal and external Pause Frame Generation.
1482 * Sending pause frames is edge triggered.
1483 * Send a Pause frame with the maximum pause time if
1484 * internal oder external FIFO full condition occurs.
1485 * Send a zero pause time frame to re-start transmission.
1486 */
1487 /* XM_PAUSE_DA = '010000C28001' (default) */
1488 /* XM_MAC_PTIME = 0xffff (maximum) */
1489 /* remember this value is defined in big endian (!) */
6b0c1480 1490 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1491
1492 mode |= XM_PAUSE_MODE;
6b0c1480 1493 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1494 } else {
1495 /*
1496 * disable pause frame generation is required for 1000BT
1497 * because the XMAC is not reset if the link is going down
1498 */
1499 /* Disable Pause Mode in Mode Register */
1500 mode &= ~XM_PAUSE_MODE;
1501
6b0c1480 1502 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1503 }
1504
6b0c1480 1505 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1506
1507 msk = XM_DEF_MSK;
89bf5f23
SH		 1508 /* disable GP0 interrupt bit for external Phy */
1509 msk |= XM_IS_INP_ASS;
baef58b1 1510
6b0c1480
SH		 1511 xm_write16(hw, port, XM_IMSK, msk);
1512 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1513
1514 /* get MMU Command Reg. */
6b0c1480 1515 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1516 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1517 cmd |= XM_MMU_GMII_FD;
1518
89bf5f23
SH		 1519 /*
1520 * Workaround BCOM Errata (#10523) for all BCom Phys
1521 * Enable Power Management after link up
1522 */
1523 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1524 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1525 & ~PHY_B_AC_DIS_PM);
1526 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1527
1528 /* enable Rx/Tx */
6b0c1480 1529 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1530 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1531 skge_link_up(skge);
1532}
1533
1534
45bada65 1535static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1536{
1537 struct skge_hw *hw = skge->hw;
1538 int port = skge->port;
45bada65
SH		 1539 u16 isrc;
1540
1541 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1542 if (netif_msg_intr(skge))
1543 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1544 skge->netdev->name, isrc);
baef58b1 1545
45bada65
SH		 1546 if (isrc & PHY_B_IS_PSE)
1547 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1548 hw->dev[port]->name);
baef58b1
SH		 1549
1550 /* Workaround BCom Errata:
1551 * enable and disable loopback mode if "NO HCD" occurs.
1552 */
45bada65 1553 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1554 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1555 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1556 ctrl | PHY_CT_LOOP);
6b0c1480 1557 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1558 ctrl & ~PHY_CT_LOOP);
1559 }
1560
45bada65
SH		 1561 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1562 bcom_check_link(hw, port);
baef58b1 1563
baef58b1
SH		 1564}
1565
1566/* Marvell Phy Initailization */
1567static void yukon_init(struct skge_hw *hw, int port)
1568{
1569 struct skge_port *skge = netdev_priv(hw->dev[port]);
1570 u16 ctrl, ct1000, adv;
1571 u16 ledctrl, ledover;
1572
1573 pr_debug("yukon_init\n");
1574 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1575 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1576
1577 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1578 PHY_M_EC_MAC_S_MSK);
1579 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1580
c506a509 1581 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1582
6b0c1480 1583 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1584 }
1585
6b0c1480 1586 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1587 if (skge->autoneg == AUTONEG_DISABLE)
1588 ctrl &= ~PHY_CT_ANE;
1589
1590 ctrl |= PHY_CT_RESET;
6b0c1480 1591 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1592
1593 ctrl = 0;
1594 ct1000 = 0;
b18f2091 1595 adv = PHY_AN_CSMA;
baef58b1
SH		 1596
1597 if (skge->autoneg == AUTONEG_ENABLE) {
1598 if (iscopper(hw)) {
1599 if (skge->advertising & ADVERTISED_1000baseT_Full)
1600 ct1000 |= PHY_M_1000C_AFD;
1601 if (skge->advertising & ADVERTISED_1000baseT_Half)
1602 ct1000 |= PHY_M_1000C_AHD;
1603 if (skge->advertising & ADVERTISED_100baseT_Full)
1604 adv |= PHY_M_AN_100_FD;
1605 if (skge->advertising & ADVERTISED_100baseT_Half)
1606 adv |= PHY_M_AN_100_HD;
1607 if (skge->advertising & ADVERTISED_10baseT_Full)
1608 adv |= PHY_M_AN_10_FD;
1609 if (skge->advertising & ADVERTISED_10baseT_Half)
1610 adv |= PHY_M_AN_10_HD;
45bada65 1611 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1612 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1613
45bada65
SH		 1614 /* Set Flow-control capabilities */
1615 adv |= phy_pause_map[skge->flow_control];
1616
baef58b1
SH		 1617 /* Restart Auto-negotiation */
1618 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1619 } else {
1620 /* forced speed/duplex settings */
1621 ct1000 = PHY_M_1000C_MSE;
1622
1623 if (skge->duplex == DUPLEX_FULL)
1624 ctrl |= PHY_CT_DUP_MD;
1625
1626 switch (skge->speed) {
1627 case SPEED_1000:
1628 ctrl |= PHY_CT_SP1000;
1629 break;
1630 case SPEED_100:
1631 ctrl |= PHY_CT_SP100;
1632 break;
1633 }
1634
1635 ctrl |= PHY_CT_RESET;
1636 }
1637
c506a509 1638 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1639
6b0c1480
SH		 1640 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1641 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1642
1643 /* Setup Phy LED's */
1644 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1645 ledover = 0;
1646
c506a509 1647 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
baef58b1 1648
c506a509
SH		 1649 /* turn off the Rx LED (LED_RX) */
1650 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
baef58b1
SH		 1651
1652 /* disable blink mode (LED_DUPLEX) on collisions */
1653 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1655
1656 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1657 /* turn on 100 Mbps LED (LED_LINK100) */
1658 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1659 }
1660
1661 if (ledover)
6b0c1480 1662 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1663
1664 /* Enable phy interrupt on autonegotiation complete (or link up) */
1665 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1666 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1667 else
6b0c1480 1668 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1669}
1670
1671static void yukon_reset(struct skge_hw *hw, int port)
1672{
6b0c1480
SH		 1673 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1674 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1675 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1676 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1677 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1678
6b0c1480
SH		 1679 gma_write16(hw, port, GM_RX_CTRL,
1680 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1681 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1682}
1683
1684static void yukon_mac_init(struct skge_hw *hw, int port)
1685{
1686 struct skge_port *skge = netdev_priv(hw->dev[port]);
1687 int i;
1688 u32 reg;
1689 const u8 *addr = hw->dev[port]->dev_addr;
1690
1691 /* WA code for COMA mode -- set PHY reset */
1692 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1693 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1694 skge_write32(hw, B2_GP_IO,
1695 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1696
1697 /* hard reset */
6b0c1480
SH		 1698 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1699 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1700
1701 /* WA code for COMA mode -- clear PHY reset */
1702 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1703 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1704 skge_write32(hw, B2_GP_IO,
1705 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1706 & ~GP_IO_9);
1707
1708 /* Set hardware config mode */
1709 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1710 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1711 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1712
1713 /* Clear GMC reset */
6b0c1480
SH		 1714 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1715 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1716 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1717 if (skge->autoneg == AUTONEG_DISABLE) {
1718 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1719 gma_write16(hw, port, GM_GP_CTRL,
1720 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1721
1722 switch (skge->speed) {
1723 case SPEED_1000:
1724 reg |= GM_GPCR_SPEED_1000;
1725 /* fallthru */
1726 case SPEED_100:
1727 reg |= GM_GPCR_SPEED_100;
1728 }
1729
1730 if (skge->duplex == DUPLEX_FULL)
1731 reg |= GM_GPCR_DUP_FULL;
1732 } else
1733 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1734 switch (skge->flow_control) {
1735 case FLOW_MODE_NONE:
6b0c1480 1736 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1737 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1738 break;
1739 case FLOW_MODE_LOC_SEND:
1740 /* disable Rx flow-control */
1741 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1742 }
1743
6b0c1480 1744 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1745 skge_read16(hw, GMAC_IRQ_SRC);
1746
1747 spin_lock_bh(&hw->phy_lock);
1748 yukon_init(hw, port);
1749 spin_unlock_bh(&hw->phy_lock);
1750
1751 /* MIB clear */
6b0c1480
SH		 1752 reg = gma_read16(hw, port, GM_PHY_ADDR);
1753 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1754
1755 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1756 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1757 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1758
1759 /* transmit control */
6b0c1480 1760 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1761
1762 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1763 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1764 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1765
1766 /* transmit flow control */
6b0c1480 1767 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1768
1769 /* transmit parameter */
6b0c1480 1770 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1771 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1772 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1773 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1774
1775 /* serial mode register */
1776 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1777 if (hw->dev[port]->mtu > 1500)
1778 reg |= GM_SMOD_JUMBO_ENA;
1779
6b0c1480 1780 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1781
1782 /* physical address: used for pause frames */
6b0c1480 1783 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1784 /* virtual address for data */
6b0c1480 1785 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1786
1787 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1788 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1789 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1790 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1791
1792 /* Initialize Mac Fifo */
1793
1794 /* Configure Rx MAC FIFO */
6b0c1480 1795 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1796 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1797 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1798 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1 1799 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1800 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1801 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1802 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1803
1804 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1805 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1806 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1807}
1808
1809static void yukon_stop(struct skge_port *skge)
1810{
1811 struct skge_hw *hw = skge->hw;
1812 int port = skge->port;
1813
1814 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1815 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1816 skge_write32(hw, B2_GP_IO,
1817 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1818 }
1819
6b0c1480
SH		 1820 gma_write16(hw, port, GM_GP_CTRL,
1821 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1822 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1823 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1824
1825 /* set GPHY Control reset */
6b0c1480
SH		 1826 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1827 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1828}
1829
1830static void yukon_get_stats(struct skge_port *skge, u64 *data)
1831{
1832 struct skge_hw *hw = skge->hw;
1833 int port = skge->port;
1834 int i;
1835
6b0c1480
SH		 1836 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1837 | gma_read32(hw, port, GM_TXO_OK_LO);
1838 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1839 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1840
1841 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1842 data[i] = gma_read32(hw, port,
baef58b1
SH		 1843 skge_stats[i].gma_offset);
1844}
1845
1846static void yukon_mac_intr(struct skge_hw *hw, int port)
1847{
7e676d91
SH		 1848 struct net_device *dev = hw->dev[port];
1849 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1850 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1851
7e676d91
SH		 1852 if (netif_msg_intr(skge))
1853 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1854 dev->name, status);
1855
baef58b1
SH		 1856 if (status & GM_IS_RX_FF_OR) {
1857 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1858 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1859 }
1860 if (status & GM_IS_TX_FF_UR) {
1861 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1862 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1863 }
1864
1865}
1866
1867static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1868{
95566065 1869 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1870 case PHY_M_PS_SPEED_1000:
1871 return SPEED_1000;
1872 case PHY_M_PS_SPEED_100:
1873 return SPEED_100;
1874 default:
1875 return SPEED_10;
1876 }
1877}
1878
1879static void yukon_link_up(struct skge_port *skge)
1880{
1881 struct skge_hw *hw = skge->hw;
1882 int port = skge->port;
1883 u16 reg;
1884
1885 pr_debug("yukon_link_up\n");
1886
1887 /* Enable Transmit FIFO Underrun */
1888 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1889
6b0c1480 1890 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1891 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1892 reg |= GM_GPCR_DUP_FULL;
1893
1894 /* enable Rx/Tx */
1895 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1896 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1897
6b0c1480 1898 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1899 skge_link_up(skge);
1900}
1901
1902static void yukon_link_down(struct skge_port *skge)
1903{
1904 struct skge_hw *hw = skge->hw;
1905 int port = skge->port;
1906
1907 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1908 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1909 gm_phy_write(hw, port, GM_GP_CTRL,
1910 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1911 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1912
c506a509 1913 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1914 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1915 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1916 gm_phy_read(hw, port,
baef58b1
SH		 1917 PHY_MARV_AUNE_ADV)
1918 | PHY_M_AN_ASP);
1919
1920 }
1921
1922 yukon_reset(hw, port);
1923 skge_link_down(skge);
1924
1925 yukon_init(hw, port);
1926}
1927
1928static void yukon_phy_intr(struct skge_port *skge)
1929{
1930 struct skge_hw *hw = skge->hw;
1931 int port = skge->port;
1932 const char *reason = NULL;
1933 u16 istatus, phystat;
1934
6b0c1480
SH		 1935 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1936 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1937
1938 if (netif_msg_intr(skge))
1939 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1940 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1941
1942 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1943 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1944 & PHY_M_AN_RF) {
1945 reason = "remote fault";
1946 goto failed;
1947 }
1948
c506a509 1949 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1950 reason = "master/slave fault";
1951 goto failed;
1952 }
1953
1954 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1955 reason = "speed/duplex";
1956 goto failed;
1957 }
1958
1959 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1960 ? DUPLEX_FULL : DUPLEX_HALF;
1961 skge->speed = yukon_speed(hw, phystat);
1962
baef58b1
SH		 1963 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1964 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1965 case PHY_M_PS_PAUSE_MSK:
1966 skge->flow_control = FLOW_MODE_SYMMETRIC;
1967 break;
1968 case PHY_M_PS_RX_P_EN:
1969 skge->flow_control = FLOW_MODE_REM_SEND;
1970 break;
1971 case PHY_M_PS_TX_P_EN:
1972 skge->flow_control = FLOW_MODE_LOC_SEND;
1973 break;
1974 default:
1975 skge->flow_control = FLOW_MODE_NONE;
1976 }
1977
1978 if (skge->flow_control == FLOW_MODE_NONE ||
1979 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1980 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1981 else
6b0c1480 1982 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1983 yukon_link_up(skge);
1984 return;
1985 }
1986
1987 if (istatus & PHY_M_IS_LSP_CHANGE)
1988 skge->speed = yukon_speed(hw, phystat);
1989
1990 if (istatus & PHY_M_IS_DUP_CHANGE)
1991 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1992 if (istatus & PHY_M_IS_LST_CHANGE) {
1993 if (phystat & PHY_M_PS_LINK_UP)
1994 yukon_link_up(skge);
1995 else
1996 yukon_link_down(skge);
1997 }
1998 return;
1999 failed:
2000 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2001 skge->netdev->name, reason);
2002
2003 /* XXX restart autonegotiation? */
2004}
2005
2006static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2007{
2008 u32 end;
2009
2010 start /= 8;
2011 len /= 8;
2012 end = start + len - 1;
2013
2014 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2015 skge_write32(hw, RB_ADDR(q, RB_START), start);
2016 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2017 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2018 skge_write32(hw, RB_ADDR(q, RB_END), end);
2019
2020 if (q == Q_R1 || q == Q_R2) {
2021 /* Set thresholds on receive queue's */
2022 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2023 start + (2*len)/3);
2024 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2025 start + (len/3));
2026 } else {
2027 /* Enable store & forward on Tx queue's because
2028 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2029 */
2030 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2031 }
2032
2033 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2034}
2035
2036/* Setup Bus Memory Interface */
2037static void skge_qset(struct skge_port *skge, u16 q,
2038 const struct skge_element *e)
2039{
2040 struct skge_hw *hw = skge->hw;
2041 u32 watermark = 0x600;
2042 u64 base = skge->dma + (e->desc - skge->mem);
2043
2044 /* optimization to reduce window on 32bit/33mhz */
2045 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2046 watermark /= 2;
2047
2048 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2049 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2050 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2051 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2052}
2053
2054static int skge_up(struct net_device *dev)
2055{
2056 struct skge_port *skge = netdev_priv(dev);
2057 struct skge_hw *hw = skge->hw;
2058 int port = skge->port;
2059 u32 chunk, ram_addr;
2060 size_t rx_size, tx_size;
2061 int err;
2062
2063 if (netif_msg_ifup(skge))
2064 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2065
19a33d4e
SH		 2066 if (dev->mtu > RX_BUF_SIZE)
2067 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2068 else
2069 skge->rx_buf_size = RX_BUF_SIZE;
2070
2071
baef58b1
SH		 2072 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2073 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2074 skge->mem_size = tx_size + rx_size;
2075 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2076 if (!skge->mem)
2077 return -ENOMEM;
2078
2079 memset(skge->mem, 0, skge->mem_size);
2080
2081 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2082 goto free_pci_mem;
2083
19a33d4e
SH		 2084 err = skge_rx_fill(skge);
2085 if (err)
baef58b1
SH		 2086 goto free_rx_ring;
2087
2088 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2089 skge->dma + rx_size)))
2090 goto free_rx_ring;
2091
2092 skge->tx_avail = skge->tx_ring.count - 1;
2093
7e676d91
SH		 2094 /* Enable IRQ from port */
2095 hw->intr_mask |= portirqmask[port];
2096 skge_write32(hw, B0_IMSK, hw->intr_mask);
2097
baef58b1
SH		 2098 /* Initialze MAC */
2099 if (hw->chip_id == CHIP_ID_GENESIS)
2100 genesis_mac_init(hw, port);
2101 else
2102 yukon_mac_init(hw, port);
2103
2104 /* Configure RAMbuffers */
981d0377 2105 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2106 ram_addr = hw->ram_offset + 2 * chunk * port;
2107
2108 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2109 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2110
2111 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2112 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2113 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2114
2115 /* Start receiver BMU */
2116 wmb();
2117 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2118
2119 pr_debug("skge_up completed\n");
2120 return 0;
2121
2122 free_rx_ring:
2123 skge_rx_clean(skge);
2124 kfree(skge->rx_ring.start);
2125 free_pci_mem:
2126 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2127
2128 return err;
2129}
2130
2131static int skge_down(struct net_device *dev)
2132{
2133 struct skge_port *skge = netdev_priv(dev);
2134 struct skge_hw *hw = skge->hw;
2135 int port = skge->port;
2136
2137 if (netif_msg_ifdown(skge))
2138 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2139
2140 netif_stop_queue(dev);
2141
2142 del_timer_sync(&skge->led_blink);
baef58b1
SH		 2143
2144 /* Stop transmitter */
2145 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2146 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2147 RB_RST_SET|RB_DIS_OP_MD);
2148
2149 if (hw->chip_id == CHIP_ID_GENESIS)
2150 genesis_stop(skge);
2151 else
2152 yukon_stop(skge);
2153
2154 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2155 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2156 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2157
2158 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2159 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2160 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2161
2162 /* Reset PCI FIFO */
2163 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2164 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2165
2166 /* Reset the RAM Buffer async Tx queue */
2167 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2168 /* stop receiver */
2169 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2170 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2171 RB_RST_SET|RB_DIS_OP_MD);
2172 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2173
2174 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2175 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2176 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2177 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2178 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2179 } else {
6b0c1480
SH		 2180 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2181 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2182 }
2183
2184 /* turn off led's */
2185 skge_write16(hw, B0_LED, LED_STAT_OFF);
2186
2187 skge_tx_clean(skge);
2188 skge_rx_clean(skge);
2189
2190 kfree(skge->rx_ring.start);
2191 kfree(skge->tx_ring.start);
2192 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2193 return 0;
2194}
2195
2196static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2197{
2198 struct skge_port *skge = netdev_priv(dev);
2199 struct skge_hw *hw = skge->hw;
2200 struct skge_ring *ring = &skge->tx_ring;
2201 struct skge_element *e;
2202 struct skge_tx_desc *td;
2203 int i;
2204 u32 control, len;
2205 u64 map;
2206 unsigned long flags;
2207
2208 skb = skb_padto(skb, ETH_ZLEN);
2209 if (!skb)
2210 return NETDEV_TX_OK;
2211
2212 local_irq_save(flags);
2213 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2214 /* Collision - tell upper layer to requeue */
2215 local_irq_restore(flags);
2216 return NETDEV_TX_LOCKED;
2217 }
baef58b1
SH		 2218
2219 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2220 netif_stop_queue(dev);
2221 spin_unlock_irqrestore(&skge->tx_lock, flags);
2222
2223 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2224 dev->name);
2225 return NETDEV_TX_BUSY;
2226 }
2227
2228 e = ring->to_use;
2229 td = e->desc;
2230 e->skb = skb;
2231 len = skb_headlen(skb);
2232 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2233 pci_unmap_addr_set(e, mapaddr, map);
2234 pci_unmap_len_set(e, maplen, len);
2235
2236 td->dma_lo = map;
2237 td->dma_hi = map >> 32;
2238
2239 if (skb->ip_summed == CHECKSUM_HW) {
2240 const struct iphdr *ip
2241 = (const struct iphdr *) (skb->data + ETH_HLEN);
2242 int offset = skb->h.raw - skb->data;
2243
2244 /* This seems backwards, but it is what the sk98lin
2245 * does. Looks like hardware is wrong?
2246 */
2247 if (ip->protocol == IPPROTO_UDP
981d0377 2248 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2249 control = BMU_TCP_CHECK;
2250 else
2251 control = BMU_UDP_CHECK;
2252
2253 td->csum_offs = 0;
2254 td->csum_start = offset;
2255 td->csum_write = offset + skb->csum;
2256 } else
2257 control = BMU_CHECK;
2258
2259 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2260 control |= BMU_EOF| BMU_IRQ_EOF;
2261 else {
2262 struct skge_tx_desc *tf = td;
2263
2264 control |= BMU_STFWD;
2265 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2266 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2267
2268 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2269 frag->size, PCI_DMA_TODEVICE);
2270
2271 e = e->next;
2272 e->skb = NULL;
2273 tf = e->desc;
2274 tf->dma_lo = map;
2275 tf->dma_hi = (u64) map >> 32;
2276 pci_unmap_addr_set(e, mapaddr, map);
2277 pci_unmap_len_set(e, maplen, frag->size);
2278
2279 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2280 }
2281 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2282 }
2283 /* Make sure all the descriptors written */
2284 wmb();
2285 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2286 wmb();
2287
2288 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2289
2290 if (netif_msg_tx_queued(skge))
0b2d7fea 2291 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2292 dev->name, e - ring->start, skb->len);
2293
2294 ring->to_use = e->next;
2295 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2296 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2297 pr_debug("%s: transmit queue full\n", dev->name);
2298 netif_stop_queue(dev);
2299 }
2300
2301 dev->trans_start = jiffies;
2302 spin_unlock_irqrestore(&skge->tx_lock, flags);
2303
2304 return NETDEV_TX_OK;
2305}
2306
2307static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2308{
19a33d4e 2309 /* This ring element can be skb or fragment */
baef58b1
SH		 2310 if (e->skb) {
2311 pci_unmap_single(hw->pdev,
2312 pci_unmap_addr(e, mapaddr),
2313 pci_unmap_len(e, maplen),
2314 PCI_DMA_TODEVICE);
2315 dev_kfree_skb_any(e->skb);
2316 e->skb = NULL;
2317 } else {
2318 pci_unmap_page(hw->pdev,
2319 pci_unmap_addr(e, mapaddr),
2320 pci_unmap_len(e, maplen),
2321 PCI_DMA_TODEVICE);
2322 }
2323}
2324
2325static void skge_tx_clean(struct skge_port *skge)
2326{
2327 struct skge_ring *ring = &skge->tx_ring;
2328 struct skge_element *e;
2329 unsigned long flags;
2330
2331 spin_lock_irqsave(&skge->tx_lock, flags);
2332 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2333 ++skge->tx_avail;
2334 skge_tx_free(skge->hw, e);
2335 }
2336 ring->to_clean = e;
2337 spin_unlock_irqrestore(&skge->tx_lock, flags);
2338}
2339
2340static void skge_tx_timeout(struct net_device *dev)
2341{
2342 struct skge_port *skge = netdev_priv(dev);
2343
2344 if (netif_msg_timer(skge))
2345 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2346
2347 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2348 skge_tx_clean(skge);
2349}
2350
2351static int skge_change_mtu(struct net_device *dev, int new_mtu)
2352{
2353 int err = 0;
19a33d4e 2354 int running = netif_running(dev);
baef58b1 2355
95566065 2356 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2357 return -EINVAL;
2358
baef58b1 2359
19a33d4e 2360 if (running)
baef58b1 2361 skge_down(dev);
19a33d4e
SH		 2362 dev->mtu = new_mtu;
2363 if (running)
baef58b1 2364 skge_up(dev);
baef58b1
SH		 2365
2366 return err;
2367}
2368
2369static void genesis_set_multicast(struct net_device *dev)
2370{
2371 struct skge_port *skge = netdev_priv(dev);
2372 struct skge_hw *hw = skge->hw;
2373 int port = skge->port;
2374 int i, count = dev->mc_count;
2375 struct dev_mc_list *list = dev->mc_list;
2376 u32 mode;
2377 u8 filter[8];
2378
45bada65
SH		 2379 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2380
6b0c1480 2381 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2382 mode |= XM_MD_ENA_HASH;
2383 if (dev->flags & IFF_PROMISC)
2384 mode |= XM_MD_ENA_PROM;
2385 else
2386 mode &= ~XM_MD_ENA_PROM;
2387
2388 if (dev->flags & IFF_ALLMULTI)
2389 memset(filter, 0xff, sizeof(filter));
2390 else {
2391 memset(filter, 0, sizeof(filter));
95566065 2392 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2393 u32 crc, bit;
2394 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2395 bit = ~crc & 0x3f;
baef58b1
SH		 2396 filter[bit/8] |= 1 << (bit%8);
2397 }
2398 }
2399
6b0c1480 2400 xm_write32(hw, port, XM_MODE, mode);
45bada65 2401 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2402}
2403
2404static void yukon_set_multicast(struct net_device *dev)
2405{
2406 struct skge_port *skge = netdev_priv(dev);
2407 struct skge_hw *hw = skge->hw;
2408 int port = skge->port;
2409 struct dev_mc_list *list = dev->mc_list;
2410 u16 reg;
2411 u8 filter[8];
2412
2413 memset(filter, 0, sizeof(filter));
2414
6b0c1480 2415 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2416 reg |= GM_RXCR_UCF_ENA;
2417
2418 if (dev->flags & IFF_PROMISC) /* promiscious */
2419 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2420 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2421 memset(filter, 0xff, sizeof(filter));
2422 else if (dev->mc_count == 0) /* no multicast */
2423 reg &= ~GM_RXCR_MCF_ENA;
2424 else {
2425 int i;
2426 reg |= GM_RXCR_MCF_ENA;
2427
95566065 2428 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2429 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2430 filter[bit/8] |= 1 << (bit%8);
2431 }
2432 }
2433
2434
6b0c1480 2435 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2436 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2437 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2438 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2439 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2440 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2441 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2442 (u16)filter[6] | ((u16)filter[7] << 8));
2443
6b0c1480 2444 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2445}
2446
2447static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2448{
2449 if (hw->chip_id == CHIP_ID_GENESIS)
2450 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2451 else
2452 return (status & GMR_FS_ANY_ERR) ||
2453 (status & GMR_FS_RX_OK) == 0;
2454}
2455
2456static void skge_rx_error(struct skge_port *skge, int slot,
2457 u32 control, u32 status)
2458{
2459 if (netif_msg_rx_err(skge))
2460 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2461 skge->netdev->name, slot, control, status);
2462
19a33d4e 2463 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
baef58b1 2464 skge->net_stats.rx_length_errors++;
19a33d4e
SH		 2465 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2466 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2467 skge->net_stats.rx_length_errors++;
2468 if (status & XMR_FS_FRA_ERR)
2469 skge->net_stats.rx_frame_errors++;
2470 if (status & XMR_FS_FCS_ERR)
2471 skge->net_stats.rx_crc_errors++;
2472 } else {
2473 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2474 skge->net_stats.rx_length_errors++;
2475 if (status & GMR_FS_FRAGMENT)
2476 skge->net_stats.rx_frame_errors++;
2477 if (status & GMR_FS_CRC_ERR)
2478 skge->net_stats.rx_crc_errors++;
2479 }
2480}
2481
2482/* Get receive buffer from descriptor.
2483 * Handles copy of small buffers and reallocation failures
2484 */
2485static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2486 struct skge_element *e,
2487 unsigned int len)
2488{
2489 struct sk_buff *nskb, *skb;
2490
2491 if (len < RX_COPY_THRESHOLD) {
2492 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2493 if (unlikely(!nskb))
2494 return NULL;
2495
2496 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2497 pci_unmap_addr(e, mapaddr),
2498 len, PCI_DMA_FROMDEVICE);
2499 memcpy(nskb->data, e->skb->data, len);
2500 pci_dma_sync_single_for_device(skge->hw->pdev,
2501 pci_unmap_addr(e, mapaddr),
2502 len, PCI_DMA_FROMDEVICE);
2503
2504 if (skge->rx_csum) {
2505 struct skge_rx_desc *rd = e->desc;
2506 nskb->csum = le16_to_cpu(rd->csum2);
2507 nskb->ip_summed = CHECKSUM_HW;
baef58b1 2508 }
19a33d4e
SH		 2509 skge_rx_reuse(e, skge->rx_buf_size);
2510 return nskb;
2511 } else {
2512 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2513 if (unlikely(!nskb))
2514 return NULL;
2515
2516 pci_unmap_single(skge->hw->pdev,
2517 pci_unmap_addr(e, mapaddr),
2518 pci_unmap_len(e, maplen),
2519 PCI_DMA_FROMDEVICE);
2520 skb = e->skb;
2521 if (skge->rx_csum) {
2522 struct skge_rx_desc *rd = e->desc;
2523 skb->csum = le16_to_cpu(rd->csum2);
2524 skb->ip_summed = CHECKSUM_HW;
2525 }
2526
2527 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2528 return skb;
baef58b1
SH		 2529 }
2530}
2531
19a33d4e 2532
baef58b1
SH		 2533static int skge_poll(struct net_device *dev, int *budget)
2534{
2535 struct skge_port *skge = netdev_priv(dev);
2536 struct skge_hw *hw = skge->hw;
2537 struct skge_ring *ring = &skge->rx_ring;
2538 struct skge_element *e;
2539 unsigned int to_do = min(dev->quota, *budget);
2540 unsigned int work_done = 0;
7e676d91
SH		 2541
2542 pr_debug("skge_poll\n");
baef58b1 2543
19a33d4e 2544 for (e = ring->to_clean; work_done < to_do; e = e->next) {
baef58b1 2545 struct skge_rx_desc *rd = e->desc;
19a33d4e 2546 struct sk_buff *skb;
baef58b1
SH		 2547 u32 control, len, status;
2548
2549 rmb();
2550 control = rd->control;
2551 if (control & BMU_OWN)
2552 break;
2553
2554 len = control & BMU_BBC;
baef58b1 2555 status = rd->status;
19a33d4e
SH		 2556
2557 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2558 || bad_phy_status(hw, status))) {
baef58b1 2559 skge_rx_error(skge, e - ring->start, control, status);
19a33d4e 2560 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2561 continue;
2562 }
2563
2564 if (netif_msg_rx_status(skge))
0b2d7fea 2565 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2566 dev->name, e - ring->start, rd->status, len);
2567
19a33d4e
SH		 2568 skb = skge_rx_get(skge, e, len);
2569 if (likely(skb)) {
2570 skb_put(skb, len);
2571 skb->protocol = eth_type_trans(skb, dev);
baef58b1 2572
19a33d4e
SH		 2573 dev->last_rx = jiffies;
2574 netif_receive_skb(skb);
baef58b1 2575
19a33d4e
SH		 2576 ++work_done;
2577 } else
2578 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2579 }
2580 ring->to_clean = e;
2581
baef58b1
SH		 2582 /* restart receiver */
2583 wmb();
2584 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2585 CSR_START | CSR_IRQ_CL_F);
2586
19a33d4e
SH		 2587 *budget -= work_done;
2588 dev->quota -= work_done;
2589
2590 if (work_done >= to_do)
2591 return 1; /* not done */
baef58b1 2592
19a33d4e
SH		 2593 local_irq_disable();
2594 __netif_rx_complete(dev);
2595 hw->intr_mask |= portirqmask[skge->port];
2596 skge_write32(hw, B0_IMSK, hw->intr_mask);
2597 local_irq_enable();
2598 return 0;
baef58b1
SH		 2599}
2600
2601static inline void skge_tx_intr(struct net_device *dev)
2602{
2603 struct skge_port *skge = netdev_priv(dev);
2604 struct skge_hw *hw = skge->hw;
2605 struct skge_ring *ring = &skge->tx_ring;
2606 struct skge_element *e;
2607
2608 spin_lock(&skge->tx_lock);
95566065 2609 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2610 struct skge_tx_desc *td = e->desc;
2611 u32 control;
2612
2613 rmb();
2614 control = td->control;
2615 if (control & BMU_OWN)
2616 break;
2617
2618 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2619 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2620 dev->name, e - ring->start, td->status);
2621
2622 skge_tx_free(hw, e);
2623 e->skb = NULL;
2624 ++skge->tx_avail;
2625 }
2626 ring->to_clean = e;
2627 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2628
2629 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2630 netif_wake_queue(dev);
2631
2632 spin_unlock(&skge->tx_lock);
2633}
2634
f6620cab
SH		 2635/* Parity errors seem to happen when Genesis is connected to a switch
2636 * with no other ports present. Heartbeat error??
2637 */
baef58b1
SH		 2638static void skge_mac_parity(struct skge_hw *hw, int port)
2639{
f6620cab
SH		 2640 struct net_device *dev = hw->dev[port];
2641
2642 if (dev) {
2643 struct skge_port *skge = netdev_priv(dev);
2644 ++skge->net_stats.tx_heartbeat_errors;
2645 }
baef58b1
SH		 2646
2647 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2648 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2649 MFF_CLR_PERR);
2650 else
2651 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2652 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2653 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2654 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2655}
2656
2657static void skge_pci_clear(struct skge_hw *hw)
2658{
2659 u16 status;
2660
467b3417 2661 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2662 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2663 pci_write_config_word(hw->pdev, PCI_STATUS,
2664 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2665 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2666}
2667
2668static void skge_mac_intr(struct skge_hw *hw, int port)
2669{
95566065 2670 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2671 genesis_mac_intr(hw, port);
2672 else
2673 yukon_mac_intr(hw, port);
2674}
2675
2676/* Handle device specific framing and timeout interrupts */
2677static void skge_error_irq(struct skge_hw *hw)
2678{
2679 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2680
2681 if (hw->chip_id == CHIP_ID_GENESIS) {
2682 /* clear xmac errors */
2683 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2684 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2685 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2686 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2687 } else {
2688 /* Timestamp (unused) overflow */
2689 if (hwstatus & IS_IRQ_TIST_OV)
2690 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2691
2692 if (hwstatus & IS_IRQ_SENSOR) {
2693 /* no sensors on 32-bit Yukon */
2694 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2695 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2696 skge_write32(hw, B0_HWE_IMSK,
2697 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2698 } else
2699 printk(KERN_WARNING PFX "sensor interrupt\n");
2700 }
2701
2702
2703 }
2704
2705 if (hwstatus & IS_RAM_RD_PAR) {
2706 printk(KERN_ERR PFX "Ram read data parity error\n");
2707 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2708 }
2709
2710 if (hwstatus & IS_RAM_WR_PAR) {
2711 printk(KERN_ERR PFX "Ram write data parity error\n");
2712 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2713 }
2714
2715 if (hwstatus & IS_M1_PAR_ERR)
2716 skge_mac_parity(hw, 0);
2717
2718 if (hwstatus & IS_M2_PAR_ERR)
2719 skge_mac_parity(hw, 1);
2720
2721 if (hwstatus & IS_R1_PAR_ERR)
2722 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2723
2724 if (hwstatus & IS_R2_PAR_ERR)
2725 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2726
2727 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2728 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2729 hwstatus);
2730
2731 skge_pci_clear(hw);
2732
2733 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2734 if (hwstatus & IS_IRQ_STAT) {
2735 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2736 hwstatus);
2737 hw->intr_mask &= ~IS_HW_ERR;
2738 }
2739 }
2740}
2741
2742/*
2743 * Interrrupt from PHY are handled in tasklet (soft irq)
2744 * because accessing phy registers requires spin wait which might
2745 * cause excess interrupt latency.
2746 */
2747static void skge_extirq(unsigned long data)
2748{
2749 struct skge_hw *hw = (struct skge_hw *) data;
2750 int port;
2751
2752 spin_lock(&hw->phy_lock);
2753 for (port = 0; port < 2; port++) {
2754 struct net_device *dev = hw->dev[port];
2755
2756 if (dev && netif_running(dev)) {
2757 struct skge_port *skge = netdev_priv(dev);
2758
2759 if (hw->chip_id != CHIP_ID_GENESIS)
2760 yukon_phy_intr(skge);
89bf5f23 2761 else
45bada65 2762 bcom_phy_intr(skge);
baef58b1
SH		 2763 }
2764 }
2765 spin_unlock(&hw->phy_lock);
2766
2767 local_irq_disable();
2768 hw->intr_mask |= IS_EXT_REG;
2769 skge_write32(hw, B0_IMSK, hw->intr_mask);
2770 local_irq_enable();
2771}
2772
2773static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2774{
2775 struct skge_hw *hw = dev_id;
2776 u32 status = skge_read32(hw, B0_SP_ISRC);
2777
2778 if (status == 0 || status == ~0) /* hotplug or shared irq */
2779 return IRQ_NONE;
2780
2781 status &= hw->intr_mask;
7e676d91 2782 if (status & IS_R1_F) {
baef58b1 2783 hw->intr_mask &= ~IS_R1_F;
7e676d91 2784 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2785 }
2786
7e676d91 2787 if (status & IS_R2_F) {
baef58b1 2788 hw->intr_mask &= ~IS_R2_F;
7e676d91 2789 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2790 }
2791
2792 if (status & IS_XA1_F)
2793 skge_tx_intr(hw->dev[0]);
2794
2795 if (status & IS_XA2_F)
2796 skge_tx_intr(hw->dev[1]);
2797
d25f5a67
SH		 2798 if (status & IS_PA_TO_RX1) {
2799 struct skge_port *skge = netdev_priv(hw->dev[0]);
2800 ++skge->net_stats.rx_over_errors;
2801 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2802 }
2803
2804 if (status & IS_PA_TO_RX2) {
2805 struct skge_port *skge = netdev_priv(hw->dev[1]);
2806 ++skge->net_stats.rx_over_errors;
2807 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2808 }
2809
2810 if (status & IS_PA_TO_TX1)
2811 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2812
2813 if (status & IS_PA_TO_TX2)
2814 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2815
baef58b1
SH		 2816 if (status & IS_MAC1)
2817 skge_mac_intr(hw, 0);
95566065 2818
baef58b1
SH		 2819 if (status & IS_MAC2)
2820 skge_mac_intr(hw, 1);
2821
2822 if (status & IS_HW_ERR)
2823 skge_error_irq(hw);
2824
2825 if (status & IS_EXT_REG) {
2826 hw->intr_mask &= ~IS_EXT_REG;
2827 tasklet_schedule(&hw->ext_tasklet);
2828 }
2829
7e676d91 2830 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2831
2832 return IRQ_HANDLED;
2833}
2834
2835#ifdef CONFIG_NET_POLL_CONTROLLER
2836static void skge_netpoll(struct net_device *dev)
2837{
2838 struct skge_port *skge = netdev_priv(dev);
2839
2840 disable_irq(dev->irq);
2841 skge_intr(dev->irq, skge->hw, NULL);
2842 enable_irq(dev->irq);
2843}
2844#endif
2845
2846static int skge_set_mac_address(struct net_device *dev, void *p)
2847{
2848 struct skge_port *skge = netdev_priv(dev);
2849 struct sockaddr *addr = p;
2850 int err = 0;
2851
2852 if (!is_valid_ether_addr(addr->sa_data))
2853 return -EADDRNOTAVAIL;
2854
2855 skge_down(dev);
2856 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2857 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2858 dev->dev_addr, ETH_ALEN);
2859 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2860 dev->dev_addr, ETH_ALEN);
2861 if (dev->flags & IFF_UP)
2862 err = skge_up(dev);
2863 return err;
2864}
2865
2866static const struct {
2867 u8 id;
2868 const char *name;
2869} skge_chips[] = {
2870 { CHIP_ID_GENESIS, "Genesis" },
2871 { CHIP_ID_YUKON, "Yukon" },
2872 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2873 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2874};
2875
2876static const char *skge_board_name(const struct skge_hw *hw)
2877{
2878 int i;
2879 static char buf[16];
2880
2881 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2882 if (skge_chips[i].id == hw->chip_id)
2883 return skge_chips[i].name;
2884
2885 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2886 return buf;
2887}
2888
2889
2890/*
2891 * Setup the board data structure, but don't bring up
2892 * the port(s)
2893 */
2894static int skge_reset(struct skge_hw *hw)
2895{
2896 u16 ctst;
981d0377
SH		 2897 u8 t8, mac_cfg;
2898 int i;
baef58b1
SH		 2899
2900 ctst = skge_read16(hw, B0_CTST);
2901
2902 /* do a SW reset */
2903 skge_write8(hw, B0_CTST, CS_RST_SET);
2904 skge_write8(hw, B0_CTST, CS_RST_CLR);
2905
2906 /* clear PCI errors, if any */
2907 skge_pci_clear(hw);
2908
2909 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2910
2911 /* restore CLK_RUN bits (for Yukon-Lite) */
2912 skge_write16(hw, B0_CTST,
2913 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2914
2915 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2916 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2917 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2918
95566065 2919 switch (hw->chip_id) {
baef58b1
SH		 2920 case CHIP_ID_GENESIS:
2921 switch (hw->phy_type) {
baef58b1
SH		 2922 case SK_PHY_BCOM:
2923 hw->phy_addr = PHY_ADDR_BCOM;
2924 break;
2925 default:
2926 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2927 pci_name(hw->pdev), hw->phy_type);
2928 return -EOPNOTSUPP;
2929 }
2930 break;
2931
2932 case CHIP_ID_YUKON:
2933 case CHIP_ID_YUKON_LITE:
2934 case CHIP_ID_YUKON_LP:
2935 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2936 hw->phy_type = SK_PHY_MARV_COPPER;
2937
2938 hw->phy_addr = PHY_ADDR_MARV;
2939 if (!iscopper(hw))
2940 hw->phy_type = SK_PHY_MARV_FIBER;
2941
2942 break;
2943
2944 default:
2945 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2946 pci_name(hw->pdev), hw->chip_id);
2947 return -EOPNOTSUPP;
2948 }
2949
981d0377
SH		 2950 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2951 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2952 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2953
2954 /* read the adapters RAM size */
2955 t8 = skge_read8(hw, B2_E_0);
2956 if (hw->chip_id == CHIP_ID_GENESIS) {
2957 if (t8 == 3) {
2958 /* special case: 4 x 64k x 36, offset = 0x80000 */
2959 hw->ram_size = 0x100000;
2960 hw->ram_offset = 0x80000;
2961 } else
2962 hw->ram_size = t8 * 512;
2963 }
2964 else if (t8 == 0)
2965 hw->ram_size = 0x20000;
2966 else
2967 hw->ram_size = t8 * 4096;
2968
2969 if (hw->chip_id == CHIP_ID_GENESIS)
2970 genesis_init(hw);
2971 else {
2972 /* switch power to VCC (WA for VAUX problem) */
2973 skge_write8(hw, B0_POWER_CTRL,
2974 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2975 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2976 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2977 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2978 }
2979 }
2980
2981 /* turn off hardware timer (unused) */
2982 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2983 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2984 skge_write8(hw, B0_LED, LED_STAT_ON);
2985
2986 /* enable the Tx Arbiters */
981d0377 2987 for (i = 0; i < hw->ports; i++)
6b0c1480 2988 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2989
2990 /* Initialize ram interface */
2991 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2992
2993 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2994 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2995 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2996 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2997 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2998 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2999 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3000 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3001 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3002 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3003 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3004 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3005
3006 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3007
3008 /* Set interrupt moderation for Transmit only
3009 * Receive interrupts avoided by NAPI
3010 */
3011 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3012 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3013 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3014
7e676d91 3015 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3016 skge_write32(hw, B0_IMSK, hw->intr_mask);
3017
3018 if (hw->chip_id != CHIP_ID_GENESIS)
3019 skge_write8(hw, GMAC_IRQ_MSK, 0);
3020
3021 spin_lock_bh(&hw->phy_lock);
981d0377 3022 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3023 if (hw->chip_id == CHIP_ID_GENESIS)
3024 genesis_reset(hw, i);
3025 else
3026 yukon_reset(hw, i);
3027 }
3028 spin_unlock_bh(&hw->phy_lock);
3029
3030 return 0;
3031}
3032
3033/* Initialize network device */
981d0377
SH		 3034static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3035 int highmem)
baef58b1
SH		 3036{
3037 struct skge_port *skge;
3038 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3039
3040 if (!dev) {
3041 printk(KERN_ERR "skge etherdev alloc failed");
3042 return NULL;
3043 }
3044
3045 SET_MODULE_OWNER(dev);
3046 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3047 dev->open = skge_up;
3048 dev->stop = skge_down;
3049 dev->hard_start_xmit = skge_xmit_frame;
3050 dev->get_stats = skge_get_stats;
3051 if (hw->chip_id == CHIP_ID_GENESIS)
3052 dev->set_multicast_list = genesis_set_multicast;
3053 else
3054 dev->set_multicast_list = yukon_set_multicast;
3055
3056 dev->set_mac_address = skge_set_mac_address;
3057 dev->change_mtu = skge_change_mtu;
3058 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3059 dev->tx_timeout = skge_tx_timeout;
3060 dev->watchdog_timeo = TX_WATCHDOG;
3061 dev->poll = skge_poll;
3062 dev->weight = NAPI_WEIGHT;
3063#ifdef CONFIG_NET_POLL_CONTROLLER
3064 dev->poll_controller = skge_netpoll;
3065#endif
3066 dev->irq = hw->pdev->irq;
3067 dev->features = NETIF_F_LLTX;
981d0377
SH		 3068 if (highmem)
3069 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3070
3071 skge = netdev_priv(dev);
3072 skge->netdev = dev;
3073 skge->hw = hw;
3074 skge->msg_enable = netif_msg_init(debug, default_msg);
3075 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3076 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3077
3078 /* Auto speed and flow control */
3079 skge->autoneg = AUTONEG_ENABLE;
3080 skge->flow_control = FLOW_MODE_SYMMETRIC;
3081 skge->duplex = -1;
3082 skge->speed = -1;
31b619c5 3083 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3084
3085 hw->dev[port] = dev;
3086
3087 skge->port = port;
3088
3089 spin_lock_init(&skge->tx_lock);
3090
baef58b1
SH		 3091 init_timer(&skge->led_blink);
3092 skge->led_blink.function = skge_blink_timer;
3093 skge->led_blink.data = (unsigned long) skge;
3094
3095 if (hw->chip_id != CHIP_ID_GENESIS) {
3096 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3097 skge->rx_csum = 1;
3098 }
3099
3100 /* read the mac address */
3101 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3102
3103 /* device is off until link detection */
3104 netif_carrier_off(dev);
3105 netif_stop_queue(dev);
3106
3107 return dev;
3108}
3109
3110static void __devinit skge_show_addr(struct net_device *dev)
3111{
3112 const struct skge_port *skge = netdev_priv(dev);
3113
3114 if (netif_msg_probe(skge))
3115 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3116 dev->name,
3117 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3118 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3119}
3120
3121static int __devinit skge_probe(struct pci_dev *pdev,
3122 const struct pci_device_id *ent)
3123{
3124 struct net_device *dev, *dev1;
3125 struct skge_hw *hw;
3126 int err, using_dac = 0;
3127
3128 if ((err = pci_enable_device(pdev))) {
3129 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3130 pci_name(pdev));
3131 goto err_out;
3132 }
3133
3134 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3135 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3136 pci_name(pdev));
3137 goto err_out_disable_pdev;
3138 }
3139
3140 pci_set_master(pdev);
3141
3142 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3143 using_dac = 1;
3144 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3145 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3146 pci_name(pdev));
3147 goto err_out_free_regions;
3148 }
3149
3150#ifdef __BIG_ENDIAN
3151 /* byte swap decriptors in hardware */
3152 {
3153 u32 reg;
3154
3155 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3156 reg |= PCI_REV_DESC;
3157 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3158 }
3159#endif
3160
3161 err = -ENOMEM;
3162 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3163 if (!hw) {
3164 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3165 pci_name(pdev));
3166 goto err_out_free_regions;
3167 }
3168
3169 memset(hw, 0, sizeof(*hw));
3170 hw->pdev = pdev;
3171 spin_lock_init(&hw->phy_lock);
3172 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3173
3174 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3175 if (!hw->regs) {
3176 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3177 pci_name(pdev));
3178 goto err_out_free_hw;
3179 }
3180
3181 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3182 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3183 pci_name(pdev), pdev->irq);
3184 goto err_out_iounmap;
3185 }
3186 pci_set_drvdata(pdev, hw);
3187
3188 err = skge_reset(hw);
3189 if (err)
3190 goto err_out_free_irq;
3191
3192 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3193 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3194 skge_board_name(hw), hw->chip_rev);
baef58b1 3195
981d0377 3196 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3197 goto err_out_led_off;
3198
baef58b1
SH		 3199 if ((err = register_netdev(dev))) {
3200 printk(KERN_ERR PFX "%s: cannot register net device\n",
3201 pci_name(pdev));
3202 goto err_out_free_netdev;
3203 }
3204
3205 skge_show_addr(dev);
3206
981d0377 3207 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3208 if (register_netdev(dev1) == 0)
3209 skge_show_addr(dev1);
3210 else {
3211 /* Failure to register second port need not be fatal */
3212 printk(KERN_WARNING PFX "register of second port failed\n");
3213 hw->dev[1] = NULL;
3214 free_netdev(dev1);
3215 }
3216 }
3217
3218 return 0;
3219
3220err_out_free_netdev:
3221 free_netdev(dev);
3222err_out_led_off:
3223 skge_write16(hw, B0_LED, LED_STAT_OFF);
3224err_out_free_irq:
3225 free_irq(pdev->irq, hw);
3226err_out_iounmap:
3227 iounmap(hw->regs);
3228err_out_free_hw:
3229 kfree(hw);
3230err_out_free_regions:
3231 pci_release_regions(pdev);
3232err_out_disable_pdev:
3233 pci_disable_device(pdev);
3234 pci_set_drvdata(pdev, NULL);
3235err_out:
3236 return err;
3237}
3238
3239static void __devexit skge_remove(struct pci_dev *pdev)
3240{
3241 struct skge_hw *hw = pci_get_drvdata(pdev);
3242 struct net_device *dev0, *dev1;
3243
95566065 3244 if (!hw)
baef58b1
SH		 3245 return;
3246
3247 if ((dev1 = hw->dev[1]))
3248 unregister_netdev(dev1);
3249 dev0 = hw->dev[0];
3250 unregister_netdev(dev0);
3251
3252 tasklet_kill(&hw->ext_tasklet);
3253
3254 free_irq(pdev->irq, hw);
3255 pci_release_regions(pdev);
3256 pci_disable_device(pdev);
3257 if (dev1)
3258 free_netdev(dev1);
3259 free_netdev(dev0);
3260 skge_write16(hw, B0_LED, LED_STAT_OFF);
3261 iounmap(hw->regs);
3262 kfree(hw);
3263 pci_set_drvdata(pdev, NULL);
3264}
3265
3266#ifdef CONFIG_PM
2a569579 3267static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3268{
3269 struct skge_hw *hw = pci_get_drvdata(pdev);
3270 int i, wol = 0;
3271
95566065 3272 for (i = 0; i < 2; i++) {
baef58b1
SH		 3273 struct net_device *dev = hw->dev[i];
3274
3275 if (dev) {
3276 struct skge_port *skge = netdev_priv(dev);
3277 if (netif_running(dev)) {
3278 netif_carrier_off(dev);
3279 skge_down(dev);
3280 }
3281 netif_device_detach(dev);
3282 wol |= skge->wol;
3283 }
3284 }
3285
3286 pci_save_state(pdev);
2a569579 3287 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3288 pci_disable_device(pdev);
3289 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3290
3291 return 0;
3292}
3293
3294static int skge_resume(struct pci_dev *pdev)
3295{
3296 struct skge_hw *hw = pci_get_drvdata(pdev);
3297 int i;
3298
3299 pci_set_power_state(pdev, PCI_D0);
3300 pci_restore_state(pdev);
3301 pci_enable_wake(pdev, PCI_D0, 0);
3302
3303 skge_reset(hw);
3304
95566065 3305 for (i = 0; i < 2; i++) {
baef58b1
SH		 3306 struct net_device *dev = hw->dev[i];
3307 if (dev) {
3308 netif_device_attach(dev);
95566065 3309 if (netif_running(dev))
baef58b1
SH		 3310 skge_up(dev);
3311 }
3312 }
3313 return 0;
3314}
3315#endif
3316
3317static struct pci_driver skge_driver = {
3318 .name = DRV_NAME,
3319 .id_table = skge_id_table,
3320 .probe = skge_probe,
3321 .remove = __devexit_p(skge_remove),
3322#ifdef CONFIG_PM
3323 .suspend = skge_suspend,
3324 .resume = skge_resume,
3325#endif
3326};
3327
3328static int __init skge_init_module(void)
3329{
3330 return pci_module_init(&skge_driver);
3331}
3332
3333static void __exit skge_cleanup_module(void)
3334{
3335 pci_unregister_driver(&skge_driver);
3336}
3337
3338module_init(skge_init_module);
3339module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)