projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] NetXen: driver cleanup, removed unnecessary __iomem type casts
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
370de6cd 45#define DRV_VERSION "1.9"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
64f6b64d 60#define LINK_HZ (HZ/2)
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
2d2a3871 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
ee294dcd 93static void skge_phy_reset(struct skge_port *skge);
513f533e 94static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
baef58b1 100static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 101static void genesis_link_up(struct skge_port *skge);
baef58b1 102
7e676d91 103/* Avoid conditionals by using array */
baef58b1
SH		 104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
513f533e 108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
baef58b1 109
baef58b1
SH		 110static int skge_get_regs_len(struct net_device *dev)
111{
c3f8be96 112 return 0x4000;
baef58b1
SH		 113}
114
115/*
c3f8be96
SH		 116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
baef58b1
SH		 119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
baef58b1 124 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 125
126 regs->version = 1;
c3f8be96
SH		 127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 129
c3f8be96
SH		 130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 132}
133
8f3f8193 134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 135static int wol_supported(const struct skge_hw *hw)
136{
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 139}
140
141static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142{
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147}
148
149static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
95566065 154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172}
173
8f3f8193
SH		 174/* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 176 */
177static u32 skge_supported_modes(const struct skge_hw *hw)
178{
179 u32 supported;
180
5e1705dd 181 if (hw->copper) {
31b619c5
SH		 182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
4b67be99
SH		 199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
200 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 201
202 return supported;
203}
baef58b1
SH		 204
205static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207{
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 212 ecmd->supported = skge_supported_modes(hw);
baef58b1 213
5e1705dd 214 if (hw->copper) {
baef58b1
SH		 215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
31b619c5 217 } else
baef58b1 218 ecmd->port = PORT_FIBRE;
baef58b1
SH		 219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225}
226
baef58b1
SH		 227static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228{
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
31b619c5 231 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
baef58b1 237 } else {
31b619c5
SH		 238 u32 setting;
239
2c668514 240 switch (ecmd->speed) {
baef58b1 241 case SPEED_1000:
31b619c5
SH		 242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
baef58b1
SH		 248 break;
249 case SPEED_100:
31b619c5
SH		 250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
baef58b1 258 case SPEED_10:
31b619c5
SH		 259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
baef58b1
SH		 264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
31b619c5
SH		 269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
baef58b1
SH		 275 }
276
277 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 278 skge->advertising = ecmd->advertising;
279
ee294dcd
SH		 280 if (netif_running(dev))
281 skge_phy_reset(skge);
282
baef58b1
SH		 283 return (0);
284}
285
286static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288{
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295}
296
297static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301} skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326};
327
328static int skge_get_stats_count(struct net_device *dev)
329{
330 return ARRAY_SIZE(skge_stats);
331}
332
333static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335{
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342}
343
344/* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348static struct net_device_stats *skge_get_stats(struct net_device *dev)
349{
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 362 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367}
368
369static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370{
371 int i;
372
95566065 373 switch (stringset) {
baef58b1
SH		 374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380}
381
382static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384{
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396}
397
398static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400{
401 struct skge_port *skge = netdev_priv(dev);
3b8bb472 402 int err;
baef58b1
SH		 403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 405 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
3b8bb472
SH		 413 err = skge_up(dev);
414 if (err)
415 dev_close(dev);
baef58b1
SH		 416 }
417
418 return 0;
419}
420
421static u32 skge_get_msglevel(struct net_device *netdev)
422{
423 struct skge_port *skge = netdev_priv(netdev);
424 return skge->msg_enable;
425}
426
427static void skge_set_msglevel(struct net_device *netdev, u32 value)
428{
429 struct skge_port *skge = netdev_priv(netdev);
430 skge->msg_enable = value;
431}
432
433static int skge_nway_reset(struct net_device *dev)
434{
435 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
ee294dcd 440 skge_phy_reset(skge);
baef58b1
SH		 441 return 0;
442}
443
444static int skge_set_sg(struct net_device *dev, u32 data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 struct skge_hw *hw = skge->hw;
448
449 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return -EOPNOTSUPP;
451 return ethtool_op_set_sg(dev, data);
452}
453
454static int skge_set_tx_csum(struct net_device *dev, u32 data)
455{
456 struct skge_port *skge = netdev_priv(dev);
457 struct skge_hw *hw = skge->hw;
458
459 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return -EOPNOTSUPP;
461
462 return ethtool_op_set_tx_csum(dev, data);
463}
464
465static u32 skge_get_rx_csum(struct net_device *dev)
466{
467 struct skge_port *skge = netdev_priv(dev);
468
469 return skge->rx_csum;
470}
471
472/* Only Yukon supports checksum offload. */
473static int skge_set_rx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 skge->rx_csum = data;
481 return 0;
482}
483
baef58b1
SH		 484static void skge_get_pauseparam(struct net_device *dev,
485 struct ethtool_pauseparam *ecmd)
486{
487 struct skge_port *skge = netdev_priv(dev);
488
5d5c8e03
SH		 489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
490 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
491 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 492
5d5c8e03 493 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 494}
495
496static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498{
499 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 500 struct ethtool_pauseparam old;
baef58b1 501
5d5c8e03
SH		 502 skge_get_pauseparam(dev, &old);
503
504 if (ecmd->autoneg != old.autoneg)
505 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
506 else {
507 if (ecmd->rx_pause && ecmd->tx_pause)
508 skge->flow_control = FLOW_MODE_SYMMETRIC;
509 else if (ecmd->rx_pause && !ecmd->tx_pause)
510 skge->flow_control = FLOW_MODE_SYM_OR_REM;
511 else if (!ecmd->rx_pause && ecmd->tx_pause)
512 skge->flow_control = FLOW_MODE_LOC_SEND;
513 else
514 skge->flow_control = FLOW_MODE_NONE;
515 }
baef58b1 516
e8df8554
SH		 517 if (netif_running(dev))
518 skge_phy_reset(skge);
5d5c8e03 519
baef58b1
SH		 520 return 0;
521}
522
523/* Chip internal frequency for clock calculations */
524static inline u32 hwkhz(const struct skge_hw *hw)
525{
187ff3b8 526 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 527}
528
8f3f8193 529/* Chip HZ to microseconds */
baef58b1
SH		 530static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
531{
532 return (ticks * 1000) / hwkhz(hw);
533}
534
8f3f8193 535/* Microseconds to chip HZ */
baef58b1
SH		 536static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
537{
538 return hwkhz(hw) * usec / 1000;
539}
540
541static int skge_get_coalesce(struct net_device *dev,
542 struct ethtool_coalesce *ecmd)
543{
544 struct skge_port *skge = netdev_priv(dev);
545 struct skge_hw *hw = skge->hw;
546 int port = skge->port;
547
548 ecmd->rx_coalesce_usecs = 0;
549 ecmd->tx_coalesce_usecs = 0;
550
551 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
552 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
553 u32 msk = skge_read32(hw, B2_IRQM_MSK);
554
555 if (msk & rxirqmask[port])
556 ecmd->rx_coalesce_usecs = delay;
557 if (msk & txirqmask[port])
558 ecmd->tx_coalesce_usecs = delay;
559 }
560
561 return 0;
562}
563
564/* Note: interrupt timer is per board, but can turn on/off per port */
565static int skge_set_coalesce(struct net_device *dev,
566 struct ethtool_coalesce *ecmd)
567{
568 struct skge_port *skge = netdev_priv(dev);
569 struct skge_hw *hw = skge->hw;
570 int port = skge->port;
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572 u32 delay = 25;
573
574 if (ecmd->rx_coalesce_usecs == 0)
575 msk &= ~rxirqmask[port];
576 else if (ecmd->rx_coalesce_usecs < 25 ||
577 ecmd->rx_coalesce_usecs > 33333)
578 return -EINVAL;
579 else {
580 msk |= rxirqmask[port];
581 delay = ecmd->rx_coalesce_usecs;
582 }
583
584 if (ecmd->tx_coalesce_usecs == 0)
585 msk &= ~txirqmask[port];
586 else if (ecmd->tx_coalesce_usecs < 25 ||
587 ecmd->tx_coalesce_usecs > 33333)
588 return -EINVAL;
589 else {
590 msk |= txirqmask[port];
591 delay = min(delay, ecmd->rx_coalesce_usecs);
592 }
593
594 skge_write32(hw, B2_IRQM_MSK, msk);
595 if (msk == 0)
596 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
597 else {
598 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
599 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
600 }
601 return 0;
602}
603
6abebb53
SH		 604enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
605static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 606{
6abebb53
SH		 607 struct skge_hw *hw = skge->hw;
608 int port = skge->port;
609
d85b514f 610 mutex_lock(&hw->phy_mutex);
baef58b1 611 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 612 switch (mode) {
613 case LED_MODE_OFF:
64f6b64d
SH		 614 if (hw->phy_type == SK_PHY_BCOM)
615 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
616 else {
617 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
618 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
619 }
6abebb53
SH		 620 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
621 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
622 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
623 break;
baef58b1 624
6abebb53
SH		 625 case LED_MODE_ON:
626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 628
6abebb53
SH		 629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 631
6abebb53 632 break;
baef58b1 633
6abebb53
SH		 634 case LED_MODE_TST:
635 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
636 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
637 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 638
64f6b64d
SH		 639 if (hw->phy_type == SK_PHY_BCOM)
640 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
641 else {
642 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
643 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
644 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
645 }
646
6abebb53 647 }
baef58b1 648 } else {
6abebb53
SH		 649 switch (mode) {
650 case LED_MODE_OFF:
651 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
652 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
653 PHY_M_LED_MO_DUP(MO_LED_OFF) |
654 PHY_M_LED_MO_10(MO_LED_OFF) |
655 PHY_M_LED_MO_100(MO_LED_OFF) |
656 PHY_M_LED_MO_1000(MO_LED_OFF) |
657 PHY_M_LED_MO_RX(MO_LED_OFF));
658 break;
659 case LED_MODE_ON:
660 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
661 PHY_M_LED_PULS_DUR(PULS_170MS) |
662 PHY_M_LED_BLINK_RT(BLINK_84MS) |
663 PHY_M_LEDC_TX_CTRL |
664 PHY_M_LEDC_DP_CTRL);
46a60f2d 665
6abebb53
SH		 666 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
667 PHY_M_LED_MO_RX(MO_LED_OFF) |
668 (skge->speed == SPEED_100 ?
669 PHY_M_LED_MO_100(MO_LED_ON) : 0));
670 break;
671 case LED_MODE_TST:
672 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_DUP(MO_LED_ON) |
675 PHY_M_LED_MO_10(MO_LED_ON) |
676 PHY_M_LED_MO_100(MO_LED_ON) |
677 PHY_M_LED_MO_1000(MO_LED_ON) |
678 PHY_M_LED_MO_RX(MO_LED_ON));
679 }
baef58b1 680 }
d85b514f 681 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 682}
683
684/* blink LED's for finding board */
685static int skge_phys_id(struct net_device *dev, u32 data)
686{
687 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 688 unsigned long ms;
689 enum led_mode mode = LED_MODE_TST;
baef58b1 690
95566065 691 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 692 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
693 else
694 ms = data * 1000;
baef58b1 695
6abebb53
SH		 696 while (ms > 0) {
697 skge_led(skge, mode);
698 mode ^= LED_MODE_TST;
baef58b1 699
6abebb53
SH		 700 if (msleep_interruptible(BLINK_MS))
701 break;
702 ms -= BLINK_MS;
703 }
baef58b1 704
6abebb53
SH		 705 /* back to regular LED state */
706 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 707
708 return 0;
709}
710
7282d491 711static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 712 .get_settings = skge_get_settings,
713 .set_settings = skge_set_settings,
714 .get_drvinfo = skge_get_drvinfo,
715 .get_regs_len = skge_get_regs_len,
716 .get_regs = skge_get_regs,
717 .get_wol = skge_get_wol,
718 .set_wol = skge_set_wol,
719 .get_msglevel = skge_get_msglevel,
720 .set_msglevel = skge_set_msglevel,
721 .nway_reset = skge_nway_reset,
722 .get_link = ethtool_op_get_link,
723 .get_ringparam = skge_get_ring_param,
724 .set_ringparam = skge_set_ring_param,
725 .get_pauseparam = skge_get_pauseparam,
726 .set_pauseparam = skge_set_pauseparam,
727 .get_coalesce = skge_get_coalesce,
728 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 729 .get_sg = ethtool_op_get_sg,
730 .set_sg = skge_set_sg,
731 .get_tx_csum = ethtool_op_get_tx_csum,
732 .set_tx_csum = skge_set_tx_csum,
733 .get_rx_csum = skge_get_rx_csum,
734 .set_rx_csum = skge_set_rx_csum,
735 .get_strings = skge_get_strings,
736 .phys_id = skge_phys_id,
737 .get_stats_count = skge_get_stats_count,
738 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 739 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 740};
741
742/*
743 * Allocate ring elements and chain them together
744 * One-to-one association of board descriptors with ring elements
745 */
c3da1447 746static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 747{
748 struct skge_tx_desc *d;
749 struct skge_element *e;
750 int i;
751
ff7907ae 752 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 753 if (!ring->start)
754 return -ENOMEM;
755
756 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
757 e->desc = d;
758 if (i == ring->count - 1) {
759 e->next = ring->start;
760 d->next_offset = base;
761 } else {
762 e->next = e + 1;
763 d->next_offset = base + (i+1) * sizeof(*d);
764 }
765 }
766 ring->to_use = ring->to_clean = ring->start;
767
768 return 0;
769}
770
19a33d4e
SH		 771/* Allocate and setup a new buffer for receiving */
772static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
773 struct sk_buff *skb, unsigned int bufsize)
774{
775 struct skge_rx_desc *rd = e->desc;
776 u64 map;
baef58b1
SH		 777
778 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
779 PCI_DMA_FROMDEVICE);
780
781 rd->dma_lo = map;
782 rd->dma_hi = map >> 32;
783 e->skb = skb;
784 rd->csum1_start = ETH_HLEN;
785 rd->csum2_start = ETH_HLEN;
786 rd->csum1 = 0;
787 rd->csum2 = 0;
788
789 wmb();
790
791 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
792 pci_unmap_addr_set(e, mapaddr, map);
793 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 794}
795
19a33d4e
SH		 796/* Resume receiving using existing skb,
797 * Note: DMA address is not changed by chip.
798 * MTU not changed while receiver active.
799 */
5a011447 800static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 801{
802 struct skge_rx_desc *rd = e->desc;
803
804 rd->csum2 = 0;
805 rd->csum2_start = ETH_HLEN;
806
807 wmb();
808
809 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
810}
811
812
813/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 814static void skge_rx_clean(struct skge_port *skge)
815{
816 struct skge_hw *hw = skge->hw;
817 struct skge_ring *ring = &skge->rx_ring;
818 struct skge_element *e;
819
19a33d4e
SH		 820 e = ring->start;
821 do {
baef58b1
SH		 822 struct skge_rx_desc *rd = e->desc;
823 rd->control = 0;
19a33d4e
SH		 824 if (e->skb) {
825 pci_unmap_single(hw->pdev,
826 pci_unmap_addr(e, mapaddr),
827 pci_unmap_len(e, maplen),
828 PCI_DMA_FROMDEVICE);
829 dev_kfree_skb(e->skb);
830 e->skb = NULL;
831 }
832 } while ((e = e->next) != ring->start);
baef58b1
SH		 833}
834
19a33d4e 835
baef58b1 836/* Allocate buffers for receive ring
19a33d4e 837 * For receive: to_clean is next received frame.
baef58b1 838 */
c54f9765 839static int skge_rx_fill(struct net_device *dev)
baef58b1 840{
c54f9765 841 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 842 struct skge_ring *ring = &skge->rx_ring;
843 struct skge_element *e;
baef58b1 844
19a33d4e
SH		 845 e = ring->start;
846 do {
383181ac 847 struct sk_buff *skb;
baef58b1 848
c54f9765
SH		 849 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
850 GFP_KERNEL);
19a33d4e
SH		 851 if (!skb)
852 return -ENOMEM;
853
383181ac
SH		 854 skb_reserve(skb, NET_IP_ALIGN);
855 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 856 } while ( (e = e->next) != ring->start);
baef58b1 857
19a33d4e
SH		 858 ring->to_clean = ring->start;
859 return 0;
baef58b1
SH		 860}
861
5d5c8e03
SH		 862static const char *skge_pause(enum pause_status status)
863{
864 switch(status) {
865 case FLOW_STAT_NONE:
866 return "none";
867 case FLOW_STAT_REM_SEND:
868 return "rx only";
869 case FLOW_STAT_LOC_SEND:
870 return "tx_only";
871 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
872 return "both";
873 default:
874 return "indeterminated";
875 }
876}
877
878
baef58b1
SH		 879static void skge_link_up(struct skge_port *skge)
880{
46a60f2d 881 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 882 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
883
baef58b1 884 netif_carrier_on(skge->netdev);
29b4e886 885 netif_wake_queue(skge->netdev);
baef58b1 886
5d5c8e03 887 if (netif_msg_link(skge)) {
baef58b1
SH		 888 printk(KERN_INFO PFX
889 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
890 skge->netdev->name, skge->speed,
891 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 892 skge_pause(skge->flow_status));
893 }
baef58b1
SH		 894}
895
896static void skge_link_down(struct skge_port *skge)
897{
54cfb5aa 898 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 899 netif_carrier_off(skge->netdev);
900 netif_stop_queue(skge->netdev);
901
902 if (netif_msg_link(skge))
903 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
904}
905
a1bc9b87
SH		 906
907static void xm_link_down(struct skge_hw *hw, int port)
908{
909 struct net_device *dev = hw->dev[port];
910 struct skge_port *skge = netdev_priv(dev);
911 u16 cmd, msk;
912
913 if (hw->phy_type == SK_PHY_XMAC) {
914 msk = xm_read16(hw, port, XM_IMSK);
915 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
916 xm_write16(hw, port, XM_IMSK, msk);
917 }
918
919 cmd = xm_read16(hw, port, XM_MMU_CMD);
920 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
921 xm_write16(hw, port, XM_MMU_CMD, cmd);
922 /* dummy read to ensure writing */
923 (void) xm_read16(hw, port, XM_MMU_CMD);
924
925 if (netif_carrier_ok(dev))
926 skge_link_down(skge);
927}
928
2cd8e5d3 929static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 930{
931 int i;
baef58b1 932
6b0c1480 933 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 934 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 935
64f6b64d
SH		 936 if (hw->phy_type == SK_PHY_XMAC)
937 goto ready;
938
89bf5f23 939 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 940 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 941 goto ready;
0781191c 942 udelay(1);
baef58b1
SH		 943 }
944
2cd8e5d3 945 return -ETIMEDOUT;
89bf5f23 946 ready:
2cd8e5d3 947 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 948
2cd8e5d3
SH		 949 return 0;
950}
951
952static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
953{
954 u16 v = 0;
955 if (__xm_phy_read(hw, port, reg, &v))
956 printk(KERN_WARNING PFX "%s: phy read timed out\n",
957 hw->dev[port]->name);
baef58b1
SH		 958 return v;
959}
960
2cd8e5d3 961static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 962{
963 int i;
964
6b0c1480 965 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 966 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 967 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 968 goto ready;
89bf5f23 969 udelay(1);
baef58b1 970 }
2cd8e5d3 971 return -EIO;
baef58b1
SH		 972
973 ready:
6b0c1480 974 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 975 for (i = 0; i < PHY_RETRIES; i++) {
976 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
977 return 0;
978 udelay(1);
979 }
980 return -ETIMEDOUT;
baef58b1
SH		 981}
982
983static void genesis_init(struct skge_hw *hw)
984{
985 /* set blink source counter */
986 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
987 skge_write8(hw, B2_BSC_CTRL, BSC_START);
988
989 /* configure mac arbiter */
990 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
991
992 /* configure mac arbiter timeout values */
993 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
994 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
995 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
996 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
997
998 skge_write8(hw, B3_MA_RCINI_RX1, 0);
999 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1000 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1001 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1002
1003 /* configure packet arbiter timeout */
1004 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1005 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1006 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1007 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1008 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1009}
1010
1011static void genesis_reset(struct skge_hw *hw, int port)
1012{
45bada65 1013 const u8 zero[8] = { 0 };
baef58b1 1014
46a60f2d
SH		 1015 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1016
baef58b1 1017 /* reset the statistics module */
6b0c1480
SH		 1018 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1019 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1020 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1021 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1022 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1023
89bf5f23 1024 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1025 if (hw->phy_type == SK_PHY_BCOM)
1026 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1027
45bada65 1028 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1029}
1030
1031
45bada65
SH		 1032/* Convert mode to MII values */
1033static const u16 phy_pause_map[] = {
1034 [FLOW_MODE_NONE] = 0,
1035 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1036 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1037 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1038};
1039
4b67be99
SH		 1040/* special defines for FIBER (88E1011S only) */
1041static const u16 fiber_pause_map[] = {
1042 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1043 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1044 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1045 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1046};
1047
45bada65
SH		 1048
1049/* Check status of Broadcom phy link */
1050static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1051{
45bada65
SH		 1052 struct net_device *dev = hw->dev[port];
1053 struct skge_port *skge = netdev_priv(dev);
1054 u16 status;
1055
1056 /* read twice because of latch */
1057 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1058 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1059
45bada65 1060 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1061 xm_link_down(hw, port);
64f6b64d
SH		 1062 return;
1063 }
45bada65 1064
64f6b64d
SH		 1065 if (skge->autoneg == AUTONEG_ENABLE) {
1066 u16 lpa, aux;
45bada65 1067
64f6b64d
SH		 1068 if (!(status & PHY_ST_AN_OVER))
1069 return;
45bada65 1070
64f6b64d
SH		 1071 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1072 if (lpa & PHY_B_AN_RF) {
1073 printk(KERN_NOTICE PFX "%s: remote fault\n",
1074 dev->name);
1075 return;
1076 }
45bada65 1077
64f6b64d
SH		 1078 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1079
1080 /* Check Duplex mismatch */
1081 switch (aux & PHY_B_AS_AN_RES_MSK) {
1082 case PHY_B_RES_1000FD:
1083 skge->duplex = DUPLEX_FULL;
1084 break;
1085 case PHY_B_RES_1000HD:
1086 skge->duplex = DUPLEX_HALF;
1087 break;
1088 default:
1089 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1090 dev->name);
1091 return;
45bada65
SH		 1092 }
1093
64f6b64d
SH		 1094 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1095 switch (aux & PHY_B_AS_PAUSE_MSK) {
1096 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1097 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1098 break;
1099 case PHY_B_AS_PRR:
5d5c8e03 1100 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1101 break;
1102 case PHY_B_AS_PRT:
5d5c8e03 1103 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1104 break;
1105 default:
5d5c8e03 1106 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1107 }
1108 skge->speed = SPEED_1000;
45bada65 1109 }
64f6b64d
SH		 1110
1111 if (!netif_carrier_ok(dev))
1112 genesis_link_up(skge);
45bada65
SH		 1113}
1114
1115/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1116 * Phy on for 100 or 10Mbit operation
1117 */
64f6b64d 1118static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1119{
1120 struct skge_hw *hw = skge->hw;
1121 int port = skge->port;
baef58b1 1122 int i;
45bada65 1123 u16 id1, r, ext, ctl;
baef58b1
SH		 1124
1125 /* magic workaround patterns for Broadcom */
1126 static const struct {
1127 u16 reg;
1128 u16 val;
1129 } A1hack[] = {
1130 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1131 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1132 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1133 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1134 }, C0hack[] = {
1135 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1136 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1137 };
1138
45bada65
SH		 1139 /* read Id from external PHY (all have the same address) */
1140 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1141
1142 /* Optimize MDIO transfer by suppressing preamble. */
1143 r = xm_read16(hw, port, XM_MMU_CMD);
1144 r |= XM_MMU_NO_PRE;
1145 xm_write16(hw, port, XM_MMU_CMD,r);
1146
2c668514 1147 switch (id1) {
45bada65
SH		 1148 case PHY_BCOM_ID1_C0:
1149 /*
1150 * Workaround BCOM Errata for the C0 type.
1151 * Write magic patterns to reserved registers.
1152 */
1153 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1154 xm_phy_write(hw, port,
1155 C0hack[i].reg, C0hack[i].val);
1156
1157 break;
1158 case PHY_BCOM_ID1_A1:
1159 /*
1160 * Workaround BCOM Errata for the A1 type.
1161 * Write magic patterns to reserved registers.
1162 */
1163 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1164 xm_phy_write(hw, port,
1165 A1hack[i].reg, A1hack[i].val);
1166 break;
1167 }
1168
1169 /*
1170 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1171 * Disable Power Management after reset.
1172 */
1173 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1174 r |= PHY_B_AC_DIS_PM;
1175 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1176
1177 /* Dummy read */
1178 xm_read16(hw, port, XM_ISRC);
1179
1180 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1181 ctl = PHY_CT_SP1000; /* always 1000mbit */
1182
1183 if (skge->autoneg == AUTONEG_ENABLE) {
1184 /*
1185 * Workaround BCOM Errata #1 for the C5 type.
1186 * 1000Base-T Link Acquisition Failure in Slave Mode
1187 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1188 */
1189 u16 adv = PHY_B_1000C_RD;
1190 if (skge->advertising & ADVERTISED_1000baseT_Half)
1191 adv |= PHY_B_1000C_AHD;
1192 if (skge->advertising & ADVERTISED_1000baseT_Full)
1193 adv |= PHY_B_1000C_AFD;
1194 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1195
1196 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1197 } else {
1198 if (skge->duplex == DUPLEX_FULL)
1199 ctl |= PHY_CT_DUP_MD;
1200 /* Force to slave */
1201 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1202 }
1203
1204 /* Set autonegotiation pause parameters */
1205 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1206 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1207
1208 /* Handle Jumbo frames */
64f6b64d 1209 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1210 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1211 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1212
1213 ext |= PHY_B_PEC_HIGH_LA;
1214
1215 }
1216
1217 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1218 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1219
8f3f8193 1220 /* Use link status change interrupt */
45bada65 1221 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1222}
45bada65 1223
64f6b64d
SH		 1224static void xm_phy_init(struct skge_port *skge)
1225{
1226 struct skge_hw *hw = skge->hw;
1227 int port = skge->port;
1228 u16 ctrl = 0;
1229
1230 if (skge->autoneg == AUTONEG_ENABLE) {
1231 if (skge->advertising & ADVERTISED_1000baseT_Half)
1232 ctrl |= PHY_X_AN_HD;
1233 if (skge->advertising & ADVERTISED_1000baseT_Full)
1234 ctrl |= PHY_X_AN_FD;
1235
4b67be99 1236 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1237
1238 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1239
1240 /* Restart Auto-negotiation */
1241 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1242 } else {
1243 /* Set DuplexMode in Config register */
1244 if (skge->duplex == DUPLEX_FULL)
1245 ctrl |= PHY_CT_DUP_MD;
1246 /*
1247 * Do NOT enable Auto-negotiation here. This would hold
1248 * the link down because no IDLEs are transmitted
1249 */
1250 }
1251
1252 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1253
1254 /* Poll PHY for status changes */
1255 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1256}
1257
1258static void xm_check_link(struct net_device *dev)
1259{
1260 struct skge_port *skge = netdev_priv(dev);
1261 struct skge_hw *hw = skge->hw;
1262 int port = skge->port;
1263 u16 status;
1264
1265 /* read twice because of latch */
1266 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1267 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1268
1269 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1270 xm_link_down(hw, port);
64f6b64d
SH		 1271 return;
1272 }
1273
1274 if (skge->autoneg == AUTONEG_ENABLE) {
1275 u16 lpa, res;
1276
1277 if (!(status & PHY_ST_AN_OVER))
1278 return;
1279
1280 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1281 if (lpa & PHY_B_AN_RF) {
1282 printk(KERN_NOTICE PFX "%s: remote fault\n",
1283 dev->name);
1284 return;
1285 }
1286
1287 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1288
1289 /* Check Duplex mismatch */
1290 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1291 case PHY_X_RS_FD:
1292 skge->duplex = DUPLEX_FULL;
1293 break;
1294 case PHY_X_RS_HD:
1295 skge->duplex = DUPLEX_HALF;
1296 break;
1297 default:
1298 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1299 dev->name);
1300 return;
1301 }
1302
1303 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1304 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1305 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1306 (lpa & PHY_X_P_SYM_MD))
1307 skge->flow_status = FLOW_STAT_SYMMETRIC;
1308 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1309 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1310 /* Enable PAUSE receive, disable PAUSE transmit */
1311 skge->flow_status = FLOW_STAT_REM_SEND;
1312 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1313 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1314 /* Disable PAUSE receive, enable PAUSE transmit */
1315 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1316 else
5d5c8e03 1317 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1318
1319 skge->speed = SPEED_1000;
1320 }
1321
1322 if (!netif_carrier_ok(dev))
1323 genesis_link_up(skge);
1324}
1325
1326/* Poll to check for link coming up.
1327 * Since internal PHY is wired to a level triggered pin, can't
1328 * get an interrupt when carrier is detected.
1329 */
1330static void xm_link_timer(void *arg)
1331{
1332 struct net_device *dev = arg;
1333 struct skge_port *skge = netdev_priv(arg);
1334 struct skge_hw *hw = skge->hw;
1335 int port = skge->port;
1336
1337 if (!netif_running(dev))
1338 return;
1339
1340 if (netif_carrier_ok(dev)) {
1341 xm_read16(hw, port, XM_ISRC);
1342 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1343 goto nochange;
1344 } else {
1345 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1346 goto nochange;
1347 xm_read16(hw, port, XM_ISRC);
1348 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1349 goto nochange;
1350 }
1351
1352 mutex_lock(&hw->phy_mutex);
1353 xm_check_link(dev);
1354 mutex_unlock(&hw->phy_mutex);
1355
1356nochange:
1357 schedule_delayed_work(&skge->link_thread, LINK_HZ);
45bada65
SH		 1358}
1359
1360static void genesis_mac_init(struct skge_hw *hw, int port)
1361{
1362 struct net_device *dev = hw->dev[port];
1363 struct skge_port *skge = netdev_priv(dev);
1364 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1365 int i;
1366 u32 r;
1367 const u8 zero[6] = { 0 };
1368
0781191c
SH		 1369 for (i = 0; i < 10; i++) {
1370 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1371 MFF_SET_MAC_RST);
1372 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1373 goto reset_ok;
1374 udelay(1);
1375 }
baef58b1 1376
0781191c
SH		 1377 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1378
1379 reset_ok:
baef58b1 1380 /* Unreset the XMAC. */
6b0c1480 1381 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1382
1383 /*
1384 * Perform additional initialization for external PHYs,
1385 * namely for the 1000baseTX cards that use the XMAC's
1386 * GMII mode.
1387 */
64f6b64d
SH		 1388 if (hw->phy_type != SK_PHY_XMAC) {
1389 /* Take external Phy out of reset */
1390 r = skge_read32(hw, B2_GP_IO);
1391 if (port == 0)
1392 r |= GP_DIR_0|GP_IO_0;
1393 else
1394 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1395
64f6b64d 1396 skge_write32(hw, B2_GP_IO, r);
0781191c 1397
64f6b64d
SH		 1398 /* Enable GMII interface */
1399 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1400 }
89bf5f23 1401
89bf5f23 1402
64f6b64d
SH		 1403 switch(hw->phy_type) {
1404 case SK_PHY_XMAC:
1405 xm_phy_init(skge);
1406 break;
1407 case SK_PHY_BCOM:
1408 bcom_phy_init(skge);
1409 bcom_check_link(hw, port);
1410 }
89bf5f23 1411
45bada65
SH		 1412 /* Set Station Address */
1413 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1414
45bada65
SH		 1415 /* We don't use match addresses so clear */
1416 for (i = 1; i < 16; i++)
1417 xm_outaddr(hw, port, XM_EXM(i), zero);
1418
0781191c
SH		 1419 /* Clear MIB counters */
1420 xm_write16(hw, port, XM_STAT_CMD,
1421 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1422 /* Clear two times according to Errata #3 */
1423 xm_write16(hw, port, XM_STAT_CMD,
1424 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1425
45bada65
SH		 1426 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1427 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1428
1429 /* We don't need the FCS appended to the packet. */
1430 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1431 if (jumbo)
1432 r |= XM_RX_BIG_PK_OK;
89bf5f23 1433
45bada65 1434 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1435 /*
45bada65
SH		 1436 * If in manual half duplex mode the other side might be in
1437 * full duplex mode, so ignore if a carrier extension is not seen
1438 * on frames received
89bf5f23 1439 */
45bada65 1440 r |= XM_RX_DIS_CEXT;
baef58b1 1441 }
45bada65 1442 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1443
baef58b1
SH		 1444
1445 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1446 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1447
1448 /*
1449 * Bump up the transmit threshold. This helps hold off transmit
1450 * underruns when we're blasting traffic from both ports at once.
1451 */
1452 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1453
1454 /*
1455 * Enable the reception of all error frames. This is is
1456 * a necessary evil due to the design of the XMAC. The
1457 * XMAC's receive FIFO is only 8K in size, however jumbo
1458 * frames can be up to 9000 bytes in length. When bad
1459 * frame filtering is enabled, the XMAC's RX FIFO operates
1460 * in 'store and forward' mode. For this to work, the
1461 * entire frame has to fit into the FIFO, but that means
1462 * that jumbo frames larger than 8192 bytes will be
1463 * truncated. Disabling all bad frame filtering causes
1464 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1465 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1466 * RX FIFO as soon as the FIFO threshold is reached.
1467 */
45bada65 1468 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1469
baef58b1
SH		 1470
1471 /*
45bada65
SH		 1472 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1473 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1474 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1475 */
45bada65
SH		 1476 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1477
1478 /*
1479 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1480 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1481 * and 'Octets Tx OK Hi Cnt Ov'.
1482 */
1483 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1484
1485 /* Configure MAC arbiter */
1486 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1487
1488 /* configure timeout values */
1489 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1490 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1491 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1492 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1493
1494 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1495 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1496 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1497 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1498
1499 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1500 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1501 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1502 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1503
1504 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1505 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1506 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1507 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1508
45bada65 1509 if (jumbo) {
baef58b1 1510 /* Enable frame flushing if jumbo frames used */
6b0c1480 1511 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1512 } else {
1513 /* enable timeout timers if normal frames */
1514 skge_write16(hw, B3_PA_CTRL,
45bada65 1515 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1516 }
baef58b1
SH		 1517}
1518
1519static void genesis_stop(struct skge_port *skge)
1520{
1521 struct skge_hw *hw = skge->hw;
1522 int port = skge->port;
89bf5f23 1523 u32 reg;
baef58b1 1524
46a60f2d
SH		 1525 genesis_reset(hw, port);
1526
baef58b1
SH		 1527 /* Clear Tx packet arbiter timeout IRQ */
1528 skge_write16(hw, B3_PA_CTRL,
1529 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1530
1531 /*
8f3f8193 1532 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1533 * terminate if we don't flush the XMAC's transmit FIFO !
1534 */
6b0c1480
SH		 1535 xm_write32(hw, port, XM_MODE,
1536 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1537
1538
1539 /* Reset the MAC */
6b0c1480 1540 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1541
1542 /* For external PHYs there must be special handling */
64f6b64d
SH		 1543 if (hw->phy_type != SK_PHY_XMAC) {
1544 reg = skge_read32(hw, B2_GP_IO);
1545 if (port == 0) {
1546 reg |= GP_DIR_0;
1547 reg &= ~GP_IO_0;
1548 } else {
1549 reg |= GP_DIR_2;
1550 reg &= ~GP_IO_2;
1551 }
1552 skge_write32(hw, B2_GP_IO, reg);
1553 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1554 }
1555
6b0c1480
SH		 1556 xm_write16(hw, port, XM_MMU_CMD,
1557 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1558 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1559
6b0c1480 1560 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1561}
1562
1563
1564static void genesis_get_stats(struct skge_port *skge, u64 *data)
1565{
1566 struct skge_hw *hw = skge->hw;
1567 int port = skge->port;
1568 int i;
1569 unsigned long timeout = jiffies + HZ;
1570
6b0c1480 1571 xm_write16(hw, port,
baef58b1
SH		 1572 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1573
1574 /* wait for update to complete */
6b0c1480 1575 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1576 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1577 if (time_after(jiffies, timeout))
1578 break;
1579 udelay(10);
1580 }
1581
1582 /* special case for 64 bit octet counter */
6b0c1480
SH		 1583 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1584 | xm_read32(hw, port, XM_TXO_OK_LO);
1585 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1586 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1587
1588 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1589 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1590}
1591
1592static void genesis_mac_intr(struct skge_hw *hw, int port)
1593{
1594 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1595 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1596
7e676d91
SH		 1597 if (netif_msg_intr(skge))
1598 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1599 skge->netdev->name, status);
baef58b1 1600
a1bc9b87
SH		 1601 if (hw->phy_type == SK_PHY_XMAC &&
1602 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1603 xm_link_down(hw, port);
1604
baef58b1 1605 if (status & XM_IS_TXF_UR) {
6b0c1480 1606 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1607 ++skge->net_stats.tx_fifo_errors;
1608 }
1609 if (status & XM_IS_RXF_OV) {
6b0c1480 1610 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1611 ++skge->net_stats.rx_fifo_errors;
1612 }
1613}
1614
baef58b1
SH		 1615static void genesis_link_up(struct skge_port *skge)
1616{
1617 struct skge_hw *hw = skge->hw;
1618 int port = skge->port;
a1bc9b87 1619 u16 cmd, msk;
64f6b64d 1620 u32 mode;
baef58b1 1621
6b0c1480 1622 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1623
1624 /*
1625 * enabling pause frame reception is required for 1000BT
1626 * because the XMAC is not reset if the link is going down
1627 */
5d5c8e03
SH		 1628 if (skge->flow_status == FLOW_STAT_NONE ||
1629 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1630 /* Disable Pause Frame Reception */
baef58b1
SH		 1631 cmd |= XM_MMU_IGN_PF;
1632 else
1633 /* Enable Pause Frame Reception */
1634 cmd &= ~XM_MMU_IGN_PF;
1635
6b0c1480 1636 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1637
6b0c1480 1638 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1639 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1640 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1641 /*
1642 * Configure Pause Frame Generation
1643 * Use internal and external Pause Frame Generation.
1644 * Sending pause frames is edge triggered.
1645 * Send a Pause frame with the maximum pause time if
1646 * internal oder external FIFO full condition occurs.
1647 * Send a zero pause time frame to re-start transmission.
1648 */
1649 /* XM_PAUSE_DA = '010000C28001' (default) */
1650 /* XM_MAC_PTIME = 0xffff (maximum) */
1651 /* remember this value is defined in big endian (!) */
6b0c1480 1652 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1653
1654 mode |= XM_PAUSE_MODE;
6b0c1480 1655 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1656 } else {
1657 /*
1658 * disable pause frame generation is required for 1000BT
1659 * because the XMAC is not reset if the link is going down
1660 */
1661 /* Disable Pause Mode in Mode Register */
1662 mode &= ~XM_PAUSE_MODE;
1663
6b0c1480 1664 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1665 }
1666
6b0c1480 1667 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87
SH		 1668 msk = XM_DEF_MSK;
1669 if (hw->phy_type != SK_PHY_XMAC)
1670 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1671
1672 xm_write16(hw, port, XM_IMSK, msk);
6b0c1480 1673 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1674
1675 /* get MMU Command Reg. */
6b0c1480 1676 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1677 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1678 cmd |= XM_MMU_GMII_FD;
1679
89bf5f23
SH		 1680 /*
1681 * Workaround BCOM Errata (#10523) for all BCom Phys
1682 * Enable Power Management after link up
1683 */
64f6b64d
SH		 1684 if (hw->phy_type == SK_PHY_BCOM) {
1685 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1686 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1687 & ~PHY_B_AC_DIS_PM);
1688 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1689 }
baef58b1
SH		 1690
1691 /* enable Rx/Tx */
6b0c1480 1692 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1693 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1694 skge_link_up(skge);
1695}
1696
1697
45bada65 1698static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1699{
1700 struct skge_hw *hw = skge->hw;
1701 int port = skge->port;
45bada65
SH		 1702 u16 isrc;
1703
1704 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1705 if (netif_msg_intr(skge))
1706 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1707 skge->netdev->name, isrc);
baef58b1 1708
45bada65
SH		 1709 if (isrc & PHY_B_IS_PSE)
1710 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1711 hw->dev[port]->name);
baef58b1
SH		 1712
1713 /* Workaround BCom Errata:
1714 * enable and disable loopback mode if "NO HCD" occurs.
1715 */
45bada65 1716 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1717 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1718 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1719 ctrl | PHY_CT_LOOP);
6b0c1480 1720 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1721 ctrl & ~PHY_CT_LOOP);
1722 }
1723
45bada65
SH		 1724 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1725 bcom_check_link(hw, port);
baef58b1 1726
baef58b1
SH		 1727}
1728
2cd8e5d3
SH		 1729static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1730{
1731 int i;
1732
1733 gma_write16(hw, port, GM_SMI_DATA, val);
1734 gma_write16(hw, port, GM_SMI_CTRL,
1735 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1736 for (i = 0; i < PHY_RETRIES; i++) {
1737 udelay(1);
1738
1739 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1740 return 0;
1741 }
1742
1743 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1744 hw->dev[port]->name);
1745 return -EIO;
1746}
1747
1748static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1749{
1750 int i;
1751
1752 gma_write16(hw, port, GM_SMI_CTRL,
1753 GM_SMI_CT_PHY_AD(hw->phy_addr)
1754 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1755
1756 for (i = 0; i < PHY_RETRIES; i++) {
1757 udelay(1);
1758 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1759 goto ready;
1760 }
1761
1762 return -ETIMEDOUT;
1763 ready:
1764 *val = gma_read16(hw, port, GM_SMI_DATA);
1765 return 0;
1766}
1767
1768static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1769{
1770 u16 v = 0;
1771 if (__gm_phy_read(hw, port, reg, &v))
1772 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1773 hw->dev[port]->name);
1774 return v;
1775}
1776
8f3f8193 1777/* Marvell Phy Initialization */
baef58b1
SH		 1778static void yukon_init(struct skge_hw *hw, int port)
1779{
1780 struct skge_port *skge = netdev_priv(hw->dev[port]);
1781 u16 ctrl, ct1000, adv;
baef58b1 1782
baef58b1 1783 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1784 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1785
1786 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1787 PHY_M_EC_MAC_S_MSK);
1788 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1789
c506a509 1790 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1791
6b0c1480 1792 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1793 }
1794
6b0c1480 1795 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1796 if (skge->autoneg == AUTONEG_DISABLE)
1797 ctrl &= ~PHY_CT_ANE;
1798
1799 ctrl |= PHY_CT_RESET;
6b0c1480 1800 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1801
1802 ctrl = 0;
1803 ct1000 = 0;
b18f2091 1804 adv = PHY_AN_CSMA;
baef58b1
SH		 1805
1806 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1807 if (hw->copper) {
baef58b1
SH		 1808 if (skge->advertising & ADVERTISED_1000baseT_Full)
1809 ct1000 |= PHY_M_1000C_AFD;
1810 if (skge->advertising & ADVERTISED_1000baseT_Half)
1811 ct1000 |= PHY_M_1000C_AHD;
1812 if (skge->advertising & ADVERTISED_100baseT_Full)
1813 adv |= PHY_M_AN_100_FD;
1814 if (skge->advertising & ADVERTISED_100baseT_Half)
1815 adv |= PHY_M_AN_100_HD;
1816 if (skge->advertising & ADVERTISED_10baseT_Full)
1817 adv |= PHY_M_AN_10_FD;
1818 if (skge->advertising & ADVERTISED_10baseT_Half)
1819 adv |= PHY_M_AN_10_HD;
baef58b1 1820
4b67be99
SH		 1821 /* Set Flow-control capabilities */
1822 adv |= phy_pause_map[skge->flow_control];
1823 } else {
1824 if (skge->advertising & ADVERTISED_1000baseT_Full)
1825 adv |= PHY_M_AN_1000X_AFD;
1826 if (skge->advertising & ADVERTISED_1000baseT_Half)
1827 adv |= PHY_M_AN_1000X_AHD;
1828
1829 adv |= fiber_pause_map[skge->flow_control];
1830 }
45bada65 1831
baef58b1
SH		 1832 /* Restart Auto-negotiation */
1833 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1834 } else {
1835 /* forced speed/duplex settings */
1836 ct1000 = PHY_M_1000C_MSE;
1837
1838 if (skge->duplex == DUPLEX_FULL)
1839 ctrl |= PHY_CT_DUP_MD;
1840
1841 switch (skge->speed) {
1842 case SPEED_1000:
1843 ctrl |= PHY_CT_SP1000;
1844 break;
1845 case SPEED_100:
1846 ctrl |= PHY_CT_SP100;
1847 break;
1848 }
1849
1850 ctrl |= PHY_CT_RESET;
1851 }
1852
c506a509 1853 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1854
6b0c1480
SH		 1855 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1856 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1857
baef58b1
SH		 1858 /* Enable phy interrupt on autonegotiation complete (or link up) */
1859 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1860 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1861 else
4cde06ed 1862 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1863}
1864
1865static void yukon_reset(struct skge_hw *hw, int port)
1866{
6b0c1480
SH		 1867 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1868 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1869 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1870 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1871 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1872
6b0c1480
SH		 1873 gma_write16(hw, port, GM_RX_CTRL,
1874 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1875 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1876}
1877
c8868611
SH		 1878/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1879static int is_yukon_lite_a0(struct skge_hw *hw)
1880{
1881 u32 reg;
1882 int ret;
1883
1884 if (hw->chip_id != CHIP_ID_YUKON)
1885 return 0;
1886
1887 reg = skge_read32(hw, B2_FAR);
1888 skge_write8(hw, B2_FAR + 3, 0xff);
1889 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1890 skge_write32(hw, B2_FAR, reg);
1891 return ret;
1892}
1893
baef58b1
SH		 1894static void yukon_mac_init(struct skge_hw *hw, int port)
1895{
1896 struct skge_port *skge = netdev_priv(hw->dev[port]);
1897 int i;
1898 u32 reg;
1899 const u8 *addr = hw->dev[port]->dev_addr;
1900
1901 /* WA code for COMA mode -- set PHY reset */
1902 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1903 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1904 reg = skge_read32(hw, B2_GP_IO);
1905 reg |= GP_DIR_9 | GP_IO_9;
1906 skge_write32(hw, B2_GP_IO, reg);
1907 }
baef58b1
SH		 1908
1909 /* hard reset */
6b0c1480
SH		 1910 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1911 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1912
1913 /* WA code for COMA mode -- clear PHY reset */
1914 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1915 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1916 reg = skge_read32(hw, B2_GP_IO);
1917 reg |= GP_DIR_9;
1918 reg &= ~GP_IO_9;
1919 skge_write32(hw, B2_GP_IO, reg);
1920 }
baef58b1
SH		 1921
1922 /* Set hardware config mode */
1923 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1924 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1925 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1926
1927 /* Clear GMC reset */
6b0c1480
SH		 1928 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1929 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1930 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1931
baef58b1
SH		 1932 if (skge->autoneg == AUTONEG_DISABLE) {
1933 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1934 gma_write16(hw, port, GM_GP_CTRL,
1935 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1936
1937 switch (skge->speed) {
1938 case SPEED_1000:
564f9abb 1939 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1940 reg |= GM_GPCR_SPEED_1000;
564f9abb 1941 break;
baef58b1 1942 case SPEED_100:
564f9abb 1943 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1944 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1945 break;
1946 case SPEED_10:
1947 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1948 break;
baef58b1
SH		 1949 }
1950
1951 if (skge->duplex == DUPLEX_FULL)
1952 reg |= GM_GPCR_DUP_FULL;
1953 } else
1954 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1955
baef58b1
SH		 1956 switch (skge->flow_control) {
1957 case FLOW_MODE_NONE:
6b0c1480 1958 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1959 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1960 break;
1961 case FLOW_MODE_LOC_SEND:
1962 /* disable Rx flow-control */
1963 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 1964 break;
1965 case FLOW_MODE_SYMMETRIC:
1966 case FLOW_MODE_SYM_OR_REM:
1967 /* enable Tx & Rx flow-control */
1968 break;
baef58b1
SH		 1969 }
1970
6b0c1480 1971 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1972 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1973
baef58b1 1974 yukon_init(hw, port);
baef58b1
SH		 1975
1976 /* MIB clear */
6b0c1480
SH		 1977 reg = gma_read16(hw, port, GM_PHY_ADDR);
1978 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1979
1980 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1981 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1982 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1983
1984 /* transmit control */
6b0c1480 1985 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1986
1987 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1988 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1989 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1990
1991 /* transmit flow control */
6b0c1480 1992 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1993
1994 /* transmit parameter */
6b0c1480 1995 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1996 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1997 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1998 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1999
2000 /* serial mode register */
2001 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2002 if (hw->dev[port]->mtu > 1500)
2003 reg |= GM_SMOD_JUMBO_ENA;
2004
6b0c1480 2005 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2006
2007 /* physical address: used for pause frames */
6b0c1480 2008 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2009 /* virtual address for data */
6b0c1480 2010 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2011
2012 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2013 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2014 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2015 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2016
2017 /* Initialize Mac Fifo */
2018
2019 /* Configure Rx MAC FIFO */
6b0c1480 2020 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2021 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2022
2023 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2024 if (is_yukon_lite_a0(hw))
baef58b1 2025 reg &= ~GMF_RX_F_FL_ON;
c8868611 2026
6b0c1480
SH		 2027 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2028 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2029 /*
2030 * because Pause Packet Truncation in GMAC is not working
2031 * we have to increase the Flush Threshold to 64 bytes
2032 * in order to flush pause packets in Rx FIFO on Yukon-1
2033 */
2034 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2035
2036 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2037 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2038 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2039}
2040
355ec572
SH		 2041/* Go into power down mode */
2042static void yukon_suspend(struct skge_hw *hw, int port)
2043{
2044 u16 ctrl;
2045
2046 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2047 ctrl |= PHY_M_PC_POL_R_DIS;
2048 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2049
2050 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2051 ctrl |= PHY_CT_RESET;
2052 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2053
2054 /* switch IEEE compatible power down mode on */
2055 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2056 ctrl |= PHY_CT_PDOWN;
2057 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2058}
2059
baef58b1
SH		 2060static void yukon_stop(struct skge_port *skge)
2061{
2062 struct skge_hw *hw = skge->hw;
2063 int port = skge->port;
2064
46a60f2d
SH		 2065 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2066 yukon_reset(hw, port);
baef58b1 2067
6b0c1480
SH		 2068 gma_write16(hw, port, GM_GP_CTRL,
2069 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2070 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2071 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2072
355ec572 2073 yukon_suspend(hw, port);
46a60f2d 2074
baef58b1 2075 /* set GPHY Control reset */
46a60f2d
SH		 2076 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2077 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2078}
2079
2080static void yukon_get_stats(struct skge_port *skge, u64 *data)
2081{
2082 struct skge_hw *hw = skge->hw;
2083 int port = skge->port;
2084 int i;
2085
6b0c1480
SH		 2086 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2087 | gma_read32(hw, port, GM_TXO_OK_LO);
2088 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2089 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2090
2091 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2092 data[i] = gma_read32(hw, port,
baef58b1
SH		 2093 skge_stats[i].gma_offset);
2094}
2095
2096static void yukon_mac_intr(struct skge_hw *hw, int port)
2097{
7e676d91
SH		 2098 struct net_device *dev = hw->dev[port];
2099 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2100 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2101
7e676d91
SH		 2102 if (netif_msg_intr(skge))
2103 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2104 dev->name, status);
2105
baef58b1
SH		 2106 if (status & GM_IS_RX_FF_OR) {
2107 ++skge->net_stats.rx_fifo_errors;
d8a09943 2108 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2109 }
d8a09943 2110
baef58b1
SH		 2111 if (status & GM_IS_TX_FF_UR) {
2112 ++skge->net_stats.tx_fifo_errors;
d8a09943 2113 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2114 }
2115
2116}
2117
2118static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2119{
95566065 2120 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2121 case PHY_M_PS_SPEED_1000:
2122 return SPEED_1000;
2123 case PHY_M_PS_SPEED_100:
2124 return SPEED_100;
2125 default:
2126 return SPEED_10;
2127 }
2128}
2129
2130static void yukon_link_up(struct skge_port *skge)
2131{
2132 struct skge_hw *hw = skge->hw;
2133 int port = skge->port;
2134 u16 reg;
2135
baef58b1 2136 /* Enable Transmit FIFO Underrun */
46a60f2d 2137 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2138
6b0c1480 2139 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2140 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2141 reg |= GM_GPCR_DUP_FULL;
2142
2143 /* enable Rx/Tx */
2144 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2145 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2146
4cde06ed 2147 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2148 skge_link_up(skge);
2149}
2150
2151static void yukon_link_down(struct skge_port *skge)
2152{
2153 struct skge_hw *hw = skge->hw;
2154 int port = skge->port;
d8a09943 2155 u16 ctrl;
baef58b1 2156
d8a09943
SH		 2157 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2158 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2159 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2160
5d5c8e03
SH		 2161 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2162 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2163 ctrl |= PHY_M_AN_ASP;
baef58b1 2164 /* restore Asymmetric Pause bit */
5d5c8e03 2165 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2166 }
2167
baef58b1
SH		 2168 skge_link_down(skge);
2169
2170 yukon_init(hw, port);
2171}
2172
2173static void yukon_phy_intr(struct skge_port *skge)
2174{
2175 struct skge_hw *hw = skge->hw;
2176 int port = skge->port;
2177 const char *reason = NULL;
2178 u16 istatus, phystat;
2179
6b0c1480
SH		 2180 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2181 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2182
2183 if (netif_msg_intr(skge))
2184 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2185 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2186
2187 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2188 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2189 & PHY_M_AN_RF) {
2190 reason = "remote fault";
2191 goto failed;
2192 }
2193
c506a509 2194 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2195 reason = "master/slave fault";
2196 goto failed;
2197 }
2198
2199 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2200 reason = "speed/duplex";
2201 goto failed;
2202 }
2203
2204 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2205 ? DUPLEX_FULL : DUPLEX_HALF;
2206 skge->speed = yukon_speed(hw, phystat);
2207
baef58b1
SH		 2208 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2209 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2210 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2211 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2212 break;
2213 case PHY_M_PS_RX_P_EN:
5d5c8e03 2214 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2215 break;
2216 case PHY_M_PS_TX_P_EN:
5d5c8e03 2217 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2218 break;
2219 default:
5d5c8e03 2220 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2221 }
2222
5d5c8e03 2223 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2224 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2225 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2226 else
6b0c1480 2227 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2228 yukon_link_up(skge);
2229 return;
2230 }
2231
2232 if (istatus & PHY_M_IS_LSP_CHANGE)
2233 skge->speed = yukon_speed(hw, phystat);
2234
2235 if (istatus & PHY_M_IS_DUP_CHANGE)
2236 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2237 if (istatus & PHY_M_IS_LST_CHANGE) {
2238 if (phystat & PHY_M_PS_LINK_UP)
2239 yukon_link_up(skge);
2240 else
2241 yukon_link_down(skge);
2242 }
2243 return;
2244 failed:
2245 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2246 skge->netdev->name, reason);
2247
2248 /* XXX restart autonegotiation? */
2249}
2250
ee294dcd
SH		 2251static void skge_phy_reset(struct skge_port *skge)
2252{
2253 struct skge_hw *hw = skge->hw;
2254 int port = skge->port;
2255
2256 netif_stop_queue(skge->netdev);
2257 netif_carrier_off(skge->netdev);
2258
d85b514f 2259 mutex_lock(&hw->phy_mutex);
ee294dcd
SH		 2260 if (hw->chip_id == CHIP_ID_GENESIS) {
2261 genesis_reset(hw, port);
2262 genesis_mac_init(hw, port);
2263 } else {
2264 yukon_reset(hw, port);
2265 yukon_init(hw, port);
2266 }
d85b514f 2267 mutex_unlock(&hw->phy_mutex);
75814090
SH		 2268
2269 dev->set_multicast_list(dev);
ee294dcd
SH		 2270}
2271
2cd8e5d3
SH		 2272/* Basic MII support */
2273static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2274{
2275 struct mii_ioctl_data *data = if_mii(ifr);
2276 struct skge_port *skge = netdev_priv(dev);
2277 struct skge_hw *hw = skge->hw;
2278 int err = -EOPNOTSUPP;
2279
2280 if (!netif_running(dev))
2281 return -ENODEV; /* Phy still in reset */
2282
2283 switch(cmd) {
2284 case SIOCGMIIPHY:
2285 data->phy_id = hw->phy_addr;
2286
2287 /* fallthru */
2288 case SIOCGMIIREG: {
2289 u16 val = 0;
d85b514f 2290 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2291 if (hw->chip_id == CHIP_ID_GENESIS)
2292 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2293 else
2294 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
d85b514f 2295 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2296 data->val_out = val;
2297 break;
2298 }
2299
2300 case SIOCSMIIREG:
2301 if (!capable(CAP_NET_ADMIN))
2302 return -EPERM;
2303
d85b514f 2304 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2305 if (hw->chip_id == CHIP_ID_GENESIS)
2306 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2307 data->val_in);
2308 else
2309 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2310 data->val_in);
d85b514f 2311 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2312 break;
2313 }
2314 return err;
2315}
2316
baef58b1
SH		 2317static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2318{
2319 u32 end;
2320
2321 start /= 8;
2322 len /= 8;
2323 end = start + len - 1;
2324
2325 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2326 skge_write32(hw, RB_ADDR(q, RB_START), start);
2327 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2328 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2329 skge_write32(hw, RB_ADDR(q, RB_END), end);
2330
2331 if (q == Q_R1 || q == Q_R2) {
2332 /* Set thresholds on receive queue's */
2333 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2334 start + (2*len)/3);
2335 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2336 start + (len/3));
2337 } else {
2338 /* Enable store & forward on Tx queue's because
2339 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2340 */
2341 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2342 }
2343
2344 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2345}
2346
2347/* Setup Bus Memory Interface */
2348static void skge_qset(struct skge_port *skge, u16 q,
2349 const struct skge_element *e)
2350{
2351 struct skge_hw *hw = skge->hw;
2352 u32 watermark = 0x600;
2353 u64 base = skge->dma + (e->desc - skge->mem);
2354
2355 /* optimization to reduce window on 32bit/33mhz */
2356 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2357 watermark /= 2;
2358
2359 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2360 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2361 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2362 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2363}
2364
2365static int skge_up(struct net_device *dev)
2366{
2367 struct skge_port *skge = netdev_priv(dev);
2368 struct skge_hw *hw = skge->hw;
2369 int port = skge->port;
2370 u32 chunk, ram_addr;
2371 size_t rx_size, tx_size;
2372 int err;
2373
2374 if (netif_msg_ifup(skge))
2375 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2376
19a33d4e 2377 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2378 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2379 else
2380 skge->rx_buf_size = RX_BUF_SIZE;
2381
2382
baef58b1
SH		 2383 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2384 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2385 skge->mem_size = tx_size + rx_size;
2386 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2387 if (!skge->mem)
2388 return -ENOMEM;
2389
c3da1447
SH		 2390 BUG_ON(skge->dma & 7);
2391
2392 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2393 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2394 err = -EINVAL;
2395 goto free_pci_mem;
2396 }
2397
baef58b1
SH		 2398 memset(skge->mem, 0, skge->mem_size);
2399
203babb6
SH		 2400 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2401 if (err)
baef58b1
SH		 2402 goto free_pci_mem;
2403
c54f9765 2404 err = skge_rx_fill(dev);
19a33d4e 2405 if (err)
baef58b1
SH		 2406 goto free_rx_ring;
2407
203babb6
SH		 2408 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2409 skge->dma + rx_size);
2410 if (err)
baef58b1
SH		 2411 goto free_rx_ring;
2412
8f3f8193 2413 /* Initialize MAC */
d85b514f 2414 mutex_lock(&hw->phy_mutex);
baef58b1
SH		 2415 if (hw->chip_id == CHIP_ID_GENESIS)
2416 genesis_mac_init(hw, port);
2417 else
2418 yukon_mac_init(hw, port);
d85b514f 2419 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 2420
2421 /* Configure RAMbuffers */
981d0377 2422 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2423 ram_addr = hw->ram_offset + 2 * chunk * port;
2424
2425 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2426 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2427
2428 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2429 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2430 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2431
2432 /* Start receiver BMU */
2433 wmb();
2434 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2435 skge_led(skge, LED_MODE_ON);
baef58b1 2436
239e44e1 2437 netif_poll_enable(dev);
baef58b1
SH		 2438 return 0;
2439
2440 free_rx_ring:
2441 skge_rx_clean(skge);
2442 kfree(skge->rx_ring.start);
2443 free_pci_mem:
2444 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2445 skge->mem = NULL;
baef58b1
SH		 2446
2447 return err;
2448}
2449
2450static int skge_down(struct net_device *dev)
2451{
2452 struct skge_port *skge = netdev_priv(dev);
2453 struct skge_hw *hw = skge->hw;
2454 int port = skge->port;
2455
7731a4ea
SH		 2456 if (skge->mem == NULL)
2457 return 0;
2458
baef58b1
SH		 2459 if (netif_msg_ifdown(skge))
2460 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2461
2462 netif_stop_queue(dev);
64f6b64d
SH		 2463 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2464 cancel_rearming_delayed_work(&skge->link_thread);
baef58b1 2465
46a60f2d
SH		 2466 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2467 if (hw->chip_id == CHIP_ID_GENESIS)
2468 genesis_stop(skge);
2469 else
2470 yukon_stop(skge);
2471
baef58b1
SH		 2472 /* Stop transmitter */
2473 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2474 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2475 RB_RST_SET|RB_DIS_OP_MD);
2476
baef58b1
SH		 2477
2478 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2479 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2480 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2481
2482 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2483 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2484 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2485
2486 /* Reset PCI FIFO */
2487 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2488 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2489
2490 /* Reset the RAM Buffer async Tx queue */
2491 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2492 /* stop receiver */
2493 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2494 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2495 RB_RST_SET|RB_DIS_OP_MD);
2496 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2497
2498 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2499 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2500 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2501 } else {
6b0c1480
SH		 2502 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2503 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2504 }
2505
6abebb53 2506 skge_led(skge, LED_MODE_OFF);
baef58b1 2507
239e44e1 2508 netif_poll_disable(dev);
513f533e 2509 skge_tx_clean(dev);
baef58b1
SH		 2510 skge_rx_clean(skge);
2511
2512 kfree(skge->rx_ring.start);
2513 kfree(skge->tx_ring.start);
2514 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2515 skge->mem = NULL;
baef58b1
SH		 2516 return 0;
2517}
2518
29b4e886
SH		 2519static inline int skge_avail(const struct skge_ring *ring)
2520{
2521 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2522 + (ring->to_clean - ring->to_use) - 1;
2523}
2524
baef58b1
SH		 2525static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2526{
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2529 struct skge_element *e;
2530 struct skge_tx_desc *td;
2531 int i;
2532 u32 control, len;
2533 u64 map;
baef58b1 2534
5b057c6b 2535 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2536 return NETDEV_TX_OK;
2537
513f533e 2538 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2539 return NETDEV_TX_BUSY;
baef58b1 2540
7c442fa1 2541 e = skge->tx_ring.to_use;
baef58b1 2542 td = e->desc;
7c442fa1 2543 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2544 e->skb = skb;
2545 len = skb_headlen(skb);
2546 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2547 pci_unmap_addr_set(e, mapaddr, map);
2548 pci_unmap_len_set(e, maplen, len);
2549
2550 td->dma_lo = map;
2551 td->dma_hi = map >> 32;
2552
84fa7933 2553 if (skb->ip_summed == CHECKSUM_PARTIAL) {
baef58b1
SH		 2554 int offset = skb->h.raw - skb->data;
2555
2556 /* This seems backwards, but it is what the sk98lin
2557 * does. Looks like hardware is wrong?
2558 */
ea182d4a 2559 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2560 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2561 control = BMU_TCP_CHECK;
2562 else
2563 control = BMU_UDP_CHECK;
2564
2565 td->csum_offs = 0;
2566 td->csum_start = offset;
2567 td->csum_write = offset + skb->csum;
2568 } else
2569 control = BMU_CHECK;
2570
2571 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2572 control |= BMU_EOF| BMU_IRQ_EOF;
2573 else {
2574 struct skge_tx_desc *tf = td;
2575
2576 control |= BMU_STFWD;
2577 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2578 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2579
2580 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2581 frag->size, PCI_DMA_TODEVICE);
2582
2583 e = e->next;
7c442fa1 2584 e->skb = skb;
baef58b1 2585 tf = e->desc;
7c442fa1
SH		 2586 BUG_ON(tf->control & BMU_OWN);
2587
baef58b1
SH		 2588 tf->dma_lo = map;
2589 tf->dma_hi = (u64) map >> 32;
2590 pci_unmap_addr_set(e, mapaddr, map);
2591 pci_unmap_len_set(e, maplen, frag->size);
2592
2593 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2594 }
2595 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2596 }
2597 /* Make sure all the descriptors written */
2598 wmb();
2599 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2600 wmb();
2601
2602 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2603
7c442fa1 2604 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2605 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2606 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2607
7c442fa1 2608 skge->tx_ring.to_use = e->next;
9db96479 2609 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2610 pr_debug("%s: transmit queue full\n", dev->name);
2611 netif_stop_queue(dev);
2612 }
2613
c68ce71a
SH		 2614 dev->trans_start = jiffies;
2615
baef58b1
SH		 2616 return NETDEV_TX_OK;
2617}
2618
7c442fa1
SH		 2619
2620/* Free resources associated with this reing element */
2621static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2622 u32 control)
866b4f3e
SH		 2623{
2624 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2625
7c442fa1 2626 BUG_ON(!e->skb);
866b4f3e 2627
7c442fa1
SH		 2628 /* skb header vs. fragment */
2629 if (control & BMU_STF)
866b4f3e 2630 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2631 pci_unmap_len(e, maplen),
2632 PCI_DMA_TODEVICE);
2633 else
2634 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2635 pci_unmap_len(e, maplen),
2636 PCI_DMA_TODEVICE);
866b4f3e 2637
7c442fa1
SH		 2638 if (control & BMU_EOF) {
2639 if (unlikely(netif_msg_tx_done(skge)))
2640 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2641 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2642
513f533e 2643 dev_kfree_skb(e->skb);
baef58b1 2644 }
7c442fa1 2645 e->skb = NULL;
baef58b1
SH		 2646}
2647
7c442fa1 2648/* Free all buffers in transmit ring */
513f533e 2649static void skge_tx_clean(struct net_device *dev)
baef58b1 2650{
513f533e 2651 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2652 struct skge_element *e;
baef58b1 2653
513f533e 2654 netif_tx_lock_bh(dev);
7c442fa1
SH		 2655 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2656 struct skge_tx_desc *td = e->desc;
2657 skge_tx_free(skge, e, td->control);
2658 td->control = 0;
2659 }
2660
2661 skge->tx_ring.to_clean = e;
513f533e
SH		 2662 netif_wake_queue(dev);
2663 netif_tx_unlock_bh(dev);
baef58b1
SH		 2664}
2665
2666static void skge_tx_timeout(struct net_device *dev)
2667{
2668 struct skge_port *skge = netdev_priv(dev);
2669
2670 if (netif_msg_timer(skge))
2671 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2672
2673 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2674 skge_tx_clean(dev);
baef58b1
SH		 2675}
2676
2677static int skge_change_mtu(struct net_device *dev, int new_mtu)
2678{
7731a4ea 2679 int err;
baef58b1 2680
95566065 2681 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2682 return -EINVAL;
2683
7731a4ea
SH		 2684 if (!netif_running(dev)) {
2685 dev->mtu = new_mtu;
2686 return 0;
2687 }
2688
2689 skge_down(dev);
baef58b1 2690
19a33d4e 2691 dev->mtu = new_mtu;
7731a4ea
SH		 2692
2693 err = skge_up(dev);
2694 if (err)
2695 dev_close(dev);
baef58b1
SH		 2696
2697 return err;
2698}
2699
2700static void genesis_set_multicast(struct net_device *dev)
2701{
2702 struct skge_port *skge = netdev_priv(dev);
2703 struct skge_hw *hw = skge->hw;
2704 int port = skge->port;
2705 int i, count = dev->mc_count;
2706 struct dev_mc_list *list = dev->mc_list;
2707 u32 mode;
2708 u8 filter[8];
2709
6b0c1480 2710 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2711 mode |= XM_MD_ENA_HASH;
2712 if (dev->flags & IFF_PROMISC)
2713 mode |= XM_MD_ENA_PROM;
2714 else
2715 mode &= ~XM_MD_ENA_PROM;
2716
2717 if (dev->flags & IFF_ALLMULTI)
2718 memset(filter, 0xff, sizeof(filter));
2719 else {
2720 memset(filter, 0, sizeof(filter));
95566065 2721 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2722 u32 crc, bit;
2723 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2724 bit = ~crc & 0x3f;
baef58b1
SH		 2725 filter[bit/8] |= 1 << (bit%8);
2726 }
2727 }
2728
6b0c1480 2729 xm_write32(hw, port, XM_MODE, mode);
45bada65 2730 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2731}
2732
2733static void yukon_set_multicast(struct net_device *dev)
2734{
2735 struct skge_port *skge = netdev_priv(dev);
2736 struct skge_hw *hw = skge->hw;
2737 int port = skge->port;
2738 struct dev_mc_list *list = dev->mc_list;
2739 u16 reg;
2740 u8 filter[8];
2741
2742 memset(filter, 0, sizeof(filter));
2743
6b0c1480 2744 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2745 reg |= GM_RXCR_UCF_ENA;
2746
8f3f8193 2747 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2748 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2749 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2750 memset(filter, 0xff, sizeof(filter));
2751 else if (dev->mc_count == 0) /* no multicast */
2752 reg &= ~GM_RXCR_MCF_ENA;
2753 else {
2754 int i;
2755 reg |= GM_RXCR_MCF_ENA;
2756
95566065 2757 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2758 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2759 filter[bit/8] |= 1 << (bit%8);
2760 }
2761 }
2762
2763
6b0c1480 2764 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2765 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2766 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2767 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2768 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2769 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2770 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2771 (u16)filter[6] | ((u16)filter[7] << 8));
2772
6b0c1480 2773 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2774}
2775
383181ac
SH		 2776static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2777{
2778 if (hw->chip_id == CHIP_ID_GENESIS)
2779 return status >> XMR_FS_LEN_SHIFT;
2780 else
2781 return status >> GMR_FS_LEN_SHIFT;
2782}
2783
baef58b1
SH		 2784static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2785{
2786 if (hw->chip_id == CHIP_ID_GENESIS)
2787 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2788 else
2789 return (status & GMR_FS_ANY_ERR) ||
2790 (status & GMR_FS_RX_OK) == 0;
2791}
2792
19a33d4e
SH		 2793
2794/* Get receive buffer from descriptor.
2795 * Handles copy of small buffers and reallocation failures
2796 */
c54f9765
SH		 2797static struct sk_buff *skge_rx_get(struct net_device *dev,
2798 struct skge_element *e,
2799 u32 control, u32 status, u16 csum)
19a33d4e 2800{
c54f9765 2801 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2802 struct sk_buff *skb;
2803 u16 len = control & BMU_BBC;
2804
2805 if (unlikely(netif_msg_rx_status(skge)))
2806 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2807 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2808 status, len);
2809
2810 if (len > skge->rx_buf_size)
2811 goto error;
2812
2813 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2814 goto error;
2815
2816 if (bad_phy_status(skge->hw, status))
2817 goto error;
2818
2819 if (phy_length(skge->hw, status) != len)
2820 goto error;
19a33d4e
SH		 2821
2822 if (len < RX_COPY_THRESHOLD) {
c54f9765 2823 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2824 if (!skb)
2825 goto resubmit;
19a33d4e 2826
383181ac 2827 skb_reserve(skb, 2);
19a33d4e
SH		 2828 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2829 pci_unmap_addr(e, mapaddr),
2830 len, PCI_DMA_FROMDEVICE);
383181ac 2831 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2832 pci_dma_sync_single_for_device(skge->hw->pdev,
2833 pci_unmap_addr(e, mapaddr),
2834 len, PCI_DMA_FROMDEVICE);
19a33d4e 2835 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2836 } else {
383181ac 2837 struct sk_buff *nskb;
c54f9765 2838 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 2839 if (!nskb)
2840 goto resubmit;
19a33d4e 2841
901ccefb 2842 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2843 pci_unmap_single(skge->hw->pdev,
2844 pci_unmap_addr(e, mapaddr),
2845 pci_unmap_len(e, maplen),
2846 PCI_DMA_FROMDEVICE);
2847 skb = e->skb;
383181ac 2848 prefetch(skb->data);
19a33d4e 2849 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2850 }
383181ac
SH		 2851
2852 skb_put(skb, len);
383181ac
SH		 2853 if (skge->rx_csum) {
2854 skb->csum = csum;
84fa7933 2855 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 2856 }
2857
c54f9765 2858 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 2859
2860 return skb;
2861error:
2862
2863 if (netif_msg_rx_err(skge))
2864 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 2865 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2866 control, status);
2867
2868 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2869 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2870 skge->net_stats.rx_length_errors++;
2871 if (status & XMR_FS_FRA_ERR)
2872 skge->net_stats.rx_frame_errors++;
2873 if (status & XMR_FS_FCS_ERR)
2874 skge->net_stats.rx_crc_errors++;
2875 } else {
2876 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2877 skge->net_stats.rx_length_errors++;
2878 if (status & GMR_FS_FRAGMENT)
2879 skge->net_stats.rx_frame_errors++;
2880 if (status & GMR_FS_CRC_ERR)
2881 skge->net_stats.rx_crc_errors++;
2882 }
2883
2884resubmit:
2885 skge_rx_reuse(e, skge->rx_buf_size);
2886 return NULL;
baef58b1
SH		 2887}
2888
7c442fa1 2889/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 2890static void skge_tx_done(struct net_device *dev)
00a6cae2 2891{
7c442fa1 2892 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2893 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2894 struct skge_element *e;
2895
513f533e 2896 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2897
513f533e 2898 netif_tx_lock(dev);
866b4f3e 2899 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2900 struct skge_tx_desc *td = e->desc;
00a6cae2 2901
866b4f3e 2902 if (td->control & BMU_OWN)
00a6cae2
SH		 2903 break;
2904
7c442fa1 2905 skge_tx_free(skge, e, td->control);
00a6cae2 2906 }
7c442fa1 2907 skge->tx_ring.to_clean = e;
866b4f3e 2908
513f533e
SH		 2909 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2910 netif_wake_queue(dev);
00a6cae2 2911
513f533e 2912 netif_tx_unlock(dev);
00a6cae2 2913}
19a33d4e 2914
baef58b1
SH		 2915static int skge_poll(struct net_device *dev, int *budget)
2916{
2917 struct skge_port *skge = netdev_priv(dev);
2918 struct skge_hw *hw = skge->hw;
2919 struct skge_ring *ring = &skge->rx_ring;
2920 struct skge_element *e;
00a6cae2
SH		 2921 int to_do = min(dev->quota, *budget);
2922 int work_done = 0;
2923
513f533e
SH		 2924 skge_tx_done(dev);
2925
2926 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2927
1631aef1 2928 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2929 struct skge_rx_desc *rd = e->desc;
19a33d4e 2930 struct sk_buff *skb;
383181ac 2931 u32 control;
baef58b1
SH		 2932
2933 rmb();
2934 control = rd->control;
2935 if (control & BMU_OWN)
2936 break;
2937
c54f9765 2938 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 2939 if (likely(skb)) {
19a33d4e
SH		 2940 dev->last_rx = jiffies;
2941 netif_receive_skb(skb);
baef58b1 2942
19a33d4e 2943 ++work_done;
5a011447 2944 }
baef58b1
SH		 2945 }
2946 ring->to_clean = e;
2947
baef58b1
SH		 2948 /* restart receiver */
2949 wmb();
a9cdab86 2950 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2951
19a33d4e
SH		 2952 *budget -= work_done;
2953 dev->quota -= work_done;
2954
2955 if (work_done >= to_do)
2956 return 1; /* not done */
baef58b1 2957
7c442fa1 2958 spin_lock_irq(&hw->hw_lock);
513f533e
SH		 2959 __netif_rx_complete(dev);
2960 hw->intr_mask |= irqmask[skge->port];
80dd857d 2961 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 2962 skge_read32(hw, B0_IMSK);
7c442fa1 2963 spin_unlock_irq(&hw->hw_lock);
1631aef1 2964
19a33d4e 2965 return 0;
baef58b1
SH		 2966}
2967
f6620cab
SH		 2968/* Parity errors seem to happen when Genesis is connected to a switch
2969 * with no other ports present. Heartbeat error??
2970 */
baef58b1
SH		 2971static void skge_mac_parity(struct skge_hw *hw, int port)
2972{
f6620cab
SH		 2973 struct net_device *dev = hw->dev[port];
2974
2975 if (dev) {
2976 struct skge_port *skge = netdev_priv(dev);
2977 ++skge->net_stats.tx_heartbeat_errors;
2978 }
baef58b1
SH		 2979
2980 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2981 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2982 MFF_CLR_PERR);
2983 else
2984 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2985 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2986 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2987 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2988}
2989
baef58b1
SH		 2990static void skge_mac_intr(struct skge_hw *hw, int port)
2991{
95566065 2992 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2993 genesis_mac_intr(hw, port);
2994 else
2995 yukon_mac_intr(hw, port);
2996}
2997
2998/* Handle device specific framing and timeout interrupts */
2999static void skge_error_irq(struct skge_hw *hw)
3000{
3001 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3002
3003 if (hw->chip_id == CHIP_ID_GENESIS) {
3004 /* clear xmac errors */
3005 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3006 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3007 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3008 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3009 } else {
3010 /* Timestamp (unused) overflow */
3011 if (hwstatus & IS_IRQ_TIST_OV)
3012 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3013 }
3014
3015 if (hwstatus & IS_RAM_RD_PAR) {
3016 printk(KERN_ERR PFX "Ram read data parity error\n");
3017 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3018 }
3019
3020 if (hwstatus & IS_RAM_WR_PAR) {
3021 printk(KERN_ERR PFX "Ram write data parity error\n");
3022 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3023 }
3024
3025 if (hwstatus & IS_M1_PAR_ERR)
3026 skge_mac_parity(hw, 0);
3027
3028 if (hwstatus & IS_M2_PAR_ERR)
3029 skge_mac_parity(hw, 1);
3030
b9d64acc
SH		 3031 if (hwstatus & IS_R1_PAR_ERR) {
3032 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3033 hw->dev[0]->name);
baef58b1 3034 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3035 }
baef58b1 3036
b9d64acc
SH		 3037 if (hwstatus & IS_R2_PAR_ERR) {
3038 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3039 hw->dev[1]->name);
baef58b1 3040 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3041 }
baef58b1
SH		 3042
3043 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3044 u16 pci_status, pci_cmd;
3045
3046 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
3047 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 3048
b9d64acc
SH		 3049 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
3050 pci_name(hw->pdev), pci_cmd, pci_status);
3051
3052 /* Write the error bits back to clear them. */
3053 pci_status &= PCI_STATUS_ERROR_BITS;
3054 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3055 pci_write_config_word(hw->pdev, PCI_COMMAND,
3056 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3057 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
3058 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3059
050ec18a 3060 /* if error still set then just ignore it */
baef58b1
SH		 3061 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3062 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 3063 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3064 hw->intr_mask &= ~IS_HW_ERR;
3065 }
3066 }
3067}
3068
3069/*
d85b514f 3070 * Interrupt from PHY are handled in work queue
baef58b1
SH		 3071 * because accessing phy registers requires spin wait which might
3072 * cause excess interrupt latency.
3073 */
d85b514f 3074static void skge_extirq(void *arg)
baef58b1 3075{
d85b514f 3076 struct skge_hw *hw = arg;
baef58b1
SH		 3077 int port;
3078
d85b514f 3079 mutex_lock(&hw->phy_mutex);
cfc3ed79 3080 for (port = 0; port < hw->ports; port++) {
baef58b1 3081 struct net_device *dev = hw->dev[port];
cfc3ed79 3082 struct skge_port *skge = netdev_priv(dev);
baef58b1 3083
cfc3ed79 3084 if (netif_running(dev)) {
baef58b1
SH		 3085 if (hw->chip_id != CHIP_ID_GENESIS)
3086 yukon_phy_intr(skge);
64f6b64d 3087 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3088 bcom_phy_intr(skge);
baef58b1
SH		 3089 }
3090 }
d85b514f 3091 mutex_unlock(&hw->phy_mutex);
baef58b1 3092
7c442fa1 3093 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3094 hw->intr_mask |= IS_EXT_REG;
3095 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3096 skge_read32(hw, B0_IMSK);
7c442fa1 3097 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3098}
3099
7d12e780 3100static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3101{
3102 struct skge_hw *hw = dev_id;
cfc3ed79 3103 u32 status;
29365c90 3104 int handled = 0;
baef58b1 3105
29365c90 3106 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3107 /* Reading this register masks IRQ */
3108 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3109 if (status == 0 || status == ~0)
29365c90 3110 goto out;
baef58b1 3111
29365c90 3112 handled = 1;
7c442fa1 3113 status &= hw->intr_mask;
cfc3ed79
SH		 3114 if (status & IS_EXT_REG) {
3115 hw->intr_mask &= ~IS_EXT_REG;
d85b514f 3116 schedule_work(&hw->phy_work);
cfc3ed79
SH		 3117 }
3118
513f533e
SH		 3119 if (status & (IS_XA1_F|IS_R1_F)) {
3120 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
7c442fa1 3121 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 3122 }
3123
7c442fa1
SH		 3124 if (status & IS_PA_TO_TX1)
3125 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3126
d25f5a67
SH		 3127 if (status & IS_PA_TO_RX1) {
3128 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3129
d25f5a67 3130 ++skge->net_stats.rx_over_errors;
7c442fa1 3131 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3132 }
3133
d25f5a67 3134
baef58b1
SH		 3135 if (status & IS_MAC1)
3136 skge_mac_intr(hw, 0);
95566065 3137
7c442fa1 3138 if (hw->dev[1]) {
513f533e
SH		 3139 if (status & (IS_XA2_F|IS_R2_F)) {
3140 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
7c442fa1
SH		 3141 netif_rx_schedule(hw->dev[1]);
3142 }
3143
3144 if (status & IS_PA_TO_RX2) {
3145 struct skge_port *skge = netdev_priv(hw->dev[1]);
3146 ++skge->net_stats.rx_over_errors;
3147 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3148 }
3149
3150 if (status & IS_PA_TO_TX2)
3151 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3152
3153 if (status & IS_MAC2)
3154 skge_mac_intr(hw, 1);
3155 }
baef58b1
SH		 3156
3157 if (status & IS_HW_ERR)
3158 skge_error_irq(hw);
3159
7e676d91 3160 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3161 skge_read32(hw, B0_IMSK);
29365c90 3162out:
7c442fa1 3163 spin_unlock(&hw->hw_lock);
baef58b1 3164
29365c90 3165 return IRQ_RETVAL(handled);
baef58b1
SH		 3166}
3167
3168#ifdef CONFIG_NET_POLL_CONTROLLER
3169static void skge_netpoll(struct net_device *dev)
3170{
3171 struct skge_port *skge = netdev_priv(dev);
3172
3173 disable_irq(dev->irq);
7d12e780 3174 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3175 enable_irq(dev->irq);
3176}
3177#endif
3178
3179static int skge_set_mac_address(struct net_device *dev, void *p)
3180{
3181 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3182 struct skge_hw *hw = skge->hw;
3183 unsigned port = skge->port;
3184 const struct sockaddr *addr = p;
baef58b1
SH		 3185
3186 if (!is_valid_ether_addr(addr->sa_data))
3187 return -EADDRNOTAVAIL;
3188
d85b514f 3189 mutex_lock(&hw->phy_mutex);
baef58b1 3190 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3191 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 3192 dev->dev_addr, ETH_ALEN);
c2681dd8 3193 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 3194 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 3195
3196 if (hw->chip_id == CHIP_ID_GENESIS)
3197 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3198 else {
3199 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3200 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3201 }
d85b514f 3202 mutex_unlock(&hw->phy_mutex);
c2681dd8
SH		 3203
3204 return 0;
baef58b1
SH		 3205}
3206
3207static const struct {
3208 u8 id;
3209 const char *name;
3210} skge_chips[] = {
3211 { CHIP_ID_GENESIS, "Genesis" },
3212 { CHIP_ID_YUKON, "Yukon" },
3213 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3214 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3215};
3216
3217static const char *skge_board_name(const struct skge_hw *hw)
3218{
3219 int i;
3220 static char buf[16];
3221
3222 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3223 if (skge_chips[i].id == hw->chip_id)
3224 return skge_chips[i].name;
3225
3226 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3227 return buf;
3228}
3229
3230
3231/*
3232 * Setup the board data structure, but don't bring up
3233 * the port(s)
3234 */
3235static int skge_reset(struct skge_hw *hw)
3236{
adba9e23 3237 u32 reg;
b9d64acc 3238 u16 ctst, pci_status;
64f6b64d 3239 u8 t8, mac_cfg, pmd_type;
981d0377 3240 int i;
baef58b1
SH		 3241
3242 ctst = skge_read16(hw, B0_CTST);
3243
3244 /* do a SW reset */
3245 skge_write8(hw, B0_CTST, CS_RST_SET);
3246 skge_write8(hw, B0_CTST, CS_RST_CLR);
3247
3248 /* clear PCI errors, if any */
b9d64acc
SH		 3249 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3250 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3251
b9d64acc
SH		 3252 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3253 pci_write_config_word(hw->pdev, PCI_STATUS,
3254 pci_status | PCI_STATUS_ERROR_BITS);
3255 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3256 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3257
3258 /* restore CLK_RUN bits (for Yukon-Lite) */
3259 skge_write16(hw, B0_CTST,
3260 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3261
3262 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3263 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3264 pmd_type = skge_read8(hw, B2_PMD_TYP);
3265 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3266
95566065 3267 switch (hw->chip_id) {
baef58b1 3268 case CHIP_ID_GENESIS:
64f6b64d
SH		 3269 switch (hw->phy_type) {
3270 case SK_PHY_XMAC:
3271 hw->phy_addr = PHY_ADDR_XMAC;
3272 break;
baef58b1
SH		 3273 case SK_PHY_BCOM:
3274 hw->phy_addr = PHY_ADDR_BCOM;
3275 break;
3276 default:
3277 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
64f6b64d 3278 pci_name(hw->pdev), hw->phy_type);
baef58b1
SH		 3279 return -EOPNOTSUPP;
3280 }
3281 break;
3282
3283 case CHIP_ID_YUKON:
3284 case CHIP_ID_YUKON_LITE:
3285 case CHIP_ID_YUKON_LP:
64f6b64d 3286 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3287 hw->copper = 1;
baef58b1
SH		 3288
3289 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3290 break;
3291
3292 default:
3293 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3294 pci_name(hw->pdev), hw->chip_id);
3295 return -EOPNOTSUPP;
3296 }
3297
981d0377
SH		 3298 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3299 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3300 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3301
3302 /* read the adapters RAM size */
3303 t8 = skge_read8(hw, B2_E_0);
3304 if (hw->chip_id == CHIP_ID_GENESIS) {
3305 if (t8 == 3) {
3306 /* special case: 4 x 64k x 36, offset = 0x80000 */
3307 hw->ram_size = 0x100000;
3308 hw->ram_offset = 0x80000;
3309 } else
3310 hw->ram_size = t8 * 512;
3311 }
3312 else if (t8 == 0)
3313 hw->ram_size = 0x20000;
3314 else
3315 hw->ram_size = t8 * 4096;
3316
64f6b64d 3317 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
cfc3ed79
SH		 3318 if (hw->ports > 1)
3319 hw->intr_mask |= IS_PORT_2;
3320
64f6b64d
SH		 3321 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3322 hw->intr_mask |= IS_EXT_REG;
3323
baef58b1
SH		 3324 if (hw->chip_id == CHIP_ID_GENESIS)
3325 genesis_init(hw);
3326 else {
3327 /* switch power to VCC (WA for VAUX problem) */
3328 skge_write8(hw, B0_POWER_CTRL,
3329 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3330
050ec18a
SH		 3331 /* avoid boards with stuck Hardware error bits */
3332 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3333 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3334 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3335 hw->intr_mask &= ~IS_HW_ERR;
3336 }
3337
adba9e23
SH		 3338 /* Clear PHY COMA */
3339 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3340 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3341 reg &= ~PCI_PHY_COMA;
3342 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3343 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3344
3345
981d0377 3346 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3347 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3348 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3349 }
3350 }
3351
3352 /* turn off hardware timer (unused) */
3353 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3354 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3355 skge_write8(hw, B0_LED, LED_STAT_ON);
3356
3357 /* enable the Tx Arbiters */
981d0377 3358 for (i = 0; i < hw->ports; i++)
6b0c1480 3359 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3360
3361 /* Initialize ram interface */
3362 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3363
3364 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3365 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3366 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3367 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3368 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3369 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3370 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3371 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3372 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3373 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3374 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3375 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3376
3377 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3378
3379 /* Set interrupt moderation for Transmit only
3380 * Receive interrupts avoided by NAPI
3381 */
3382 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3383 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3384 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3385
baef58b1
SH		 3386 skge_write32(hw, B0_IMSK, hw->intr_mask);
3387
d85b514f 3388 mutex_lock(&hw->phy_mutex);
981d0377 3389 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3390 if (hw->chip_id == CHIP_ID_GENESIS)
3391 genesis_reset(hw, i);
3392 else
3393 yukon_reset(hw, i);
3394 }
d85b514f 3395 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 3396
3397 return 0;
3398}
3399
3400/* Initialize network device */
981d0377
SH		 3401static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3402 int highmem)
baef58b1
SH		 3403{
3404 struct skge_port *skge;
3405 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3406
3407 if (!dev) {
3408 printk(KERN_ERR "skge etherdev alloc failed");
3409 return NULL;
3410 }
3411
3412 SET_MODULE_OWNER(dev);
3413 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3414 dev->open = skge_up;
3415 dev->stop = skge_down;
2cd8e5d3 3416 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3417 dev->hard_start_xmit = skge_xmit_frame;
3418 dev->get_stats = skge_get_stats;
3419 if (hw->chip_id == CHIP_ID_GENESIS)
3420 dev->set_multicast_list = genesis_set_multicast;
3421 else
3422 dev->set_multicast_list = yukon_set_multicast;
3423
3424 dev->set_mac_address = skge_set_mac_address;
3425 dev->change_mtu = skge_change_mtu;
3426 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3427 dev->tx_timeout = skge_tx_timeout;
3428 dev->watchdog_timeo = TX_WATCHDOG;
3429 dev->poll = skge_poll;
3430 dev->weight = NAPI_WEIGHT;
3431#ifdef CONFIG_NET_POLL_CONTROLLER
3432 dev->poll_controller = skge_netpoll;
3433#endif
3434 dev->irq = hw->pdev->irq;
513f533e 3435
981d0377
SH		 3436 if (highmem)
3437 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3438
3439 skge = netdev_priv(dev);
3440 skge->netdev = dev;
3441 skge->hw = hw;
3442 skge->msg_enable = netif_msg_init(debug, default_msg);
3443 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3444 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3445
3446 /* Auto speed and flow control */
3447 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3448 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3449 skge->duplex = -1;
3450 skge->speed = -1;
31b619c5 3451 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3452
3453 hw->dev[port] = dev;
3454
3455 skge->port = port;
3456
64f6b64d
SH		 3457 /* Only used for Genesis XMAC */
3458 INIT_WORK(&skge->link_thread, xm_link_timer, dev);
3459
baef58b1
SH		 3460 if (hw->chip_id != CHIP_ID_GENESIS) {
3461 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3462 skge->rx_csum = 1;
3463 }
3464
3465 /* read the mac address */
3466 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3467 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3468
3469 /* device is off until link detection */
3470 netif_carrier_off(dev);
3471 netif_stop_queue(dev);
3472
3473 return dev;
3474}
3475
3476static void __devinit skge_show_addr(struct net_device *dev)
3477{
3478 const struct skge_port *skge = netdev_priv(dev);
3479
3480 if (netif_msg_probe(skge))
3481 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3482 dev->name,
3483 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3484 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3485}
3486
3487static int __devinit skge_probe(struct pci_dev *pdev,
3488 const struct pci_device_id *ent)
3489{
3490 struct net_device *dev, *dev1;
3491 struct skge_hw *hw;
3492 int err, using_dac = 0;
3493
203babb6
SH		 3494 err = pci_enable_device(pdev);
3495 if (err) {
baef58b1
SH		 3496 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3497 pci_name(pdev));
3498 goto err_out;
3499 }
3500
203babb6
SH		 3501 err = pci_request_regions(pdev, DRV_NAME);
3502 if (err) {
baef58b1
SH		 3503 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3504 pci_name(pdev));
3505 goto err_out_disable_pdev;
3506 }
3507
3508 pci_set_master(pdev);
3509
93aea718 3510 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3511 using_dac = 1;
77783a78 3512 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3513 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3514 using_dac = 0;
3515 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3516 }
3517
3518 if (err) {
3519 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3520 pci_name(pdev));
3521 goto err_out_free_regions;
baef58b1
SH		 3522 }
3523
3524#ifdef __BIG_ENDIAN
8f3f8193 3525 /* byte swap descriptors in hardware */
baef58b1
SH		 3526 {
3527 u32 reg;
3528
3529 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3530 reg |= PCI_REV_DESC;
3531 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3532 }
3533#endif
3534
3535 err = -ENOMEM;
7e863061 3536 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3537 if (!hw) {
3538 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3539 pci_name(pdev));
3540 goto err_out_free_regions;
3541 }
3542
baef58b1 3543 hw->pdev = pdev;
d85b514f
SH		 3544 mutex_init(&hw->phy_mutex);
3545 INIT_WORK(&hw->phy_work, skge_extirq, hw);
d38efdd6 3546 spin_lock_init(&hw->hw_lock);
baef58b1
SH		 3547
3548 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3549 if (!hw->regs) {
3550 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3551 pci_name(pdev));
3552 goto err_out_free_hw;
3553 }
3554
baef58b1
SH		 3555 err = skge_reset(hw);
3556 if (err)
ccdaa2a9 3557 goto err_out_iounmap;
baef58b1 3558
7c7459d1
GKH		 3559 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3560 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3561 skge_board_name(hw), hw->chip_rev);
baef58b1 3562
ccdaa2a9
SH		 3563 dev = skge_devinit(hw, 0, using_dac);
3564 if (!dev)
baef58b1
SH		 3565 goto err_out_led_off;
3566
631ae320
SH		 3567 if (!is_valid_ether_addr(dev->dev_addr)) {
3568 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3569 pci_name(pdev));
3570 err = -EIO;
3571 goto err_out_free_netdev;
3572 }
3573
203babb6
SH		 3574 err = register_netdev(dev);
3575 if (err) {
baef58b1
SH		 3576 printk(KERN_ERR PFX "%s: cannot register net device\n",
3577 pci_name(pdev));
3578 goto err_out_free_netdev;
3579 }
3580
ccdaa2a9
SH		 3581 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3582 if (err) {
3583 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3584 dev->name, pdev->irq);
3585 goto err_out_unregister;
3586 }
baef58b1
SH		 3587 skge_show_addr(dev);
3588
981d0377 3589 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3590 if (register_netdev(dev1) == 0)
3591 skge_show_addr(dev1);
3592 else {
3593 /* Failure to register second port need not be fatal */
3594 printk(KERN_WARNING PFX "register of second port failed\n");
3595 hw->dev[1] = NULL;
3596 free_netdev(dev1);
3597 }
3598 }
ccdaa2a9 3599 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3600
3601 return 0;
3602
ccdaa2a9
SH		 3603err_out_unregister:
3604 unregister_netdev(dev);
baef58b1
SH		 3605err_out_free_netdev:
3606 free_netdev(dev);
3607err_out_led_off:
3608 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3609err_out_iounmap:
3610 iounmap(hw->regs);
3611err_out_free_hw:
3612 kfree(hw);
3613err_out_free_regions:
3614 pci_release_regions(pdev);
3615err_out_disable_pdev:
3616 pci_disable_device(pdev);
3617 pci_set_drvdata(pdev, NULL);
3618err_out:
3619 return err;
3620}
3621
3622static void __devexit skge_remove(struct pci_dev *pdev)
3623{
3624 struct skge_hw *hw = pci_get_drvdata(pdev);
3625 struct net_device *dev0, *dev1;
3626
95566065 3627 if (!hw)
baef58b1
SH		 3628 return;
3629
3630 if ((dev1 = hw->dev[1]))
3631 unregister_netdev(dev1);
3632 dev0 = hw->dev[0];
3633 unregister_netdev(dev0);
3634
7c442fa1
SH		 3635 spin_lock_irq(&hw->hw_lock);
3636 hw->intr_mask = 0;
46a60f2d 3637 skge_write32(hw, B0_IMSK, 0);
78bc2186 3638 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3639 spin_unlock_irq(&hw->hw_lock);
3640
46a60f2d 3641 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3642 skge_write8(hw, B0_CTST, CS_RST_SET);
3643
d85b514f 3644 flush_scheduled_work();
baef58b1
SH		 3645
3646 free_irq(pdev->irq, hw);
3647 pci_release_regions(pdev);
3648 pci_disable_device(pdev);
3649 if (dev1)
3650 free_netdev(dev1);
3651 free_netdev(dev0);
46a60f2d 3652
baef58b1
SH		 3653 iounmap(hw->regs);
3654 kfree(hw);
3655 pci_set_drvdata(pdev, NULL);
3656}
3657
3658#ifdef CONFIG_PM
2a569579 3659static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3660{
3661 struct skge_hw *hw = pci_get_drvdata(pdev);
3662 int i, wol = 0;
3663
d38efdd6
SH		 3664 pci_save_state(pdev);
3665 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3666 struct net_device *dev = hw->dev[i];
3667
d38efdd6 3668 if (netif_running(dev)) {
baef58b1 3669 struct skge_port *skge = netdev_priv(dev);
d38efdd6
SH		 3670
3671 netif_carrier_off(dev);
3672 if (skge->wol)
3673 netif_stop_queue(dev);
3674 else
3675 skge_down(dev);
baef58b1
SH		 3676 wol |= skge->wol;
3677 }
d38efdd6 3678 netif_device_detach(dev);
baef58b1
SH		 3679 }
3680
d38efdd6 3681 skge_write32(hw, B0_IMSK, 0);
2a569579 3682 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3683 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3684
3685 return 0;
3686}
3687
3688static int skge_resume(struct pci_dev *pdev)
3689{
3690 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3691 int i, err;
baef58b1
SH		 3692
3693 pci_set_power_state(pdev, PCI_D0);
3694 pci_restore_state(pdev);
3695 pci_enable_wake(pdev, PCI_D0, 0);
3696
d38efdd6
SH		 3697 err = skge_reset(hw);
3698 if (err)
3699 goto out;
baef58b1 3700
d38efdd6 3701 for (i = 0; i < hw->ports; i++) {
baef58b1 3702 struct net_device *dev = hw->dev[i];
d38efdd6
SH		 3703
3704 netif_device_attach(dev);
3705 if (netif_running(dev)) {
3706 err = skge_up(dev);
3707
3708 if (err) {
3709 printk(KERN_ERR PFX "%s: could not up: %d\n",
3710 dev->name, err);
edd702e8 3711 dev_close(dev);
d38efdd6
SH		 3712 goto out;
3713 }
baef58b1
SH		 3714 }
3715 }
d38efdd6
SH		 3716out:
3717 return err;
baef58b1
SH		 3718}
3719#endif
3720
3721static struct pci_driver skge_driver = {
3722 .name = DRV_NAME,
3723 .id_table = skge_id_table,
3724 .probe = skge_probe,
3725 .remove = __devexit_p(skge_remove),
3726#ifdef CONFIG_PM
3727 .suspend = skge_suspend,
3728 .resume = skge_resume,
3729#endif
3730};
3731
3732static int __init skge_init_module(void)
3733{
29917620 3734 return pci_register_driver(&skge_driver);
baef58b1
SH		 3735}
3736
3737static void __exit skge_cleanup_module(void)
3738{
3739 pci_unregister_driver(&skge_driver);
3740}
3741
3742module_init(skge_init_module);
3743module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)