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skge: changing MTU while running causes problems
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
a5f8f3b6 45#define DRV_VERSION "1.11"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
64f6b64d 60#define LINK_HZ (HZ/2)
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 63MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
ee294dcd 93static void skge_phy_reset(struct skge_port *skge);
513f533e 94static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
baef58b1 100static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 101static void genesis_link_up(struct skge_port *skge);
baef58b1 102
7e676d91 103/* Avoid conditionals by using array */
baef58b1
SH		 104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 108static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 110
baef58b1
SH		 111static int skge_get_regs_len(struct net_device *dev)
112{
c3f8be96 113 return 0x4000;
baef58b1
SH		 114}
115
116/*
c3f8be96
SH		 117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
baef58b1
SH		 120 */
121static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123{
124 const struct skge_port *skge = netdev_priv(dev);
baef58b1 125 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 126
127 regs->version = 1;
c3f8be96
SH		 128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 130
c3f8be96
SH		 131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 133}
134
8f3f8193 135/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 136static u32 wol_supported(const struct skge_hw *hw)
baef58b1 137{
d17ecb23 138 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 139 return 0;
d17ecb23
SH		 140
141 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
142 return 0;
143
144 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 145}
146
147static u32 pci_wake_enabled(struct pci_dev *dev)
148{
149 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
150 u16 value;
151
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
154 if (!pm)
155 return 0;
156
157 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
158
159 value &= PCI_PM_CAP_PME_MASK;
160 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
161
162 return value != 0;
163}
164
165static void skge_wol_init(struct skge_port *skge)
166{
167 struct skge_hw *hw = skge->hw;
168 int port = skge->port;
692412b3 169 u16 ctrl;
a504e64a 170
a504e64a
SH		 171 skge_write16(hw, B0_CTST, CS_RST_CLR);
172 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
173
692412b3
SH		 174 /* Turn on Vaux */
175 skge_write8(hw, B0_POWER_CTRL,
176 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 177
692412b3
SH		 178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
180 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
181 u32 reg = skge_read32(hw, B2_GP_IO);
182 reg |= GP_DIR_9;
183 reg &= ~GP_IO_9;
184 skge_write32(hw, B2_GP_IO, reg);
185 }
a504e64a 186
692412b3
SH		 187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 191
692412b3
SH		 192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_CLR);
196
197 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
198
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
201 PHY_AN_100FULL | PHY_AN_100HALF |
202 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
203 /* no 1000 HD/FD */
204 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
205 gm_phy_write(hw, port, PHY_MARV_CTRL,
206 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
207 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 208
a504e64a
SH		 209
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw, port, GM_GP_CTRL,
212 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
213 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
214
215 /* Set WOL address */
216 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
217 skge->netdev->dev_addr, ETH_ALEN);
218
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
221 ctrl = 0;
222 if (skge->wol & WAKE_PHY)
223 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
226
227 if (skge->wol & WAKE_MAGIC)
228 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
231
232 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
233 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
234
235 /* block receiver */
236 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 237}
238
239static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240{
241 struct skge_port *skge = netdev_priv(dev);
242
a504e64a
SH		 243 wol->supported = wol_supported(skge->hw);
244 wol->wolopts = skge->wol;
baef58b1
SH		 245}
246
247static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
248{
249 struct skge_port *skge = netdev_priv(dev);
250 struct skge_hw *hw = skge->hw;
251
692412b3 252 if (wol->wolopts & ~wol_supported(hw))
baef58b1
SH		 253 return -EOPNOTSUPP;
254
a504e64a 255 skge->wol = wol->wolopts;
baef58b1
SH		 256 return 0;
257}
258
8f3f8193
SH		 259/* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 261 */
262static u32 skge_supported_modes(const struct skge_hw *hw)
263{
264 u32 supported;
265
5e1705dd 266 if (hw->copper) {
31b619c5
SH		 267 supported = SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg| SUPPORTED_TP;
274
275 if (hw->chip_id == CHIP_ID_GENESIS)
276 supported &= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
4b67be99
SH		 284 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 286
287 return supported;
288}
baef58b1
SH		 289
290static int skge_get_settings(struct net_device *dev,
291 struct ethtool_cmd *ecmd)
292{
293 struct skge_port *skge = netdev_priv(dev);
294 struct skge_hw *hw = skge->hw;
295
296 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 297 ecmd->supported = skge_supported_modes(hw);
baef58b1 298
5e1705dd 299 if (hw->copper) {
baef58b1
SH		 300 ecmd->port = PORT_TP;
301 ecmd->phy_address = hw->phy_addr;
31b619c5 302 } else
baef58b1 303 ecmd->port = PORT_FIBRE;
baef58b1
SH		 304
305 ecmd->advertising = skge->advertising;
306 ecmd->autoneg = skge->autoneg;
307 ecmd->speed = skge->speed;
308 ecmd->duplex = skge->duplex;
309 return 0;
310}
311
baef58b1
SH		 312static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
313{
314 struct skge_port *skge = netdev_priv(dev);
315 const struct skge_hw *hw = skge->hw;
31b619c5 316 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
baef58b1 322 } else {
31b619c5
SH		 323 u32 setting;
324
2c668514 325 switch (ecmd->speed) {
baef58b1 326 case SPEED_1000:
31b619c5
SH		 327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
baef58b1
SH		 333 break;
334 case SPEED_100:
31b619c5
SH		 335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
baef58b1 343 case SPEED_10:
31b619c5
SH		 344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
baef58b1
SH		 349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
31b619c5
SH		 354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
baef58b1
SH		 360 }
361
362 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 363 skge->advertising = ecmd->advertising;
364
ee294dcd
SH		 365 if (netif_running(dev))
366 skge_phy_reset(skge);
367
baef58b1
SH		 368 return (0);
369}
370
371static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373{
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380}
381
382static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386} skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411};
412
b9f2c044 413static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 414{
b9f2c044
JG		 415 switch (sset) {
416 case ETH_SS_STATS:
417 return ARRAY_SIZE(skge_stats);
418 default:
419 return -EOPNOTSUPP;
420 }
baef58b1
SH		 421}
422
423static void skge_get_ethtool_stats(struct net_device *dev,
424 struct ethtool_stats *stats, u64 *data)
425{
426 struct skge_port *skge = netdev_priv(dev);
427
428 if (skge->hw->chip_id == CHIP_ID_GENESIS)
429 genesis_get_stats(skge, data);
430 else
431 yukon_get_stats(skge, data);
432}
433
434/* Use hardware MIB variables for critical path statistics and
435 * transmit feedback not reported at interrupt.
436 * Other errors are accounted for in interrupt handler.
437 */
438static struct net_device_stats *skge_get_stats(struct net_device *dev)
439{
440 struct skge_port *skge = netdev_priv(dev);
441 u64 data[ARRAY_SIZE(skge_stats)];
442
443 if (skge->hw->chip_id == CHIP_ID_GENESIS)
444 genesis_get_stats(skge, data);
445 else
446 yukon_get_stats(skge, data);
447
448 skge->net_stats.tx_bytes = data[0];
449 skge->net_stats.rx_bytes = data[1];
450 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
451 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 452 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 453 skge->net_stats.collisions = data[10];
454 skge->net_stats.tx_aborted_errors = data[12];
455
456 return &skge->net_stats;
457}
458
459static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
460{
461 int i;
462
95566065 463 switch (stringset) {
baef58b1
SH		 464 case ETH_SS_STATS:
465 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
466 memcpy(data + i * ETH_GSTRING_LEN,
467 skge_stats[i].name, ETH_GSTRING_LEN);
468 break;
469 }
470}
471
472static void skge_get_ring_param(struct net_device *dev,
473 struct ethtool_ringparam *p)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 p->rx_max_pending = MAX_RX_RING_SIZE;
478 p->tx_max_pending = MAX_TX_RING_SIZE;
479 p->rx_mini_max_pending = 0;
480 p->rx_jumbo_max_pending = 0;
481
482 p->rx_pending = skge->rx_ring.count;
483 p->tx_pending = skge->tx_ring.count;
484 p->rx_mini_pending = 0;
485 p->rx_jumbo_pending = 0;
486}
487
488static int skge_set_ring_param(struct net_device *dev,
489 struct ethtool_ringparam *p)
490{
491 struct skge_port *skge = netdev_priv(dev);
3b8bb472 492 int err;
baef58b1
SH		 493
494 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 495 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 496 return -EINVAL;
497
498 skge->rx_ring.count = p->rx_pending;
499 skge->tx_ring.count = p->tx_pending;
500
501 if (netif_running(dev)) {
502 skge_down(dev);
3b8bb472
SH		 503 err = skge_up(dev);
504 if (err)
505 dev_close(dev);
baef58b1
SH		 506 }
507
508 return 0;
509}
510
511static u32 skge_get_msglevel(struct net_device *netdev)
512{
513 struct skge_port *skge = netdev_priv(netdev);
514 return skge->msg_enable;
515}
516
517static void skge_set_msglevel(struct net_device *netdev, u32 value)
518{
519 struct skge_port *skge = netdev_priv(netdev);
520 skge->msg_enable = value;
521}
522
523static int skge_nway_reset(struct net_device *dev)
524{
525 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 526
527 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
528 return -EINVAL;
529
ee294dcd 530 skge_phy_reset(skge);
baef58b1
SH		 531 return 0;
532}
533
534static int skge_set_sg(struct net_device *dev, u32 data)
535{
536 struct skge_port *skge = netdev_priv(dev);
537 struct skge_hw *hw = skge->hw;
538
539 if (hw->chip_id == CHIP_ID_GENESIS && data)
540 return -EOPNOTSUPP;
541 return ethtool_op_set_sg(dev, data);
542}
543
544static int skge_set_tx_csum(struct net_device *dev, u32 data)
545{
546 struct skge_port *skge = netdev_priv(dev);
547 struct skge_hw *hw = skge->hw;
548
549 if (hw->chip_id == CHIP_ID_GENESIS && data)
550 return -EOPNOTSUPP;
551
552 return ethtool_op_set_tx_csum(dev, data);
553}
554
555static u32 skge_get_rx_csum(struct net_device *dev)
556{
557 struct skge_port *skge = netdev_priv(dev);
558
559 return skge->rx_csum;
560}
561
562/* Only Yukon supports checksum offload. */
563static int skge_set_rx_csum(struct net_device *dev, u32 data)
564{
565 struct skge_port *skge = netdev_priv(dev);
566
567 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
568 return -EOPNOTSUPP;
569
570 skge->rx_csum = data;
571 return 0;
572}
573
baef58b1
SH		 574static void skge_get_pauseparam(struct net_device *dev,
575 struct ethtool_pauseparam *ecmd)
576{
577 struct skge_port *skge = netdev_priv(dev);
578
5d5c8e03
SH		 579 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
580 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
581 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 582
5d5c8e03 583 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 584}
585
586static int skge_set_pauseparam(struct net_device *dev,
587 struct ethtool_pauseparam *ecmd)
588{
589 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 590 struct ethtool_pauseparam old;
baef58b1 591
5d5c8e03
SH		 592 skge_get_pauseparam(dev, &old);
593
594 if (ecmd->autoneg != old.autoneg)
595 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
596 else {
597 if (ecmd->rx_pause && ecmd->tx_pause)
598 skge->flow_control = FLOW_MODE_SYMMETRIC;
599 else if (ecmd->rx_pause && !ecmd->tx_pause)
600 skge->flow_control = FLOW_MODE_SYM_OR_REM;
601 else if (!ecmd->rx_pause && ecmd->tx_pause)
602 skge->flow_control = FLOW_MODE_LOC_SEND;
603 else
604 skge->flow_control = FLOW_MODE_NONE;
605 }
baef58b1 606
e8df8554
SH		 607 if (netif_running(dev))
608 skge_phy_reset(skge);
5d5c8e03 609
baef58b1
SH		 610 return 0;
611}
612
613/* Chip internal frequency for clock calculations */
614static inline u32 hwkhz(const struct skge_hw *hw)
615{
187ff3b8 616 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 617}
618
8f3f8193 619/* Chip HZ to microseconds */
baef58b1
SH		 620static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
621{
622 return (ticks * 1000) / hwkhz(hw);
623}
624
8f3f8193 625/* Microseconds to chip HZ */
baef58b1
SH		 626static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
627{
628 return hwkhz(hw) * usec / 1000;
629}
630
631static int skge_get_coalesce(struct net_device *dev,
632 struct ethtool_coalesce *ecmd)
633{
634 struct skge_port *skge = netdev_priv(dev);
635 struct skge_hw *hw = skge->hw;
636 int port = skge->port;
637
638 ecmd->rx_coalesce_usecs = 0;
639 ecmd->tx_coalesce_usecs = 0;
640
641 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
642 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
643 u32 msk = skge_read32(hw, B2_IRQM_MSK);
644
645 if (msk & rxirqmask[port])
646 ecmd->rx_coalesce_usecs = delay;
647 if (msk & txirqmask[port])
648 ecmd->tx_coalesce_usecs = delay;
649 }
650
651 return 0;
652}
653
654/* Note: interrupt timer is per board, but can turn on/off per port */
655static int skge_set_coalesce(struct net_device *dev,
656 struct ethtool_coalesce *ecmd)
657{
658 struct skge_port *skge = netdev_priv(dev);
659 struct skge_hw *hw = skge->hw;
660 int port = skge->port;
661 u32 msk = skge_read32(hw, B2_IRQM_MSK);
662 u32 delay = 25;
663
664 if (ecmd->rx_coalesce_usecs == 0)
665 msk &= ~rxirqmask[port];
666 else if (ecmd->rx_coalesce_usecs < 25 ||
667 ecmd->rx_coalesce_usecs > 33333)
668 return -EINVAL;
669 else {
670 msk |= rxirqmask[port];
671 delay = ecmd->rx_coalesce_usecs;
672 }
673
674 if (ecmd->tx_coalesce_usecs == 0)
675 msk &= ~txirqmask[port];
676 else if (ecmd->tx_coalesce_usecs < 25 ||
677 ecmd->tx_coalesce_usecs > 33333)
678 return -EINVAL;
679 else {
680 msk |= txirqmask[port];
681 delay = min(delay, ecmd->rx_coalesce_usecs);
682 }
683
684 skge_write32(hw, B2_IRQM_MSK, msk);
685 if (msk == 0)
686 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
687 else {
688 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
689 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
690 }
691 return 0;
692}
693
6abebb53
SH		 694enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
695static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 696{
6abebb53
SH		 697 struct skge_hw *hw = skge->hw;
698 int port = skge->port;
699
9cbe330f 700 spin_lock_bh(&hw->phy_lock);
baef58b1 701 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 702 switch (mode) {
703 case LED_MODE_OFF:
64f6b64d
SH		 704 if (hw->phy_type == SK_PHY_BCOM)
705 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
706 else {
707 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
709 }
6abebb53
SH		 710 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
713 break;
baef58b1 714
6abebb53
SH		 715 case LED_MODE_ON:
716 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
717 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 718
6abebb53
SH		 719 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 721
6abebb53 722 break;
baef58b1 723
6abebb53
SH		 724 case LED_MODE_TST:
725 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
726 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
727 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 728
64f6b64d
SH		 729 if (hw->phy_type == SK_PHY_BCOM)
730 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
731 else {
732 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
733 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
734 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
735 }
736
6abebb53 737 }
baef58b1 738 } else {
6abebb53
SH		 739 switch (mode) {
740 case LED_MODE_OFF:
741 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
742 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
743 PHY_M_LED_MO_DUP(MO_LED_OFF) |
744 PHY_M_LED_MO_10(MO_LED_OFF) |
745 PHY_M_LED_MO_100(MO_LED_OFF) |
746 PHY_M_LED_MO_1000(MO_LED_OFF) |
747 PHY_M_LED_MO_RX(MO_LED_OFF));
748 break;
749 case LED_MODE_ON:
750 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
751 PHY_M_LED_PULS_DUR(PULS_170MS) |
752 PHY_M_LED_BLINK_RT(BLINK_84MS) |
753 PHY_M_LEDC_TX_CTRL |
754 PHY_M_LEDC_DP_CTRL);
46a60f2d 755
6abebb53
SH		 756 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
757 PHY_M_LED_MO_RX(MO_LED_OFF) |
758 (skge->speed == SPEED_100 ?
759 PHY_M_LED_MO_100(MO_LED_ON) : 0));
760 break;
761 case LED_MODE_TST:
762 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
763 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
764 PHY_M_LED_MO_DUP(MO_LED_ON) |
765 PHY_M_LED_MO_10(MO_LED_ON) |
766 PHY_M_LED_MO_100(MO_LED_ON) |
767 PHY_M_LED_MO_1000(MO_LED_ON) |
768 PHY_M_LED_MO_RX(MO_LED_ON));
769 }
baef58b1 770 }
9cbe330f 771 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 772}
773
774/* blink LED's for finding board */
775static int skge_phys_id(struct net_device *dev, u32 data)
776{
777 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 778 unsigned long ms;
779 enum led_mode mode = LED_MODE_TST;
baef58b1 780
95566065 781 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 782 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
783 else
784 ms = data * 1000;
baef58b1 785
6abebb53
SH		 786 while (ms > 0) {
787 skge_led(skge, mode);
788 mode ^= LED_MODE_TST;
baef58b1 789
6abebb53
SH		 790 if (msleep_interruptible(BLINK_MS))
791 break;
792 ms -= BLINK_MS;
793 }
baef58b1 794
6abebb53
SH		 795 /* back to regular LED state */
796 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 797
798 return 0;
799}
800
7282d491 801static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 802 .get_settings = skge_get_settings,
803 .set_settings = skge_set_settings,
804 .get_drvinfo = skge_get_drvinfo,
805 .get_regs_len = skge_get_regs_len,
806 .get_regs = skge_get_regs,
807 .get_wol = skge_get_wol,
808 .set_wol = skge_set_wol,
809 .get_msglevel = skge_get_msglevel,
810 .set_msglevel = skge_set_msglevel,
811 .nway_reset = skge_nway_reset,
812 .get_link = ethtool_op_get_link,
813 .get_ringparam = skge_get_ring_param,
814 .set_ringparam = skge_set_ring_param,
815 .get_pauseparam = skge_get_pauseparam,
816 .set_pauseparam = skge_set_pauseparam,
817 .get_coalesce = skge_get_coalesce,
818 .set_coalesce = skge_set_coalesce,
baef58b1 819 .set_sg = skge_set_sg,
baef58b1
SH		 820 .set_tx_csum = skge_set_tx_csum,
821 .get_rx_csum = skge_get_rx_csum,
822 .set_rx_csum = skge_set_rx_csum,
823 .get_strings = skge_get_strings,
824 .phys_id = skge_phys_id,
b9f2c044 825 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 826 .get_ethtool_stats = skge_get_ethtool_stats,
827};
828
829/*
830 * Allocate ring elements and chain them together
831 * One-to-one association of board descriptors with ring elements
832 */
c3da1447 833static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 834{
835 struct skge_tx_desc *d;
836 struct skge_element *e;
837 int i;
838
cd861280 839 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 840 if (!ring->start)
841 return -ENOMEM;
842
843 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
844 e->desc = d;
845 if (i == ring->count - 1) {
846 e->next = ring->start;
847 d->next_offset = base;
848 } else {
849 e->next = e + 1;
850 d->next_offset = base + (i+1) * sizeof(*d);
851 }
852 }
853 ring->to_use = ring->to_clean = ring->start;
854
855 return 0;
856}
857
19a33d4e
SH		 858/* Allocate and setup a new buffer for receiving */
859static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
860 struct sk_buff *skb, unsigned int bufsize)
861{
862 struct skge_rx_desc *rd = e->desc;
863 u64 map;
baef58b1
SH		 864
865 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
866 PCI_DMA_FROMDEVICE);
867
868 rd->dma_lo = map;
869 rd->dma_hi = map >> 32;
870 e->skb = skb;
871 rd->csum1_start = ETH_HLEN;
872 rd->csum2_start = ETH_HLEN;
873 rd->csum1 = 0;
874 rd->csum2 = 0;
875
876 wmb();
877
878 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
879 pci_unmap_addr_set(e, mapaddr, map);
880 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 881}
882
19a33d4e
SH		 883/* Resume receiving using existing skb,
884 * Note: DMA address is not changed by chip.
885 * MTU not changed while receiver active.
886 */
5a011447 887static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 888{
889 struct skge_rx_desc *rd = e->desc;
890
891 rd->csum2 = 0;
892 rd->csum2_start = ETH_HLEN;
893
894 wmb();
895
896 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
897}
898
899
900/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 901static void skge_rx_clean(struct skge_port *skge)
902{
903 struct skge_hw *hw = skge->hw;
904 struct skge_ring *ring = &skge->rx_ring;
905 struct skge_element *e;
906
19a33d4e
SH		 907 e = ring->start;
908 do {
baef58b1
SH		 909 struct skge_rx_desc *rd = e->desc;
910 rd->control = 0;
19a33d4e
SH		 911 if (e->skb) {
912 pci_unmap_single(hw->pdev,
913 pci_unmap_addr(e, mapaddr),
914 pci_unmap_len(e, maplen),
915 PCI_DMA_FROMDEVICE);
916 dev_kfree_skb(e->skb);
917 e->skb = NULL;
918 }
919 } while ((e = e->next) != ring->start);
baef58b1
SH		 920}
921
19a33d4e 922
baef58b1 923/* Allocate buffers for receive ring
19a33d4e 924 * For receive: to_clean is next received frame.
baef58b1 925 */
c54f9765 926static int skge_rx_fill(struct net_device *dev)
baef58b1 927{
c54f9765 928 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 929 struct skge_ring *ring = &skge->rx_ring;
930 struct skge_element *e;
baef58b1 931
19a33d4e
SH		 932 e = ring->start;
933 do {
383181ac 934 struct sk_buff *skb;
baef58b1 935
c54f9765
SH		 936 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
937 GFP_KERNEL);
19a33d4e
SH		 938 if (!skb)
939 return -ENOMEM;
940
383181ac
SH		 941 skb_reserve(skb, NET_IP_ALIGN);
942 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 943 } while ( (e = e->next) != ring->start);
baef58b1 944
19a33d4e
SH		 945 ring->to_clean = ring->start;
946 return 0;
baef58b1
SH		 947}
948
5d5c8e03
SH		 949static const char *skge_pause(enum pause_status status)
950{
951 switch(status) {
952 case FLOW_STAT_NONE:
953 return "none";
954 case FLOW_STAT_REM_SEND:
955 return "rx only";
956 case FLOW_STAT_LOC_SEND:
957 return "tx_only";
958 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
959 return "both";
960 default:
961 return "indeterminated";
962 }
963}
964
965
baef58b1
SH		 966static void skge_link_up(struct skge_port *skge)
967{
46a60f2d 968 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 969 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
970
baef58b1 971 netif_carrier_on(skge->netdev);
29b4e886 972 netif_wake_queue(skge->netdev);
baef58b1 973
5d5c8e03 974 if (netif_msg_link(skge)) {
baef58b1
SH		 975 printk(KERN_INFO PFX
976 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
977 skge->netdev->name, skge->speed,
978 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 979 skge_pause(skge->flow_status));
980 }
baef58b1
SH		 981}
982
983static void skge_link_down(struct skge_port *skge)
984{
54cfb5aa 985 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 986 netif_carrier_off(skge->netdev);
987 netif_stop_queue(skge->netdev);
988
989 if (netif_msg_link(skge))
990 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
991}
992
a1bc9b87
SH		 993
994static void xm_link_down(struct skge_hw *hw, int port)
995{
996 struct net_device *dev = hw->dev[port];
997 struct skge_port *skge = netdev_priv(dev);
998 u16 cmd, msk;
999
1000 if (hw->phy_type == SK_PHY_XMAC) {
1001 msk = xm_read16(hw, port, XM_IMSK);
1002 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
1003 xm_write16(hw, port, XM_IMSK, msk);
1004 }
1005
1006 cmd = xm_read16(hw, port, XM_MMU_CMD);
1007 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1008 xm_write16(hw, port, XM_MMU_CMD, cmd);
1009 /* dummy read to ensure writing */
1010 (void) xm_read16(hw, port, XM_MMU_CMD);
1011
1012 if (netif_carrier_ok(dev))
1013 skge_link_down(skge);
1014}
1015
2cd8e5d3 1016static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1017{
1018 int i;
baef58b1 1019
6b0c1480 1020 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1021 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1022
64f6b64d
SH		 1023 if (hw->phy_type == SK_PHY_XMAC)
1024 goto ready;
1025
89bf5f23 1026 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1027 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1028 goto ready;
0781191c 1029 udelay(1);
baef58b1
SH		 1030 }
1031
2cd8e5d3 1032 return -ETIMEDOUT;
89bf5f23 1033 ready:
2cd8e5d3 1034 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1035
2cd8e5d3
SH		 1036 return 0;
1037}
1038
1039static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1040{
1041 u16 v = 0;
1042 if (__xm_phy_read(hw, port, reg, &v))
1043 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1044 hw->dev[port]->name);
baef58b1
SH		 1045 return v;
1046}
1047
2cd8e5d3 1048static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1049{
1050 int i;
1051
6b0c1480 1052 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1053 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1054 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1055 goto ready;
89bf5f23 1056 udelay(1);
baef58b1 1057 }
2cd8e5d3 1058 return -EIO;
baef58b1
SH		 1059
1060 ready:
6b0c1480 1061 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1062 for (i = 0; i < PHY_RETRIES; i++) {
1063 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1064 return 0;
1065 udelay(1);
1066 }
1067 return -ETIMEDOUT;
baef58b1
SH		 1068}
1069
1070static void genesis_init(struct skge_hw *hw)
1071{
1072 /* set blink source counter */
1073 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1074 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1075
1076 /* configure mac arbiter */
1077 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1078
1079 /* configure mac arbiter timeout values */
1080 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1081 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1082 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1083 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1084
1085 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1086 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1087 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1088 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1089
1090 /* configure packet arbiter timeout */
1091 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1092 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1093 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1094 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1095 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1096}
1097
1098static void genesis_reset(struct skge_hw *hw, int port)
1099{
45bada65 1100 const u8 zero[8] = { 0 };
baef58b1 1101
46a60f2d
SH		 1102 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1103
baef58b1 1104 /* reset the statistics module */
6b0c1480
SH		 1105 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1106 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1107 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1108 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1109 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1110
89bf5f23 1111 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1112 if (hw->phy_type == SK_PHY_BCOM)
1113 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1114
45bada65 1115 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1116}
1117
1118
45bada65
SH		 1119/* Convert mode to MII values */
1120static const u16 phy_pause_map[] = {
1121 [FLOW_MODE_NONE] = 0,
1122 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1123 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1124 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1125};
1126
4b67be99
SH		 1127/* special defines for FIBER (88E1011S only) */
1128static const u16 fiber_pause_map[] = {
1129 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1130 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1131 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1132 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1133};
1134
45bada65
SH		 1135
1136/* Check status of Broadcom phy link */
1137static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1138{
45bada65
SH		 1139 struct net_device *dev = hw->dev[port];
1140 struct skge_port *skge = netdev_priv(dev);
1141 u16 status;
1142
1143 /* read twice because of latch */
1144 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1145 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1146
45bada65 1147 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1148 xm_link_down(hw, port);
64f6b64d
SH		 1149 return;
1150 }
45bada65 1151
64f6b64d
SH		 1152 if (skge->autoneg == AUTONEG_ENABLE) {
1153 u16 lpa, aux;
45bada65 1154
64f6b64d
SH		 1155 if (!(status & PHY_ST_AN_OVER))
1156 return;
45bada65 1157
64f6b64d
SH		 1158 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1159 if (lpa & PHY_B_AN_RF) {
1160 printk(KERN_NOTICE PFX "%s: remote fault\n",
1161 dev->name);
1162 return;
1163 }
45bada65 1164
64f6b64d
SH		 1165 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1166
1167 /* Check Duplex mismatch */
1168 switch (aux & PHY_B_AS_AN_RES_MSK) {
1169 case PHY_B_RES_1000FD:
1170 skge->duplex = DUPLEX_FULL;
1171 break;
1172 case PHY_B_RES_1000HD:
1173 skge->duplex = DUPLEX_HALF;
1174 break;
1175 default:
1176 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1177 dev->name);
1178 return;
45bada65
SH		 1179 }
1180
64f6b64d
SH		 1181 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1182 switch (aux & PHY_B_AS_PAUSE_MSK) {
1183 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1184 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1185 break;
1186 case PHY_B_AS_PRR:
5d5c8e03 1187 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1188 break;
1189 case PHY_B_AS_PRT:
5d5c8e03 1190 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1191 break;
1192 default:
5d5c8e03 1193 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1194 }
1195 skge->speed = SPEED_1000;
45bada65 1196 }
64f6b64d
SH		 1197
1198 if (!netif_carrier_ok(dev))
1199 genesis_link_up(skge);
45bada65
SH		 1200}
1201
1202/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1203 * Phy on for 100 or 10Mbit operation
1204 */
64f6b64d 1205static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1206{
1207 struct skge_hw *hw = skge->hw;
1208 int port = skge->port;
baef58b1 1209 int i;
45bada65 1210 u16 id1, r, ext, ctl;
baef58b1
SH		 1211
1212 /* magic workaround patterns for Broadcom */
1213 static const struct {
1214 u16 reg;
1215 u16 val;
1216 } A1hack[] = {
1217 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1218 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1219 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1220 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1221 }, C0hack[] = {
1222 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1223 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1224 };
1225
45bada65
SH		 1226 /* read Id from external PHY (all have the same address) */
1227 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1228
1229 /* Optimize MDIO transfer by suppressing preamble. */
1230 r = xm_read16(hw, port, XM_MMU_CMD);
1231 r |= XM_MMU_NO_PRE;
1232 xm_write16(hw, port, XM_MMU_CMD,r);
1233
2c668514 1234 switch (id1) {
45bada65
SH		 1235 case PHY_BCOM_ID1_C0:
1236 /*
1237 * Workaround BCOM Errata for the C0 type.
1238 * Write magic patterns to reserved registers.
1239 */
1240 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1241 xm_phy_write(hw, port,
1242 C0hack[i].reg, C0hack[i].val);
1243
1244 break;
1245 case PHY_BCOM_ID1_A1:
1246 /*
1247 * Workaround BCOM Errata for the A1 type.
1248 * Write magic patterns to reserved registers.
1249 */
1250 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1251 xm_phy_write(hw, port,
1252 A1hack[i].reg, A1hack[i].val);
1253 break;
1254 }
1255
1256 /*
1257 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1258 * Disable Power Management after reset.
1259 */
1260 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1261 r |= PHY_B_AC_DIS_PM;
1262 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1263
1264 /* Dummy read */
1265 xm_read16(hw, port, XM_ISRC);
1266
1267 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1268 ctl = PHY_CT_SP1000; /* always 1000mbit */
1269
1270 if (skge->autoneg == AUTONEG_ENABLE) {
1271 /*
1272 * Workaround BCOM Errata #1 for the C5 type.
1273 * 1000Base-T Link Acquisition Failure in Slave Mode
1274 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1275 */
1276 u16 adv = PHY_B_1000C_RD;
1277 if (skge->advertising & ADVERTISED_1000baseT_Half)
1278 adv |= PHY_B_1000C_AHD;
1279 if (skge->advertising & ADVERTISED_1000baseT_Full)
1280 adv |= PHY_B_1000C_AFD;
1281 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1282
1283 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1284 } else {
1285 if (skge->duplex == DUPLEX_FULL)
1286 ctl |= PHY_CT_DUP_MD;
1287 /* Force to slave */
1288 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1289 }
1290
1291 /* Set autonegotiation pause parameters */
1292 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1293 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1294
1295 /* Handle Jumbo frames */
64f6b64d 1296 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1297 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1298 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1299
1300 ext |= PHY_B_PEC_HIGH_LA;
1301
1302 }
1303
1304 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1305 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1306
8f3f8193 1307 /* Use link status change interrupt */
45bada65 1308 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1309}
45bada65 1310
64f6b64d
SH		 1311static void xm_phy_init(struct skge_port *skge)
1312{
1313 struct skge_hw *hw = skge->hw;
1314 int port = skge->port;
1315 u16 ctrl = 0;
1316
1317 if (skge->autoneg == AUTONEG_ENABLE) {
1318 if (skge->advertising & ADVERTISED_1000baseT_Half)
1319 ctrl |= PHY_X_AN_HD;
1320 if (skge->advertising & ADVERTISED_1000baseT_Full)
1321 ctrl |= PHY_X_AN_FD;
1322
4b67be99 1323 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1324
1325 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1326
1327 /* Restart Auto-negotiation */
1328 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1329 } else {
1330 /* Set DuplexMode in Config register */
1331 if (skge->duplex == DUPLEX_FULL)
1332 ctrl |= PHY_CT_DUP_MD;
1333 /*
1334 * Do NOT enable Auto-negotiation here. This would hold
1335 * the link down because no IDLEs are transmitted
1336 */
1337 }
1338
1339 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1340
1341 /* Poll PHY for status changes */
9cbe330f 1342 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1343}
1344
1345static void xm_check_link(struct net_device *dev)
1346{
1347 struct skge_port *skge = netdev_priv(dev);
1348 struct skge_hw *hw = skge->hw;
1349 int port = skge->port;
1350 u16 status;
1351
1352 /* read twice because of latch */
1353 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1354 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1355
1356 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1357 xm_link_down(hw, port);
64f6b64d
SH		 1358 return;
1359 }
1360
1361 if (skge->autoneg == AUTONEG_ENABLE) {
1362 u16 lpa, res;
1363
1364 if (!(status & PHY_ST_AN_OVER))
1365 return;
1366
1367 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1368 if (lpa & PHY_B_AN_RF) {
1369 printk(KERN_NOTICE PFX "%s: remote fault\n",
1370 dev->name);
1371 return;
1372 }
1373
1374 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1375
1376 /* Check Duplex mismatch */
1377 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1378 case PHY_X_RS_FD:
1379 skge->duplex = DUPLEX_FULL;
1380 break;
1381 case PHY_X_RS_HD:
1382 skge->duplex = DUPLEX_HALF;
1383 break;
1384 default:
1385 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1386 dev->name);
1387 return;
1388 }
1389
1390 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1391 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1392 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1393 (lpa & PHY_X_P_SYM_MD))
1394 skge->flow_status = FLOW_STAT_SYMMETRIC;
1395 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1396 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1397 /* Enable PAUSE receive, disable PAUSE transmit */
1398 skge->flow_status = FLOW_STAT_REM_SEND;
1399 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1400 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1401 /* Disable PAUSE receive, enable PAUSE transmit */
1402 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1403 else
5d5c8e03 1404 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1405
1406 skge->speed = SPEED_1000;
1407 }
1408
1409 if (!netif_carrier_ok(dev))
1410 genesis_link_up(skge);
1411}
1412
1413/* Poll to check for link coming up.
1414 * Since internal PHY is wired to a level triggered pin, can't
1415 * get an interrupt when carrier is detected.
1416 */
9cbe330f 1417static void xm_link_timer(unsigned long arg)
64f6b64d 1418{
9cbe330f 1419 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1420 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1421 struct skge_hw *hw = skge->hw;
1422 int port = skge->port;
1423
1424 if (!netif_running(dev))
1425 return;
1426
1427 if (netif_carrier_ok(dev)) {
1428 xm_read16(hw, port, XM_ISRC);
1429 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1430 goto nochange;
1431 } else {
1432 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1433 goto nochange;
1434 xm_read16(hw, port, XM_ISRC);
1435 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1436 goto nochange;
1437 }
1438
9cbe330f 1439 spin_lock(&hw->phy_lock);
64f6b64d 1440 xm_check_link(dev);
9cbe330f 1441 spin_unlock(&hw->phy_lock);
64f6b64d
SH		 1442
1443nochange:
208491d8 1444 if (netif_running(dev))
9cbe330f 1445 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
45bada65
SH		 1446}
1447
1448static void genesis_mac_init(struct skge_hw *hw, int port)
1449{
1450 struct net_device *dev = hw->dev[port];
1451 struct skge_port *skge = netdev_priv(dev);
1452 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1453 int i;
1454 u32 r;
1455 const u8 zero[6] = { 0 };
1456
0781191c
SH		 1457 for (i = 0; i < 10; i++) {
1458 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1459 MFF_SET_MAC_RST);
1460 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1461 goto reset_ok;
1462 udelay(1);
1463 }
baef58b1 1464
0781191c
SH		 1465 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1466
1467 reset_ok:
baef58b1 1468 /* Unreset the XMAC. */
6b0c1480 1469 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1470
1471 /*
1472 * Perform additional initialization for external PHYs,
1473 * namely for the 1000baseTX cards that use the XMAC's
1474 * GMII mode.
1475 */
64f6b64d
SH		 1476 if (hw->phy_type != SK_PHY_XMAC) {
1477 /* Take external Phy out of reset */
1478 r = skge_read32(hw, B2_GP_IO);
1479 if (port == 0)
1480 r |= GP_DIR_0|GP_IO_0;
1481 else
1482 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1483
64f6b64d 1484 skge_write32(hw, B2_GP_IO, r);
0781191c 1485
64f6b64d
SH		 1486 /* Enable GMII interface */
1487 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1488 }
89bf5f23 1489
89bf5f23 1490
64f6b64d
SH		 1491 switch(hw->phy_type) {
1492 case SK_PHY_XMAC:
1493 xm_phy_init(skge);
1494 break;
1495 case SK_PHY_BCOM:
1496 bcom_phy_init(skge);
1497 bcom_check_link(hw, port);
1498 }
89bf5f23 1499
45bada65
SH		 1500 /* Set Station Address */
1501 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1502
45bada65
SH		 1503 /* We don't use match addresses so clear */
1504 for (i = 1; i < 16; i++)
1505 xm_outaddr(hw, port, XM_EXM(i), zero);
1506
0781191c
SH		 1507 /* Clear MIB counters */
1508 xm_write16(hw, port, XM_STAT_CMD,
1509 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1510 /* Clear two times according to Errata #3 */
1511 xm_write16(hw, port, XM_STAT_CMD,
1512 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1513
45bada65
SH		 1514 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1515 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1516
1517 /* We don't need the FCS appended to the packet. */
1518 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1519 if (jumbo)
1520 r |= XM_RX_BIG_PK_OK;
89bf5f23 1521
45bada65 1522 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1523 /*
45bada65
SH		 1524 * If in manual half duplex mode the other side might be in
1525 * full duplex mode, so ignore if a carrier extension is not seen
1526 * on frames received
89bf5f23 1527 */
45bada65 1528 r |= XM_RX_DIS_CEXT;
baef58b1 1529 }
45bada65 1530 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1531
baef58b1
SH		 1532
1533 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1534 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1535
1536 /*
1537 * Bump up the transmit threshold. This helps hold off transmit
1538 * underruns when we're blasting traffic from both ports at once.
1539 */
1540 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1541
1542 /*
1543 * Enable the reception of all error frames. This is is
1544 * a necessary evil due to the design of the XMAC. The
1545 * XMAC's receive FIFO is only 8K in size, however jumbo
1546 * frames can be up to 9000 bytes in length. When bad
1547 * frame filtering is enabled, the XMAC's RX FIFO operates
1548 * in 'store and forward' mode. For this to work, the
1549 * entire frame has to fit into the FIFO, but that means
1550 * that jumbo frames larger than 8192 bytes will be
1551 * truncated. Disabling all bad frame filtering causes
1552 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1553 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1554 * RX FIFO as soon as the FIFO threshold is reached.
1555 */
45bada65 1556 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1557
baef58b1
SH		 1558
1559 /*
45bada65
SH		 1560 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1561 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1562 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1563 */
45bada65
SH		 1564 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1565
1566 /*
1567 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1568 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1569 * and 'Octets Tx OK Hi Cnt Ov'.
1570 */
1571 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1572
1573 /* Configure MAC arbiter */
1574 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1575
1576 /* configure timeout values */
1577 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1578 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1579 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1580 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1581
1582 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1583 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1584 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1585 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1586
1587 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1588 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1589 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1590 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1591
1592 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1593 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1594 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1595 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1596
45bada65 1597 if (jumbo) {
baef58b1 1598 /* Enable frame flushing if jumbo frames used */
6b0c1480 1599 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1600 } else {
1601 /* enable timeout timers if normal frames */
1602 skge_write16(hw, B3_PA_CTRL,
45bada65 1603 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1604 }
baef58b1
SH		 1605}
1606
1607static void genesis_stop(struct skge_port *skge)
1608{
1609 struct skge_hw *hw = skge->hw;
1610 int port = skge->port;
89bf5f23 1611 u32 reg;
baef58b1 1612
46a60f2d
SH		 1613 genesis_reset(hw, port);
1614
baef58b1
SH		 1615 /* Clear Tx packet arbiter timeout IRQ */
1616 skge_write16(hw, B3_PA_CTRL,
1617 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1618
1619 /*
8f3f8193 1620 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1621 * terminate if we don't flush the XMAC's transmit FIFO !
1622 */
6b0c1480
SH		 1623 xm_write32(hw, port, XM_MODE,
1624 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1625
1626
1627 /* Reset the MAC */
6b0c1480 1628 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1629
1630 /* For external PHYs there must be special handling */
64f6b64d
SH		 1631 if (hw->phy_type != SK_PHY_XMAC) {
1632 reg = skge_read32(hw, B2_GP_IO);
1633 if (port == 0) {
1634 reg |= GP_DIR_0;
1635 reg &= ~GP_IO_0;
1636 } else {
1637 reg |= GP_DIR_2;
1638 reg &= ~GP_IO_2;
1639 }
1640 skge_write32(hw, B2_GP_IO, reg);
1641 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1642 }
1643
6b0c1480
SH		 1644 xm_write16(hw, port, XM_MMU_CMD,
1645 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1646 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1647
6b0c1480 1648 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1649}
1650
1651
1652static void genesis_get_stats(struct skge_port *skge, u64 *data)
1653{
1654 struct skge_hw *hw = skge->hw;
1655 int port = skge->port;
1656 int i;
1657 unsigned long timeout = jiffies + HZ;
1658
6b0c1480 1659 xm_write16(hw, port,
baef58b1
SH		 1660 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1661
1662 /* wait for update to complete */
6b0c1480 1663 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1664 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1665 if (time_after(jiffies, timeout))
1666 break;
1667 udelay(10);
1668 }
1669
1670 /* special case for 64 bit octet counter */
6b0c1480
SH		 1671 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1672 | xm_read32(hw, port, XM_TXO_OK_LO);
1673 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1674 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1675
1676 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1677 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1678}
1679
1680static void genesis_mac_intr(struct skge_hw *hw, int port)
1681{
1682 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1683 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1684
7e676d91
SH		 1685 if (netif_msg_intr(skge))
1686 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1687 skge->netdev->name, status);
baef58b1 1688
a1bc9b87
SH		 1689 if (hw->phy_type == SK_PHY_XMAC &&
1690 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1691 xm_link_down(hw, port);
1692
baef58b1 1693 if (status & XM_IS_TXF_UR) {
6b0c1480 1694 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1695 ++skge->net_stats.tx_fifo_errors;
1696 }
1697 if (status & XM_IS_RXF_OV) {
6b0c1480 1698 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1699 ++skge->net_stats.rx_fifo_errors;
1700 }
1701}
1702
baef58b1
SH		 1703static void genesis_link_up(struct skge_port *skge)
1704{
1705 struct skge_hw *hw = skge->hw;
1706 int port = skge->port;
a1bc9b87 1707 u16 cmd, msk;
64f6b64d 1708 u32 mode;
baef58b1 1709
6b0c1480 1710 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1711
1712 /*
1713 * enabling pause frame reception is required for 1000BT
1714 * because the XMAC is not reset if the link is going down
1715 */
5d5c8e03
SH		 1716 if (skge->flow_status == FLOW_STAT_NONE ||
1717 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1718 /* Disable Pause Frame Reception */
baef58b1
SH		 1719 cmd |= XM_MMU_IGN_PF;
1720 else
1721 /* Enable Pause Frame Reception */
1722 cmd &= ~XM_MMU_IGN_PF;
1723
6b0c1480 1724 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1725
6b0c1480 1726 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1727 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1728 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1729 /*
1730 * Configure Pause Frame Generation
1731 * Use internal and external Pause Frame Generation.
1732 * Sending pause frames is edge triggered.
1733 * Send a Pause frame with the maximum pause time if
1734 * internal oder external FIFO full condition occurs.
1735 * Send a zero pause time frame to re-start transmission.
1736 */
1737 /* XM_PAUSE_DA = '010000C28001' (default) */
1738 /* XM_MAC_PTIME = 0xffff (maximum) */
1739 /* remember this value is defined in big endian (!) */
6b0c1480 1740 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1741
1742 mode |= XM_PAUSE_MODE;
6b0c1480 1743 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1744 } else {
1745 /*
1746 * disable pause frame generation is required for 1000BT
1747 * because the XMAC is not reset if the link is going down
1748 */
1749 /* Disable Pause Mode in Mode Register */
1750 mode &= ~XM_PAUSE_MODE;
1751
6b0c1480 1752 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1753 }
1754
6b0c1480 1755 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87
SH		 1756 msk = XM_DEF_MSK;
1757 if (hw->phy_type != SK_PHY_XMAC)
1758 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1759
1760 xm_write16(hw, port, XM_IMSK, msk);
6b0c1480 1761 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1762
1763 /* get MMU Command Reg. */
6b0c1480 1764 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1765 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1766 cmd |= XM_MMU_GMII_FD;
1767
89bf5f23
SH		 1768 /*
1769 * Workaround BCOM Errata (#10523) for all BCom Phys
1770 * Enable Power Management after link up
1771 */
64f6b64d
SH		 1772 if (hw->phy_type == SK_PHY_BCOM) {
1773 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1774 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1775 & ~PHY_B_AC_DIS_PM);
1776 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1777 }
baef58b1
SH		 1778
1779 /* enable Rx/Tx */
6b0c1480 1780 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1781 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1782 skge_link_up(skge);
1783}
1784
1785
45bada65 1786static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1787{
1788 struct skge_hw *hw = skge->hw;
1789 int port = skge->port;
45bada65
SH		 1790 u16 isrc;
1791
1792 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1793 if (netif_msg_intr(skge))
1794 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1795 skge->netdev->name, isrc);
baef58b1 1796
45bada65
SH		 1797 if (isrc & PHY_B_IS_PSE)
1798 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1799 hw->dev[port]->name);
baef58b1
SH		 1800
1801 /* Workaround BCom Errata:
1802 * enable and disable loopback mode if "NO HCD" occurs.
1803 */
45bada65 1804 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1805 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1806 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1807 ctrl | PHY_CT_LOOP);
6b0c1480 1808 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1809 ctrl & ~PHY_CT_LOOP);
1810 }
1811
45bada65
SH		 1812 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1813 bcom_check_link(hw, port);
baef58b1 1814
baef58b1
SH		 1815}
1816
2cd8e5d3
SH		 1817static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1818{
1819 int i;
1820
1821 gma_write16(hw, port, GM_SMI_DATA, val);
1822 gma_write16(hw, port, GM_SMI_CTRL,
1823 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1824 for (i = 0; i < PHY_RETRIES; i++) {
1825 udelay(1);
1826
1827 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1828 return 0;
1829 }
1830
1831 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1832 hw->dev[port]->name);
1833 return -EIO;
1834}
1835
1836static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1837{
1838 int i;
1839
1840 gma_write16(hw, port, GM_SMI_CTRL,
1841 GM_SMI_CT_PHY_AD(hw->phy_addr)
1842 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1843
1844 for (i = 0; i < PHY_RETRIES; i++) {
1845 udelay(1);
1846 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1847 goto ready;
1848 }
1849
1850 return -ETIMEDOUT;
1851 ready:
1852 *val = gma_read16(hw, port, GM_SMI_DATA);
1853 return 0;
1854}
1855
1856static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1857{
1858 u16 v = 0;
1859 if (__gm_phy_read(hw, port, reg, &v))
1860 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1861 hw->dev[port]->name);
1862 return v;
1863}
1864
8f3f8193 1865/* Marvell Phy Initialization */
baef58b1
SH		 1866static void yukon_init(struct skge_hw *hw, int port)
1867{
1868 struct skge_port *skge = netdev_priv(hw->dev[port]);
1869 u16 ctrl, ct1000, adv;
baef58b1 1870
baef58b1 1871 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1872 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1873
1874 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1875 PHY_M_EC_MAC_S_MSK);
1876 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1877
c506a509 1878 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1879
6b0c1480 1880 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1881 }
1882
6b0c1480 1883 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1884 if (skge->autoneg == AUTONEG_DISABLE)
1885 ctrl &= ~PHY_CT_ANE;
1886
1887 ctrl |= PHY_CT_RESET;
6b0c1480 1888 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1889
1890 ctrl = 0;
1891 ct1000 = 0;
b18f2091 1892 adv = PHY_AN_CSMA;
baef58b1
SH		 1893
1894 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1895 if (hw->copper) {
baef58b1
SH		 1896 if (skge->advertising & ADVERTISED_1000baseT_Full)
1897 ct1000 |= PHY_M_1000C_AFD;
1898 if (skge->advertising & ADVERTISED_1000baseT_Half)
1899 ct1000 |= PHY_M_1000C_AHD;
1900 if (skge->advertising & ADVERTISED_100baseT_Full)
1901 adv |= PHY_M_AN_100_FD;
1902 if (skge->advertising & ADVERTISED_100baseT_Half)
1903 adv |= PHY_M_AN_100_HD;
1904 if (skge->advertising & ADVERTISED_10baseT_Full)
1905 adv |= PHY_M_AN_10_FD;
1906 if (skge->advertising & ADVERTISED_10baseT_Half)
1907 adv |= PHY_M_AN_10_HD;
baef58b1 1908
4b67be99
SH		 1909 /* Set Flow-control capabilities */
1910 adv |= phy_pause_map[skge->flow_control];
1911 } else {
1912 if (skge->advertising & ADVERTISED_1000baseT_Full)
1913 adv |= PHY_M_AN_1000X_AFD;
1914 if (skge->advertising & ADVERTISED_1000baseT_Half)
1915 adv |= PHY_M_AN_1000X_AHD;
1916
1917 adv |= fiber_pause_map[skge->flow_control];
1918 }
45bada65 1919
baef58b1
SH		 1920 /* Restart Auto-negotiation */
1921 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1922 } else {
1923 /* forced speed/duplex settings */
1924 ct1000 = PHY_M_1000C_MSE;
1925
1926 if (skge->duplex == DUPLEX_FULL)
1927 ctrl |= PHY_CT_DUP_MD;
1928
1929 switch (skge->speed) {
1930 case SPEED_1000:
1931 ctrl |= PHY_CT_SP1000;
1932 break;
1933 case SPEED_100:
1934 ctrl |= PHY_CT_SP100;
1935 break;
1936 }
1937
1938 ctrl |= PHY_CT_RESET;
1939 }
1940
c506a509 1941 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1942
6b0c1480
SH		 1943 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1944 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1945
baef58b1
SH		 1946 /* Enable phy interrupt on autonegotiation complete (or link up) */
1947 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1948 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1949 else
4cde06ed 1950 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1951}
1952
1953static void yukon_reset(struct skge_hw *hw, int port)
1954{
6b0c1480
SH		 1955 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1956 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1957 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1958 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1959 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1960
6b0c1480
SH		 1961 gma_write16(hw, port, GM_RX_CTRL,
1962 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1963 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1964}
1965
c8868611
SH		 1966/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1967static int is_yukon_lite_a0(struct skge_hw *hw)
1968{
1969 u32 reg;
1970 int ret;
1971
1972 if (hw->chip_id != CHIP_ID_YUKON)
1973 return 0;
1974
1975 reg = skge_read32(hw, B2_FAR);
1976 skge_write8(hw, B2_FAR + 3, 0xff);
1977 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1978 skge_write32(hw, B2_FAR, reg);
1979 return ret;
1980}
1981
baef58b1
SH		 1982static void yukon_mac_init(struct skge_hw *hw, int port)
1983{
1984 struct skge_port *skge = netdev_priv(hw->dev[port]);
1985 int i;
1986 u32 reg;
1987 const u8 *addr = hw->dev[port]->dev_addr;
1988
1989 /* WA code for COMA mode -- set PHY reset */
1990 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1991 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1992 reg = skge_read32(hw, B2_GP_IO);
1993 reg |= GP_DIR_9 | GP_IO_9;
1994 skge_write32(hw, B2_GP_IO, reg);
1995 }
baef58b1
SH		 1996
1997 /* hard reset */
6b0c1480
SH		 1998 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1999 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2000
2001 /* WA code for COMA mode -- clear PHY reset */
2002 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2003 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2004 reg = skge_read32(hw, B2_GP_IO);
2005 reg |= GP_DIR_9;
2006 reg &= ~GP_IO_9;
2007 skge_write32(hw, B2_GP_IO, reg);
2008 }
baef58b1
SH		 2009
2010 /* Set hardware config mode */
2011 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2012 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2013 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2014
2015 /* Clear GMC reset */
6b0c1480
SH		 2016 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2017 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2018 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2019
baef58b1
SH		 2020 if (skge->autoneg == AUTONEG_DISABLE) {
2021 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2022 gma_write16(hw, port, GM_GP_CTRL,
2023 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2024
2025 switch (skge->speed) {
2026 case SPEED_1000:
564f9abb 2027 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2028 reg |= GM_GPCR_SPEED_1000;
564f9abb 2029 break;
baef58b1 2030 case SPEED_100:
564f9abb 2031 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2032 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2033 break;
2034 case SPEED_10:
2035 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2036 break;
baef58b1
SH		 2037 }
2038
2039 if (skge->duplex == DUPLEX_FULL)
2040 reg |= GM_GPCR_DUP_FULL;
2041 } else
2042 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2043
baef58b1
SH		 2044 switch (skge->flow_control) {
2045 case FLOW_MODE_NONE:
6b0c1480 2046 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2047 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2048 break;
2049 case FLOW_MODE_LOC_SEND:
2050 /* disable Rx flow-control */
2051 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2052 break;
2053 case FLOW_MODE_SYMMETRIC:
2054 case FLOW_MODE_SYM_OR_REM:
2055 /* enable Tx & Rx flow-control */
2056 break;
baef58b1
SH		 2057 }
2058
6b0c1480 2059 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2060 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2061
baef58b1 2062 yukon_init(hw, port);
baef58b1
SH		 2063
2064 /* MIB clear */
6b0c1480
SH		 2065 reg = gma_read16(hw, port, GM_PHY_ADDR);
2066 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2067
2068 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2069 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2070 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2071
2072 /* transmit control */
6b0c1480 2073 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2074
2075 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2076 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2077 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2078
2079 /* transmit flow control */
6b0c1480 2080 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2081
2082 /* transmit parameter */
6b0c1480 2083 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2084 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2085 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2086 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2087
2088 /* serial mode register */
2089 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2090 if (hw->dev[port]->mtu > 1500)
2091 reg |= GM_SMOD_JUMBO_ENA;
2092
6b0c1480 2093 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2094
2095 /* physical address: used for pause frames */
6b0c1480 2096 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2097 /* virtual address for data */
6b0c1480 2098 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2099
2100 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2101 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2102 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2103 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2104
2105 /* Initialize Mac Fifo */
2106
2107 /* Configure Rx MAC FIFO */
6b0c1480 2108 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2109 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2110
2111 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2112 if (is_yukon_lite_a0(hw))
baef58b1 2113 reg &= ~GMF_RX_F_FL_ON;
c8868611 2114
6b0c1480
SH		 2115 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2116 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2117 /*
2118 * because Pause Packet Truncation in GMAC is not working
2119 * we have to increase the Flush Threshold to 64 bytes
2120 * in order to flush pause packets in Rx FIFO on Yukon-1
2121 */
2122 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2123
2124 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2125 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2126 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2127}
2128
355ec572
SH		 2129/* Go into power down mode */
2130static void yukon_suspend(struct skge_hw *hw, int port)
2131{
2132 u16 ctrl;
2133
2134 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2135 ctrl |= PHY_M_PC_POL_R_DIS;
2136 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2137
2138 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2139 ctrl |= PHY_CT_RESET;
2140 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2141
2142 /* switch IEEE compatible power down mode on */
2143 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2144 ctrl |= PHY_CT_PDOWN;
2145 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2146}
2147
baef58b1
SH		 2148static void yukon_stop(struct skge_port *skge)
2149{
2150 struct skge_hw *hw = skge->hw;
2151 int port = skge->port;
2152
46a60f2d
SH		 2153 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2154 yukon_reset(hw, port);
baef58b1 2155
6b0c1480
SH		 2156 gma_write16(hw, port, GM_GP_CTRL,
2157 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2158 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2159 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2160
355ec572 2161 yukon_suspend(hw, port);
46a60f2d 2162
baef58b1 2163 /* set GPHY Control reset */
46a60f2d
SH		 2164 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2165 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2166}
2167
2168static void yukon_get_stats(struct skge_port *skge, u64 *data)
2169{
2170 struct skge_hw *hw = skge->hw;
2171 int port = skge->port;
2172 int i;
2173
6b0c1480
SH		 2174 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2175 | gma_read32(hw, port, GM_TXO_OK_LO);
2176 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2177 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2178
2179 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2180 data[i] = gma_read32(hw, port,
baef58b1
SH		 2181 skge_stats[i].gma_offset);
2182}
2183
2184static void yukon_mac_intr(struct skge_hw *hw, int port)
2185{
7e676d91
SH		 2186 struct net_device *dev = hw->dev[port];
2187 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2188 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2189
7e676d91
SH		 2190 if (netif_msg_intr(skge))
2191 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2192 dev->name, status);
2193
baef58b1
SH		 2194 if (status & GM_IS_RX_FF_OR) {
2195 ++skge->net_stats.rx_fifo_errors;
d8a09943 2196 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2197 }
d8a09943 2198
baef58b1
SH		 2199 if (status & GM_IS_TX_FF_UR) {
2200 ++skge->net_stats.tx_fifo_errors;
d8a09943 2201 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2202 }
2203
2204}
2205
2206static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2207{
95566065 2208 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2209 case PHY_M_PS_SPEED_1000:
2210 return SPEED_1000;
2211 case PHY_M_PS_SPEED_100:
2212 return SPEED_100;
2213 default:
2214 return SPEED_10;
2215 }
2216}
2217
2218static void yukon_link_up(struct skge_port *skge)
2219{
2220 struct skge_hw *hw = skge->hw;
2221 int port = skge->port;
2222 u16 reg;
2223
baef58b1 2224 /* Enable Transmit FIFO Underrun */
46a60f2d 2225 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2226
6b0c1480 2227 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2228 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2229 reg |= GM_GPCR_DUP_FULL;
2230
2231 /* enable Rx/Tx */
2232 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2233 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2234
4cde06ed 2235 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2236 skge_link_up(skge);
2237}
2238
2239static void yukon_link_down(struct skge_port *skge)
2240{
2241 struct skge_hw *hw = skge->hw;
2242 int port = skge->port;
d8a09943 2243 u16 ctrl;
baef58b1 2244
d8a09943
SH		 2245 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2246 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2247 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2248
5d5c8e03
SH		 2249 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2250 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2251 ctrl |= PHY_M_AN_ASP;
baef58b1 2252 /* restore Asymmetric Pause bit */
5d5c8e03 2253 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2254 }
2255
baef58b1
SH		 2256 skge_link_down(skge);
2257
2258 yukon_init(hw, port);
2259}
2260
2261static void yukon_phy_intr(struct skge_port *skge)
2262{
2263 struct skge_hw *hw = skge->hw;
2264 int port = skge->port;
2265 const char *reason = NULL;
2266 u16 istatus, phystat;
2267
6b0c1480
SH		 2268 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2269 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2270
2271 if (netif_msg_intr(skge))
2272 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2273 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2274
2275 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2276 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2277 & PHY_M_AN_RF) {
2278 reason = "remote fault";
2279 goto failed;
2280 }
2281
c506a509 2282 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2283 reason = "master/slave fault";
2284 goto failed;
2285 }
2286
2287 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2288 reason = "speed/duplex";
2289 goto failed;
2290 }
2291
2292 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2293 ? DUPLEX_FULL : DUPLEX_HALF;
2294 skge->speed = yukon_speed(hw, phystat);
2295
baef58b1
SH		 2296 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2297 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2298 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2299 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2300 break;
2301 case PHY_M_PS_RX_P_EN:
5d5c8e03 2302 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2303 break;
2304 case PHY_M_PS_TX_P_EN:
5d5c8e03 2305 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2306 break;
2307 default:
5d5c8e03 2308 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2309 }
2310
5d5c8e03 2311 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2312 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2313 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2314 else
6b0c1480 2315 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2316 yukon_link_up(skge);
2317 return;
2318 }
2319
2320 if (istatus & PHY_M_IS_LSP_CHANGE)
2321 skge->speed = yukon_speed(hw, phystat);
2322
2323 if (istatus & PHY_M_IS_DUP_CHANGE)
2324 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2325 if (istatus & PHY_M_IS_LST_CHANGE) {
2326 if (phystat & PHY_M_PS_LINK_UP)
2327 yukon_link_up(skge);
2328 else
2329 yukon_link_down(skge);
2330 }
2331 return;
2332 failed:
2333 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2334 skge->netdev->name, reason);
2335
2336 /* XXX restart autonegotiation? */
2337}
2338
ee294dcd
SH		 2339static void skge_phy_reset(struct skge_port *skge)
2340{
2341 struct skge_hw *hw = skge->hw;
2342 int port = skge->port;
aae343d4 2343 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2344
2345 netif_stop_queue(skge->netdev);
2346 netif_carrier_off(skge->netdev);
2347
9cbe330f 2348 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2349 if (hw->chip_id == CHIP_ID_GENESIS) {
2350 genesis_reset(hw, port);
2351 genesis_mac_init(hw, port);
2352 } else {
2353 yukon_reset(hw, port);
2354 yukon_init(hw, port);
2355 }
9cbe330f 2356 spin_unlock_bh(&hw->phy_lock);
75814090
SH		 2357
2358 dev->set_multicast_list(dev);
ee294dcd
SH		 2359}
2360
2cd8e5d3
SH		 2361/* Basic MII support */
2362static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2363{
2364 struct mii_ioctl_data *data = if_mii(ifr);
2365 struct skge_port *skge = netdev_priv(dev);
2366 struct skge_hw *hw = skge->hw;
2367 int err = -EOPNOTSUPP;
2368
2369 if (!netif_running(dev))
2370 return -ENODEV; /* Phy still in reset */
2371
2372 switch(cmd) {
2373 case SIOCGMIIPHY:
2374 data->phy_id = hw->phy_addr;
2375
2376 /* fallthru */
2377 case SIOCGMIIREG: {
2378 u16 val = 0;
9cbe330f 2379 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2380 if (hw->chip_id == CHIP_ID_GENESIS)
2381 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2382 else
2383 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2384 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2385 data->val_out = val;
2386 break;
2387 }
2388
2389 case SIOCSMIIREG:
2390 if (!capable(CAP_NET_ADMIN))
2391 return -EPERM;
2392
9cbe330f 2393 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2394 if (hw->chip_id == CHIP_ID_GENESIS)
2395 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2396 data->val_in);
2397 else
2398 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2399 data->val_in);
9cbe330f 2400 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2401 break;
2402 }
2403 return err;
2404}
2405
7fb7ac24
SH		 2406/* Assign Ram Buffer allocation to queue */
2407static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, u32 space)
baef58b1
SH		 2408{
2409 u32 end;
2410
7fb7ac24
SH		 2411 /* convert from K bytes to qwords used for hw register */
2412 start *= 1024/8;
2413 space *= 1024/8;
2414 end = start + space - 1;
baef58b1
SH		 2415
2416 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2417 skge_write32(hw, RB_ADDR(q, RB_START), start);
7fb7ac24 2418 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2419 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2420 skge_write32(hw, RB_ADDR(q, RB_RP), start);
baef58b1
SH		 2421
2422 if (q == Q_R1 || q == Q_R2) {
7fb7ac24
SH		 2423 u32 tp = space - space/4;
2424
baef58b1 2425 /* Set thresholds on receive queue's */
7fb7ac24
SH		 2426 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
2427 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
2428 } else if (hw->chip_id != CHIP_ID_GENESIS)
2429 /* Genesis Tx Fifo is too small for normal store/forward */
baef58b1 2430 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
baef58b1
SH		 2431
2432 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2433}
2434
2435/* Setup Bus Memory Interface */
2436static void skge_qset(struct skge_port *skge, u16 q,
2437 const struct skge_element *e)
2438{
2439 struct skge_hw *hw = skge->hw;
2440 u32 watermark = 0x600;
2441 u64 base = skge->dma + (e->desc - skge->mem);
2442
2443 /* optimization to reduce window on 32bit/33mhz */
2444 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2445 watermark /= 2;
2446
2447 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2448 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2449 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2450 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2451}
2452
2453static int skge_up(struct net_device *dev)
2454{
2455 struct skge_port *skge = netdev_priv(dev);
2456 struct skge_hw *hw = skge->hw;
2457 int port = skge->port;
7fb7ac24 2458 u32 ramaddr, ramsize, rxspace;
baef58b1
SH		 2459 size_t rx_size, tx_size;
2460 int err;
2461
fae87592
SH		 2462 if (!is_valid_ether_addr(dev->dev_addr))
2463 return -EINVAL;
2464
baef58b1
SH		 2465 if (netif_msg_ifup(skge))
2466 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2467
19a33d4e 2468 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2469 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2470 else
2471 skge->rx_buf_size = RX_BUF_SIZE;
2472
2473
baef58b1
SH		 2474 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2475 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2476 skge->mem_size = tx_size + rx_size;
2477 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2478 if (!skge->mem)
2479 return -ENOMEM;
2480
c3da1447
SH		 2481 BUG_ON(skge->dma & 7);
2482
2483 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2484 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2485 err = -EINVAL;
2486 goto free_pci_mem;
2487 }
2488
baef58b1
SH		 2489 memset(skge->mem, 0, skge->mem_size);
2490
203babb6
SH		 2491 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2492 if (err)
baef58b1
SH		 2493 goto free_pci_mem;
2494
c54f9765 2495 err = skge_rx_fill(dev);
19a33d4e 2496 if (err)
baef58b1
SH		 2497 goto free_rx_ring;
2498
203babb6
SH		 2499 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2500 skge->dma + rx_size);
2501 if (err)
baef58b1
SH		 2502 goto free_rx_ring;
2503
8f3f8193 2504 /* Initialize MAC */
9cbe330f 2505 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2506 if (hw->chip_id == CHIP_ID_GENESIS)
2507 genesis_mac_init(hw, port);
2508 else
2509 yukon_mac_init(hw, port);
9cbe330f 2510 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2511
2512 /* Configure RAMbuffers */
7fb7ac24
SH		 2513 ramsize = (hw->ram_size - hw->ram_offset) / hw->ports;
2514 ramaddr = hw->ram_offset + port * ramsize;
2515 rxspace = 8 + (2*(ramsize - 16))/3;
baef58b1 2516
7fb7ac24
SH		 2517 skge_ramset(hw, rxqaddr[port], ramaddr, rxspace);
2518 skge_ramset(hw, txqaddr[port], ramaddr + rxspace, ramsize - rxspace);
baef58b1 2519
7fb7ac24 2520 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
baef58b1 2521 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
baef58b1
SH		 2522 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2523
2524 /* Start receiver BMU */
2525 wmb();
2526 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2527 skge_led(skge, LED_MODE_ON);
baef58b1 2528
4ebabfcb
SH		 2529 spin_lock_irq(&hw->hw_lock);
2530 hw->intr_mask |= portmask[port];
2531 skge_write32(hw, B0_IMSK, hw->intr_mask);
2532 spin_unlock_irq(&hw->hw_lock);
2533
bea3348e 2534 napi_enable(&skge->napi);
baef58b1
SH		 2535 return 0;
2536
2537 free_rx_ring:
2538 skge_rx_clean(skge);
2539 kfree(skge->rx_ring.start);
2540 free_pci_mem:
2541 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2542 skge->mem = NULL;
baef58b1
SH		 2543
2544 return err;
2545}
2546
60b24b51
SH		 2547/* stop receiver */
2548static void skge_rx_stop(struct skge_hw *hw, int port)
2549{
2550 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2551 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2552 RB_RST_SET|RB_DIS_OP_MD);
2553 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2554}
2555
baef58b1
SH		 2556static int skge_down(struct net_device *dev)
2557{
2558 struct skge_port *skge = netdev_priv(dev);
2559 struct skge_hw *hw = skge->hw;
2560 int port = skge->port;
2561
7731a4ea
SH		 2562 if (skge->mem == NULL)
2563 return 0;
2564
baef58b1
SH		 2565 if (netif_msg_ifdown(skge))
2566 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2567
2568 netif_stop_queue(dev);
692412b3 2569
64f6b64d 2570 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2571 del_timer_sync(&skge->link_timer);
baef58b1 2572
bea3348e 2573 napi_disable(&skge->napi);
692412b3 2574 netif_carrier_off(dev);
4ebabfcb
SH		 2575
2576 spin_lock_irq(&hw->hw_lock);
2577 hw->intr_mask &= ~portmask[port];
2578 skge_write32(hw, B0_IMSK, hw->intr_mask);
2579 spin_unlock_irq(&hw->hw_lock);
2580
46a60f2d
SH		 2581 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2582 if (hw->chip_id == CHIP_ID_GENESIS)
2583 genesis_stop(skge);
2584 else
2585 yukon_stop(skge);
2586
baef58b1
SH		 2587 /* Stop transmitter */
2588 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2589 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2590 RB_RST_SET|RB_DIS_OP_MD);
2591
baef58b1
SH		 2592
2593 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2594 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2595 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2596
2597 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2598 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2599 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2600
2601 /* Reset PCI FIFO */
2602 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2603 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2604
2605 /* Reset the RAM Buffer async Tx queue */
2606 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2607
2608 skge_rx_stop(hw, port);
baef58b1
SH		 2609
2610 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2611 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2612 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2613 } else {
6b0c1480
SH		 2614 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2615 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2616 }
2617
6abebb53 2618 skge_led(skge, LED_MODE_OFF);
baef58b1 2619
e3a1b99f 2620 netif_tx_lock_bh(dev);
513f533e 2621 skge_tx_clean(dev);
e3a1b99f
SH		 2622 netif_tx_unlock_bh(dev);
2623
baef58b1
SH		 2624 skge_rx_clean(skge);
2625
2626 kfree(skge->rx_ring.start);
2627 kfree(skge->tx_ring.start);
2628 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2629 skge->mem = NULL;
baef58b1
SH		 2630 return 0;
2631}
2632
29b4e886
SH		 2633static inline int skge_avail(const struct skge_ring *ring)
2634{
992c9623 2635 smp_mb();
29b4e886
SH		 2636 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2637 + (ring->to_clean - ring->to_use) - 1;
2638}
2639
baef58b1
SH		 2640static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2641{
2642 struct skge_port *skge = netdev_priv(dev);
2643 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2644 struct skge_element *e;
2645 struct skge_tx_desc *td;
2646 int i;
2647 u32 control, len;
2648 u64 map;
baef58b1 2649
5b057c6b 2650 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2651 return NETDEV_TX_OK;
2652
513f533e 2653 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2654 return NETDEV_TX_BUSY;
baef58b1 2655
7c442fa1 2656 e = skge->tx_ring.to_use;
baef58b1 2657 td = e->desc;
7c442fa1 2658 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2659 e->skb = skb;
2660 len = skb_headlen(skb);
2661 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2662 pci_unmap_addr_set(e, mapaddr, map);
2663 pci_unmap_len_set(e, maplen, len);
2664
2665 td->dma_lo = map;
2666 td->dma_hi = map >> 32;
2667
84fa7933 2668 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2669 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2670
2671 /* This seems backwards, but it is what the sk98lin
2672 * does. Looks like hardware is wrong?
2673 */
b0061ce4 2674 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
981d0377 2675 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2676 control = BMU_TCP_CHECK;
2677 else
2678 control = BMU_UDP_CHECK;
2679
2680 td->csum_offs = 0;
2681 td->csum_start = offset;
ff1dcadb 2682 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2683 } else
2684 control = BMU_CHECK;
2685
2686 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2687 control |= BMU_EOF| BMU_IRQ_EOF;
2688 else {
2689 struct skge_tx_desc *tf = td;
2690
2691 control |= BMU_STFWD;
2692 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2693 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2694
2695 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2696 frag->size, PCI_DMA_TODEVICE);
2697
2698 e = e->next;
7c442fa1 2699 e->skb = skb;
baef58b1 2700 tf = e->desc;
7c442fa1
SH		 2701 BUG_ON(tf->control & BMU_OWN);
2702
baef58b1
SH		 2703 tf->dma_lo = map;
2704 tf->dma_hi = (u64) map >> 32;
2705 pci_unmap_addr_set(e, mapaddr, map);
2706 pci_unmap_len_set(e, maplen, frag->size);
2707
2708 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2709 }
2710 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2711 }
2712 /* Make sure all the descriptors written */
2713 wmb();
2714 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2715 wmb();
2716
2717 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2718
7c442fa1 2719 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2720 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2721 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2722
7c442fa1 2723 skge->tx_ring.to_use = e->next;
992c9623
SH		 2724 smp_wmb();
2725
9db96479 2726 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2727 pr_debug("%s: transmit queue full\n", dev->name);
2728 netif_stop_queue(dev);
2729 }
2730
c68ce71a
SH		 2731 dev->trans_start = jiffies;
2732
baef58b1
SH		 2733 return NETDEV_TX_OK;
2734}
2735
7c442fa1
SH		 2736
2737/* Free resources associated with this reing element */
2738static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2739 u32 control)
866b4f3e
SH		 2740{
2741 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2742
7c442fa1
SH		 2743 /* skb header vs. fragment */
2744 if (control & BMU_STF)
866b4f3e 2745 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2746 pci_unmap_len(e, maplen),
2747 PCI_DMA_TODEVICE);
2748 else
2749 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2750 pci_unmap_len(e, maplen),
2751 PCI_DMA_TODEVICE);
866b4f3e 2752
7c442fa1
SH		 2753 if (control & BMU_EOF) {
2754 if (unlikely(netif_msg_tx_done(skge)))
2755 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2756 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2757
513f533e 2758 dev_kfree_skb(e->skb);
baef58b1
SH		 2759 }
2760}
2761
7c442fa1 2762/* Free all buffers in transmit ring */
513f533e 2763static void skge_tx_clean(struct net_device *dev)
baef58b1 2764{
513f533e 2765 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2766 struct skge_element *e;
baef58b1 2767
7c442fa1
SH		 2768 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2769 struct skge_tx_desc *td = e->desc;
2770 skge_tx_free(skge, e, td->control);
2771 td->control = 0;
2772 }
2773
2774 skge->tx_ring.to_clean = e;
513f533e 2775 netif_wake_queue(dev);
baef58b1
SH		 2776}
2777
2778static void skge_tx_timeout(struct net_device *dev)
2779{
2780 struct skge_port *skge = netdev_priv(dev);
2781
2782 if (netif_msg_timer(skge))
2783 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2784
2785 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2786 skge_tx_clean(dev);
baef58b1
SH		 2787}
2788
2789static int skge_change_mtu(struct net_device *dev, int new_mtu)
2790{
60b24b51
SH		 2791 struct skge_port *skge = netdev_priv(dev);
2792 struct skge_hw *hw = skge->hw;
2793 int port = skge->port;
7731a4ea 2794 int err;
60b24b51 2795 u16 ctl, reg;
baef58b1 2796
95566065 2797 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2798 return -EINVAL;
2799
7731a4ea
SH		 2800 if (!netif_running(dev)) {
2801 dev->mtu = new_mtu;
2802 return 0;
2803 }
2804
60b24b51
SH		 2805 skge_write32(hw, B0_IMSK, 0);
2806 dev->trans_start = jiffies; /* prevent tx timeout */
2807 netif_stop_queue(dev);
2808 napi_disable(&skge->napi);
2809
2810 ctl = gma_read16(hw, port, GM_GP_CTRL);
2811 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2812
2813 skge_rx_clean(skge);
2814 skge_rx_stop(hw, port);
baef58b1 2815
19a33d4e 2816 dev->mtu = new_mtu;
7731a4ea 2817
60b24b51
SH		 2818 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2819 if (new_mtu > 1500)
2820 reg |= GM_SMOD_JUMBO_ENA;
2821 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2822
2823 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2824
2825 err = skge_rx_fill(dev);
2826 wmb();
2827 if (!err)
2828 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2829 skge_write32(hw, B0_IMSK, hw->intr_mask);
2830
7731a4ea
SH		 2831 if (err)
2832 dev_close(dev);
60b24b51
SH		 2833 else {
2834 gma_write16(hw, port, GM_GP_CTRL, ctl);
2835
2836 napi_enable(&skge->napi);
2837 netif_wake_queue(dev);
2838 }
baef58b1
SH		 2839
2840 return err;
2841}
2842
c4cd29d2
SH		 2843static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2844
2845static void genesis_add_filter(u8 filter[8], const u8 *addr)
2846{
2847 u32 crc, bit;
2848
2849 crc = ether_crc_le(ETH_ALEN, addr);
2850 bit = ~crc & 0x3f;
2851 filter[bit/8] |= 1 << (bit%8);
2852}
2853
baef58b1
SH		 2854static void genesis_set_multicast(struct net_device *dev)
2855{
2856 struct skge_port *skge = netdev_priv(dev);
2857 struct skge_hw *hw = skge->hw;
2858 int port = skge->port;
2859 int i, count = dev->mc_count;
2860 struct dev_mc_list *list = dev->mc_list;
2861 u32 mode;
2862 u8 filter[8];
2863
6b0c1480 2864 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2865 mode |= XM_MD_ENA_HASH;
2866 if (dev->flags & IFF_PROMISC)
2867 mode |= XM_MD_ENA_PROM;
2868 else
2869 mode &= ~XM_MD_ENA_PROM;
2870
2871 if (dev->flags & IFF_ALLMULTI)
2872 memset(filter, 0xff, sizeof(filter));
2873 else {
2874 memset(filter, 0, sizeof(filter));
c4cd29d2
SH		 2875
2876 if (skge->flow_status == FLOW_STAT_REM_SEND
2877 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2878 genesis_add_filter(filter, pause_mc_addr);
2879
2880 for (i = 0; list && i < count; i++, list = list->next)
2881 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2882 }
2883
6b0c1480 2884 xm_write32(hw, port, XM_MODE, mode);
45bada65 2885 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2886}
2887
c4cd29d2
SH		 2888static void yukon_add_filter(u8 filter[8], const u8 *addr)
2889{
2890 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2891 filter[bit/8] |= 1 << (bit%8);
2892}
2893
baef58b1
SH		 2894static void yukon_set_multicast(struct net_device *dev)
2895{
2896 struct skge_port *skge = netdev_priv(dev);
2897 struct skge_hw *hw = skge->hw;
2898 int port = skge->port;
2899 struct dev_mc_list *list = dev->mc_list;
c4cd29d2
SH		 2900 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2901 || skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2902 u16 reg;
2903 u8 filter[8];
2904
2905 memset(filter, 0, sizeof(filter));
2906
6b0c1480 2907 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2908 reg |= GM_RXCR_UCF_ENA;
2909
8f3f8193 2910 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2911 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2912 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2913 memset(filter, 0xff, sizeof(filter));
c4cd29d2 2914 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 2915 reg &= ~GM_RXCR_MCF_ENA;
2916 else {
2917 int i;
2918 reg |= GM_RXCR_MCF_ENA;
2919
c4cd29d2
SH		 2920 if (rx_pause)
2921 yukon_add_filter(filter, pause_mc_addr);
2922
2923 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2924 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2925 }
2926
2927
6b0c1480 2928 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2929 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2930 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2931 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2932 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2933 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2934 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2935 (u16)filter[6] | ((u16)filter[7] << 8));
2936
6b0c1480 2937 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2938}
2939
383181ac
SH		 2940static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2941{
2942 if (hw->chip_id == CHIP_ID_GENESIS)
2943 return status >> XMR_FS_LEN_SHIFT;
2944 else
2945 return status >> GMR_FS_LEN_SHIFT;
2946}
2947
baef58b1
SH		 2948static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2949{
2950 if (hw->chip_id == CHIP_ID_GENESIS)
2951 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2952 else
2953 return (status & GMR_FS_ANY_ERR) ||
2954 (status & GMR_FS_RX_OK) == 0;
2955}
2956
19a33d4e
SH		 2957
2958/* Get receive buffer from descriptor.
2959 * Handles copy of small buffers and reallocation failures
2960 */
c54f9765
SH		 2961static struct sk_buff *skge_rx_get(struct net_device *dev,
2962 struct skge_element *e,
2963 u32 control, u32 status, u16 csum)
19a33d4e 2964{
c54f9765 2965 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2966 struct sk_buff *skb;
2967 u16 len = control & BMU_BBC;
2968
2969 if (unlikely(netif_msg_rx_status(skge)))
2970 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2971 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2972 status, len);
2973
2974 if (len > skge->rx_buf_size)
2975 goto error;
2976
2977 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2978 goto error;
2979
2980 if (bad_phy_status(skge->hw, status))
2981 goto error;
2982
2983 if (phy_length(skge->hw, status) != len)
2984 goto error;
19a33d4e
SH		 2985
2986 if (len < RX_COPY_THRESHOLD) {
c54f9765 2987 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2988 if (!skb)
2989 goto resubmit;
19a33d4e 2990
383181ac 2991 skb_reserve(skb, 2);
19a33d4e
SH		 2992 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2993 pci_unmap_addr(e, mapaddr),
2994 len, PCI_DMA_FROMDEVICE);
d626f62b 2995 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e
SH		 2996 pci_dma_sync_single_for_device(skge->hw->pdev,
2997 pci_unmap_addr(e, mapaddr),
2998 len, PCI_DMA_FROMDEVICE);
19a33d4e 2999 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3000 } else {
383181ac 3001 struct sk_buff *nskb;
c54f9765 3002 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 3003 if (!nskb)
3004 goto resubmit;
19a33d4e 3005
901ccefb 3006 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 3007 pci_unmap_single(skge->hw->pdev,
3008 pci_unmap_addr(e, mapaddr),
3009 pci_unmap_len(e, maplen),
3010 PCI_DMA_FROMDEVICE);
3011 skb = e->skb;
383181ac 3012 prefetch(skb->data);
19a33d4e 3013 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3014 }
383181ac
SH		 3015
3016 skb_put(skb, len);
383181ac
SH		 3017 if (skge->rx_csum) {
3018 skb->csum = csum;
84fa7933 3019 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3020 }
3021
c54f9765 3022 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3023
3024 return skb;
3025error:
3026
3027 if (netif_msg_rx_err(skge))
3028 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 3029 dev->name, e - skge->rx_ring.start,
383181ac
SH		 3030 control, status);
3031
3032 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3033 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3034 skge->net_stats.rx_length_errors++;
3035 if (status & XMR_FS_FRA_ERR)
3036 skge->net_stats.rx_frame_errors++;
3037 if (status & XMR_FS_FCS_ERR)
3038 skge->net_stats.rx_crc_errors++;
3039 } else {
3040 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3041 skge->net_stats.rx_length_errors++;
3042 if (status & GMR_FS_FRAGMENT)
3043 skge->net_stats.rx_frame_errors++;
3044 if (status & GMR_FS_CRC_ERR)
3045 skge->net_stats.rx_crc_errors++;
3046 }
3047
3048resubmit:
3049 skge_rx_reuse(e, skge->rx_buf_size);
3050 return NULL;
baef58b1
SH		 3051}
3052
7c442fa1 3053/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3054static void skge_tx_done(struct net_device *dev)
00a6cae2 3055{
7c442fa1 3056 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3057 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3058 struct skge_element *e;
3059
513f533e 3060 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3061
866b4f3e 3062 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3063 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3064
992c9623 3065 if (control & BMU_OWN)
00a6cae2
SH		 3066 break;
3067
992c9623 3068 skge_tx_free(skge, e, control);
00a6cae2 3069 }
7c442fa1 3070 skge->tx_ring.to_clean = e;
866b4f3e 3071
992c9623
SH		 3072 /* Can run lockless until we need to synchronize to restart queue. */
3073 smp_mb();
3074
3075 if (unlikely(netif_queue_stopped(dev) &&
3076 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3077 netif_tx_lock(dev);
3078 if (unlikely(netif_queue_stopped(dev) &&
3079 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3080 netif_wake_queue(dev);
00a6cae2 3081
992c9623
SH		 3082 }
3083 netif_tx_unlock(dev);
3084 }
00a6cae2 3085}
19a33d4e 3086
bea3348e 3087static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3088{
bea3348e
SH		 3089 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3090 struct net_device *dev = skge->netdev;
baef58b1
SH		 3091 struct skge_hw *hw = skge->hw;
3092 struct skge_ring *ring = &skge->rx_ring;
3093 struct skge_element *e;
00a6cae2
SH		 3094 int work_done = 0;
3095
513f533e
SH		 3096 skge_tx_done(dev);
3097
3098 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3099
1631aef1 3100 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3101 struct skge_rx_desc *rd = e->desc;
19a33d4e 3102 struct sk_buff *skb;
383181ac 3103 u32 control;
baef58b1
SH		 3104
3105 rmb();
3106 control = rd->control;
3107 if (control & BMU_OWN)
3108 break;
3109
c54f9765 3110 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3111 if (likely(skb)) {
19a33d4e
SH		 3112 dev->last_rx = jiffies;
3113 netif_receive_skb(skb);
baef58b1 3114
19a33d4e 3115 ++work_done;
5a011447 3116 }
baef58b1
SH		 3117 }
3118 ring->to_clean = e;
3119
baef58b1
SH		 3120 /* restart receiver */
3121 wmb();
a9cdab86 3122 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3123
bea3348e
SH		 3124 if (work_done < to_do) {
3125 spin_lock_irq(&hw->hw_lock);
3126 __netif_rx_complete(dev, napi);
3127 hw->intr_mask |= napimask[skge->port];
3128 skge_write32(hw, B0_IMSK, hw->intr_mask);
3129 skge_read32(hw, B0_IMSK);
3130 spin_unlock_irq(&hw->hw_lock);
3131 }
1631aef1 3132
bea3348e 3133 return work_done;
baef58b1
SH		 3134}
3135
f6620cab
SH		 3136/* Parity errors seem to happen when Genesis is connected to a switch
3137 * with no other ports present. Heartbeat error??
3138 */
baef58b1
SH		 3139static void skge_mac_parity(struct skge_hw *hw, int port)
3140{
f6620cab
SH		 3141 struct net_device *dev = hw->dev[port];
3142
3143 if (dev) {
3144 struct skge_port *skge = netdev_priv(dev);
3145 ++skge->net_stats.tx_heartbeat_errors;
3146 }
baef58b1
SH		 3147
3148 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3149 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3150 MFF_CLR_PERR);
3151 else
3152 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3153 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3154 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3155 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3156}
3157
baef58b1
SH		 3158static void skge_mac_intr(struct skge_hw *hw, int port)
3159{
95566065 3160 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3161 genesis_mac_intr(hw, port);
3162 else
3163 yukon_mac_intr(hw, port);
3164}
3165
3166/* Handle device specific framing and timeout interrupts */
3167static void skge_error_irq(struct skge_hw *hw)
3168{
1479d13c 3169 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3170 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3171
3172 if (hw->chip_id == CHIP_ID_GENESIS) {
3173 /* clear xmac errors */
3174 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3175 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3176 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3177 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3178 } else {
3179 /* Timestamp (unused) overflow */
3180 if (hwstatus & IS_IRQ_TIST_OV)
3181 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3182 }
3183
3184 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3185 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3186 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3187 }
3188
3189 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3190 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3191 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3192 }
3193
3194 if (hwstatus & IS_M1_PAR_ERR)
3195 skge_mac_parity(hw, 0);
3196
3197 if (hwstatus & IS_M2_PAR_ERR)
3198 skge_mac_parity(hw, 1);
3199
b9d64acc 3200 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3201 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3202 hw->dev[0]->name);
baef58b1 3203 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3204 }
baef58b1 3205
b9d64acc 3206 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3207 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3208 hw->dev[1]->name);
baef58b1 3209 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3210 }
baef58b1
SH		 3211
3212 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3213 u16 pci_status, pci_cmd;
3214
1479d13c
SH		 3215 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3216 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3217
1479d13c
SH		 3218 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3219 pci_cmd, pci_status);
b9d64acc
SH		 3220
3221 /* Write the error bits back to clear them. */
3222 pci_status &= PCI_STATUS_ERROR_BITS;
3223 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3224 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3225 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3226 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3227 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3228
050ec18a 3229 /* if error still set then just ignore it */
baef58b1
SH		 3230 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3231 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3232 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3233 hw->intr_mask &= ~IS_HW_ERR;
3234 }
3235 }
3236}
3237
3238/*
9cbe330f 3239 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3240 * because accessing phy registers requires spin wait which might
3241 * cause excess interrupt latency.
3242 */
9cbe330f 3243static void skge_extirq(unsigned long arg)
baef58b1 3244{
9cbe330f 3245 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3246 int port;
3247
cfc3ed79 3248 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3249 struct net_device *dev = hw->dev[port];
3250
cfc3ed79 3251 if (netif_running(dev)) {
9cbe330f
SH		 3252 struct skge_port *skge = netdev_priv(dev);
3253
3254 spin_lock(&hw->phy_lock);
baef58b1
SH		 3255 if (hw->chip_id != CHIP_ID_GENESIS)
3256 yukon_phy_intr(skge);
64f6b64d 3257 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3258 bcom_phy_intr(skge);
9cbe330f 3259 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3260 }
3261 }
baef58b1 3262
7c442fa1 3263 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3264 hw->intr_mask |= IS_EXT_REG;
3265 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3266 skge_read32(hw, B0_IMSK);
7c442fa1 3267 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3268}
3269
7d12e780 3270static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3271{
3272 struct skge_hw *hw = dev_id;
cfc3ed79 3273 u32 status;
29365c90 3274 int handled = 0;
baef58b1 3275
29365c90 3276 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3277 /* Reading this register masks IRQ */
3278 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3279 if (status == 0 || status == ~0)
29365c90 3280 goto out;
baef58b1 3281
29365c90 3282 handled = 1;
7c442fa1 3283 status &= hw->intr_mask;
cfc3ed79
SH		 3284 if (status & IS_EXT_REG) {
3285 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3286 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3287 }
3288
513f533e 3289 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3290 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3291 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
bea3348e 3292 netif_rx_schedule(hw->dev[0], &skge->napi);
baef58b1
SH		 3293 }
3294
7c442fa1
SH		 3295 if (status & IS_PA_TO_TX1)
3296 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3297
d25f5a67
SH		 3298 if (status & IS_PA_TO_RX1) {
3299 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3300
d25f5a67 3301 ++skge->net_stats.rx_over_errors;
7c442fa1 3302 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3303 }
3304
d25f5a67 3305
baef58b1
SH		 3306 if (status & IS_MAC1)
3307 skge_mac_intr(hw, 0);
95566065 3308
7c442fa1 3309 if (hw->dev[1]) {
bea3348e
SH		 3310 struct skge_port *skge = netdev_priv(hw->dev[1]);
3311
513f533e
SH		 3312 if (status & (IS_XA2_F|IS_R2_F)) {
3313 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
bea3348e 3314 netif_rx_schedule(hw->dev[1], &skge->napi);
7c442fa1
SH		 3315 }
3316
3317 if (status & IS_PA_TO_RX2) {
7c442fa1
SH		 3318 ++skge->net_stats.rx_over_errors;
3319 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3320 }
3321
3322 if (status & IS_PA_TO_TX2)
3323 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3324
3325 if (status & IS_MAC2)
3326 skge_mac_intr(hw, 1);
3327 }
baef58b1
SH		 3328
3329 if (status & IS_HW_ERR)
3330 skge_error_irq(hw);
3331
7e676d91 3332 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3333 skge_read32(hw, B0_IMSK);
29365c90 3334out:
7c442fa1 3335 spin_unlock(&hw->hw_lock);
baef58b1 3336
29365c90 3337 return IRQ_RETVAL(handled);
baef58b1
SH		 3338}
3339
3340#ifdef CONFIG_NET_POLL_CONTROLLER
3341static void skge_netpoll(struct net_device *dev)
3342{
3343 struct skge_port *skge = netdev_priv(dev);
3344
3345 disable_irq(dev->irq);
7d12e780 3346 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3347 enable_irq(dev->irq);
3348}
3349#endif
3350
3351static int skge_set_mac_address(struct net_device *dev, void *p)
3352{
3353 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3354 struct skge_hw *hw = skge->hw;
3355 unsigned port = skge->port;
3356 const struct sockaddr *addr = p;
2eb3e621 3357 u16 ctrl;
baef58b1
SH		 3358
3359 if (!is_valid_ether_addr(addr->sa_data))
3360 return -EADDRNOTAVAIL;
3361
baef58b1 3362 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3363
9cbe330f
SH		 3364 if (!netif_running(dev)) {
3365 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3366 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3367 } else {
3368 /* disable Rx */
3369 spin_lock_bh(&hw->phy_lock);
3370 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3371 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3372
9cbe330f
SH		 3373 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3374 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3375
2eb3e621
SH		 3376 if (hw->chip_id == CHIP_ID_GENESIS)
3377 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3378 else {
3379 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3380 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3381 }
2eb3e621 3382
9cbe330f
SH		 3383 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3384 spin_unlock_bh(&hw->phy_lock);
3385 }
c2681dd8
SH		 3386
3387 return 0;
baef58b1
SH		 3388}
3389
3390static const struct {
3391 u8 id;
3392 const char *name;
3393} skge_chips[] = {
3394 { CHIP_ID_GENESIS, "Genesis" },
3395 { CHIP_ID_YUKON, "Yukon" },
3396 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3397 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3398};
3399
3400static const char *skge_board_name(const struct skge_hw *hw)
3401{
3402 int i;
3403 static char buf[16];
3404
3405 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3406 if (skge_chips[i].id == hw->chip_id)
3407 return skge_chips[i].name;
3408
3409 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3410 return buf;
3411}
3412
3413
3414/*
3415 * Setup the board data structure, but don't bring up
3416 * the port(s)
3417 */
3418static int skge_reset(struct skge_hw *hw)
3419{
adba9e23 3420 u32 reg;
b9d64acc 3421 u16 ctst, pci_status;
64f6b64d 3422 u8 t8, mac_cfg, pmd_type;
981d0377 3423 int i;
baef58b1
SH		 3424
3425 ctst = skge_read16(hw, B0_CTST);
3426
3427 /* do a SW reset */
3428 skge_write8(hw, B0_CTST, CS_RST_SET);
3429 skge_write8(hw, B0_CTST, CS_RST_CLR);
3430
3431 /* clear PCI errors, if any */
b9d64acc
SH		 3432 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3433 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3434
b9d64acc
SH		 3435 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3436 pci_write_config_word(hw->pdev, PCI_STATUS,
3437 pci_status | PCI_STATUS_ERROR_BITS);
3438 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3439 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3440
3441 /* restore CLK_RUN bits (for Yukon-Lite) */
3442 skge_write16(hw, B0_CTST,
3443 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3444
3445 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3446 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3447 pmd_type = skge_read8(hw, B2_PMD_TYP);
3448 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3449
95566065 3450 switch (hw->chip_id) {
baef58b1 3451 case CHIP_ID_GENESIS:
64f6b64d
SH		 3452 switch (hw->phy_type) {
3453 case SK_PHY_XMAC:
3454 hw->phy_addr = PHY_ADDR_XMAC;
3455 break;
baef58b1
SH		 3456 case SK_PHY_BCOM:
3457 hw->phy_addr = PHY_ADDR_BCOM;
3458 break;
3459 default:
1479d13c
SH		 3460 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3461 hw->phy_type);
baef58b1
SH		 3462 return -EOPNOTSUPP;
3463 }
3464 break;
3465
3466 case CHIP_ID_YUKON:
3467 case CHIP_ID_YUKON_LITE:
3468 case CHIP_ID_YUKON_LP:
64f6b64d 3469 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3470 hw->copper = 1;
baef58b1
SH		 3471
3472 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3473 break;
3474
3475 default:
1479d13c
SH		 3476 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3477 hw->chip_id);
baef58b1
SH		 3478 return -EOPNOTSUPP;
3479 }
3480
981d0377
SH		 3481 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3482 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3483 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3484
3485 /* read the adapters RAM size */
3486 t8 = skge_read8(hw, B2_E_0);
3487 if (hw->chip_id == CHIP_ID_GENESIS) {
3488 if (t8 == 3) {
3489 /* special case: 4 x 64k x 36, offset = 0x80000 */
7fb7ac24
SH		 3490 hw->ram_size = 1024;
3491 hw->ram_offset = 512;
baef58b1
SH		 3492 } else
3493 hw->ram_size = t8 * 512;
7fb7ac24
SH		 3494 } else /* Yukon */
3495 hw->ram_size = t8 ? t8 * 4 : 128;
baef58b1 3496
4ebabfcb 3497 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3498
4ebabfcb 3499 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3500 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3501 hw->intr_mask |= IS_EXT_REG;
3502
baef58b1
SH		 3503 if (hw->chip_id == CHIP_ID_GENESIS)
3504 genesis_init(hw);
3505 else {
3506 /* switch power to VCC (WA for VAUX problem) */
3507 skge_write8(hw, B0_POWER_CTRL,
3508 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3509
050ec18a
SH		 3510 /* avoid boards with stuck Hardware error bits */
3511 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3512 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3513 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3514 hw->intr_mask &= ~IS_HW_ERR;
3515 }
3516
adba9e23
SH		 3517 /* Clear PHY COMA */
3518 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3519 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3520 reg &= ~PCI_PHY_COMA;
3521 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3522 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3523
3524
981d0377 3525 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3526 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3527 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3528 }
3529 }
3530
3531 /* turn off hardware timer (unused) */
3532 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3533 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3534 skge_write8(hw, B0_LED, LED_STAT_ON);
3535
3536 /* enable the Tx Arbiters */
981d0377 3537 for (i = 0; i < hw->ports; i++)
6b0c1480 3538 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3539
3540 /* Initialize ram interface */
3541 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3542
3543 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3544 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3545 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3546 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3547 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3548 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3549 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3550 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3551 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3552 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3553 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3554 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3555
3556 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3557
3558 /* Set interrupt moderation for Transmit only
3559 * Receive interrupts avoided by NAPI
3560 */
3561 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3562 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3563 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3564
baef58b1
SH		 3565 skge_write32(hw, B0_IMSK, hw->intr_mask);
3566
981d0377 3567 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3568 if (hw->chip_id == CHIP_ID_GENESIS)
3569 genesis_reset(hw, i);
3570 else
3571 yukon_reset(hw, i);
3572 }
baef58b1
SH		 3573
3574 return 0;
3575}
3576
3577/* Initialize network device */
981d0377
SH		 3578static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3579 int highmem)
baef58b1
SH		 3580{
3581 struct skge_port *skge;
3582 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3583
3584 if (!dev) {
1479d13c 3585 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3586 return NULL;
3587 }
3588
baef58b1
SH		 3589 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3590 dev->open = skge_up;
3591 dev->stop = skge_down;
2cd8e5d3 3592 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3593 dev->hard_start_xmit = skge_xmit_frame;
3594 dev->get_stats = skge_get_stats;
3595 if (hw->chip_id == CHIP_ID_GENESIS)
3596 dev->set_multicast_list = genesis_set_multicast;
3597 else
3598 dev->set_multicast_list = yukon_set_multicast;
3599
3600 dev->set_mac_address = skge_set_mac_address;
3601 dev->change_mtu = skge_change_mtu;
3602 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3603 dev->tx_timeout = skge_tx_timeout;
3604 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1
SH		 3605#ifdef CONFIG_NET_POLL_CONTROLLER
3606 dev->poll_controller = skge_netpoll;
3607#endif
3608 dev->irq = hw->pdev->irq;
513f533e 3609
981d0377
SH		 3610 if (highmem)
3611 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3612
3613 skge = netdev_priv(dev);
bea3348e 3614 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3615 skge->netdev = dev;
3616 skge->hw = hw;
3617 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3618
baef58b1
SH		 3619 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3620 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3621
3622 /* Auto speed and flow control */
3623 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3624 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3625 skge->duplex = -1;
3626 skge->speed = -1;
31b619c5 3627 skge->advertising = skge_supported_modes(hw);
5b982c5b
SH		 3628
3629 if (pci_wake_enabled(hw->pdev))
3630 skge->wol = wol_supported(hw) & WAKE_MAGIC;
baef58b1
SH		 3631
3632 hw->dev[port] = dev;
3633
3634 skge->port = port;
3635
64f6b64d 3636 /* Only used for Genesis XMAC */
9cbe330f 3637 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3638
baef58b1
SH		 3639 if (hw->chip_id != CHIP_ID_GENESIS) {
3640 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3641 skge->rx_csum = 1;
3642 }
3643
3644 /* read the mac address */
3645 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3646 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3647
3648 /* device is off until link detection */
3649 netif_carrier_off(dev);
3650 netif_stop_queue(dev);
3651
3652 return dev;
3653}
3654
3655static void __devinit skge_show_addr(struct net_device *dev)
3656{
3657 const struct skge_port *skge = netdev_priv(dev);
0795af57 3658 DECLARE_MAC_BUF(mac);
baef58b1
SH		 3659
3660 if (netif_msg_probe(skge))
0795af57
JP		 3661 printk(KERN_INFO PFX "%s: addr %s\n",
3662 dev->name, print_mac(mac, dev->dev_addr));
baef58b1
SH		 3663}
3664
3665static int __devinit skge_probe(struct pci_dev *pdev,
3666 const struct pci_device_id *ent)
3667{
3668 struct net_device *dev, *dev1;
3669 struct skge_hw *hw;
3670 int err, using_dac = 0;
3671
203babb6
SH		 3672 err = pci_enable_device(pdev);
3673 if (err) {
1479d13c 3674 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3675 goto err_out;
3676 }
3677
203babb6
SH		 3678 err = pci_request_regions(pdev, DRV_NAME);
3679 if (err) {
1479d13c 3680 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3681 goto err_out_disable_pdev;
3682 }
3683
3684 pci_set_master(pdev);
3685
93aea718 3686 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3687 using_dac = 1;
77783a78 3688 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3689 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3690 using_dac = 0;
3691 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3692 }
3693
3694 if (err) {
1479d13c 3695 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3696 goto err_out_free_regions;
baef58b1
SH		 3697 }
3698
3699#ifdef __BIG_ENDIAN
8f3f8193 3700 /* byte swap descriptors in hardware */
baef58b1
SH		 3701 {
3702 u32 reg;
3703
3704 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3705 reg |= PCI_REV_DESC;
3706 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3707 }
3708#endif
3709
3710 err = -ENOMEM;
7e863061 3711 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1 3712 if (!hw) {
1479d13c 3713 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3714 goto err_out_free_regions;
3715 }
3716
baef58b1 3717 hw->pdev = pdev;
d38efdd6 3718 spin_lock_init(&hw->hw_lock);
9cbe330f
SH		 3719 spin_lock_init(&hw->phy_lock);
3720 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
baef58b1
SH		 3721
3722 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3723 if (!hw->regs) {
1479d13c 3724 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3725 goto err_out_free_hw;
3726 }
3727
baef58b1
SH		 3728 err = skge_reset(hw);
3729 if (err)
ccdaa2a9 3730 goto err_out_iounmap;
baef58b1 3731
7c7459d1
GKH		 3732 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3733 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3734 skge_board_name(hw), hw->chip_rev);
baef58b1 3735
ccdaa2a9
SH		 3736 dev = skge_devinit(hw, 0, using_dac);
3737 if (!dev)
baef58b1
SH		 3738 goto err_out_led_off;
3739
fae87592 3740 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3741 if (!is_valid_ether_addr(dev->dev_addr))
3742 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3743
203babb6
SH		 3744 err = register_netdev(dev);
3745 if (err) {
1479d13c 3746 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3747 goto err_out_free_netdev;
3748 }
3749
ccdaa2a9
SH		 3750 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3751 if (err) {
1479d13c 3752 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3753 dev->name, pdev->irq);
3754 goto err_out_unregister;
3755 }
baef58b1
SH		 3756 skge_show_addr(dev);
3757
981d0377 3758 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3759 if (register_netdev(dev1) == 0)
3760 skge_show_addr(dev1);
3761 else {
3762 /* Failure to register second port need not be fatal */
1479d13c 3763 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1
SH		 3764 hw->dev[1] = NULL;
3765 free_netdev(dev1);
3766 }
3767 }
ccdaa2a9 3768 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3769
3770 return 0;
3771
ccdaa2a9
SH		 3772err_out_unregister:
3773 unregister_netdev(dev);
baef58b1
SH		 3774err_out_free_netdev:
3775 free_netdev(dev);
3776err_out_led_off:
3777 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3778err_out_iounmap:
3779 iounmap(hw->regs);
3780err_out_free_hw:
3781 kfree(hw);
3782err_out_free_regions:
3783 pci_release_regions(pdev);
3784err_out_disable_pdev:
3785 pci_disable_device(pdev);
3786 pci_set_drvdata(pdev, NULL);
3787err_out:
3788 return err;
3789}
3790
3791static void __devexit skge_remove(struct pci_dev *pdev)
3792{
3793 struct skge_hw *hw = pci_get_drvdata(pdev);
3794 struct net_device *dev0, *dev1;
3795
95566065 3796 if (!hw)
baef58b1
SH		 3797 return;
3798
208491d8
SH		 3799 flush_scheduled_work();
3800
baef58b1
SH		 3801 if ((dev1 = hw->dev[1]))
3802 unregister_netdev(dev1);
3803 dev0 = hw->dev[0];
3804 unregister_netdev(dev0);
3805
9cbe330f
SH		 3806 tasklet_disable(&hw->phy_task);
3807
7c442fa1
SH		 3808 spin_lock_irq(&hw->hw_lock);
3809 hw->intr_mask = 0;
46a60f2d 3810 skge_write32(hw, B0_IMSK, 0);
78bc2186 3811 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3812 spin_unlock_irq(&hw->hw_lock);
3813
46a60f2d 3814 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3815 skge_write8(hw, B0_CTST, CS_RST_SET);
3816
baef58b1
SH		 3817 free_irq(pdev->irq, hw);
3818 pci_release_regions(pdev);
3819 pci_disable_device(pdev);
3820 if (dev1)
3821 free_netdev(dev1);
3822 free_netdev(dev0);
46a60f2d 3823
baef58b1
SH		 3824 iounmap(hw->regs);
3825 kfree(hw);
3826 pci_set_drvdata(pdev, NULL);
3827}
3828
3829#ifdef CONFIG_PM
2a569579 3830static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3831{
3832 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 3833 int i, err, wol = 0;
3834
e3b7df17
SH		 3835 if (!hw)
3836 return 0;
3837
a504e64a
SH		 3838 err = pci_save_state(pdev);
3839 if (err)
3840 return err;
baef58b1 3841
d38efdd6 3842 for (i = 0; i < hw->ports; i++) {
baef58b1 3843 struct net_device *dev = hw->dev[i];
a504e64a 3844 struct skge_port *skge = netdev_priv(dev);
baef58b1 3845
a504e64a
SH		 3846 if (netif_running(dev))
3847 skge_down(dev);
3848 if (skge->wol)
3849 skge_wol_init(skge);
d38efdd6 3850
a504e64a 3851 wol |= skge->wol;
baef58b1
SH		 3852 }
3853
d38efdd6 3854 skge_write32(hw, B0_IMSK, 0);
2a569579 3855 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3856 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3857
3858 return 0;
3859}
3860
3861static int skge_resume(struct pci_dev *pdev)
3862{
3863 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3864 int i, err;
baef58b1 3865
e3b7df17
SH		 3866 if (!hw)
3867 return 0;
3868
a504e64a
SH		 3869 err = pci_set_power_state(pdev, PCI_D0);
3870 if (err)
3871 goto out;
3872
3873 err = pci_restore_state(pdev);
3874 if (err)
3875 goto out;
3876
baef58b1
SH		 3877 pci_enable_wake(pdev, PCI_D0, 0);
3878
d38efdd6
SH		 3879 err = skge_reset(hw);
3880 if (err)
3881 goto out;
baef58b1 3882
d38efdd6 3883 for (i = 0; i < hw->ports; i++) {
baef58b1 3884 struct net_device *dev = hw->dev[i];
d38efdd6 3885
d38efdd6
SH		 3886 if (netif_running(dev)) {
3887 err = skge_up(dev);
3888
3889 if (err) {
3890 printk(KERN_ERR PFX "%s: could not up: %d\n",
3891 dev->name, err);
edd702e8 3892 dev_close(dev);
d38efdd6
SH		 3893 goto out;
3894 }
baef58b1
SH		 3895 }
3896 }
d38efdd6
SH		 3897out:
3898 return err;
baef58b1
SH		 3899}
3900#endif
3901
692412b3
SH		 3902static void skge_shutdown(struct pci_dev *pdev)
3903{
3904 struct skge_hw *hw = pci_get_drvdata(pdev);
3905 int i, wol = 0;
3906
e3b7df17
SH		 3907 if (!hw)
3908 return;
3909
692412b3
SH		 3910 for (i = 0; i < hw->ports; i++) {
3911 struct net_device *dev = hw->dev[i];
3912 struct skge_port *skge = netdev_priv(dev);
3913
3914 if (skge->wol)
3915 skge_wol_init(skge);
3916 wol |= skge->wol;
3917 }
3918
3919 pci_enable_wake(pdev, PCI_D3hot, wol);
3920 pci_enable_wake(pdev, PCI_D3cold, wol);
3921
3922 pci_disable_device(pdev);
3923 pci_set_power_state(pdev, PCI_D3hot);
3924
3925}
3926
baef58b1
SH		 3927static struct pci_driver skge_driver = {
3928 .name = DRV_NAME,
3929 .id_table = skge_id_table,
3930 .probe = skge_probe,
3931 .remove = __devexit_p(skge_remove),
3932#ifdef CONFIG_PM
3933 .suspend = skge_suspend,
3934 .resume = skge_resume,
3935#endif
692412b3 3936 .shutdown = skge_shutdown,
baef58b1
SH		 3937};
3938
3939static int __init skge_init_module(void)
3940{
29917620 3941 return pci_register_driver(&skge_driver);
baef58b1
SH		 3942}
3943
3944static void __exit skge_cleanup_module(void)
3945{
3946 pci_unregister_driver(&skge_driver);
3947}
3948
3949module_init(skge_init_module);
3950module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)