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[PATCH] skge: make Genesis/Broadcom code work
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6"
46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
52#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4)
baef58b1
SH		 57
58MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
59MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(DRV_VERSION);
62
63static const u32 default_msg
64 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
65 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
66
67static int debug = -1; /* defaults above */
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 72 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
74 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
75 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
77 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
78 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
80 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
81 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 83 { 0 }
84};
85MODULE_DEVICE_TABLE(pci, skge_id_table);
86
87static int skge_up(struct net_device *dev);
88static int skge_down(struct net_device *dev);
89static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 90static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
91static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 92static void genesis_get_stats(struct skge_port *skge, u64 *data);
93static void yukon_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_init(struct skge_hw *hw, int port);
95static void yukon_reset(struct skge_hw *hw, int port);
96static void genesis_mac_init(struct skge_hw *hw, int port);
97static void genesis_reset(struct skge_hw *hw, int port);
45bada65 98static void genesis_link_up(struct skge_port *skge);
baef58b1
SH		 99
100static const int txqaddr[] = { Q_XA1, Q_XA2 };
101static const int rxqaddr[] = { Q_R1, Q_R2 };
102static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
103static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
104
105/* Don't need to look at whole 16K.
106 * last interesting register is descriptor poll timer.
107 */
108#define SKGE_REGS_LEN (29*128)
109
110static int skge_get_regs_len(struct net_device *dev)
111{
112 return SKGE_REGS_LEN;
113}
114
115/*
116 * Returns copy of control register region
117 * I/O region is divided into banks and certain regions are unreadable
118 */
119static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121{
122 const struct skge_port *skge = netdev_priv(dev);
123 unsigned long offs;
124 const void __iomem *io = skge->hw->regs;
125 static const unsigned long bankmap
126 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
127 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
128 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
129 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
130
131 regs->version = 1;
132 for (offs = 0; offs < regs->len; offs += 128) {
133 u32 len = min_t(u32, 128, regs->len - offs);
134
135 if (bankmap & (1<<(offs/128)))
136 memcpy_fromio(p + offs, io + offs, len);
137 else
138 memset(p + offs, 0, len);
139 }
140}
141
142/* Wake on Lan only supported on Yukon chps with rev 1 or above */
143static int wol_supported(const struct skge_hw *hw)
144{
145 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 146 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 147}
148
149static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152
153 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
154 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
155}
156
157static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
158{
159 struct skge_port *skge = netdev_priv(dev);
160 struct skge_hw *hw = skge->hw;
161
95566065 162 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 163 return -EOPNOTSUPP;
164
165 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
166 return -EOPNOTSUPP;
167
168 skge->wol = wol->wolopts == WAKE_MAGIC;
169
170 if (skge->wol) {
171 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
172
173 skge_write16(hw, WOL_CTRL_STAT,
174 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
175 WOL_CTL_ENA_MAGIC_PKT_UNIT);
176 } else
177 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
178
179 return 0;
180}
181
31b619c5
SH		 182/* Determine supported/adverised modes based on hardware.
183 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
184 */
185static u32 skge_supported_modes(const struct skge_hw *hw)
186{
187 u32 supported;
188
189 if (iscopper(hw)) {
190 supported = SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full
194 | SUPPORTED_1000baseT_Half
195 | SUPPORTED_1000baseT_Full
196 | SUPPORTED_Autoneg| SUPPORTED_TP;
197
198 if (hw->chip_id == CHIP_ID_GENESIS)
199 supported &= ~(SUPPORTED_10baseT_Half
200 | SUPPORTED_10baseT_Full
201 | SUPPORTED_100baseT_Half
202 | SUPPORTED_100baseT_Full);
203
204 else if (hw->chip_id == CHIP_ID_YUKON)
205 supported &= ~SUPPORTED_1000baseT_Half;
206 } else
207 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
208 | SUPPORTED_Autoneg;
209
210 return supported;
211}
baef58b1
SH		 212
213static int skge_get_settings(struct net_device *dev,
214 struct ethtool_cmd *ecmd)
215{
216 struct skge_port *skge = netdev_priv(dev);
217 struct skge_hw *hw = skge->hw;
218
219 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 220 ecmd->supported = skge_supported_modes(hw);
baef58b1
SH		 221
222 if (iscopper(hw)) {
baef58b1
SH		 223 ecmd->port = PORT_TP;
224 ecmd->phy_address = hw->phy_addr;
31b619c5 225 } else
baef58b1 226 ecmd->port = PORT_FIBRE;
baef58b1
SH		 227
228 ecmd->advertising = skge->advertising;
229 ecmd->autoneg = skge->autoneg;
230 ecmd->speed = skge->speed;
231 ecmd->duplex = skge->duplex;
232 return 0;
233}
234
baef58b1
SH		 235static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
236{
237 struct skge_port *skge = netdev_priv(dev);
238 const struct skge_hw *hw = skge->hw;
31b619c5 239 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 240
241 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 242 ecmd->advertising = supported;
243 skge->duplex = -1;
244 skge->speed = -1;
baef58b1 245 } else {
31b619c5
SH		 246 u32 setting;
247
248 switch(ecmd->speed) {
baef58b1 249 case SPEED_1000:
31b619c5
SH		 250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_1000baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_1000baseT_Half;
254 else
255 return -EINVAL;
baef58b1
SH		 256 break;
257 case SPEED_100:
31b619c5
SH		 258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_100baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_100baseT_Half;
262 else
263 return -EINVAL;
264 break;
265
baef58b1 266 case SPEED_10:
31b619c5
SH		 267 if (ecmd->duplex == DUPLEX_FULL)
268 setting = SUPPORTED_10baseT_Full;
269 else if (ecmd->duplex == DUPLEX_HALF)
270 setting = SUPPORTED_10baseT_Half;
271 else
baef58b1
SH		 272 return -EINVAL;
273 break;
274 default:
275 return -EINVAL;
276 }
31b619c5
SH		 277
278 if ((setting & supported) == 0)
279 return -EINVAL;
280
281 skge->speed = ecmd->speed;
282 skge->duplex = ecmd->duplex;
baef58b1
SH		 283 }
284
285 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 286 skge->advertising = ecmd->advertising;
287
288 if (netif_running(dev)) {
289 skge_down(dev);
290 skge_up(dev);
291 }
292 return (0);
293}
294
295static void skge_get_drvinfo(struct net_device *dev,
296 struct ethtool_drvinfo *info)
297{
298 struct skge_port *skge = netdev_priv(dev);
299
300 strcpy(info->driver, DRV_NAME);
301 strcpy(info->version, DRV_VERSION);
302 strcpy(info->fw_version, "N/A");
303 strcpy(info->bus_info, pci_name(skge->hw->pdev));
304}
305
306static const struct skge_stat {
307 char name[ETH_GSTRING_LEN];
308 u16 xmac_offset;
309 u16 gma_offset;
310} skge_stats[] = {
311 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
312 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
313
314 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
315 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
316 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
317 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
318 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
319 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
320 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
321 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
322
323 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
324 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
325 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
326 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
327 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
328 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
329
330 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
331 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
332 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
333 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
335};
336
337static int skge_get_stats_count(struct net_device *dev)
338{
339 return ARRAY_SIZE(skge_stats);
340}
341
342static void skge_get_ethtool_stats(struct net_device *dev,
343 struct ethtool_stats *stats, u64 *data)
344{
345 struct skge_port *skge = netdev_priv(dev);
346
347 if (skge->hw->chip_id == CHIP_ID_GENESIS)
348 genesis_get_stats(skge, data);
349 else
350 yukon_get_stats(skge, data);
351}
352
353/* Use hardware MIB variables for critical path statistics and
354 * transmit feedback not reported at interrupt.
355 * Other errors are accounted for in interrupt handler.
356 */
357static struct net_device_stats *skge_get_stats(struct net_device *dev)
358{
359 struct skge_port *skge = netdev_priv(dev);
360 u64 data[ARRAY_SIZE(skge_stats)];
361
362 if (skge->hw->chip_id == CHIP_ID_GENESIS)
363 genesis_get_stats(skge, data);
364 else
365 yukon_get_stats(skge, data);
366
367 skge->net_stats.tx_bytes = data[0];
368 skge->net_stats.rx_bytes = data[1];
369 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
370 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
371 skge->net_stats.multicast = data[5] + data[7];
372 skge->net_stats.collisions = data[10];
373 skge->net_stats.tx_aborted_errors = data[12];
374
375 return &skge->net_stats;
376}
377
378static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
379{
380 int i;
381
95566065 382 switch (stringset) {
baef58b1
SH		 383 case ETH_SS_STATS:
384 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
385 memcpy(data + i * ETH_GSTRING_LEN,
386 skge_stats[i].name, ETH_GSTRING_LEN);
387 break;
388 }
389}
390
391static void skge_get_ring_param(struct net_device *dev,
392 struct ethtool_ringparam *p)
393{
394 struct skge_port *skge = netdev_priv(dev);
395
396 p->rx_max_pending = MAX_RX_RING_SIZE;
397 p->tx_max_pending = MAX_TX_RING_SIZE;
398 p->rx_mini_max_pending = 0;
399 p->rx_jumbo_max_pending = 0;
400
401 p->rx_pending = skge->rx_ring.count;
402 p->tx_pending = skge->tx_ring.count;
403 p->rx_mini_pending = 0;
404 p->rx_jumbo_pending = 0;
405}
406
407static int skge_set_ring_param(struct net_device *dev,
408 struct ethtool_ringparam *p)
409{
410 struct skge_port *skge = netdev_priv(dev);
411
412 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
413 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
414 return -EINVAL;
415
416 skge->rx_ring.count = p->rx_pending;
417 skge->tx_ring.count = p->tx_pending;
418
419 if (netif_running(dev)) {
420 skge_down(dev);
421 skge_up(dev);
422 }
423
424 return 0;
425}
426
427static u32 skge_get_msglevel(struct net_device *netdev)
428{
429 struct skge_port *skge = netdev_priv(netdev);
430 return skge->msg_enable;
431}
432
433static void skge_set_msglevel(struct net_device *netdev, u32 value)
434{
435 struct skge_port *skge = netdev_priv(netdev);
436 skge->msg_enable = value;
437}
438
439static int skge_nway_reset(struct net_device *dev)
440{
441 struct skge_port *skge = netdev_priv(dev);
442 struct skge_hw *hw = skge->hw;
443 int port = skge->port;
444
445 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
446 return -EINVAL;
447
448 spin_lock_bh(&hw->phy_lock);
449 if (hw->chip_id == CHIP_ID_GENESIS) {
450 genesis_reset(hw, port);
451 genesis_mac_init(hw, port);
452 } else {
453 yukon_reset(hw, port);
454 yukon_init(hw, port);
455 }
456 spin_unlock_bh(&hw->phy_lock);
457 return 0;
458}
459
460static int skge_set_sg(struct net_device *dev, u32 data)
461{
462 struct skge_port *skge = netdev_priv(dev);
463 struct skge_hw *hw = skge->hw;
464
465 if (hw->chip_id == CHIP_ID_GENESIS && data)
466 return -EOPNOTSUPP;
467 return ethtool_op_set_sg(dev, data);
468}
469
470static int skge_set_tx_csum(struct net_device *dev, u32 data)
471{
472 struct skge_port *skge = netdev_priv(dev);
473 struct skge_hw *hw = skge->hw;
474
475 if (hw->chip_id == CHIP_ID_GENESIS && data)
476 return -EOPNOTSUPP;
477
478 return ethtool_op_set_tx_csum(dev, data);
479}
480
481static u32 skge_get_rx_csum(struct net_device *dev)
482{
483 struct skge_port *skge = netdev_priv(dev);
484
485 return skge->rx_csum;
486}
487
488/* Only Yukon supports checksum offload. */
489static int skge_set_rx_csum(struct net_device *dev, u32 data)
490{
491 struct skge_port *skge = netdev_priv(dev);
492
493 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
494 return -EOPNOTSUPP;
495
496 skge->rx_csum = data;
497 return 0;
498}
499
baef58b1
SH		 500static void skge_get_pauseparam(struct net_device *dev,
501 struct ethtool_pauseparam *ecmd)
502{
503 struct skge_port *skge = netdev_priv(dev);
504
505 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
506 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
507 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
508 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
509
510 ecmd->autoneg = skge->autoneg;
511}
512
513static int skge_set_pauseparam(struct net_device *dev,
514 struct ethtool_pauseparam *ecmd)
515{
516 struct skge_port *skge = netdev_priv(dev);
517
518 skge->autoneg = ecmd->autoneg;
519 if (ecmd->rx_pause && ecmd->tx_pause)
520 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 521 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 522 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 523 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 524 skge->flow_control = FLOW_MODE_LOC_SEND;
525 else
526 skge->flow_control = FLOW_MODE_NONE;
527
528 if (netif_running(dev)) {
529 skge_down(dev);
530 skge_up(dev);
531 }
532 return 0;
533}
534
535/* Chip internal frequency for clock calculations */
536static inline u32 hwkhz(const struct skge_hw *hw)
537{
538 if (hw->chip_id == CHIP_ID_GENESIS)
539 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 540 else
541 return 78215; /* or: 78.125 MHz */
542}
543
544/* Chip hz to microseconds */
545static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
546{
547 return (ticks * 1000) / hwkhz(hw);
548}
549
550/* Microseconds to chip hz */
551static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
552{
553 return hwkhz(hw) * usec / 1000;
554}
555
556static int skge_get_coalesce(struct net_device *dev,
557 struct ethtool_coalesce *ecmd)
558{
559 struct skge_port *skge = netdev_priv(dev);
560 struct skge_hw *hw = skge->hw;
561 int port = skge->port;
562
563 ecmd->rx_coalesce_usecs = 0;
564 ecmd->tx_coalesce_usecs = 0;
565
566 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
567 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
568 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569
570 if (msk & rxirqmask[port])
571 ecmd->rx_coalesce_usecs = delay;
572 if (msk & txirqmask[port])
573 ecmd->tx_coalesce_usecs = delay;
574 }
575
576 return 0;
577}
578
579/* Note: interrupt timer is per board, but can turn on/off per port */
580static int skge_set_coalesce(struct net_device *dev,
581 struct ethtool_coalesce *ecmd)
582{
583 struct skge_port *skge = netdev_priv(dev);
584 struct skge_hw *hw = skge->hw;
585 int port = skge->port;
586 u32 msk = skge_read32(hw, B2_IRQM_MSK);
587 u32 delay = 25;
588
589 if (ecmd->rx_coalesce_usecs == 0)
590 msk &= ~rxirqmask[port];
591 else if (ecmd->rx_coalesce_usecs < 25 ||
592 ecmd->rx_coalesce_usecs > 33333)
593 return -EINVAL;
594 else {
595 msk |= rxirqmask[port];
596 delay = ecmd->rx_coalesce_usecs;
597 }
598
599 if (ecmd->tx_coalesce_usecs == 0)
600 msk &= ~txirqmask[port];
601 else if (ecmd->tx_coalesce_usecs < 25 ||
602 ecmd->tx_coalesce_usecs > 33333)
603 return -EINVAL;
604 else {
605 msk |= txirqmask[port];
606 delay = min(delay, ecmd->rx_coalesce_usecs);
607 }
608
609 skge_write32(hw, B2_IRQM_MSK, msk);
610 if (msk == 0)
611 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
612 else {
613 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
614 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
615 }
616 return 0;
617}
618
619static void skge_led_on(struct skge_hw *hw, int port)
620{
621 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 623 skge_write8(hw, B0_LED, LED_STAT_ON);
624
6b0c1480
SH		 625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 628
89bf5f23
SH		 629 /* For Broadcom Phy only */
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
baef58b1 631 } else {
6b0c1480
SH		 632 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
633 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 634 PHY_M_LED_MO_DUP(MO_LED_ON) |
635 PHY_M_LED_MO_10(MO_LED_ON) |
636 PHY_M_LED_MO_100(MO_LED_ON) |
637 PHY_M_LED_MO_1000(MO_LED_ON) |
638 PHY_M_LED_MO_RX(MO_LED_ON));
639 }
640}
641
642static void skge_led_off(struct skge_hw *hw, int port)
643{
644 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 645 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 646 skge_write8(hw, B0_LED, LED_STAT_OFF);
647
6b0c1480
SH		 648 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
649 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1 650
89bf5f23
SH		 651 /* Broadcom only */
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
baef58b1 653 } else {
6b0c1480
SH		 654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
655 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 656 PHY_M_LED_MO_DUP(MO_LED_OFF) |
657 PHY_M_LED_MO_10(MO_LED_OFF) |
658 PHY_M_LED_MO_100(MO_LED_OFF) |
659 PHY_M_LED_MO_1000(MO_LED_OFF) |
660 PHY_M_LED_MO_RX(MO_LED_OFF));
661 }
662}
663
664static void skge_blink_timer(unsigned long data)
665{
666 struct skge_port *skge = (struct skge_port *) data;
667 struct skge_hw *hw = skge->hw;
668 unsigned long flags;
669
670 spin_lock_irqsave(&hw->phy_lock, flags);
671 if (skge->blink_on)
672 skge_led_on(hw, skge->port);
673 else
674 skge_led_off(hw, skge->port);
675 spin_unlock_irqrestore(&hw->phy_lock, flags);
676
677 skge->blink_on = !skge->blink_on;
678 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
679}
680
681/* blink LED's for finding board */
682static int skge_phys_id(struct net_device *dev, u32 data)
683{
684 struct skge_port *skge = netdev_priv(dev);
685
95566065 686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 687 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
688
689 /* start blinking */
690 skge->blink_on = 1;
691 mod_timer(&skge->led_blink, jiffies+1);
692
693 msleep_interruptible(data * 1000);
694 del_timer_sync(&skge->led_blink);
695
696 skge_led_off(skge->hw, skge->port);
697
698 return 0;
699}
700
701static struct ethtool_ops skge_ethtool_ops = {
702 .get_settings = skge_get_settings,
703 .set_settings = skge_set_settings,
704 .get_drvinfo = skge_get_drvinfo,
705 .get_regs_len = skge_get_regs_len,
706 .get_regs = skge_get_regs,
707 .get_wol = skge_get_wol,
708 .set_wol = skge_set_wol,
709 .get_msglevel = skge_get_msglevel,
710 .set_msglevel = skge_set_msglevel,
711 .nway_reset = skge_nway_reset,
712 .get_link = ethtool_op_get_link,
713 .get_ringparam = skge_get_ring_param,
714 .set_ringparam = skge_set_ring_param,
715 .get_pauseparam = skge_get_pauseparam,
716 .set_pauseparam = skge_set_pauseparam,
717 .get_coalesce = skge_get_coalesce,
718 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 719 .get_sg = ethtool_op_get_sg,
720 .set_sg = skge_set_sg,
721 .get_tx_csum = ethtool_op_get_tx_csum,
722 .set_tx_csum = skge_set_tx_csum,
723 .get_rx_csum = skge_get_rx_csum,
724 .set_rx_csum = skge_set_rx_csum,
725 .get_strings = skge_get_strings,
726 .phys_id = skge_phys_id,
727 .get_stats_count = skge_get_stats_count,
728 .get_ethtool_stats = skge_get_ethtool_stats,
729};
730
731/*
732 * Allocate ring elements and chain them together
733 * One-to-one association of board descriptors with ring elements
734 */
735static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
736{
737 struct skge_tx_desc *d;
738 struct skge_element *e;
739 int i;
740
741 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
742 if (!ring->start)
743 return -ENOMEM;
744
745 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
746 e->desc = d;
747 if (i == ring->count - 1) {
748 e->next = ring->start;
749 d->next_offset = base;
750 } else {
751 e->next = e + 1;
752 d->next_offset = base + (i+1) * sizeof(*d);
753 }
754 }
755 ring->to_use = ring->to_clean = ring->start;
756
757 return 0;
758}
759
760/* Setup buffer for receiving */
761static inline int skge_rx_alloc(struct skge_port *skge,
762 struct skge_element *e)
763{
764 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
765 struct skge_rx_desc *rd = e->desc;
766 struct sk_buff *skb;
767 u64 map;
768
769 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
770 if (unlikely(!skb)) {
771 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
772 skge->netdev->name);
773 return -ENOMEM;
774 }
775
776 skb->dev = skge->netdev;
777 skb_reserve(skb, NET_IP_ALIGN);
778
779 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
780 PCI_DMA_FROMDEVICE);
781
782 rd->dma_lo = map;
783 rd->dma_hi = map >> 32;
784 e->skb = skb;
785 rd->csum1_start = ETH_HLEN;
786 rd->csum2_start = ETH_HLEN;
787 rd->csum1 = 0;
788 rd->csum2 = 0;
789
790 wmb();
791
792 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
793 pci_unmap_addr_set(e, mapaddr, map);
794 pci_unmap_len_set(e, maplen, bufsize);
795 return 0;
796}
797
798/* Free all unused buffers in receive ring, assumes receiver stopped */
799static void skge_rx_clean(struct skge_port *skge)
800{
801 struct skge_hw *hw = skge->hw;
802 struct skge_ring *ring = &skge->rx_ring;
803 struct skge_element *e;
804
805 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
806 struct skge_rx_desc *rd = e->desc;
807 rd->control = 0;
808
809 pci_unmap_single(hw->pdev,
810 pci_unmap_addr(e, mapaddr),
811 pci_unmap_len(e, maplen),
812 PCI_DMA_FROMDEVICE);
813 dev_kfree_skb(e->skb);
814 e->skb = NULL;
815 }
816 ring->to_clean = e;
817}
818
819/* Allocate buffers for receive ring
820 * For receive: to_use is refill location
821 * to_clean is next received frame.
822 *
823 * if (to_use == to_clean)
824 * then ring all frames in ring need buffers
825 * if (to_use->next == to_clean)
826 * then ring all frames in ring have buffers
827 */
828static int skge_rx_fill(struct skge_port *skge)
829{
830 struct skge_ring *ring = &skge->rx_ring;
831 struct skge_element *e;
832 int ret = 0;
833
834 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
835 if (skge_rx_alloc(skge, e)) {
836 ret = 1;
837 break;
838 }
839
840 }
841 ring->to_use = e;
842
843 return ret;
844}
845
846static void skge_link_up(struct skge_port *skge)
847{
848 netif_carrier_on(skge->netdev);
849 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
850 netif_wake_queue(skge->netdev);
851
852 if (netif_msg_link(skge))
853 printk(KERN_INFO PFX
854 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
855 skge->netdev->name, skge->speed,
856 skge->duplex == DUPLEX_FULL ? "full" : "half",
857 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
858 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
859 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
860 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
861 "unknown");
862}
863
864static void skge_link_down(struct skge_port *skge)
865{
866 netif_carrier_off(skge->netdev);
867 netif_stop_queue(skge->netdev);
868
869 if (netif_msg_link(skge))
870 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
871}
872
6b0c1480 873static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 874{
875 int i;
876 u16 v;
877
6b0c1480
SH		 878 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
879 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 880
89bf5f23
SH		 881 /* Need to wait for external PHY */
882 for (i = 0; i < PHY_RETRIES; i++) {
883 udelay(1);
884 if (xm_read16(hw, port, XM_MMU_CMD)
885 & XM_MMU_PHY_RDY)
886 goto ready;
baef58b1
SH		 887 }
888
89bf5f23
SH		 889 printk(KERN_WARNING PFX "%s: phy read timed out\n",
890 hw->dev[port]->name);
891 return 0;
892 ready:
893 v = xm_read16(hw, port, XM_PHY_DATA);
894
baef58b1
SH		 895 return v;
896}
897
6b0c1480 898static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 899{
900 int i;
901
6b0c1480 902 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 903 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 904 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 905 goto ready;
89bf5f23 906 udelay(1);
baef58b1
SH		 907 }
908 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
909 hw->dev[port]->name);
910
911
912 ready:
6b0c1480 913 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 914 for (i = 0; i < PHY_RETRIES; i++) {
915 udelay(1);
6b0c1480 916 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 917 return;
918 }
919 printk(KERN_WARNING PFX "%s: phy write timed out\n",
920 hw->dev[port]->name);
921}
922
923static void genesis_init(struct skge_hw *hw)
924{
925 /* set blink source counter */
926 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
927 skge_write8(hw, B2_BSC_CTRL, BSC_START);
928
929 /* configure mac arbiter */
930 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
931
932 /* configure mac arbiter timeout values */
933 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
934 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
937
938 skge_write8(hw, B3_MA_RCINI_RX1, 0);
939 skge_write8(hw, B3_MA_RCINI_RX2, 0);
940 skge_write8(hw, B3_MA_RCINI_TX1, 0);
941 skge_write8(hw, B3_MA_RCINI_TX2, 0);
942
943 /* configure packet arbiter timeout */
944 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
945 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
946 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
949}
950
951static void genesis_reset(struct skge_hw *hw, int port)
952{
45bada65 953 const u8 zero[8] = { 0 };
baef58b1
SH		 954
955 /* reset the statistics module */
6b0c1480
SH		 956 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
957 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
958 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
959 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
960 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 961
89bf5f23
SH		 962 /* disable Broadcom PHY IRQ */
963 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 964
45bada65 965 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 966}
967
968
45bada65
SH		 969/* Convert mode to MII values */
970static const u16 phy_pause_map[] = {
971 [FLOW_MODE_NONE] = 0,
972 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
973 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
974 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
975};
976
977
978/* Check status of Broadcom phy link */
979static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 980{
45bada65
SH		 981 struct net_device *dev = hw->dev[port];
982 struct skge_port *skge = netdev_priv(dev);
983 u16 status;
984
985 /* read twice because of latch */
986 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
987 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
988
989 pr_debug("bcom_check_link status=0x%x\n", status);
990
991 if ((status & PHY_ST_LSYNC) == 0) {
992 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
993 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
994 xm_write16(hw, port, XM_MMU_CMD, cmd);
995 /* dummy read to ensure writing */
996 (void) xm_read16(hw, port, XM_MMU_CMD);
997
998 if (netif_carrier_ok(dev))
999 skge_link_down(skge);
1000 } else {
1001 if (skge->autoneg == AUTONEG_ENABLE &&
1002 (status & PHY_ST_AN_OVER)) {
1003 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1004 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1005
1006 if (lpa & PHY_B_AN_RF) {
1007 printk(KERN_NOTICE PFX "%s: remote fault\n",
1008 dev->name);
1009 return;
1010 }
1011
1012 /* Check Duplex mismatch */
1013 switch(aux & PHY_B_AS_AN_RES_MSK) {
1014 case PHY_B_RES_1000FD:
1015 skge->duplex = DUPLEX_FULL;
1016 break;
1017 case PHY_B_RES_1000HD:
1018 skge->duplex = DUPLEX_HALF;
1019 break;
1020 default:
1021 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1022 dev->name);
1023 return;
1024 }
1025
1026
1027 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1028 switch (aux & PHY_B_AS_PAUSE_MSK) {
1029 case PHY_B_AS_PAUSE_MSK:
1030 skge->flow_control = FLOW_MODE_SYMMETRIC;
1031 break;
1032 case PHY_B_AS_PRR:
1033 skge->flow_control = FLOW_MODE_REM_SEND;
1034 break;
1035 case PHY_B_AS_PRT:
1036 skge->flow_control = FLOW_MODE_LOC_SEND;
1037 break;
1038 default:
1039 skge->flow_control = FLOW_MODE_NONE;
1040 }
1041
1042 skge->speed = SPEED_1000;
1043 }
1044
1045 if (!netif_carrier_ok(dev))
1046 genesis_link_up(skge);
1047 }
1048}
1049
1050/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1051 * Phy on for 100 or 10Mbit operation
1052 */
1053static void bcom_phy_init(struct skge_port *skge, int jumbo)
1054{
1055 struct skge_hw *hw = skge->hw;
1056 int port = skge->port;
baef58b1 1057 int i;
45bada65 1058 u16 id1, r, ext, ctl;
baef58b1
SH		 1059
1060 /* magic workaround patterns for Broadcom */
1061 static const struct {
1062 u16 reg;
1063 u16 val;
1064 } A1hack[] = {
1065 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1066 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1067 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1068 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1069 }, C0hack[] = {
1070 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1071 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1072 };
1073
45bada65
SH		 1074 pr_debug("bcom_phy_init\n");
1075
1076 /* read Id from external PHY (all have the same address) */
1077 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1078
1079 /* Optimize MDIO transfer by suppressing preamble. */
1080 r = xm_read16(hw, port, XM_MMU_CMD);
1081 r |= XM_MMU_NO_PRE;
1082 xm_write16(hw, port, XM_MMU_CMD,r);
1083
1084 switch(id1) {
1085 case PHY_BCOM_ID1_C0:
1086 /*
1087 * Workaround BCOM Errata for the C0 type.
1088 * Write magic patterns to reserved registers.
1089 */
1090 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1091 xm_phy_write(hw, port,
1092 C0hack[i].reg, C0hack[i].val);
1093
1094 break;
1095 case PHY_BCOM_ID1_A1:
1096 /*
1097 * Workaround BCOM Errata for the A1 type.
1098 * Write magic patterns to reserved registers.
1099 */
1100 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1101 xm_phy_write(hw, port,
1102 A1hack[i].reg, A1hack[i].val);
1103 break;
1104 }
1105
1106 /*
1107 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1108 * Disable Power Management after reset.
1109 */
1110 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1111 r |= PHY_B_AC_DIS_PM;
1112 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1113
1114 /* Dummy read */
1115 xm_read16(hw, port, XM_ISRC);
1116
1117 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1118 ctl = PHY_CT_SP1000; /* always 1000mbit */
1119
1120 if (skge->autoneg == AUTONEG_ENABLE) {
1121 /*
1122 * Workaround BCOM Errata #1 for the C5 type.
1123 * 1000Base-T Link Acquisition Failure in Slave Mode
1124 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1125 */
1126 u16 adv = PHY_B_1000C_RD;
1127 if (skge->advertising & ADVERTISED_1000baseT_Half)
1128 adv |= PHY_B_1000C_AHD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Full)
1130 adv |= PHY_B_1000C_AFD;
1131 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1132
1133 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1134 } else {
1135 if (skge->duplex == DUPLEX_FULL)
1136 ctl |= PHY_CT_DUP_MD;
1137 /* Force to slave */
1138 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1139 }
1140
1141 /* Set autonegotiation pause parameters */
1142 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1143 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1144
1145 /* Handle Jumbo frames */
1146 if (jumbo) {
1147 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1148 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1149
1150 ext |= PHY_B_PEC_HIGH_LA;
1151
1152 }
1153
1154 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1155 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1156
1157 /* Use link status change interrrupt */
1158 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1159
1160 bcom_check_link(hw, port);
1161}
1162
1163static void genesis_mac_init(struct skge_hw *hw, int port)
1164{
1165 struct net_device *dev = hw->dev[port];
1166 struct skge_port *skge = netdev_priv(dev);
1167 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1168 int i;
1169 u32 r;
1170 const u8 zero[6] = { 0 };
1171
1172 /* Clear MIB counters */
1173 xm_write16(hw, port, XM_STAT_CMD,
1174 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1175 /* Clear two times according to Errata #3 */
1176 xm_write16(hw, port, XM_STAT_CMD,
1177 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1
SH		 1178
1179 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1180 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1181 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1182
6b0c1480
SH		 1183 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1184 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1185
1186 /* Unreset the XMAC. */
6b0c1480 1187 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1188
1189 /*
1190 * Perform additional initialization for external PHYs,
1191 * namely for the 1000baseTX cards that use the XMAC's
1192 * GMII mode.
1193 */
1194 spin_lock_bh(&hw->phy_lock);
45bada65 1195 /* Take external Phy out of reset */
89bf5f23
SH		 1196 r = skge_read32(hw, B2_GP_IO);
1197 if (port == 0)
1198 r |= GP_DIR_0|GP_IO_0;
1199 else
1200 r |= GP_DIR_2|GP_IO_2;
1201
1202 skge_write32(hw, B2_GP_IO, r);
1203 skge_read32(hw, B2_GP_IO);
45bada65 1204 spin_unlock_bh(&hw->phy_lock);
89bf5f23 1205
45bada65 1206 /* Enable GMII interfac */
89bf5f23
SH		 1207 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1208
45bada65 1209 bcom_phy_init(skge, jumbo);
89bf5f23 1210
45bada65
SH		 1211 /* Set Station Address */
1212 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1213
45bada65
SH		 1214 /* We don't use match addresses so clear */
1215 for (i = 1; i < 16; i++)
1216 xm_outaddr(hw, port, XM_EXM(i), zero);
1217
1218 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1219 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1220
1221 /* We don't need the FCS appended to the packet. */
1222 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1223 if (jumbo)
1224 r |= XM_RX_BIG_PK_OK;
89bf5f23 1225
45bada65 1226 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1227 /*
45bada65
SH		 1228 * If in manual half duplex mode the other side might be in
1229 * full duplex mode, so ignore if a carrier extension is not seen
1230 * on frames received
89bf5f23 1231 */
45bada65 1232 r |= XM_RX_DIS_CEXT;
baef58b1 1233 }
45bada65 1234 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1235
baef58b1
SH		 1236
1237 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1238 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1239
1240 /*
1241 * Bump up the transmit threshold. This helps hold off transmit
1242 * underruns when we're blasting traffic from both ports at once.
1243 */
1244 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1245
1246 /*
1247 * Enable the reception of all error frames. This is is
1248 * a necessary evil due to the design of the XMAC. The
1249 * XMAC's receive FIFO is only 8K in size, however jumbo
1250 * frames can be up to 9000 bytes in length. When bad
1251 * frame filtering is enabled, the XMAC's RX FIFO operates
1252 * in 'store and forward' mode. For this to work, the
1253 * entire frame has to fit into the FIFO, but that means
1254 * that jumbo frames larger than 8192 bytes will be
1255 * truncated. Disabling all bad frame filtering causes
1256 * the RX FIFO to operate in streaming mode, in which
1257 * case the XMAC will start transfering frames out of the
1258 * RX FIFO as soon as the FIFO threshold is reached.
1259 */
45bada65 1260 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1261
baef58b1
SH		 1262
1263 /*
45bada65
SH		 1264 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1265 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1266 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1267 */
45bada65
SH		 1268 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1269
1270 /*
1271 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1272 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1273 * and 'Octets Tx OK Hi Cnt Ov'.
1274 */
1275 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1276
1277 /* Configure MAC arbiter */
1278 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1279
1280 /* configure timeout values */
1281 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1282 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1283 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1284 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1285
1286 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1287 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1288 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1289 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1290
1291 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1292 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1293 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1294 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1295
1296 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1297 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1298 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1299 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1300
45bada65 1301 if (jumbo) {
baef58b1 1302 /* Enable frame flushing if jumbo frames used */
6b0c1480 1303 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1304 } else {
1305 /* enable timeout timers if normal frames */
1306 skge_write16(hw, B3_PA_CTRL,
45bada65 1307 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1308 }
baef58b1
SH		 1309}
1310
1311static void genesis_stop(struct skge_port *skge)
1312{
1313 struct skge_hw *hw = skge->hw;
1314 int port = skge->port;
89bf5f23 1315 u32 reg;
baef58b1
SH		 1316
1317 /* Clear Tx packet arbiter timeout IRQ */
1318 skge_write16(hw, B3_PA_CTRL,
1319 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1320
1321 /*
1322 * If the transfer stucks at the MAC the STOP command will not
1323 * terminate if we don't flush the XMAC's transmit FIFO !
1324 */
6b0c1480
SH		 1325 xm_write32(hw, port, XM_MODE,
1326 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1327
1328
1329 /* Reset the MAC */
6b0c1480 1330 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1331
1332 /* For external PHYs there must be special handling */
89bf5f23
SH		 1333 reg = skge_read32(hw, B2_GP_IO);
1334 if (port == 0) {
1335 reg |= GP_DIR_0;
1336 reg &= ~GP_IO_0;
1337 } else {
1338 reg |= GP_DIR_2;
1339 reg &= ~GP_IO_2;
baef58b1 1340 }
89bf5f23
SH		 1341 skge_write32(hw, B2_GP_IO, reg);
1342 skge_read32(hw, B2_GP_IO);
baef58b1 1343
6b0c1480
SH		 1344 xm_write16(hw, port, XM_MMU_CMD,
1345 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1346 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1347
6b0c1480 1348 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1349}
1350
1351
1352static void genesis_get_stats(struct skge_port *skge, u64 *data)
1353{
1354 struct skge_hw *hw = skge->hw;
1355 int port = skge->port;
1356 int i;
1357 unsigned long timeout = jiffies + HZ;
1358
6b0c1480 1359 xm_write16(hw, port,
baef58b1
SH		 1360 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1361
1362 /* wait for update to complete */
6b0c1480 1363 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1364 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1365 if (time_after(jiffies, timeout))
1366 break;
1367 udelay(10);
1368 }
1369
1370 /* special case for 64 bit octet counter */
6b0c1480
SH		 1371 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1372 | xm_read32(hw, port, XM_TXO_OK_LO);
1373 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1374 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1375
1376 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1377 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1378}
1379
1380static void genesis_mac_intr(struct skge_hw *hw, int port)
1381{
1382 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1383 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1384
1385 pr_debug("genesis_intr status %x\n", status);
baef58b1
SH		 1386
1387 if (status & XM_IS_TXF_UR) {
6b0c1480 1388 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1389 ++skge->net_stats.tx_fifo_errors;
1390 }
1391 if (status & XM_IS_RXF_OV) {
6b0c1480 1392 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1393 ++skge->net_stats.rx_fifo_errors;
1394 }
1395}
1396
6b0c1480 1397static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1398{
1399 int i;
1400
6b0c1480
SH		 1401 gma_write16(hw, port, GM_SMI_DATA, val);
1402 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1403 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1404 for (i = 0; i < PHY_RETRIES; i++) {
1405 udelay(1);
1406
6b0c1480 1407 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1408 break;
1409 }
1410}
1411
6b0c1480 1412static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1413{
1414 int i;
1415
6b0c1480 1416 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1417 GM_SMI_CT_PHY_AD(hw->phy_addr)
1418 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1419
1420 for (i = 0; i < PHY_RETRIES; i++) {
1421 udelay(1);
6b0c1480 1422 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1423 goto ready;
1424 }
1425
1426 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1427 hw->dev[port]->name);
1428 return 0;
1429 ready:
6b0c1480 1430 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1431}
1432
baef58b1
SH		 1433static void genesis_link_up(struct skge_port *skge)
1434{
1435 struct skge_hw *hw = skge->hw;
1436 int port = skge->port;
1437 u16 cmd;
1438 u32 mode, msk;
1439
1440 pr_debug("genesis_link_up\n");
6b0c1480 1441 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1442
1443 /*
1444 * enabling pause frame reception is required for 1000BT
1445 * because the XMAC is not reset if the link is going down
1446 */
1447 if (skge->flow_control == FLOW_MODE_NONE ||
1448 skge->flow_control == FLOW_MODE_LOC_SEND)
1449 cmd |= XM_MMU_IGN_PF;
1450 else
1451 /* Enable Pause Frame Reception */
1452 cmd &= ~XM_MMU_IGN_PF;
1453
6b0c1480 1454 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1455
6b0c1480 1456 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1457 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1458 skge->flow_control == FLOW_MODE_LOC_SEND) {
1459 /*
1460 * Configure Pause Frame Generation
1461 * Use internal and external Pause Frame Generation.
1462 * Sending pause frames is edge triggered.
1463 * Send a Pause frame with the maximum pause time if
1464 * internal oder external FIFO full condition occurs.
1465 * Send a zero pause time frame to re-start transmission.
1466 */
1467 /* XM_PAUSE_DA = '010000C28001' (default) */
1468 /* XM_MAC_PTIME = 0xffff (maximum) */
1469 /* remember this value is defined in big endian (!) */
6b0c1480 1470 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1471
1472 mode |= XM_PAUSE_MODE;
6b0c1480 1473 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1474 } else {
1475 /*
1476 * disable pause frame generation is required for 1000BT
1477 * because the XMAC is not reset if the link is going down
1478 */
1479 /* Disable Pause Mode in Mode Register */
1480 mode &= ~XM_PAUSE_MODE;
1481
6b0c1480 1482 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1483 }
1484
6b0c1480 1485 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1486
1487 msk = XM_DEF_MSK;
89bf5f23
SH		 1488 /* disable GP0 interrupt bit for external Phy */
1489 msk |= XM_IS_INP_ASS;
baef58b1 1490
6b0c1480
SH		 1491 xm_write16(hw, port, XM_IMSK, msk);
1492 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1493
1494 /* get MMU Command Reg. */
6b0c1480 1495 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1496 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1497 cmd |= XM_MMU_GMII_FD;
1498
89bf5f23
SH		 1499 /*
1500 * Workaround BCOM Errata (#10523) for all BCom Phys
1501 * Enable Power Management after link up
1502 */
1503 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1504 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1505 & ~PHY_B_AC_DIS_PM);
1506 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1507
1508 /* enable Rx/Tx */
6b0c1480 1509 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1510 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1511 skge_link_up(skge);
1512}
1513
1514
45bada65 1515static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1516{
1517 struct skge_hw *hw = skge->hw;
1518 int port = skge->port;
45bada65
SH		 1519 u16 isrc;
1520
1521 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1522 pr_debug("bcom_phy_interrupt status=0x%x\n", isrc);
baef58b1 1523
45bada65
SH		 1524 if (isrc & PHY_B_IS_PSE)
1525 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1526 hw->dev[port]->name);
baef58b1
SH		 1527
1528 /* Workaround BCom Errata:
1529 * enable and disable loopback mode if "NO HCD" occurs.
1530 */
45bada65 1531 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1532 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1533 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1534 ctrl | PHY_CT_LOOP);
6b0c1480 1535 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1536 ctrl & ~PHY_CT_LOOP);
1537 }
1538
45bada65
SH		 1539 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1540 bcom_check_link(hw, port);
baef58b1 1541
baef58b1
SH		 1542}
1543
1544/* Marvell Phy Initailization */
1545static void yukon_init(struct skge_hw *hw, int port)
1546{
1547 struct skge_port *skge = netdev_priv(hw->dev[port]);
1548 u16 ctrl, ct1000, adv;
1549 u16 ledctrl, ledover;
1550
1551 pr_debug("yukon_init\n");
1552 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1553 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1554
1555 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1556 PHY_M_EC_MAC_S_MSK);
1557 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1558
c506a509 1559 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1560
6b0c1480 1561 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1562 }
1563
6b0c1480 1564 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1565 if (skge->autoneg == AUTONEG_DISABLE)
1566 ctrl &= ~PHY_CT_ANE;
1567
1568 ctrl |= PHY_CT_RESET;
6b0c1480 1569 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1570
1571 ctrl = 0;
1572 ct1000 = 0;
b18f2091 1573 adv = PHY_AN_CSMA;
baef58b1
SH		 1574
1575 if (skge->autoneg == AUTONEG_ENABLE) {
1576 if (iscopper(hw)) {
1577 if (skge->advertising & ADVERTISED_1000baseT_Full)
1578 ct1000 |= PHY_M_1000C_AFD;
1579 if (skge->advertising & ADVERTISED_1000baseT_Half)
1580 ct1000 |= PHY_M_1000C_AHD;
1581 if (skge->advertising & ADVERTISED_100baseT_Full)
1582 adv |= PHY_M_AN_100_FD;
1583 if (skge->advertising & ADVERTISED_100baseT_Half)
1584 adv |= PHY_M_AN_100_HD;
1585 if (skge->advertising & ADVERTISED_10baseT_Full)
1586 adv |= PHY_M_AN_10_FD;
1587 if (skge->advertising & ADVERTISED_10baseT_Half)
1588 adv |= PHY_M_AN_10_HD;
45bada65 1589 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1590 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1591
45bada65
SH		 1592 /* Set Flow-control capabilities */
1593 adv |= phy_pause_map[skge->flow_control];
1594
baef58b1
SH		 1595 /* Restart Auto-negotiation */
1596 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1597 } else {
1598 /* forced speed/duplex settings */
1599 ct1000 = PHY_M_1000C_MSE;
1600
1601 if (skge->duplex == DUPLEX_FULL)
1602 ctrl |= PHY_CT_DUP_MD;
1603
1604 switch (skge->speed) {
1605 case SPEED_1000:
1606 ctrl |= PHY_CT_SP1000;
1607 break;
1608 case SPEED_100:
1609 ctrl |= PHY_CT_SP100;
1610 break;
1611 }
1612
1613 ctrl |= PHY_CT_RESET;
1614 }
1615
c506a509 1616 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1617
6b0c1480
SH		 1618 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1619 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1620
1621 /* Setup Phy LED's */
1622 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1623 ledover = 0;
1624
c506a509 1625 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
baef58b1 1626
c506a509
SH		 1627 /* turn off the Rx LED (LED_RX) */
1628 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
baef58b1
SH		 1629
1630 /* disable blink mode (LED_DUPLEX) on collisions */
1631 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1632 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1633
1634 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1635 /* turn on 100 Mbps LED (LED_LINK100) */
1636 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1637 }
1638
1639 if (ledover)
6b0c1480 1640 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1641
1642 /* Enable phy interrupt on autonegotiation complete (or link up) */
1643 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1644 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1645 else
6b0c1480 1646 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1647}
1648
1649static void yukon_reset(struct skge_hw *hw, int port)
1650{
6b0c1480
SH		 1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1652 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1653 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1655 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1656
6b0c1480
SH		 1657 gma_write16(hw, port, GM_RX_CTRL,
1658 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1659 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1660}
1661
1662static void yukon_mac_init(struct skge_hw *hw, int port)
1663{
1664 struct skge_port *skge = netdev_priv(hw->dev[port]);
1665 int i;
1666 u32 reg;
1667 const u8 *addr = hw->dev[port]->dev_addr;
1668
1669 /* WA code for COMA mode -- set PHY reset */
1670 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1671 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1672 skge_write32(hw, B2_GP_IO,
1673 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1674
1675 /* hard reset */
6b0c1480
SH		 1676 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1677 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1678
1679 /* WA code for COMA mode -- clear PHY reset */
1680 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1681 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1682 skge_write32(hw, B2_GP_IO,
1683 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1684 & ~GP_IO_9);
1685
1686 /* Set hardware config mode */
1687 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1688 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1689 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1690
1691 /* Clear GMC reset */
6b0c1480
SH		 1692 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1694 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1695 if (skge->autoneg == AUTONEG_DISABLE) {
1696 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1697 gma_write16(hw, port, GM_GP_CTRL,
1698 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1699
1700 switch (skge->speed) {
1701 case SPEED_1000:
1702 reg |= GM_GPCR_SPEED_1000;
1703 /* fallthru */
1704 case SPEED_100:
1705 reg |= GM_GPCR_SPEED_100;
1706 }
1707
1708 if (skge->duplex == DUPLEX_FULL)
1709 reg |= GM_GPCR_DUP_FULL;
1710 } else
1711 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1712 switch (skge->flow_control) {
1713 case FLOW_MODE_NONE:
6b0c1480 1714 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1715 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1716 break;
1717 case FLOW_MODE_LOC_SEND:
1718 /* disable Rx flow-control */
1719 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1720 }
1721
6b0c1480 1722 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1723 skge_read16(hw, GMAC_IRQ_SRC);
1724
1725 spin_lock_bh(&hw->phy_lock);
1726 yukon_init(hw, port);
1727 spin_unlock_bh(&hw->phy_lock);
1728
1729 /* MIB clear */
6b0c1480
SH		 1730 reg = gma_read16(hw, port, GM_PHY_ADDR);
1731 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1732
1733 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1734 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1735 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1736
1737 /* transmit control */
6b0c1480 1738 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1739
1740 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1741 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1742 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1743
1744 /* transmit flow control */
6b0c1480 1745 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1746
1747 /* transmit parameter */
6b0c1480 1748 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1749 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1750 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1751 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1752
1753 /* serial mode register */
1754 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1755 if (hw->dev[port]->mtu > 1500)
1756 reg |= GM_SMOD_JUMBO_ENA;
1757
6b0c1480 1758 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1759
1760 /* physical address: used for pause frames */
6b0c1480 1761 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1762 /* virtual address for data */
6b0c1480 1763 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1764
1765 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1766 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1767 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1768 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1769
1770 /* Initialize Mac Fifo */
1771
1772 /* Configure Rx MAC FIFO */
6b0c1480 1773 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1774 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1775 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1776 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1 1777 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1778 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1779 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1780 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1781
1782 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1783 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1784 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1785}
1786
1787static void yukon_stop(struct skge_port *skge)
1788{
1789 struct skge_hw *hw = skge->hw;
1790 int port = skge->port;
1791
1792 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1793 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1794 skge_write32(hw, B2_GP_IO,
1795 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1796 }
1797
6b0c1480
SH		 1798 gma_write16(hw, port, GM_GP_CTRL,
1799 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1800 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1801 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1802
1803 /* set GPHY Control reset */
6b0c1480
SH		 1804 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1805 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1806}
1807
1808static void yukon_get_stats(struct skge_port *skge, u64 *data)
1809{
1810 struct skge_hw *hw = skge->hw;
1811 int port = skge->port;
1812 int i;
1813
6b0c1480
SH		 1814 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1815 | gma_read32(hw, port, GM_TXO_OK_LO);
1816 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1817 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1818
1819 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1820 data[i] = gma_read32(hw, port,
baef58b1
SH		 1821 skge_stats[i].gma_offset);
1822}
1823
1824static void yukon_mac_intr(struct skge_hw *hw, int port)
1825{
1826 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1827 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1
SH		 1828
1829 pr_debug("yukon_intr status %x\n", status);
1830 if (status & GM_IS_RX_FF_OR) {
1831 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1832 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1833 }
1834 if (status & GM_IS_TX_FF_UR) {
1835 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1836 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1837 }
1838
1839}
1840
1841static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1842{
95566065 1843 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1844 case PHY_M_PS_SPEED_1000:
1845 return SPEED_1000;
1846 case PHY_M_PS_SPEED_100:
1847 return SPEED_100;
1848 default:
1849 return SPEED_10;
1850 }
1851}
1852
1853static void yukon_link_up(struct skge_port *skge)
1854{
1855 struct skge_hw *hw = skge->hw;
1856 int port = skge->port;
1857 u16 reg;
1858
1859 pr_debug("yukon_link_up\n");
1860
1861 /* Enable Transmit FIFO Underrun */
1862 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1863
6b0c1480 1864 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1865 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1866 reg |= GM_GPCR_DUP_FULL;
1867
1868 /* enable Rx/Tx */
1869 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1870 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1871
6b0c1480 1872 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1873 skge_link_up(skge);
1874}
1875
1876static void yukon_link_down(struct skge_port *skge)
1877{
1878 struct skge_hw *hw = skge->hw;
1879 int port = skge->port;
1880
1881 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1882 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1883 gm_phy_write(hw, port, GM_GP_CTRL,
1884 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1885 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1886
c506a509 1887 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1888 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1889 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1890 gm_phy_read(hw, port,
baef58b1
SH		 1891 PHY_MARV_AUNE_ADV)
1892 | PHY_M_AN_ASP);
1893
1894 }
1895
1896 yukon_reset(hw, port);
1897 skge_link_down(skge);
1898
1899 yukon_init(hw, port);
1900}
1901
1902static void yukon_phy_intr(struct skge_port *skge)
1903{
1904 struct skge_hw *hw = skge->hw;
1905 int port = skge->port;
1906 const char *reason = NULL;
1907 u16 istatus, phystat;
1908
6b0c1480
SH		 1909 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1910 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
baef58b1
SH		 1911 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
1912
1913 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1914 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1915 & PHY_M_AN_RF) {
1916 reason = "remote fault";
1917 goto failed;
1918 }
1919
c506a509 1920 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1921 reason = "master/slave fault";
1922 goto failed;
1923 }
1924
1925 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1926 reason = "speed/duplex";
1927 goto failed;
1928 }
1929
1930 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1931 ? DUPLEX_FULL : DUPLEX_HALF;
1932 skge->speed = yukon_speed(hw, phystat);
1933
baef58b1
SH		 1934 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1935 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1936 case PHY_M_PS_PAUSE_MSK:
1937 skge->flow_control = FLOW_MODE_SYMMETRIC;
1938 break;
1939 case PHY_M_PS_RX_P_EN:
1940 skge->flow_control = FLOW_MODE_REM_SEND;
1941 break;
1942 case PHY_M_PS_TX_P_EN:
1943 skge->flow_control = FLOW_MODE_LOC_SEND;
1944 break;
1945 default:
1946 skge->flow_control = FLOW_MODE_NONE;
1947 }
1948
1949 if (skge->flow_control == FLOW_MODE_NONE ||
1950 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1951 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1952 else
6b0c1480 1953 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1954 yukon_link_up(skge);
1955 return;
1956 }
1957
1958 if (istatus & PHY_M_IS_LSP_CHANGE)
1959 skge->speed = yukon_speed(hw, phystat);
1960
1961 if (istatus & PHY_M_IS_DUP_CHANGE)
1962 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1963 if (istatus & PHY_M_IS_LST_CHANGE) {
1964 if (phystat & PHY_M_PS_LINK_UP)
1965 yukon_link_up(skge);
1966 else
1967 yukon_link_down(skge);
1968 }
1969 return;
1970 failed:
1971 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1972 skge->netdev->name, reason);
1973
1974 /* XXX restart autonegotiation? */
1975}
1976
1977static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1978{
1979 u32 end;
1980
1981 start /= 8;
1982 len /= 8;
1983 end = start + len - 1;
1984
1985 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1986 skge_write32(hw, RB_ADDR(q, RB_START), start);
1987 skge_write32(hw, RB_ADDR(q, RB_WP), start);
1988 skge_write32(hw, RB_ADDR(q, RB_RP), start);
1989 skge_write32(hw, RB_ADDR(q, RB_END), end);
1990
1991 if (q == Q_R1 || q == Q_R2) {
1992 /* Set thresholds on receive queue's */
1993 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
1994 start + (2*len)/3);
1995 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
1996 start + (len/3));
1997 } else {
1998 /* Enable store & forward on Tx queue's because
1999 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2000 */
2001 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2002 }
2003
2004 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2005}
2006
2007/* Setup Bus Memory Interface */
2008static void skge_qset(struct skge_port *skge, u16 q,
2009 const struct skge_element *e)
2010{
2011 struct skge_hw *hw = skge->hw;
2012 u32 watermark = 0x600;
2013 u64 base = skge->dma + (e->desc - skge->mem);
2014
2015 /* optimization to reduce window on 32bit/33mhz */
2016 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2017 watermark /= 2;
2018
2019 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2020 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2021 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2022 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2023}
2024
2025static int skge_up(struct net_device *dev)
2026{
2027 struct skge_port *skge = netdev_priv(dev);
2028 struct skge_hw *hw = skge->hw;
2029 int port = skge->port;
2030 u32 chunk, ram_addr;
2031 size_t rx_size, tx_size;
2032 int err;
2033
2034 if (netif_msg_ifup(skge))
2035 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2036
2037 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2038 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2039 skge->mem_size = tx_size + rx_size;
2040 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2041 if (!skge->mem)
2042 return -ENOMEM;
2043
2044 memset(skge->mem, 0, skge->mem_size);
2045
2046 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2047 goto free_pci_mem;
2048
2049 if (skge_rx_fill(skge))
2050 goto free_rx_ring;
2051
2052 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2053 skge->dma + rx_size)))
2054 goto free_rx_ring;
2055
2056 skge->tx_avail = skge->tx_ring.count - 1;
2057
2058 /* Initialze MAC */
2059 if (hw->chip_id == CHIP_ID_GENESIS)
2060 genesis_mac_init(hw, port);
2061 else
2062 yukon_mac_init(hw, port);
2063
2064 /* Configure RAMbuffers */
981d0377 2065 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2066 ram_addr = hw->ram_offset + 2 * chunk * port;
2067
2068 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2069 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2070
2071 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2072 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2073 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2074
2075 /* Start receiver BMU */
2076 wmb();
2077 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2078
2079 pr_debug("skge_up completed\n");
2080 return 0;
2081
2082 free_rx_ring:
2083 skge_rx_clean(skge);
2084 kfree(skge->rx_ring.start);
2085 free_pci_mem:
2086 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2087
2088 return err;
2089}
2090
2091static int skge_down(struct net_device *dev)
2092{
2093 struct skge_port *skge = netdev_priv(dev);
2094 struct skge_hw *hw = skge->hw;
2095 int port = skge->port;
2096
2097 if (netif_msg_ifdown(skge))
2098 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2099
2100 netif_stop_queue(dev);
2101
2102 del_timer_sync(&skge->led_blink);
baef58b1
SH		 2103
2104 /* Stop transmitter */
2105 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2106 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2107 RB_RST_SET|RB_DIS_OP_MD);
2108
2109 if (hw->chip_id == CHIP_ID_GENESIS)
2110 genesis_stop(skge);
2111 else
2112 yukon_stop(skge);
2113
2114 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2115 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2116 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2117
2118 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2119 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2120 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2121
2122 /* Reset PCI FIFO */
2123 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2124 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2125
2126 /* Reset the RAM Buffer async Tx queue */
2127 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2128 /* stop receiver */
2129 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2130 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2131 RB_RST_SET|RB_DIS_OP_MD);
2132 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2133
2134 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2135 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2136 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2137 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2138 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2139 } else {
6b0c1480
SH		 2140 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2141 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2142 }
2143
2144 /* turn off led's */
2145 skge_write16(hw, B0_LED, LED_STAT_OFF);
2146
2147 skge_tx_clean(skge);
2148 skge_rx_clean(skge);
2149
2150 kfree(skge->rx_ring.start);
2151 kfree(skge->tx_ring.start);
2152 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2153 return 0;
2154}
2155
2156static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2157{
2158 struct skge_port *skge = netdev_priv(dev);
2159 struct skge_hw *hw = skge->hw;
2160 struct skge_ring *ring = &skge->tx_ring;
2161 struct skge_element *e;
2162 struct skge_tx_desc *td;
2163 int i;
2164 u32 control, len;
2165 u64 map;
2166 unsigned long flags;
2167
2168 skb = skb_padto(skb, ETH_ZLEN);
2169 if (!skb)
2170 return NETDEV_TX_OK;
2171
2172 local_irq_save(flags);
2173 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2174 /* Collision - tell upper layer to requeue */
2175 local_irq_restore(flags);
2176 return NETDEV_TX_LOCKED;
2177 }
baef58b1
SH		 2178
2179 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2180 netif_stop_queue(dev);
2181 spin_unlock_irqrestore(&skge->tx_lock, flags);
2182
2183 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2184 dev->name);
2185 return NETDEV_TX_BUSY;
2186 }
2187
2188 e = ring->to_use;
2189 td = e->desc;
2190 e->skb = skb;
2191 len = skb_headlen(skb);
2192 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2193 pci_unmap_addr_set(e, mapaddr, map);
2194 pci_unmap_len_set(e, maplen, len);
2195
2196 td->dma_lo = map;
2197 td->dma_hi = map >> 32;
2198
2199 if (skb->ip_summed == CHECKSUM_HW) {
2200 const struct iphdr *ip
2201 = (const struct iphdr *) (skb->data + ETH_HLEN);
2202 int offset = skb->h.raw - skb->data;
2203
2204 /* This seems backwards, but it is what the sk98lin
2205 * does. Looks like hardware is wrong?
2206 */
2207 if (ip->protocol == IPPROTO_UDP
981d0377 2208 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2209 control = BMU_TCP_CHECK;
2210 else
2211 control = BMU_UDP_CHECK;
2212
2213 td->csum_offs = 0;
2214 td->csum_start = offset;
2215 td->csum_write = offset + skb->csum;
2216 } else
2217 control = BMU_CHECK;
2218
2219 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2220 control |= BMU_EOF| BMU_IRQ_EOF;
2221 else {
2222 struct skge_tx_desc *tf = td;
2223
2224 control |= BMU_STFWD;
2225 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2226 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2227
2228 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2229 frag->size, PCI_DMA_TODEVICE);
2230
2231 e = e->next;
2232 e->skb = NULL;
2233 tf = e->desc;
2234 tf->dma_lo = map;
2235 tf->dma_hi = (u64) map >> 32;
2236 pci_unmap_addr_set(e, mapaddr, map);
2237 pci_unmap_len_set(e, maplen, frag->size);
2238
2239 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2240 }
2241 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2242 }
2243 /* Make sure all the descriptors written */
2244 wmb();
2245 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2246 wmb();
2247
2248 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2249
2250 if (netif_msg_tx_queued(skge))
0b2d7fea 2251 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2252 dev->name, e - ring->start, skb->len);
2253
2254 ring->to_use = e->next;
2255 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2256 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2257 pr_debug("%s: transmit queue full\n", dev->name);
2258 netif_stop_queue(dev);
2259 }
2260
2261 dev->trans_start = jiffies;
2262 spin_unlock_irqrestore(&skge->tx_lock, flags);
2263
2264 return NETDEV_TX_OK;
2265}
2266
2267static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2268{
2269 if (e->skb) {
2270 pci_unmap_single(hw->pdev,
2271 pci_unmap_addr(e, mapaddr),
2272 pci_unmap_len(e, maplen),
2273 PCI_DMA_TODEVICE);
2274 dev_kfree_skb_any(e->skb);
2275 e->skb = NULL;
2276 } else {
2277 pci_unmap_page(hw->pdev,
2278 pci_unmap_addr(e, mapaddr),
2279 pci_unmap_len(e, maplen),
2280 PCI_DMA_TODEVICE);
2281 }
2282}
2283
2284static void skge_tx_clean(struct skge_port *skge)
2285{
2286 struct skge_ring *ring = &skge->tx_ring;
2287 struct skge_element *e;
2288 unsigned long flags;
2289
2290 spin_lock_irqsave(&skge->tx_lock, flags);
2291 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2292 ++skge->tx_avail;
2293 skge_tx_free(skge->hw, e);
2294 }
2295 ring->to_clean = e;
2296 spin_unlock_irqrestore(&skge->tx_lock, flags);
2297}
2298
2299static void skge_tx_timeout(struct net_device *dev)
2300{
2301 struct skge_port *skge = netdev_priv(dev);
2302
2303 if (netif_msg_timer(skge))
2304 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2305
2306 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2307 skge_tx_clean(skge);
2308}
2309
2310static int skge_change_mtu(struct net_device *dev, int new_mtu)
2311{
2312 int err = 0;
2313
95566065 2314 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2315 return -EINVAL;
2316
2317 dev->mtu = new_mtu;
2318
2319 if (netif_running(dev)) {
2320 skge_down(dev);
2321 skge_up(dev);
2322 }
2323
2324 return err;
2325}
2326
2327static void genesis_set_multicast(struct net_device *dev)
2328{
2329 struct skge_port *skge = netdev_priv(dev);
2330 struct skge_hw *hw = skge->hw;
2331 int port = skge->port;
2332 int i, count = dev->mc_count;
2333 struct dev_mc_list *list = dev->mc_list;
2334 u32 mode;
2335 u8 filter[8];
2336
45bada65
SH		 2337 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2338
6b0c1480 2339 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2340 mode |= XM_MD_ENA_HASH;
2341 if (dev->flags & IFF_PROMISC)
2342 mode |= XM_MD_ENA_PROM;
2343 else
2344 mode &= ~XM_MD_ENA_PROM;
2345
2346 if (dev->flags & IFF_ALLMULTI)
2347 memset(filter, 0xff, sizeof(filter));
2348 else {
2349 memset(filter, 0, sizeof(filter));
95566065 2350 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2351 u32 crc, bit;
2352 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2353 bit = ~crc & 0x3f;
baef58b1
SH		 2354 filter[bit/8] |= 1 << (bit%8);
2355 }
2356 }
2357
6b0c1480 2358 xm_write32(hw, port, XM_MODE, mode);
45bada65 2359 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2360}
2361
2362static void yukon_set_multicast(struct net_device *dev)
2363{
2364 struct skge_port *skge = netdev_priv(dev);
2365 struct skge_hw *hw = skge->hw;
2366 int port = skge->port;
2367 struct dev_mc_list *list = dev->mc_list;
2368 u16 reg;
2369 u8 filter[8];
2370
2371 memset(filter, 0, sizeof(filter));
2372
6b0c1480 2373 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2374 reg |= GM_RXCR_UCF_ENA;
2375
2376 if (dev->flags & IFF_PROMISC) /* promiscious */
2377 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2378 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2379 memset(filter, 0xff, sizeof(filter));
2380 else if (dev->mc_count == 0) /* no multicast */
2381 reg &= ~GM_RXCR_MCF_ENA;
2382 else {
2383 int i;
2384 reg |= GM_RXCR_MCF_ENA;
2385
95566065 2386 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2387 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2388 filter[bit/8] |= 1 << (bit%8);
2389 }
2390 }
2391
2392
6b0c1480 2393 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2394 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2395 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2396 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2397 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2398 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2399 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2400 (u16)filter[6] | ((u16)filter[7] << 8));
2401
6b0c1480 2402 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2403}
2404
2405static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2406{
2407 if (hw->chip_id == CHIP_ID_GENESIS)
2408 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2409 else
2410 return (status & GMR_FS_ANY_ERR) ||
2411 (status & GMR_FS_RX_OK) == 0;
2412}
2413
2414static void skge_rx_error(struct skge_port *skge, int slot,
2415 u32 control, u32 status)
2416{
2417 if (netif_msg_rx_err(skge))
2418 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2419 skge->netdev->name, slot, control, status);
2420
2421 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2422 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2423 skge->net_stats.rx_length_errors++;
2424 else {
2425 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2426 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2427 skge->net_stats.rx_length_errors++;
2428 if (status & XMR_FS_FRA_ERR)
2429 skge->net_stats.rx_frame_errors++;
2430 if (status & XMR_FS_FCS_ERR)
2431 skge->net_stats.rx_crc_errors++;
2432 } else {
2433 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2434 skge->net_stats.rx_length_errors++;
2435 if (status & GMR_FS_FRAGMENT)
2436 skge->net_stats.rx_frame_errors++;
2437 if (status & GMR_FS_CRC_ERR)
2438 skge->net_stats.rx_crc_errors++;
2439 }
2440 }
2441}
2442
2443static int skge_poll(struct net_device *dev, int *budget)
2444{
2445 struct skge_port *skge = netdev_priv(dev);
2446 struct skge_hw *hw = skge->hw;
2447 struct skge_ring *ring = &skge->rx_ring;
2448 struct skge_element *e;
2449 unsigned int to_do = min(dev->quota, *budget);
2450 unsigned int work_done = 0;
2451 int done;
2452 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2453
2454 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2455 e = e->next) {
2456 struct skge_rx_desc *rd = e->desc;
2457 struct sk_buff *skb = e->skb;
2458 u32 control, len, status;
2459
2460 rmb();
2461 control = rd->control;
2462 if (control & BMU_OWN)
2463 break;
2464
2465 len = control & BMU_BBC;
2466 e->skb = NULL;
2467
2468 pci_unmap_single(hw->pdev,
2469 pci_unmap_addr(e, mapaddr),
2470 pci_unmap_len(e, maplen),
2471 PCI_DMA_FROMDEVICE);
2472
2473 status = rd->status;
2474 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2475 || len > dev->mtu + VLAN_ETH_HLEN
2476 || bad_phy_status(hw, status)) {
2477 skge_rx_error(skge, e - ring->start, control, status);
2478 dev_kfree_skb(skb);
2479 continue;
2480 }
2481
2482 if (netif_msg_rx_status(skge))
0b2d7fea 2483 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2484 dev->name, e - ring->start, rd->status, len);
2485
2486 skb_put(skb, len);
2487 skb->protocol = eth_type_trans(skb, dev);
2488
2489 if (skge->rx_csum) {
2490 skb->csum = le16_to_cpu(rd->csum2);
2491 skb->ip_summed = CHECKSUM_HW;
2492 }
2493
2494 dev->last_rx = jiffies;
2495 netif_receive_skb(skb);
2496
2497 ++work_done;
2498 }
2499 ring->to_clean = e;
2500
2501 *budget -= work_done;
2502 dev->quota -= work_done;
2503 done = work_done < to_do;
2504
2505 if (skge_rx_fill(skge))
2506 done = 0;
2507
2508 /* restart receiver */
2509 wmb();
2510 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2511 CSR_START | CSR_IRQ_CL_F);
2512
2513 if (done) {
2514 local_irq_disable();
2515 hw->intr_mask |= irqmask[skge->port];
2516 /* Order is important since data can get interrupted */
2517 skge_write32(hw, B0_IMSK, hw->intr_mask);
2518 __netif_rx_complete(dev);
2519 local_irq_enable();
2520 }
2521
2522 return !done;
2523}
2524
2525static inline void skge_tx_intr(struct net_device *dev)
2526{
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 struct skge_ring *ring = &skge->tx_ring;
2530 struct skge_element *e;
2531
2532 spin_lock(&skge->tx_lock);
95566065 2533 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2534 struct skge_tx_desc *td = e->desc;
2535 u32 control;
2536
2537 rmb();
2538 control = td->control;
2539 if (control & BMU_OWN)
2540 break;
2541
2542 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2543 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2544 dev->name, e - ring->start, td->status);
2545
2546 skge_tx_free(hw, e);
2547 e->skb = NULL;
2548 ++skge->tx_avail;
2549 }
2550 ring->to_clean = e;
2551 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2552
2553 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2554 netif_wake_queue(dev);
2555
2556 spin_unlock(&skge->tx_lock);
2557}
2558
2559static void skge_mac_parity(struct skge_hw *hw, int port)
2560{
2561 printk(KERN_ERR PFX "%s: mac data parity error\n",
2562 hw->dev[port] ? hw->dev[port]->name
2563 : (port == 0 ? "(port A)": "(port B"));
2564
2565 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2566 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2567 MFF_CLR_PERR);
2568 else
2569 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2570 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2571 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2572 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2573}
2574
2575static void skge_pci_clear(struct skge_hw *hw)
2576{
2577 u16 status;
2578
467b3417 2579 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2580 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2581 pci_write_config_word(hw->pdev, PCI_STATUS,
2582 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2583 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2584}
2585
2586static void skge_mac_intr(struct skge_hw *hw, int port)
2587{
95566065 2588 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2589 genesis_mac_intr(hw, port);
2590 else
2591 yukon_mac_intr(hw, port);
2592}
2593
2594/* Handle device specific framing and timeout interrupts */
2595static void skge_error_irq(struct skge_hw *hw)
2596{
2597 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2598
2599 if (hw->chip_id == CHIP_ID_GENESIS) {
2600 /* clear xmac errors */
2601 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2602 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2603 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2604 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2605 } else {
2606 /* Timestamp (unused) overflow */
2607 if (hwstatus & IS_IRQ_TIST_OV)
2608 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2609
2610 if (hwstatus & IS_IRQ_SENSOR) {
2611 /* no sensors on 32-bit Yukon */
2612 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2613 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2614 skge_write32(hw, B0_HWE_IMSK,
2615 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2616 } else
2617 printk(KERN_WARNING PFX "sensor interrupt\n");
2618 }
2619
2620
2621 }
2622
2623 if (hwstatus & IS_RAM_RD_PAR) {
2624 printk(KERN_ERR PFX "Ram read data parity error\n");
2625 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2626 }
2627
2628 if (hwstatus & IS_RAM_WR_PAR) {
2629 printk(KERN_ERR PFX "Ram write data parity error\n");
2630 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2631 }
2632
2633 if (hwstatus & IS_M1_PAR_ERR)
2634 skge_mac_parity(hw, 0);
2635
2636 if (hwstatus & IS_M2_PAR_ERR)
2637 skge_mac_parity(hw, 1);
2638
2639 if (hwstatus & IS_R1_PAR_ERR)
2640 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2641
2642 if (hwstatus & IS_R2_PAR_ERR)
2643 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2644
2645 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2646 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2647 hwstatus);
2648
2649 skge_pci_clear(hw);
2650
2651 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2652 if (hwstatus & IS_IRQ_STAT) {
2653 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2654 hwstatus);
2655 hw->intr_mask &= ~IS_HW_ERR;
2656 }
2657 }
2658}
2659
2660/*
2661 * Interrrupt from PHY are handled in tasklet (soft irq)
2662 * because accessing phy registers requires spin wait which might
2663 * cause excess interrupt latency.
2664 */
2665static void skge_extirq(unsigned long data)
2666{
2667 struct skge_hw *hw = (struct skge_hw *) data;
2668 int port;
2669
2670 spin_lock(&hw->phy_lock);
2671 for (port = 0; port < 2; port++) {
2672 struct net_device *dev = hw->dev[port];
2673
2674 if (dev && netif_running(dev)) {
2675 struct skge_port *skge = netdev_priv(dev);
2676
2677 if (hw->chip_id != CHIP_ID_GENESIS)
2678 yukon_phy_intr(skge);
89bf5f23 2679 else
45bada65 2680 bcom_phy_intr(skge);
baef58b1
SH		 2681 }
2682 }
2683 spin_unlock(&hw->phy_lock);
2684
2685 local_irq_disable();
2686 hw->intr_mask |= IS_EXT_REG;
2687 skge_write32(hw, B0_IMSK, hw->intr_mask);
2688 local_irq_enable();
2689}
2690
2691static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2692{
2693 struct skge_hw *hw = dev_id;
2694 u32 status = skge_read32(hw, B0_SP_ISRC);
2695
2696 if (status == 0 || status == ~0) /* hotplug or shared irq */
2697 return IRQ_NONE;
2698
2699 status &= hw->intr_mask;
2700
2701 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2702 status &= ~IS_R1_F;
2703 hw->intr_mask &= ~IS_R1_F;
2704 skge_write32(hw, B0_IMSK, hw->intr_mask);
2705 __netif_rx_schedule(hw->dev[0]);
2706 }
2707
2708 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2709 status &= ~IS_R2_F;
2710 hw->intr_mask &= ~IS_R2_F;
2711 skge_write32(hw, B0_IMSK, hw->intr_mask);
2712 __netif_rx_schedule(hw->dev[1]);
2713 }
2714
2715 if (status & IS_XA1_F)
2716 skge_tx_intr(hw->dev[0]);
2717
2718 if (status & IS_XA2_F)
2719 skge_tx_intr(hw->dev[1]);
2720
2721 if (status & IS_MAC1)
2722 skge_mac_intr(hw, 0);
95566065 2723
baef58b1
SH		 2724 if (status & IS_MAC2)
2725 skge_mac_intr(hw, 1);
2726
2727 if (status & IS_HW_ERR)
2728 skge_error_irq(hw);
2729
2730 if (status & IS_EXT_REG) {
2731 hw->intr_mask &= ~IS_EXT_REG;
2732 tasklet_schedule(&hw->ext_tasklet);
2733 }
2734
2735 if (status)
2736 skge_write32(hw, B0_IMSK, hw->intr_mask);
2737
2738 return IRQ_HANDLED;
2739}
2740
2741#ifdef CONFIG_NET_POLL_CONTROLLER
2742static void skge_netpoll(struct net_device *dev)
2743{
2744 struct skge_port *skge = netdev_priv(dev);
2745
2746 disable_irq(dev->irq);
2747 skge_intr(dev->irq, skge->hw, NULL);
2748 enable_irq(dev->irq);
2749}
2750#endif
2751
2752static int skge_set_mac_address(struct net_device *dev, void *p)
2753{
2754 struct skge_port *skge = netdev_priv(dev);
2755 struct sockaddr *addr = p;
2756 int err = 0;
2757
2758 if (!is_valid_ether_addr(addr->sa_data))
2759 return -EADDRNOTAVAIL;
2760
2761 skge_down(dev);
2762 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2763 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2764 dev->dev_addr, ETH_ALEN);
2765 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2766 dev->dev_addr, ETH_ALEN);
2767 if (dev->flags & IFF_UP)
2768 err = skge_up(dev);
2769 return err;
2770}
2771
2772static const struct {
2773 u8 id;
2774 const char *name;
2775} skge_chips[] = {
2776 { CHIP_ID_GENESIS, "Genesis" },
2777 { CHIP_ID_YUKON, "Yukon" },
2778 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2779 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2780};
2781
2782static const char *skge_board_name(const struct skge_hw *hw)
2783{
2784 int i;
2785 static char buf[16];
2786
2787 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2788 if (skge_chips[i].id == hw->chip_id)
2789 return skge_chips[i].name;
2790
2791 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2792 return buf;
2793}
2794
2795
2796/*
2797 * Setup the board data structure, but don't bring up
2798 * the port(s)
2799 */
2800static int skge_reset(struct skge_hw *hw)
2801{
2802 u16 ctst;
981d0377
SH		 2803 u8 t8, mac_cfg;
2804 int i;
baef58b1
SH		 2805
2806 ctst = skge_read16(hw, B0_CTST);
2807
2808 /* do a SW reset */
2809 skge_write8(hw, B0_CTST, CS_RST_SET);
2810 skge_write8(hw, B0_CTST, CS_RST_CLR);
2811
2812 /* clear PCI errors, if any */
2813 skge_pci_clear(hw);
2814
2815 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2816
2817 /* restore CLK_RUN bits (for Yukon-Lite) */
2818 skge_write16(hw, B0_CTST,
2819 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2820
2821 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2822 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2823 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2824
95566065 2825 switch (hw->chip_id) {
baef58b1
SH		 2826 case CHIP_ID_GENESIS:
2827 switch (hw->phy_type) {
baef58b1
SH		 2828 case SK_PHY_BCOM:
2829 hw->phy_addr = PHY_ADDR_BCOM;
2830 break;
2831 default:
2832 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2833 pci_name(hw->pdev), hw->phy_type);
2834 return -EOPNOTSUPP;
2835 }
2836 break;
2837
2838 case CHIP_ID_YUKON:
2839 case CHIP_ID_YUKON_LITE:
2840 case CHIP_ID_YUKON_LP:
2841 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2842 hw->phy_type = SK_PHY_MARV_COPPER;
2843
2844 hw->phy_addr = PHY_ADDR_MARV;
2845 if (!iscopper(hw))
2846 hw->phy_type = SK_PHY_MARV_FIBER;
2847
2848 break;
2849
2850 default:
2851 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2852 pci_name(hw->pdev), hw->chip_id);
2853 return -EOPNOTSUPP;
2854 }
2855
981d0377
SH		 2856 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2857 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2858 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2859
2860 /* read the adapters RAM size */
2861 t8 = skge_read8(hw, B2_E_0);
2862 if (hw->chip_id == CHIP_ID_GENESIS) {
2863 if (t8 == 3) {
2864 /* special case: 4 x 64k x 36, offset = 0x80000 */
2865 hw->ram_size = 0x100000;
2866 hw->ram_offset = 0x80000;
2867 } else
2868 hw->ram_size = t8 * 512;
2869 }
2870 else if (t8 == 0)
2871 hw->ram_size = 0x20000;
2872 else
2873 hw->ram_size = t8 * 4096;
2874
2875 if (hw->chip_id == CHIP_ID_GENESIS)
2876 genesis_init(hw);
2877 else {
2878 /* switch power to VCC (WA for VAUX problem) */
2879 skge_write8(hw, B0_POWER_CTRL,
2880 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2881 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2882 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2883 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2884 }
2885 }
2886
2887 /* turn off hardware timer (unused) */
2888 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2889 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2890 skge_write8(hw, B0_LED, LED_STAT_ON);
2891
2892 /* enable the Tx Arbiters */
981d0377 2893 for (i = 0; i < hw->ports; i++)
6b0c1480 2894 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2895
2896 /* Initialize ram interface */
2897 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2898
2899 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2900 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2901 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2902 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2903 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2904 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2905 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2906 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2907 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2908 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2909 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2910 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2911
2912 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2913
2914 /* Set interrupt moderation for Transmit only
2915 * Receive interrupts avoided by NAPI
2916 */
2917 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2918 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2919 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2920
2921 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
981d0377 2922 if (hw->ports > 1)
baef58b1
SH		 2923 hw->intr_mask |= IS_PORT_2;
2924 skge_write32(hw, B0_IMSK, hw->intr_mask);
2925
2926 if (hw->chip_id != CHIP_ID_GENESIS)
2927 skge_write8(hw, GMAC_IRQ_MSK, 0);
2928
2929 spin_lock_bh(&hw->phy_lock);
981d0377 2930 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 2931 if (hw->chip_id == CHIP_ID_GENESIS)
2932 genesis_reset(hw, i);
2933 else
2934 yukon_reset(hw, i);
2935 }
2936 spin_unlock_bh(&hw->phy_lock);
2937
2938 return 0;
2939}
2940
2941/* Initialize network device */
981d0377
SH		 2942static struct net_device *skge_devinit(struct skge_hw *hw, int port,
2943 int highmem)
baef58b1
SH		 2944{
2945 struct skge_port *skge;
2946 struct net_device *dev = alloc_etherdev(sizeof(*skge));
2947
2948 if (!dev) {
2949 printk(KERN_ERR "skge etherdev alloc failed");
2950 return NULL;
2951 }
2952
2953 SET_MODULE_OWNER(dev);
2954 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2955 dev->open = skge_up;
2956 dev->stop = skge_down;
2957 dev->hard_start_xmit = skge_xmit_frame;
2958 dev->get_stats = skge_get_stats;
2959 if (hw->chip_id == CHIP_ID_GENESIS)
2960 dev->set_multicast_list = genesis_set_multicast;
2961 else
2962 dev->set_multicast_list = yukon_set_multicast;
2963
2964 dev->set_mac_address = skge_set_mac_address;
2965 dev->change_mtu = skge_change_mtu;
2966 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
2967 dev->tx_timeout = skge_tx_timeout;
2968 dev->watchdog_timeo = TX_WATCHDOG;
2969 dev->poll = skge_poll;
2970 dev->weight = NAPI_WEIGHT;
2971#ifdef CONFIG_NET_POLL_CONTROLLER
2972 dev->poll_controller = skge_netpoll;
2973#endif
2974 dev->irq = hw->pdev->irq;
2975 dev->features = NETIF_F_LLTX;
981d0377
SH		 2976 if (highmem)
2977 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 2978
2979 skge = netdev_priv(dev);
2980 skge->netdev = dev;
2981 skge->hw = hw;
2982 skge->msg_enable = netif_msg_init(debug, default_msg);
2983 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
2984 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
2985
2986 /* Auto speed and flow control */
2987 skge->autoneg = AUTONEG_ENABLE;
2988 skge->flow_control = FLOW_MODE_SYMMETRIC;
2989 skge->duplex = -1;
2990 skge->speed = -1;
31b619c5 2991 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 2992
2993 hw->dev[port] = dev;
2994
2995 skge->port = port;
2996
2997 spin_lock_init(&skge->tx_lock);
2998
baef58b1
SH		 2999 init_timer(&skge->led_blink);
3000 skge->led_blink.function = skge_blink_timer;
3001 skge->led_blink.data = (unsigned long) skge;
3002
3003 if (hw->chip_id != CHIP_ID_GENESIS) {
3004 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3005 skge->rx_csum = 1;
3006 }
3007
3008 /* read the mac address */
3009 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3010
3011 /* device is off until link detection */
3012 netif_carrier_off(dev);
3013 netif_stop_queue(dev);
3014
3015 return dev;
3016}
3017
3018static void __devinit skge_show_addr(struct net_device *dev)
3019{
3020 const struct skge_port *skge = netdev_priv(dev);
3021
3022 if (netif_msg_probe(skge))
3023 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3024 dev->name,
3025 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3026 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3027}
3028
3029static int __devinit skge_probe(struct pci_dev *pdev,
3030 const struct pci_device_id *ent)
3031{
3032 struct net_device *dev, *dev1;
3033 struct skge_hw *hw;
3034 int err, using_dac = 0;
3035
3036 if ((err = pci_enable_device(pdev))) {
3037 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3038 pci_name(pdev));
3039 goto err_out;
3040 }
3041
3042 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3043 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3044 pci_name(pdev));
3045 goto err_out_disable_pdev;
3046 }
3047
3048 pci_set_master(pdev);
3049
3050 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3051 using_dac = 1;
3052 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3053 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3054 pci_name(pdev));
3055 goto err_out_free_regions;
3056 }
3057
3058#ifdef __BIG_ENDIAN
3059 /* byte swap decriptors in hardware */
3060 {
3061 u32 reg;
3062
3063 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3064 reg |= PCI_REV_DESC;
3065 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3066 }
3067#endif
3068
3069 err = -ENOMEM;
3070 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3071 if (!hw) {
3072 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3073 pci_name(pdev));
3074 goto err_out_free_regions;
3075 }
3076
3077 memset(hw, 0, sizeof(*hw));
3078 hw->pdev = pdev;
3079 spin_lock_init(&hw->phy_lock);
3080 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3081
3082 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3083 if (!hw->regs) {
3084 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3085 pci_name(pdev));
3086 goto err_out_free_hw;
3087 }
3088
3089 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3090 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3091 pci_name(pdev), pdev->irq);
3092 goto err_out_iounmap;
3093 }
3094 pci_set_drvdata(pdev, hw);
3095
3096 err = skge_reset(hw);
3097 if (err)
3098 goto err_out_free_irq;
3099
3100 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3101 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3102 skge_board_name(hw), hw->chip_rev);
baef58b1 3103
981d0377 3104 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3105 goto err_out_led_off;
3106
baef58b1
SH		 3107 if ((err = register_netdev(dev))) {
3108 printk(KERN_ERR PFX "%s: cannot register net device\n",
3109 pci_name(pdev));
3110 goto err_out_free_netdev;
3111 }
3112
3113 skge_show_addr(dev);
3114
981d0377 3115 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3116 if (register_netdev(dev1) == 0)
3117 skge_show_addr(dev1);
3118 else {
3119 /* Failure to register second port need not be fatal */
3120 printk(KERN_WARNING PFX "register of second port failed\n");
3121 hw->dev[1] = NULL;
3122 free_netdev(dev1);
3123 }
3124 }
3125
3126 return 0;
3127
3128err_out_free_netdev:
3129 free_netdev(dev);
3130err_out_led_off:
3131 skge_write16(hw, B0_LED, LED_STAT_OFF);
3132err_out_free_irq:
3133 free_irq(pdev->irq, hw);
3134err_out_iounmap:
3135 iounmap(hw->regs);
3136err_out_free_hw:
3137 kfree(hw);
3138err_out_free_regions:
3139 pci_release_regions(pdev);
3140err_out_disable_pdev:
3141 pci_disable_device(pdev);
3142 pci_set_drvdata(pdev, NULL);
3143err_out:
3144 return err;
3145}
3146
3147static void __devexit skge_remove(struct pci_dev *pdev)
3148{
3149 struct skge_hw *hw = pci_get_drvdata(pdev);
3150 struct net_device *dev0, *dev1;
3151
95566065 3152 if (!hw)
baef58b1
SH		 3153 return;
3154
3155 if ((dev1 = hw->dev[1]))
3156 unregister_netdev(dev1);
3157 dev0 = hw->dev[0];
3158 unregister_netdev(dev0);
3159
3160 tasklet_kill(&hw->ext_tasklet);
3161
3162 free_irq(pdev->irq, hw);
3163 pci_release_regions(pdev);
3164 pci_disable_device(pdev);
3165 if (dev1)
3166 free_netdev(dev1);
3167 free_netdev(dev0);
3168 skge_write16(hw, B0_LED, LED_STAT_OFF);
3169 iounmap(hw->regs);
3170 kfree(hw);
3171 pci_set_drvdata(pdev, NULL);
3172}
3173
3174#ifdef CONFIG_PM
3175static int skge_suspend(struct pci_dev *pdev, u32 state)
3176{
3177 struct skge_hw *hw = pci_get_drvdata(pdev);
3178 int i, wol = 0;
3179
95566065 3180 for (i = 0; i < 2; i++) {
baef58b1
SH		 3181 struct net_device *dev = hw->dev[i];
3182
3183 if (dev) {
3184 struct skge_port *skge = netdev_priv(dev);
3185 if (netif_running(dev)) {
3186 netif_carrier_off(dev);
3187 skge_down(dev);
3188 }
3189 netif_device_detach(dev);
3190 wol |= skge->wol;
3191 }
3192 }
3193
3194 pci_save_state(pdev);
3195 pci_enable_wake(pdev, state, wol);
3196 pci_disable_device(pdev);
3197 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3198
3199 return 0;
3200}
3201
3202static int skge_resume(struct pci_dev *pdev)
3203{
3204 struct skge_hw *hw = pci_get_drvdata(pdev);
3205 int i;
3206
3207 pci_set_power_state(pdev, PCI_D0);
3208 pci_restore_state(pdev);
3209 pci_enable_wake(pdev, PCI_D0, 0);
3210
3211 skge_reset(hw);
3212
95566065 3213 for (i = 0; i < 2; i++) {
baef58b1
SH		 3214 struct net_device *dev = hw->dev[i];
3215 if (dev) {
3216 netif_device_attach(dev);
95566065 3217 if (netif_running(dev))
baef58b1
SH		 3218 skge_up(dev);
3219 }
3220 }
3221 return 0;
3222}
3223#endif
3224
3225static struct pci_driver skge_driver = {
3226 .name = DRV_NAME,
3227 .id_table = skge_id_table,
3228 .probe = skge_probe,
3229 .remove = __devexit_p(skge_remove),
3230#ifdef CONFIG_PM
3231 .suspend = skge_suspend,
3232 .resume = skge_resume,
3233#endif
3234};
3235
3236static int __init skge_init_module(void)
3237{
3238 return pci_module_init(&skge_driver);
3239}
3240
3241static void __exit skge_cleanup_module(void)
3242{
3243 pci_unregister_driver(&skge_driver);
3244}
3245
3246module_init(skge_init_module);
3247module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)