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[PATCH] sis190: initialisation of MAC address.
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / sis190.c
CommitLineData
890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/netdevice.h>
43afb949 25#include <linux/rtnetlink.h>
890e8d0a
FR		 26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/pci.h>
29#include <linux/mii.h>
30#include <linux/delay.h>
31#include <linux/crc32.h>
32#include <linux/dma-mapping.h>
33#include <asm/irq.h>
34
35#define net_drv(p, arg...) if (netif_msg_drv(p)) \
36 printk(arg)
37#define net_probe(p, arg...) if (netif_msg_probe(p)) \
38 printk(arg)
39#define net_link(p, arg...) if (netif_msg_link(p)) \
40 printk(arg)
41#define net_intr(p, arg...) if (netif_msg_intr(p)) \
42 printk(arg)
43#define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
44 printk(arg)
45
46#ifdef CONFIG_SIS190_NAPI
47#define NAPI_SUFFIX "-NAPI"
48#else
49#define NAPI_SUFFIX ""
50#endif
51
52#define DRV_VERSION "1.2" NAPI_SUFFIX
53#define DRV_NAME "sis190"
54#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
55#define PFX DRV_NAME ": "
56
57#ifdef CONFIG_SIS190_NAPI
58#define sis190_rx_skb netif_receive_skb
59#define sis190_rx_quota(count, quota) min(count, quota)
60#else
61#define sis190_rx_skb netif_rx
62#define sis190_rx_quota(count, quota) count
63#endif
64
65#define MAC_ADDR_LEN 6
66
67#define NUM_TX_DESC 64
68#define NUM_RX_DESC 64
69#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
70#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
71#define RX_BUF_SIZE 1536
72
73#define SIS190_REGS_SIZE 0x80
74#define SIS190_TX_TIMEOUT (6*HZ)
75#define SIS190_PHY_TIMEOUT (10*HZ)
76#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
77 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
78 NETIF_MSG_IFDOWN)
79
80/* Enhanced PHY access register bit definitions */
81#define EhnMIIread 0x0000
82#define EhnMIIwrite 0x0020
83#define EhnMIIdataShift 16
84#define EhnMIIpmdShift 6 /* 7016 only */
85#define EhnMIIregShift 11
86#define EhnMIIreq 0x0010
87#define EhnMIInotDone 0x0010
88
89/* Write/read MMIO register */
90#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
91#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
92#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
93#define SIS_R8(reg) readb (ioaddr + (reg))
94#define SIS_R16(reg) readw (ioaddr + (reg))
95#define SIS_R32(reg) readl (ioaddr + (reg))
96
97#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
98
99enum sis190_registers {
100 TxControl = 0x00,
101 TxDescStartAddr = 0x04,
188f23ba
FR		 102 rsv0 = 0x08, // reserved
103 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 104 RxControl = 0x10,
105 RxDescStartAddr = 0x14,
188f23ba
FR		 106 rsv1 = 0x18, // reserved
107 RxSts = 0x1c, // unused
890e8d0a
FR		 108 IntrStatus = 0x20,
109 IntrMask = 0x24,
110 IntrControl = 0x28,
188f23ba
FR		 111 IntrTimer = 0x2c, // unused (Interupt Timer)
112 PMControl = 0x30, // unused (Power Mgmt Control/Status)
113 rsv2 = 0x34, // reserved
890e8d0a
FR		 114 ROMControl = 0x38,
115 ROMInterface = 0x3c,
116 StationControl = 0x40,
117 GMIIControl = 0x44,
188f23ba
FR		 118 GIoCR = 0x48, // unused (GMAC IO Compensation)
119 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 120 TxMacControl = 0x50,
188f23ba
FR		 121 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
122 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
123 rsv3 = 0x5c, // reserved
890e8d0a
FR		 124 RxMacControl = 0x60,
125 RxMacAddr = 0x62,
126 RxHashTable = 0x68,
127 // Undocumented = 0x6c,
188f23ba
FR		 128 RxWolCtrl = 0x70,
129 RxWolData = 0x74, // unused (Rx WOL Data Access)
130 RxMPSControl = 0x78, // unused (Rx MPS Control)
131 rsv4 = 0x7c, // reserved
890e8d0a
FR		 132};
133
134enum sis190_register_content {
135 /* IntrStatus */
136 SoftInt = 0x40000000, // unused
137 Timeup = 0x20000000, // unused
138 PauseFrame = 0x00080000, // unused
139 MagicPacket = 0x00040000, // unused
140 WakeupFrame = 0x00020000, // unused
141 LinkChange = 0x00010000,
142 RxQEmpty = 0x00000080,
143 RxQInt = 0x00000040,
144 TxQ1Empty = 0x00000020, // unused
145 TxQ1Int = 0x00000010,
146 TxQ0Empty = 0x00000008, // unused
147 TxQ0Int = 0x00000004,
148 RxHalt = 0x00000002,
149 TxHalt = 0x00000001,
150
151 /* RxStatusDesc */
152 RxRES = 0x00200000, // unused
153 RxCRC = 0x00080000,
154 RxRUNT = 0x00100000, // unused
155 RxRWT = 0x00400000, // unused
156
157 /* {Rx/Tx}CmdBits */
158 CmdReset = 0x10,
159 CmdRxEnb = 0x08, // unused
160 CmdTxEnb = 0x01,
161 RxBufEmpty = 0x01, // unused
162
163 /* Cfg9346Bits */
164 Cfg9346_Lock = 0x00, // unused
165 Cfg9346_Unlock = 0xc0, // unused
166
167 /* RxMacControl */
168 AcceptErr = 0x20, // unused
169 AcceptRunt = 0x10, // unused
170 AcceptBroadcast = 0x0800,
171 AcceptMulticast = 0x0400,
172 AcceptMyPhys = 0x0200,
173 AcceptAllPhys = 0x0100,
174
175 /* RxConfigBits */
176 RxCfgFIFOShift = 13,
177 RxCfgDMAShift = 8, // 0x1a in RxControl ?
178
179 /* TxConfigBits */
180 TxInterFrameGapShift = 24,
181 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
182
183 /* StationControl */
184 _1000bpsF = 0x1c00,
185 _1000bpsH = 0x0c00,
186 _100bpsF = 0x1800,
187 _100bpsH = 0x0800,
188 _10bpsF = 0x1400,
189 _10bpsH = 0x0400,
190
191 LinkStatus = 0x02, // unused
192 FullDup = 0x01, // unused
193
194 /* TBICSRBit */
195 TBILinkOK = 0x02000000, // unused
196};
197
198struct TxDesc {
199 u32 PSize;
200 u32 status;
201 u32 addr;
202 u32 size;
203};
204
205struct RxDesc {
206 u32 PSize;
207 u32 status;
208 u32 addr;
209 u32 size;
210};
211
212enum _DescStatusBit {
213 /* _Desc.status */
214 OWNbit = 0x80000000,
215 INTbit = 0x40000000,
216 DEFbit = 0x00200000,
217 CRCbit = 0x00020000,
218 PADbit = 0x00010000,
219 /* _Desc.size */
220 RingEnd = (1 << 31),
221 /* _Desc.PSize */
222 RxSizeMask = 0x0000ffff
223};
224
40292fb0
FR		 225enum sis190_eeprom_access_register_bits {
226 EECS = 0x00000001, // unused
227 EECLK = 0x00000002, // unused
228 EEDO = 0x00000008, // unused
229 EEDI = 0x00000004, // unused
230 EEREQ = 0x00000080,
231 EEROP = 0x00000200,
232 EEWOP = 0x00000100 // unused
233};
234
830fb7d2
FR		 235/* EEPROM Addresses */
236enum sis190_eeprom_address {
237 EEPROMSignature = 0x00,
238 EEPROMCLK = 0x01, // unused
239 EEPROMInfo = 0x02,
240 EEPROMMACAddr = 0x03
241};
242
890e8d0a
FR		 243struct sis190_private {
244 void __iomem *mmio_addr;
245 struct pci_dev *pci_dev;
246 struct net_device_stats stats;
247 spinlock_t lock;
248 u32 rx_buf_sz;
249 u32 cur_rx;
250 u32 cur_tx;
251 u32 dirty_rx;
252 u32 dirty_tx;
253 dma_addr_t rx_dma;
254 dma_addr_t tx_dma;
255 struct RxDesc *RxDescRing;
256 struct TxDesc *TxDescRing;
257 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
258 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
259 struct work_struct phy_task;
260 struct timer_list timer;
261 u32 msg_enable;
43afb949 262 struct mii_if_info mii_if;
890e8d0a
FR		 263};
264
265const static struct {
266 const char *name;
267 u8 version; /* depend on docs */
268 u32 RxConfigMask; /* clear the bits supported by this chip */
269} sis_chip_info[] = {
270 { DRV_NAME, 0x00, 0xff7e1880, },
271};
272
273static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
274 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
275 { 0, },
276};
277
278MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
279
280static int rx_copybreak = 200;
281
282static struct {
283 u32 msg_enable;
284} debug = { -1 };
285
286MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
287module_param(rx_copybreak, int, 0);
288MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
289module_param_named(debug, debug.msg_enable, int, 0);
290MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
291MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
292MODULE_VERSION(DRV_VERSION);
293MODULE_LICENSE("GPL");
294
295static const u32 sis190_intr_mask =
296 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt;
297
298/*
299 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
300 * The chips use a 64 element hash table based on the Ethernet CRC.
301 */
302static int multicast_filter_limit = 32;
303
304static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
305{
306 unsigned int i;
307
308 SIS_W32(GMIIControl, ctl);
309
310 msleep(1);
311
312 for (i = 0; i < 100; i++) {
313 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
314 break;
315 msleep(1);
316 }
317
318 if (i > 999)
319 printk(KERN_ERR PFX "PHY command failed !\n");
320}
321
322static void mdio_write(void __iomem *ioaddr, int reg, int val)
323{
324 u32 pmd = 1;
325
326 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
327 (((u32) reg) << EhnMIIregShift) | (pmd << EhnMIIpmdShift) |
328 (((u32) val) << EhnMIIdataShift));
329}
330
331static int mdio_read(void __iomem *ioaddr, int reg)
332{
333 u32 pmd = 1;
334
335 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
336 (((u32) reg) << EhnMIIregShift) | (pmd << EhnMIIpmdShift));
337
338 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
339}
340
43afb949
FR		 341static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
342{
343 struct sis190_private *tp = netdev_priv(dev);
344
345 mdio_write(tp->mmio_addr, reg, val);
346}
347
348static int __mdio_read(struct net_device *dev, int phy_id, int reg)
349{
350 struct sis190_private *tp = netdev_priv(dev);
351
352 return mdio_read(tp->mmio_addr, reg);
353}
354
40292fb0 355static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 356{
40292fb0 357 u16 data = 0xffff;
890e8d0a 358 unsigned int i;
890e8d0a
FR		 359
360 if (!(SIS_R32(ROMControl) & 0x0002))
361 return 0;
362
40292fb0 363 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 364
365 for (i = 0; i < 200; i++) {
40292fb0
FR		 366 if (!(SIS_R32(ROMInterface) & EEREQ)) {
367 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 368 break;
40292fb0 369 }
890e8d0a
FR		 370 msleep(1);
371 }
372
890e8d0a
FR		 373 return data;
374}
375
376static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
377{
378 SIS_W32(IntrMask, 0x00);
379 SIS_W32(IntrStatus, 0xffffffff);
380 SIS_PCI_COMMIT();
381}
382
383static void sis190_asic_down(void __iomem *ioaddr)
384{
385 /* Stop the chip's Tx and Rx DMA processes. */
386
387 SIS_W32(TxControl, 0x1a00);
388 SIS_W32(RxControl, 0x1a00);
389
390 sis190_irq_mask_and_ack(ioaddr);
391}
392
393static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
394{
395 desc->size |= cpu_to_le32(RingEnd);
396}
397
398static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
399{
400 u32 eor = le32_to_cpu(desc->size) & RingEnd;
401
402 desc->PSize = 0x0;
403 desc->size = cpu_to_le32(rx_buf_sz | eor);
404 wmb();
405 desc->status = cpu_to_le32(OWNbit | INTbit);
406}
407
408static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
409 u32 rx_buf_sz)
410{
411 desc->addr = cpu_to_le32(mapping);
412 sis190_give_to_asic(desc, rx_buf_sz);
413}
414
415static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
416{
417 desc->PSize = 0x0;
418 desc->addr = 0xdeadbeef;
419 desc->size &= cpu_to_le32(RingEnd);
420 wmb();
421 desc->status = 0x0;
422}
423
424static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
425 struct RxDesc *desc, u32 rx_buf_sz)
426{
427 struct sk_buff *skb;
428 dma_addr_t mapping;
429 int ret = 0;
430
431 skb = dev_alloc_skb(rx_buf_sz);
432 if (!skb)
433 goto err_out;
434
435 *sk_buff = skb;
436
437 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
438 PCI_DMA_FROMDEVICE);
439
440 sis190_map_to_asic(desc, mapping, rx_buf_sz);
441out:
442 return ret;
443
444err_out:
445 ret = -ENOMEM;
446 sis190_make_unusable_by_asic(desc);
447 goto out;
448}
449
450static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
451 u32 start, u32 end)
452{
453 u32 cur;
454
455 for (cur = start; cur < end; cur++) {
456 int ret, i = cur % NUM_RX_DESC;
457
458 if (tp->Rx_skbuff[i])
459 continue;
460
461 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
462 tp->RxDescRing + i, tp->rx_buf_sz);
463 if (ret < 0)
464 break;
465 }
466 return cur - start;
467}
468
469static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
470 struct RxDesc *desc, int rx_buf_sz)
471{
472 int ret = -1;
473
474 if (pkt_size < rx_copybreak) {
475 struct sk_buff *skb;
476
477 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
478 if (skb) {
479 skb_reserve(skb, NET_IP_ALIGN);
480 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
481 *sk_buff = skb;
482 sis190_give_to_asic(desc, rx_buf_sz);
483 ret = 0;
484 }
485 }
486 return ret;
487}
488
489static int sis190_rx_interrupt(struct net_device *dev,
490 struct sis190_private *tp, void __iomem *ioaddr)
491{
492 struct net_device_stats *stats = &tp->stats;
493 u32 rx_left, cur_rx = tp->cur_rx;
494 u32 delta, count;
495
496 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
497 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
498
499 for (; rx_left > 0; rx_left--, cur_rx++) {
500 unsigned int entry = cur_rx % NUM_RX_DESC;
501 struct RxDesc *desc = tp->RxDescRing + entry;
502 u32 status;
503
504 if (desc->status & OWNbit)
505 break;
506
507 status = le32_to_cpu(desc->PSize);
508
509 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
510 // status);
511
512 if (status & RxCRC) {
513 net_intr(tp, KERN_INFO "%s: bad crc. status = %08x.\n",
514 dev->name, status);
515 stats->rx_errors++;
516 stats->rx_crc_errors++;
517 sis190_give_to_asic(desc, tp->rx_buf_sz);
518 } else if (!(status & PADbit)) {
519 net_intr(tp, KERN_INFO "%s: bad pad. status = %08x.\n",
520 dev->name, status);
521 stats->rx_errors++;
522 stats->rx_length_errors++;
523 sis190_give_to_asic(desc, tp->rx_buf_sz);
524 } else {
525 struct sk_buff *skb = tp->Rx_skbuff[entry];
526 int pkt_size = (status & RxSizeMask) - 4;
527 void (*pci_action)(struct pci_dev *, dma_addr_t,
528 size_t, int) = pci_dma_sync_single_for_device;
529
530 if (unlikely(pkt_size > tp->rx_buf_sz)) {
531 net_intr(tp, KERN_INFO
532 "%s: (frag) status = %08x.\n",
533 dev->name, status);
534 stats->rx_dropped++;
535 stats->rx_length_errors++;
536 sis190_give_to_asic(desc, tp->rx_buf_sz);
537 continue;
538 }
539
540 pci_dma_sync_single_for_cpu(tp->pci_dev,
541 le32_to_cpu(desc->addr), tp->rx_buf_sz,
542 PCI_DMA_FROMDEVICE);
543
544 if (sis190_try_rx_copy(&skb, pkt_size, desc,
545 tp->rx_buf_sz)) {
546 pci_action = pci_unmap_single;
547 tp->Rx_skbuff[entry] = NULL;
548 sis190_make_unusable_by_asic(desc);
549 }
550
551 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
552 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
553
554 skb->dev = dev;
555 skb_put(skb, pkt_size);
556 skb->protocol = eth_type_trans(skb, dev);
557
558 sis190_rx_skb(skb);
559
560 dev->last_rx = jiffies;
561 stats->rx_bytes += pkt_size;
562 stats->rx_packets++;
563 }
564 }
565 count = cur_rx - tp->cur_rx;
566 tp->cur_rx = cur_rx;
567
568 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
569 if (!delta && count && netif_msg_intr(tp))
570 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
571 tp->dirty_rx += delta;
572
573 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
574 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
575
576 return count;
577}
578
579static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
580 struct TxDesc *desc)
581{
582 unsigned int len;
583
584 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
585
586 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
587
588 memset(desc, 0x00, sizeof(*desc));
589}
590
591static void sis190_tx_interrupt(struct net_device *dev,
592 struct sis190_private *tp, void __iomem *ioaddr)
593{
594 u32 pending, dirty_tx = tp->dirty_tx;
595 /*
596 * It would not be needed if queueing was allowed to be enabled
597 * again too early (hint: think preempt and unclocked smp systems).
598 */
599 unsigned int queue_stopped;
600
601 smp_rmb();
602 pending = tp->cur_tx - dirty_tx;
603 queue_stopped = (pending == NUM_TX_DESC);
604
605 for (; pending; pending--, dirty_tx++) {
606 unsigned int entry = dirty_tx % NUM_TX_DESC;
607 struct TxDesc *txd = tp->TxDescRing + entry;
608 struct sk_buff *skb;
609
610 if (le32_to_cpu(txd->status) & OWNbit)
611 break;
612
613 skb = tp->Tx_skbuff[entry];
614
615 tp->stats.tx_packets++;
616 tp->stats.tx_bytes += skb->len;
617
618 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
619 tp->Tx_skbuff[entry] = NULL;
620 dev_kfree_skb_irq(skb);
621 }
622
623 if (tp->dirty_tx != dirty_tx) {
624 tp->dirty_tx = dirty_tx;
625 smp_wmb();
626 if (queue_stopped)
627 netif_wake_queue(dev);
628 }
629}
630
631/*
632 * The interrupt handler does all of the Rx thread work and cleans up after
633 * the Tx thread.
634 */
635static irqreturn_t sis190_interrupt(int irq, void *__dev, struct pt_regs *regs)
636{
637 struct net_device *dev = __dev;
638 struct sis190_private *tp = netdev_priv(dev);
639 void __iomem *ioaddr = tp->mmio_addr;
640 unsigned int handled = 0;
641 u32 status;
642
643 status = SIS_R32(IntrStatus);
644
645 if ((status == 0xffffffff) || !status)
646 goto out;
647
648 handled = 1;
649
650 if (unlikely(!netif_running(dev))) {
651 sis190_asic_down(ioaddr);
652 goto out;
653 }
654
655 SIS_W32(IntrStatus, status);
656
657 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
658
659 if (status & LinkChange) {
660 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
661 schedule_work(&tp->phy_task);
662 }
663
664 if (status & RxQInt)
665 sis190_rx_interrupt(dev, tp, ioaddr);
666
667 if (status & TxQ0Int)
668 sis190_tx_interrupt(dev, tp, ioaddr);
669out:
670 return IRQ_RETVAL(handled);
671}
672
4405d3b5
FR		 673#ifdef CONFIG_NET_POLL_CONTROLLER
674static void sis190_netpoll(struct net_device *dev)
675{
676 struct sis190_private *tp = netdev_priv(dev);
677 struct pci_dev *pdev = tp->pci_dev;
678
679 disable_irq(pdev->irq);
680 sis190_interrupt(pdev->irq, dev, NULL);
681 enable_irq(pdev->irq);
682}
683#endif
684
890e8d0a
FR		 685static void sis190_free_rx_skb(struct sis190_private *tp,
686 struct sk_buff **sk_buff, struct RxDesc *desc)
687{
688 struct pci_dev *pdev = tp->pci_dev;
689
690 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
691 PCI_DMA_FROMDEVICE);
692 dev_kfree_skb(*sk_buff);
693 *sk_buff = NULL;
694 sis190_make_unusable_by_asic(desc);
695}
696
697static void sis190_rx_clear(struct sis190_private *tp)
698{
699 unsigned int i;
700
701 for (i = 0; i < NUM_RX_DESC; i++) {
702 if (!tp->Rx_skbuff[i])
703 continue;
704 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
705 }
706}
707
708static void sis190_init_ring_indexes(struct sis190_private *tp)
709{
710 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
711}
712
713static int sis190_init_ring(struct net_device *dev)
714{
715 struct sis190_private *tp = netdev_priv(dev);
716
717 sis190_init_ring_indexes(tp);
718
719 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
720 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
721
722 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
723 goto err_rx_clear;
724
725 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
726
727 return 0;
728
729err_rx_clear:
730 sis190_rx_clear(tp);
731 return -ENOMEM;
732}
733
734static void sis190_set_rx_mode(struct net_device *dev)
735{
736 struct sis190_private *tp = netdev_priv(dev);
737 void __iomem *ioaddr = tp->mmio_addr;
738 unsigned long flags;
739 u32 mc_filter[2]; /* Multicast hash filter */
740 u16 rx_mode;
741
742 if (dev->flags & IFF_PROMISC) {
743 /* Unconditionally log net taps. */
744 net_drv(tp, KERN_NOTICE "%s: Promiscuous mode enabled.\n",
745 dev->name);
746 rx_mode =
747 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
748 AcceptAllPhys;
749 mc_filter[1] = mc_filter[0] = 0xffffffff;
750 } else if ((dev->mc_count > multicast_filter_limit) ||
751 (dev->flags & IFF_ALLMULTI)) {
752 /* Too many to filter perfectly -- accept all multicasts. */
753 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
754 mc_filter[1] = mc_filter[0] = 0xffffffff;
755 } else {
756 struct dev_mc_list *mclist;
757 unsigned int i;
758
759 rx_mode = AcceptBroadcast | AcceptMyPhys;
760 mc_filter[1] = mc_filter[0] = 0;
761 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
762 i++, mclist = mclist->next) {
763 int bit_nr =
764 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
765 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
766 rx_mode |= AcceptMulticast;
767 }
768 }
769
770 spin_lock_irqsave(&tp->lock, flags);
771
772 SIS_W16(RxMacControl, rx_mode | 0x2);
773 SIS_W32(RxHashTable, mc_filter[0]);
774 SIS_W32(RxHashTable + 4, mc_filter[1]);
775
776 spin_unlock_irqrestore(&tp->lock, flags);
777}
778
779static void sis190_soft_reset(void __iomem *ioaddr)
780{
781 SIS_W32(IntrControl, 0x8000);
782 SIS_PCI_COMMIT();
783 msleep(1);
784 SIS_W32(IntrControl, 0x0);
785 sis190_asic_down(ioaddr);
786 msleep(1);
787}
788
789static void sis190_hw_start(struct net_device *dev)
790{
791 struct sis190_private *tp = netdev_priv(dev);
792 void __iomem *ioaddr = tp->mmio_addr;
793
794 sis190_soft_reset(ioaddr);
795
796 SIS_W32(TxDescStartAddr, tp->tx_dma);
797 SIS_W32(RxDescStartAddr, tp->rx_dma);
798
799 SIS_W32(IntrStatus, 0xffffffff);
800 SIS_W32(IntrMask, 0x0);
801 /*
802 * Default is 100Mbps.
803 * A bit strange: 100Mbps is 0x1801 elsewhere -- FR 2005/06/09
804 */
805 SIS_W16(StationControl, 0x1901);
806 SIS_W32(GMIIControl, 0x0);
807 SIS_W32(TxMacControl, 0x60);
808 SIS_W16(RxMacControl, 0x02);
809 SIS_W32(RxHashTable, 0x0);
810 SIS_W32(0x6c, 0x0);
188f23ba
FR		 811 SIS_W32(RxWolCtrl, 0x0);
812 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 813
814 SIS_PCI_COMMIT();
815
816 sis190_set_rx_mode(dev);
817
818 /* Enable all known interrupts by setting the interrupt mask. */
819 SIS_W32(IntrMask, sis190_intr_mask);
820
821 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
822 SIS_W32(RxControl, 0x1a1d);
823
824 netif_start_queue(dev);
825}
826
827static void sis190_phy_task(void * data)
828{
829 struct net_device *dev = data;
830 struct sis190_private *tp = netdev_priv(dev);
831 void __iomem *ioaddr = tp->mmio_addr;
832 u16 val;
833
43afb949
FR		 834 rtnl_lock();
835
890e8d0a
FR		 836 val = mdio_read(ioaddr, MII_BMCR);
837 if (val & BMCR_RESET) {
838 // FIXME: needlessly high ? -- FR 02/07/2005
839 mod_timer(&tp->timer, jiffies + HZ/10);
840 } else if (!(mdio_read(ioaddr, MII_BMSR) & BMSR_ANEGCOMPLETE)) {
841 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
842 dev->name);
843 mdio_write(ioaddr, MII_BMCR, val | BMCR_RESET);
844 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
845 } else {
846 /* Rejoice ! */
847 struct {
848 int val;
849 const char *msg;
850 u16 ctl;
851 } reg31[] = {
852 { LPA_1000XFULL | LPA_SLCT,
853 "1000 Mbps Full Duplex",
854 0x01 | _1000bpsF },
855 { LPA_1000XHALF | LPA_SLCT,
856 "1000 Mbps Half Duplex",
857 0x01 | _1000bpsH },
858 { LPA_100FULL,
859 "100 Mbps Full Duplex",
860 0x01 | _100bpsF },
861 { LPA_100HALF,
862 "100 Mbps Half Duplex",
863 0x01 | _100bpsH },
864 { LPA_10FULL,
865 "10 Mbps Full Duplex",
866 0x01 | _10bpsF },
867 { LPA_10HALF,
868 "10 Mbps Half Duplex",
869 0x01 | _10bpsH },
870 { 0, "unknown", 0x0000 }
871 }, *p;
872
873 val = mdio_read(ioaddr, 0x1f);
874 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
875
876 val = mdio_read(ioaddr, MII_LPA);
877 net_link(tp, KERN_INFO "%s: mii lpa = %04x.\n", dev->name, val);
878
879 for (p = reg31; p->ctl; p++) {
880 if ((val & p->val) == p->val)
881 break;
882 }
883 if (p->ctl)
884 SIS_W16(StationControl, p->ctl);
885 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
886 p->msg);
887 netif_carrier_on(dev);
888 }
43afb949
FR		 889
890 rtnl_unlock();
890e8d0a
FR		 891}
892
893static void sis190_phy_timer(unsigned long __opaque)
894{
895 struct net_device *dev = (struct net_device *)__opaque;
896 struct sis190_private *tp = netdev_priv(dev);
897
898 if (likely(netif_running(dev)))
899 schedule_work(&tp->phy_task);
900}
901
902static inline void sis190_delete_timer(struct net_device *dev)
903{
904 struct sis190_private *tp = netdev_priv(dev);
905
906 del_timer_sync(&tp->timer);
907}
908
909static inline void sis190_request_timer(struct net_device *dev)
910{
911 struct sis190_private *tp = netdev_priv(dev);
912 struct timer_list *timer = &tp->timer;
913
914 init_timer(timer);
915 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
916 timer->data = (unsigned long)dev;
917 timer->function = sis190_phy_timer;
918 add_timer(timer);
919}
920
921static void sis190_set_rxbufsize(struct sis190_private *tp,
922 struct net_device *dev)
923{
924 unsigned int mtu = dev->mtu;
925
926 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
927}
928
929static int sis190_open(struct net_device *dev)
930{
931 struct sis190_private *tp = netdev_priv(dev);
932 struct pci_dev *pdev = tp->pci_dev;
933 int rc = -ENOMEM;
934
935 sis190_set_rxbufsize(tp, dev);
936
937 /*
938 * Rx and Tx descriptors need 256 bytes alignment.
939 * pci_alloc_consistent() guarantees a stronger alignment.
940 */
941 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
942 if (!tp->TxDescRing)
943 goto out;
944
945 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
946 if (!tp->RxDescRing)
947 goto err_free_tx_0;
948
949 rc = sis190_init_ring(dev);
950 if (rc < 0)
951 goto err_free_rx_1;
952
953 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
954
955 sis190_request_timer(dev);
956
957 rc = request_irq(dev->irq, sis190_interrupt, SA_SHIRQ, dev->name, dev);
958 if (rc < 0)
959 goto err_release_timer_2;
960
961 sis190_hw_start(dev);
962out:
963 return rc;
964
965err_release_timer_2:
966 sis190_delete_timer(dev);
967 sis190_rx_clear(tp);
968err_free_rx_1:
969 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
970 tp->rx_dma);
971err_free_tx_0:
972 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
973 tp->tx_dma);
974 goto out;
975}
976
977static void sis190_tx_clear(struct sis190_private *tp)
978{
979 unsigned int i;
980
981 for (i = 0; i < NUM_TX_DESC; i++) {
982 struct sk_buff *skb = tp->Tx_skbuff[i];
983
984 if (!skb)
985 continue;
986
987 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
988 tp->Tx_skbuff[i] = NULL;
989 dev_kfree_skb(skb);
990
991 tp->stats.tx_dropped++;
992 }
993 tp->cur_tx = tp->dirty_tx = 0;
994}
995
996static void sis190_down(struct net_device *dev)
997{
998 struct sis190_private *tp = netdev_priv(dev);
999 void __iomem *ioaddr = tp->mmio_addr;
1000 unsigned int poll_locked = 0;
1001
1002 sis190_delete_timer(dev);
1003
1004 netif_stop_queue(dev);
1005
1006 flush_scheduled_work();
1007
1008 do {
1009 spin_lock_irq(&tp->lock);
1010
1011 sis190_asic_down(ioaddr);
1012
1013 spin_unlock_irq(&tp->lock);
1014
1015 synchronize_irq(dev->irq);
1016
1017 if (!poll_locked) {
1018 netif_poll_disable(dev);
1019 poll_locked++;
1020 }
1021
1022 synchronize_sched();
1023
1024 } while (SIS_R32(IntrMask));
1025
1026 sis190_tx_clear(tp);
1027 sis190_rx_clear(tp);
1028}
1029
1030static int sis190_close(struct net_device *dev)
1031{
1032 struct sis190_private *tp = netdev_priv(dev);
1033 struct pci_dev *pdev = tp->pci_dev;
1034
1035 sis190_down(dev);
1036
1037 free_irq(dev->irq, dev);
1038
1039 netif_poll_enable(dev);
1040
1041 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1042 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1043
1044 tp->TxDescRing = NULL;
1045 tp->RxDescRing = NULL;
1046
1047 return 0;
1048}
1049
1050static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1051{
1052 struct sis190_private *tp = netdev_priv(dev);
1053 void __iomem *ioaddr = tp->mmio_addr;
1054 u32 len, entry, dirty_tx;
1055 struct TxDesc *desc;
1056 dma_addr_t mapping;
1057
1058 if (unlikely(skb->len < ETH_ZLEN)) {
1059 skb = skb_padto(skb, ETH_ZLEN);
1060 if (!skb) {
1061 tp->stats.tx_dropped++;
1062 goto out;
1063 }
1064 len = ETH_ZLEN;
1065 } else {
1066 len = skb->len;
1067 }
1068
1069 entry = tp->cur_tx % NUM_TX_DESC;
1070 desc = tp->TxDescRing + entry;
1071
1072 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1073 netif_stop_queue(dev);
1074 net_tx_err(tp, KERN_ERR PFX
1075 "%s: BUG! Tx Ring full when queue awake!\n",
1076 dev->name);
1077 return NETDEV_TX_BUSY;
1078 }
1079
1080 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1081
1082 tp->Tx_skbuff[entry] = skb;
1083
1084 desc->PSize = cpu_to_le32(len);
1085 desc->addr = cpu_to_le32(mapping);
1086
1087 desc->size = cpu_to_le32(len);
1088 if (entry == (NUM_TX_DESC - 1))
1089 desc->size |= cpu_to_le32(RingEnd);
1090
1091 wmb();
1092
1093 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1094
1095 tp->cur_tx++;
1096
1097 smp_wmb();
1098
1099 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1100
1101 dev->trans_start = jiffies;
1102
1103 dirty_tx = tp->dirty_tx;
1104 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1105 netif_stop_queue(dev);
1106 smp_rmb();
1107 if (dirty_tx != tp->dirty_tx)
1108 netif_wake_queue(dev);
1109 }
1110out:
1111 return NETDEV_TX_OK;
1112}
1113
1114static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1115{
1116 struct sis190_private *tp = netdev_priv(dev);
1117
1118 return &tp->stats;
1119}
1120
1121static void sis190_release_board(struct pci_dev *pdev)
1122{
1123 struct net_device *dev = pci_get_drvdata(pdev);
1124 struct sis190_private *tp = netdev_priv(dev);
1125
1126 iounmap(tp->mmio_addr);
1127 pci_release_regions(pdev);
1128 pci_disable_device(pdev);
1129 free_netdev(dev);
1130}
1131
1132static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1133{
1134 struct sis190_private *tp;
1135 struct net_device *dev;
1136 void __iomem *ioaddr;
1137 int rc;
1138
1139 dev = alloc_etherdev(sizeof(*tp));
1140 if (!dev) {
1141 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1142 rc = -ENOMEM;
1143 goto err_out_0;
1144 }
1145
1146 SET_MODULE_OWNER(dev);
1147 SET_NETDEV_DEV(dev, &pdev->dev);
1148
1149 tp = netdev_priv(dev);
1150 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1151
1152 rc = pci_enable_device(pdev);
1153 if (rc < 0) {
1154 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1155 goto err_free_dev_1;
1156 }
1157
1158 rc = -ENODEV;
1159
1160 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1161 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1162 pci_name(pdev));
1163 goto err_pci_disable_2;
1164 }
1165 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1166 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1167 pci_name(pdev));
1168 goto err_pci_disable_2;
1169 }
1170
1171 rc = pci_request_regions(pdev, DRV_NAME);
1172 if (rc < 0) {
1173 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1174 pci_name(pdev));
1175 goto err_pci_disable_2;
1176 }
1177
1178 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1179 if (rc < 0) {
1180 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1181 pci_name(pdev));
1182 goto err_free_res_3;
1183 }
1184
1185 pci_set_master(pdev);
1186
1187 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1188 if (!ioaddr) {
1189 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1190 pci_name(pdev));
1191 rc = -EIO;
1192 goto err_free_res_3;
1193 }
1194
1195 tp->pci_dev = pdev;
1196 tp->mmio_addr = ioaddr;
1197
43afb949
FR		 1198 tp->mii_if.dev = dev;
1199 tp->mii_if.mdio_read = __mdio_read;
1200 tp->mii_if.mdio_write = __mdio_write;
1201 // tp->mii_if.phy_id = XXX;
1202 tp->mii_if.phy_id_mask = 0x1f;
1203 tp->mii_if.reg_num_mask = 0x1f;
1204
890e8d0a
FR		 1205 sis190_irq_mask_and_ack(ioaddr);
1206
1207 sis190_soft_reset(ioaddr);
1208out:
1209 return dev;
1210
1211err_free_res_3:
1212 pci_release_regions(pdev);
1213err_pci_disable_2:
1214 pci_disable_device(pdev);
1215err_free_dev_1:
1216 free_netdev(dev);
1217err_out_0:
1218 dev = ERR_PTR(rc);
1219 goto out;
1220}
1221
1222static void sis190_tx_timeout(struct net_device *dev)
1223{
1224 struct sis190_private *tp = netdev_priv(dev);
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 u8 tmp8;
1227
1228 /* Disable Tx, if not already */
1229 tmp8 = SIS_R8(TxControl);
1230 if (tmp8 & CmdTxEnb)
1231 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1232
188f23ba
FR		 1233
1234 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1235 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1236
890e8d0a
FR		 1237 /* Disable interrupts by clearing the interrupt mask. */
1238 SIS_W32(IntrMask, 0x0000);
1239
1240 /* Stop a shared interrupt from scavenging while we are. */
1241 spin_lock_irq(&tp->lock);
1242 sis190_tx_clear(tp);
1243 spin_unlock_irq(&tp->lock);
1244
1245 /* ...and finally, reset everything. */
1246 sis190_hw_start(dev);
1247
1248 netif_wake_queue(dev);
1249}
1250
830fb7d2
FR		 1251static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1252 struct net_device *dev)
1253{
1254 struct sis190_private *tp = netdev_priv(dev);
1255 void __iomem *ioaddr = tp->mmio_addr;
1256 u16 sig;
1257 int i;
1258
1259 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1260 pci_name(pdev));
1261
1262 /* Check to see if there is a sane EEPROM */
1263 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1264
1265 if ((sig == 0xffff) || (sig == 0x0000)) {
1266 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1267 pci_name(pdev), sig);
1268 return -EIO;
1269 }
1270
1271 /* Get MAC address from EEPROM */
1272 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1273 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1274
1275 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w);
1276 }
1277
1278 return 0;
1279}
1280
1281/**
1282 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1283 * @pdev: PCI device
1284 * @dev: network device to get address for
1285 *
1286 * SiS965 model, use APC CMOS RAM to store MAC address.
1287 * APC CMOS RAM is accessed through ISA bridge.
1288 * MAC address is read into @net_dev->dev_addr.
1289 */
1290static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1291 struct net_device *dev)
1292{
1293 struct sis190_private *tp = netdev_priv(dev);
1294 struct pci_dev *isa_bridge;
1295 u8 reg, tmp8;
1296 int i;
1297
1298 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1299 pci_name(pdev));
1300
1301 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1302 if (!isa_bridge) {
1303 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1304 pci_name(pdev));
1305 return -EIO;
1306 }
1307
1308 /* Enable port 78h & 79h to access APC Registers. */
1309 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1310 reg = (tmp8 & ~0x02);
1311 pci_write_config_byte(isa_bridge, 0x48, reg);
1312 udelay(50);
1313 pci_read_config_byte(isa_bridge, 0x48, &reg);
1314
1315 for (i = 0; i < MAC_ADDR_LEN; i++) {
1316 outb(0x9 + i, 0x78);
1317 dev->dev_addr[i] = inb(0x79);
1318 }
1319
1320 outb(0x12, 0x78);
1321 reg = inb(0x79);
1322
1323 /* Restore the value to ISA Bridge */
1324 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1325 pci_dev_put(isa_bridge);
1326
1327 return 0;
1328}
1329
1330/**
1331 * sis190_init_rxfilter - Initialize the Rx filter
1332 * @dev: network device to initialize
1333 *
1334 * Set receive filter address to our MAC address
1335 * and enable packet filtering.
1336 */
1337static inline void sis190_init_rxfilter(struct net_device *dev)
1338{
1339 struct sis190_private *tp = netdev_priv(dev);
1340 void __iomem *ioaddr = tp->mmio_addr;
1341 u16 ctl;
1342 int i;
1343
1344 ctl = SIS_R16(RxMacControl);
1345 /*
1346 * Disable packet filtering before setting filter.
1347 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1348 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1349 */
1350 SIS_W16(RxMacControl, ctl & ~0x0f00);
1351
1352 for (i = 0; i < MAC_ADDR_LEN; i++)
1353 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1354
1355 SIS_W16(RxMacControl, ctl);
1356 SIS_PCI_COMMIT();
1357}
1358
1359static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1360{
1361 u8 from;
1362
1363 pci_read_config_byte(pdev, 0x73, &from);
1364
1365 return (from & 0x00000001) ?
1366 sis190_get_mac_addr_from_apc(pdev, dev) :
1367 sis190_get_mac_addr_from_eeprom(pdev, dev);
1368}
1369
890e8d0a
FR		 1370static void sis190_set_speed_auto(struct net_device *dev)
1371{
1372 struct sis190_private *tp = netdev_priv(dev);
1373 void __iomem *ioaddr = tp->mmio_addr;
1374 int val;
1375
1376 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1377
1378 val = mdio_read(ioaddr, MII_ADVERTISE);
1379
1380 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1381 // unchanged.
1382 mdio_write(ioaddr, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1383 ADVERTISE_100FULL | ADVERTISE_10FULL |
1384 ADVERTISE_100HALF | ADVERTISE_10HALF);
1385
1386 // Enable 1000 Full Mode.
1387 mdio_write(ioaddr, MII_CTRL1000, ADVERTISE_1000FULL);
1388
1389 // Enable auto-negotiation and restart auto-negotiation.
1390 mdio_write(ioaddr, MII_BMCR,
1391 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1392}
1393
43afb949
FR		 1394static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1395{
1396 struct sis190_private *tp = netdev_priv(dev);
1397
1398 return mii_ethtool_gset(&tp->mii_if, cmd);
1399}
1400
1401static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1402{
1403 struct sis190_private *tp = netdev_priv(dev);
1404
1405 return mii_ethtool_sset(&tp->mii_if, cmd);
1406}
1407
890e8d0a
FR		 1408static void sis190_get_drvinfo(struct net_device *dev,
1409 struct ethtool_drvinfo *info)
1410{
1411 struct sis190_private *tp = netdev_priv(dev);
1412
1413 strcpy(info->driver, DRV_NAME);
1414 strcpy(info->version, DRV_VERSION);
1415 strcpy(info->bus_info, pci_name(tp->pci_dev));
1416}
1417
1418static int sis190_get_regs_len(struct net_device *dev)
1419{
1420 return SIS190_REGS_SIZE;
1421}
1422
1423static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1424 void *p)
1425{
1426 struct sis190_private *tp = netdev_priv(dev);
1427 unsigned long flags;
1428
1429 if (regs->len > SIS190_REGS_SIZE)
1430 regs->len = SIS190_REGS_SIZE;
1431
1432 spin_lock_irqsave(&tp->lock, flags);
1433 memcpy_fromio(p, tp->mmio_addr, regs->len);
1434 spin_unlock_irqrestore(&tp->lock, flags);
1435}
1436
43afb949
FR		 1437static int sis190_nway_reset(struct net_device *dev)
1438{
1439 struct sis190_private *tp = netdev_priv(dev);
1440
1441 return mii_nway_restart(&tp->mii_if);
1442}
1443
890e8d0a
FR		 1444static u32 sis190_get_msglevel(struct net_device *dev)
1445{
1446 struct sis190_private *tp = netdev_priv(dev);
1447
1448 return tp->msg_enable;
1449}
1450
1451static void sis190_set_msglevel(struct net_device *dev, u32 value)
1452{
1453 struct sis190_private *tp = netdev_priv(dev);
1454
1455 tp->msg_enable = value;
1456}
1457
1458static struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1459 .get_settings = sis190_get_settings,
1460 .set_settings = sis190_set_settings,
890e8d0a
FR		 1461 .get_drvinfo = sis190_get_drvinfo,
1462 .get_regs_len = sis190_get_regs_len,
1463 .get_regs = sis190_get_regs,
1464 .get_link = ethtool_op_get_link,
1465 .get_msglevel = sis190_get_msglevel,
1466 .set_msglevel = sis190_set_msglevel,
43afb949 1467 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1468};
1469
43afb949
FR		 1470static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1471{
1472 struct sis190_private *tp = netdev_priv(dev);
1473
1474 return !netif_running(dev) ? -EINVAL :
1475 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1476}
1477
890e8d0a
FR		 1478static int __devinit sis190_init_one(struct pci_dev *pdev,
1479 const struct pci_device_id *ent)
1480{
1481 static int printed_version = 0;
1482 struct sis190_private *tp;
1483 struct net_device *dev;
1484 void __iomem *ioaddr;
830fb7d2 1485 int rc;
890e8d0a
FR		 1486
1487 if (!printed_version) {
1488 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1489 printed_version = 1;
1490 }
1491
1492 dev = sis190_init_board(pdev);
1493 if (IS_ERR(dev)) {
1494 rc = PTR_ERR(dev);
1495 goto out;
1496 }
1497
1498 tp = netdev_priv(dev);
1499 ioaddr = tp->mmio_addr;
1500
830fb7d2
FR		 1501 rc = sis190_get_mac_addr(pdev, dev);
1502 if (rc < 0)
1503 goto err_release_board;
890e8d0a 1504
830fb7d2 1505 sis190_init_rxfilter(dev);
890e8d0a
FR		 1506
1507 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1508
1509 dev->open = sis190_open;
1510 dev->stop = sis190_close;
43afb949 1511 dev->do_ioctl = sis190_ioctl;
890e8d0a
FR		 1512 dev->get_stats = sis190_get_stats;
1513 dev->tx_timeout = sis190_tx_timeout;
1514 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1515 dev->hard_start_xmit = sis190_start_xmit;
4405d3b5
FR		 1516#ifdef CONFIG_NET_POLL_CONTROLLER
1517 dev->poll_controller = sis190_netpoll;
1518#endif
890e8d0a
FR		 1519 dev->set_multicast_list = sis190_set_rx_mode;
1520 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1521 dev->irq = pdev->irq;
1522 dev->base_addr = (unsigned long) 0xdead;
1523
1524 spin_lock_init(&tp->lock);
1525 rc = register_netdev(dev);
830fb7d2
FR		 1526 if (rc < 0)
1527 goto err_release_board;
890e8d0a
FR		 1528
1529 pci_set_drvdata(pdev, dev);
1530
1531 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1532 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1533 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1534 ioaddr, dev->irq,
1535 dev->dev_addr[0], dev->dev_addr[1],
1536 dev->dev_addr[2], dev->dev_addr[3],
1537 dev->dev_addr[4], dev->dev_addr[5]);
1538
1539 netif_carrier_off(dev);
1540
1541 sis190_set_speed_auto(dev);
1542out:
1543 return rc;
830fb7d2
FR		 1544
1545err_release_board:
1546 sis190_release_board(pdev);
1547 goto out;
890e8d0a
FR		 1548}
1549
1550static void __devexit sis190_remove_one(struct pci_dev *pdev)
1551{
1552 struct net_device *dev = pci_get_drvdata(pdev);
1553
1554 unregister_netdev(dev);
1555 sis190_release_board(pdev);
1556 pci_set_drvdata(pdev, NULL);
1557}
1558
1559static struct pci_driver sis190_pci_driver = {
1560 .name = DRV_NAME,
1561 .id_table = sis190_pci_tbl,
1562 .probe = sis190_init_one,
1563 .remove = __devexit_p(sis190_remove_one),
1564};
1565
1566static int __init sis190_init_module(void)
1567{
1568 return pci_module_init(&sis190_pci_driver);
1569}
1570
1571static void __exit sis190_cleanup_module(void)
1572{
1573 pci_unregister_driver(&sis190_pci_driver);
1574}
1575
1576module_init(sis190_init_module);
1577module_exit(sis190_cleanup_module);