projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] sis190: make 10Mbps the default when handling the StationControl register
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / sis190.c
CommitLineData
890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/netdevice.h>
43afb949 25#include <linux/rtnetlink.h>
890e8d0a
FR		 26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/pci.h>
29#include <linux/mii.h>
30#include <linux/delay.h>
31#include <linux/crc32.h>
32#include <linux/dma-mapping.h>
33#include <asm/irq.h>
34
35#define net_drv(p, arg...) if (netif_msg_drv(p)) \
36 printk(arg)
37#define net_probe(p, arg...) if (netif_msg_probe(p)) \
38 printk(arg)
39#define net_link(p, arg...) if (netif_msg_link(p)) \
40 printk(arg)
41#define net_intr(p, arg...) if (netif_msg_intr(p)) \
42 printk(arg)
43#define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
44 printk(arg)
45
fcb9821d
FR		 46#define PHY_MAX_ADDR 32
47#define PHY_ID_ANY 0x1f
48#define MII_REG_ANY 0x1f
49
890e8d0a
FR		 50#ifdef CONFIG_SIS190_NAPI
51#define NAPI_SUFFIX "-NAPI"
52#else
53#define NAPI_SUFFIX ""
54#endif
55
56#define DRV_VERSION "1.2" NAPI_SUFFIX
57#define DRV_NAME "sis190"
58#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
59#define PFX DRV_NAME ": "
60
61#ifdef CONFIG_SIS190_NAPI
62#define sis190_rx_skb netif_receive_skb
63#define sis190_rx_quota(count, quota) min(count, quota)
64#else
65#define sis190_rx_skb netif_rx
66#define sis190_rx_quota(count, quota) count
67#endif
68
69#define MAC_ADDR_LEN 6
70
bcad5e53
FR		 71#define NUM_TX_DESC 64 /* [8..1024] */
72#define NUM_RX_DESC 64 /* [8..8192] */
890e8d0a
FR		 73#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75#define RX_BUF_SIZE 1536
8b5641d4 76#define RX_BUF_MASK 0xfff8
890e8d0a
FR		 77
78#define SIS190_REGS_SIZE 0x80
79#define SIS190_TX_TIMEOUT (6*HZ)
80#define SIS190_PHY_TIMEOUT (10*HZ)
81#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
83 NETIF_MSG_IFDOWN)
84
85/* Enhanced PHY access register bit definitions */
86#define EhnMIIread 0x0000
87#define EhnMIIwrite 0x0020
88#define EhnMIIdataShift 16
89#define EhnMIIpmdShift 6 /* 7016 only */
90#define EhnMIIregShift 11
91#define EhnMIIreq 0x0010
92#define EhnMIInotDone 0x0010
93
94/* Write/read MMIO register */
95#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
96#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
97#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
98#define SIS_R8(reg) readb (ioaddr + (reg))
99#define SIS_R16(reg) readw (ioaddr + (reg))
100#define SIS_R32(reg) readl (ioaddr + (reg))
101
102#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
103
104enum sis190_registers {
105 TxControl = 0x00,
106 TxDescStartAddr = 0x04,
188f23ba
FR		 107 rsv0 = 0x08, // reserved
108 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 109 RxControl = 0x10,
110 RxDescStartAddr = 0x14,
188f23ba
FR		 111 rsv1 = 0x18, // reserved
112 RxSts = 0x1c, // unused
890e8d0a
FR		 113 IntrStatus = 0x20,
114 IntrMask = 0x24,
115 IntrControl = 0x28,
188f23ba
FR		 116 IntrTimer = 0x2c, // unused (Interupt Timer)
117 PMControl = 0x30, // unused (Power Mgmt Control/Status)
118 rsv2 = 0x34, // reserved
890e8d0a
FR		 119 ROMControl = 0x38,
120 ROMInterface = 0x3c,
121 StationControl = 0x40,
122 GMIIControl = 0x44,
188f23ba
FR		 123 GIoCR = 0x48, // unused (GMAC IO Compensation)
124 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 125 TxMacControl = 0x50,
188f23ba
FR		 126 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
127 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
128 rsv3 = 0x5c, // reserved
890e8d0a
FR		 129 RxMacControl = 0x60,
130 RxMacAddr = 0x62,
131 RxHashTable = 0x68,
132 // Undocumented = 0x6c,
188f23ba
FR		 133 RxWolCtrl = 0x70,
134 RxWolData = 0x74, // unused (Rx WOL Data Access)
135 RxMPSControl = 0x78, // unused (Rx MPS Control)
136 rsv4 = 0x7c, // reserved
890e8d0a
FR		 137};
138
139enum sis190_register_content {
140 /* IntrStatus */
141 SoftInt = 0x40000000, // unused
142 Timeup = 0x20000000, // unused
143 PauseFrame = 0x00080000, // unused
144 MagicPacket = 0x00040000, // unused
145 WakeupFrame = 0x00020000, // unused
146 LinkChange = 0x00010000,
147 RxQEmpty = 0x00000080,
148 RxQInt = 0x00000040,
149 TxQ1Empty = 0x00000020, // unused
150 TxQ1Int = 0x00000010,
151 TxQ0Empty = 0x00000008, // unused
152 TxQ0Int = 0x00000004,
153 RxHalt = 0x00000002,
154 TxHalt = 0x00000001,
155
890e8d0a
FR		 156 /* {Rx/Tx}CmdBits */
157 CmdReset = 0x10,
158 CmdRxEnb = 0x08, // unused
159 CmdTxEnb = 0x01,
160 RxBufEmpty = 0x01, // unused
161
162 /* Cfg9346Bits */
163 Cfg9346_Lock = 0x00, // unused
164 Cfg9346_Unlock = 0xc0, // unused
165
166 /* RxMacControl */
167 AcceptErr = 0x20, // unused
168 AcceptRunt = 0x10, // unused
169 AcceptBroadcast = 0x0800,
170 AcceptMulticast = 0x0400,
171 AcceptMyPhys = 0x0200,
172 AcceptAllPhys = 0x0100,
173
174 /* RxConfigBits */
175 RxCfgFIFOShift = 13,
176 RxCfgDMAShift = 8, // 0x1a in RxControl ?
177
178 /* TxConfigBits */
179 TxInterFrameGapShift = 24,
180 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
181
890e8d0a
FR		 182 LinkStatus = 0x02, // unused
183 FullDup = 0x01, // unused
184
185 /* TBICSRBit */
186 TBILinkOK = 0x02000000, // unused
187};
188
189struct TxDesc {
3cec93c7
FR		 190 __le32 PSize;
191 __le32 status;
192 __le32 addr;
193 __le32 size;
890e8d0a
FR		 194};
195
196struct RxDesc {
3cec93c7
FR		 197 __le32 PSize;
198 __le32 status;
199 __le32 addr;
200 __le32 size;
890e8d0a
FR		 201};
202
203enum _DescStatusBit {
204 /* _Desc.status */
bcad5e53
FR		 205 OWNbit = 0x80000000, // RXOWN/TXOWN
206 INTbit = 0x40000000, // RXINT/TXINT
207 CRCbit = 0x00020000, // CRCOFF/CRCEN
208 PADbit = 0x00010000, // PREADD/PADEN
890e8d0a 209 /* _Desc.size */
bcad5e53
FR		 210 RingEnd = 0x80000000,
211 /* TxDesc.status */
212 LSEN = 0x08000000, // TSO ? -- FR
213 IPCS = 0x04000000,
214 TCPCS = 0x02000000,
215 UDPCS = 0x01000000,
216 BSTEN = 0x00800000,
217 EXTEN = 0x00400000,
218 DEFEN = 0x00200000,
219 BKFEN = 0x00100000,
220 CRSEN = 0x00080000,
221 COLEN = 0x00040000,
222 THOL3 = 0x30000000,
223 THOL2 = 0x20000000,
224 THOL1 = 0x10000000,
225 THOL0 = 0x00000000,
226 /* RxDesc.status */
227 IPON = 0x20000000,
228 TCPON = 0x10000000,
229 UDPON = 0x08000000,
230 Wakup = 0x00400000,
231 Magic = 0x00200000,
232 Pause = 0x00100000,
233 DEFbit = 0x00200000,
234 BCAST = 0x000c0000,
235 MCAST = 0x00080000,
236 UCAST = 0x00040000,
237 /* RxDesc.PSize */
238 TAGON = 0x80000000,
239 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
240 ABORT = 0x00800000,
241 SHORT = 0x00400000,
242 LIMIT = 0x00200000,
243 MIIER = 0x00100000,
244 OVRUN = 0x00080000,
245 NIBON = 0x00040000,
246 COLON = 0x00020000,
247 CRCOK = 0x00010000,
890e8d0a 248 RxSizeMask = 0x0000ffff
bcad5e53
FR		 249 /*
250 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
251 * provide two (unused with Linux) Tx queues. No publically
252 * available documentation alas.
253 */
890e8d0a
FR		 254};
255
40292fb0
FR		 256enum sis190_eeprom_access_register_bits {
257 EECS = 0x00000001, // unused
258 EECLK = 0x00000002, // unused
259 EEDO = 0x00000008, // unused
260 EEDI = 0x00000004, // unused
261 EEREQ = 0x00000080,
262 EEROP = 0x00000200,
263 EEWOP = 0x00000100 // unused
264};
265
830fb7d2
FR		 266/* EEPROM Addresses */
267enum sis190_eeprom_address {
268 EEPROMSignature = 0x00,
269 EEPROMCLK = 0x01, // unused
270 EEPROMInfo = 0x02,
271 EEPROMMACAddr = 0x03
272};
273
900eb9d6
FR		 274enum sis190_feature {
275 F_HAS_RGMII = 1,
276 F_PHY_88E1111 = 2
277};
278
890e8d0a
FR		 279struct sis190_private {
280 void __iomem *mmio_addr;
281 struct pci_dev *pci_dev;
282 struct net_device_stats stats;
283 spinlock_t lock;
284 u32 rx_buf_sz;
285 u32 cur_rx;
286 u32 cur_tx;
287 u32 dirty_rx;
288 u32 dirty_tx;
289 dma_addr_t rx_dma;
290 dma_addr_t tx_dma;
291 struct RxDesc *RxDescRing;
292 struct TxDesc *TxDescRing;
293 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
294 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
295 struct work_struct phy_task;
296 struct timer_list timer;
297 u32 msg_enable;
43afb949 298 struct mii_if_info mii_if;
fcb9821d 299 struct list_head first_phy;
900eb9d6 300 u32 features;
fcb9821d
FR		 301};
302
303struct sis190_phy {
304 struct list_head list;
305 int phy_id;
306 u16 id[2];
307 u16 status;
308 u8 type;
309};
310
311enum sis190_phy_type {
312 UNKNOWN = 0x00,
313 HOME = 0x01,
314 LAN = 0x02,
315 MIX = 0x03
316};
317
318static struct mii_chip_info {
319 const char *name;
320 u16 id[2];
321 unsigned int type;
900eb9d6 322 u32 feature;
fcb9821d 323} mii_chip_table[] = {
900eb9d6
FR		 324 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, 0 },
325 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
326 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
327 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
fcb9821d 328 { NULL, }
890e8d0a
FR		 329};
330
331const static struct {
332 const char *name;
333 u8 version; /* depend on docs */
334 u32 RxConfigMask; /* clear the bits supported by this chip */
335} sis_chip_info[] = {
336 { DRV_NAME, 0x00, 0xff7e1880, },
337};
338
339static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
340 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
341 { 0, },
342};
343
344MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
345
346static int rx_copybreak = 200;
347
348static struct {
349 u32 msg_enable;
350} debug = { -1 };
351
352MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
353module_param(rx_copybreak, int, 0);
354MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
355module_param_named(debug, debug.msg_enable, int, 0);
356MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
357MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
358MODULE_VERSION(DRV_VERSION);
359MODULE_LICENSE("GPL");
360
361static const u32 sis190_intr_mask =
21461380 362 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
890e8d0a
FR		 363
364/*
365 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
366 * The chips use a 64 element hash table based on the Ethernet CRC.
367 */
368static int multicast_filter_limit = 32;
369
370static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
371{
372 unsigned int i;
373
374 SIS_W32(GMIIControl, ctl);
375
376 msleep(1);
377
378 for (i = 0; i < 100; i++) {
379 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
380 break;
381 msleep(1);
382 }
383
384 if (i > 999)
385 printk(KERN_ERR PFX "PHY command failed !\n");
386}
387
9ede109b 388static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
890e8d0a 389{
890e8d0a 390 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
9ede109b 391 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
890e8d0a
FR		 392 (((u32) val) << EhnMIIdataShift));
393}
394
9ede109b 395static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
890e8d0a 396{
890e8d0a 397 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
9ede109b 398 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
890e8d0a
FR		 399
400 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
401}
402
43afb949
FR		 403static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
404{
405 struct sis190_private *tp = netdev_priv(dev);
406
9ede109b 407 mdio_write(tp->mmio_addr, phy_id, reg, val);
43afb949
FR		 408}
409
410static int __mdio_read(struct net_device *dev, int phy_id, int reg)
411{
412 struct sis190_private *tp = netdev_priv(dev);
413
9ede109b 414 return mdio_read(tp->mmio_addr, phy_id, reg);
43afb949
FR		 415}
416
fc10c39d
FR		 417static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
418{
419 mdio_read(ioaddr, phy_id, reg);
420 return mdio_read(ioaddr, phy_id, reg);
421}
422
40292fb0 423static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 424{
40292fb0 425 u16 data = 0xffff;
890e8d0a 426 unsigned int i;
890e8d0a
FR		 427
428 if (!(SIS_R32(ROMControl) & 0x0002))
429 return 0;
430
40292fb0 431 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 432
433 for (i = 0; i < 200; i++) {
40292fb0
FR		 434 if (!(SIS_R32(ROMInterface) & EEREQ)) {
435 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 436 break;
40292fb0 437 }
890e8d0a
FR		 438 msleep(1);
439 }
440
890e8d0a
FR		 441 return data;
442}
443
444static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
445{
446 SIS_W32(IntrMask, 0x00);
447 SIS_W32(IntrStatus, 0xffffffff);
448 SIS_PCI_COMMIT();
449}
450
451static void sis190_asic_down(void __iomem *ioaddr)
452{
453 /* Stop the chip's Tx and Rx DMA processes. */
454
455 SIS_W32(TxControl, 0x1a00);
456 SIS_W32(RxControl, 0x1a00);
457
458 sis190_irq_mask_and_ack(ioaddr);
459}
460
461static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
462{
463 desc->size |= cpu_to_le32(RingEnd);
464}
465
466static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
467{
468 u32 eor = le32_to_cpu(desc->size) & RingEnd;
469
470 desc->PSize = 0x0;
8b5641d4 471 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
890e8d0a
FR		 472 wmb();
473 desc->status = cpu_to_le32(OWNbit | INTbit);
474}
475
476static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
477 u32 rx_buf_sz)
478{
479 desc->addr = cpu_to_le32(mapping);
480 sis190_give_to_asic(desc, rx_buf_sz);
481}
482
483static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
484{
485 desc->PSize = 0x0;
486 desc->addr = 0xdeadbeef;
487 desc->size &= cpu_to_le32(RingEnd);
488 wmb();
489 desc->status = 0x0;
490}
491
492static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
493 struct RxDesc *desc, u32 rx_buf_sz)
494{
495 struct sk_buff *skb;
496 dma_addr_t mapping;
497 int ret = 0;
498
499 skb = dev_alloc_skb(rx_buf_sz);
500 if (!skb)
501 goto err_out;
502
503 *sk_buff = skb;
504
505 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
506 PCI_DMA_FROMDEVICE);
507
508 sis190_map_to_asic(desc, mapping, rx_buf_sz);
509out:
510 return ret;
511
512err_out:
513 ret = -ENOMEM;
514 sis190_make_unusable_by_asic(desc);
515 goto out;
516}
517
518static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
519 u32 start, u32 end)
520{
521 u32 cur;
522
523 for (cur = start; cur < end; cur++) {
524 int ret, i = cur % NUM_RX_DESC;
525
526 if (tp->Rx_skbuff[i])
527 continue;
528
529 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
530 tp->RxDescRing + i, tp->rx_buf_sz);
531 if (ret < 0)
532 break;
533 }
534 return cur - start;
535}
536
537static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
538 struct RxDesc *desc, int rx_buf_sz)
539{
540 int ret = -1;
541
542 if (pkt_size < rx_copybreak) {
543 struct sk_buff *skb;
544
545 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
546 if (skb) {
547 skb_reserve(skb, NET_IP_ALIGN);
548 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
549 *sk_buff = skb;
550 sis190_give_to_asic(desc, rx_buf_sz);
551 ret = 0;
552 }
553 }
554 return ret;
555}
556
bcad5e53
FR		 557static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
558{
559#define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
560
561 if ((status & CRCOK) && !(status & ErrMask))
562 return 0;
563
564 if (!(status & CRCOK))
565 stats->rx_crc_errors++;
566 else if (status & OVRUN)
567 stats->rx_over_errors++;
568 else if (status & (SHORT | LIMIT))
569 stats->rx_length_errors++;
570 else if (status & (MIIER | NIBON | COLON))
571 stats->rx_frame_errors++;
572
573 stats->rx_errors++;
574 return -1;
575}
576
890e8d0a
FR		 577static int sis190_rx_interrupt(struct net_device *dev,
578 struct sis190_private *tp, void __iomem *ioaddr)
579{
580 struct net_device_stats *stats = &tp->stats;
581 u32 rx_left, cur_rx = tp->cur_rx;
582 u32 delta, count;
583
584 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
585 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
586
587 for (; rx_left > 0; rx_left--, cur_rx++) {
588 unsigned int entry = cur_rx % NUM_RX_DESC;
589 struct RxDesc *desc = tp->RxDescRing + entry;
590 u32 status;
591
592 if (desc->status & OWNbit)
593 break;
594
595 status = le32_to_cpu(desc->PSize);
596
597 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
598 // status);
599
bcad5e53 600 if (sis190_rx_pkt_err(status, stats) < 0)
890e8d0a 601 sis190_give_to_asic(desc, tp->rx_buf_sz);
bcad5e53 602 else {
890e8d0a
FR		 603 struct sk_buff *skb = tp->Rx_skbuff[entry];
604 int pkt_size = (status & RxSizeMask) - 4;
605 void (*pci_action)(struct pci_dev *, dma_addr_t,
606 size_t, int) = pci_dma_sync_single_for_device;
607
608 if (unlikely(pkt_size > tp->rx_buf_sz)) {
609 net_intr(tp, KERN_INFO
610 "%s: (frag) status = %08x.\n",
611 dev->name, status);
612 stats->rx_dropped++;
613 stats->rx_length_errors++;
614 sis190_give_to_asic(desc, tp->rx_buf_sz);
615 continue;
616 }
617
618 pci_dma_sync_single_for_cpu(tp->pci_dev,
619 le32_to_cpu(desc->addr), tp->rx_buf_sz,
620 PCI_DMA_FROMDEVICE);
621
622 if (sis190_try_rx_copy(&skb, pkt_size, desc,
623 tp->rx_buf_sz)) {
624 pci_action = pci_unmap_single;
625 tp->Rx_skbuff[entry] = NULL;
626 sis190_make_unusable_by_asic(desc);
627 }
628
629 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
630 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
631
632 skb->dev = dev;
633 skb_put(skb, pkt_size);
634 skb->protocol = eth_type_trans(skb, dev);
635
636 sis190_rx_skb(skb);
637
638 dev->last_rx = jiffies;
890e8d0a 639 stats->rx_packets++;
bcad5e53
FR		 640 stats->rx_bytes += pkt_size;
641 if ((status & BCAST) == MCAST)
642 stats->multicast++;
890e8d0a
FR		 643 }
644 }
645 count = cur_rx - tp->cur_rx;
646 tp->cur_rx = cur_rx;
647
648 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
649 if (!delta && count && netif_msg_intr(tp))
650 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
651 tp->dirty_rx += delta;
652
653 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
654 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
655
656 return count;
657}
658
659static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
660 struct TxDesc *desc)
661{
662 unsigned int len;
663
664 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
665
666 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
667
668 memset(desc, 0x00, sizeof(*desc));
669}
670
671static void sis190_tx_interrupt(struct net_device *dev,
672 struct sis190_private *tp, void __iomem *ioaddr)
673{
674 u32 pending, dirty_tx = tp->dirty_tx;
675 /*
676 * It would not be needed if queueing was allowed to be enabled
677 * again too early (hint: think preempt and unclocked smp systems).
678 */
679 unsigned int queue_stopped;
680
681 smp_rmb();
682 pending = tp->cur_tx - dirty_tx;
683 queue_stopped = (pending == NUM_TX_DESC);
684
685 for (; pending; pending--, dirty_tx++) {
686 unsigned int entry = dirty_tx % NUM_TX_DESC;
687 struct TxDesc *txd = tp->TxDescRing + entry;
688 struct sk_buff *skb;
689
690 if (le32_to_cpu(txd->status) & OWNbit)
691 break;
692
693 skb = tp->Tx_skbuff[entry];
694
695 tp->stats.tx_packets++;
696 tp->stats.tx_bytes += skb->len;
697
698 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
699 tp->Tx_skbuff[entry] = NULL;
700 dev_kfree_skb_irq(skb);
701 }
702
703 if (tp->dirty_tx != dirty_tx) {
704 tp->dirty_tx = dirty_tx;
705 smp_wmb();
706 if (queue_stopped)
707 netif_wake_queue(dev);
708 }
709}
710
711/*
712 * The interrupt handler does all of the Rx thread work and cleans up after
713 * the Tx thread.
714 */
715static irqreturn_t sis190_interrupt(int irq, void *__dev, struct pt_regs *regs)
716{
717 struct net_device *dev = __dev;
718 struct sis190_private *tp = netdev_priv(dev);
719 void __iomem *ioaddr = tp->mmio_addr;
720 unsigned int handled = 0;
721 u32 status;
722
723 status = SIS_R32(IntrStatus);
724
725 if ((status == 0xffffffff) || !status)
726 goto out;
727
728 handled = 1;
729
730 if (unlikely(!netif_running(dev))) {
731 sis190_asic_down(ioaddr);
732 goto out;
733 }
734
735 SIS_W32(IntrStatus, status);
736
737 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
738
739 if (status & LinkChange) {
740 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
741 schedule_work(&tp->phy_task);
742 }
743
744 if (status & RxQInt)
745 sis190_rx_interrupt(dev, tp, ioaddr);
746
747 if (status & TxQ0Int)
748 sis190_tx_interrupt(dev, tp, ioaddr);
749out:
750 return IRQ_RETVAL(handled);
751}
752
4405d3b5
FR		 753#ifdef CONFIG_NET_POLL_CONTROLLER
754static void sis190_netpoll(struct net_device *dev)
755{
756 struct sis190_private *tp = netdev_priv(dev);
757 struct pci_dev *pdev = tp->pci_dev;
758
759 disable_irq(pdev->irq);
760 sis190_interrupt(pdev->irq, dev, NULL);
761 enable_irq(pdev->irq);
762}
763#endif
764
890e8d0a
FR		 765static void sis190_free_rx_skb(struct sis190_private *tp,
766 struct sk_buff **sk_buff, struct RxDesc *desc)
767{
768 struct pci_dev *pdev = tp->pci_dev;
769
770 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
771 PCI_DMA_FROMDEVICE);
772 dev_kfree_skb(*sk_buff);
773 *sk_buff = NULL;
774 sis190_make_unusable_by_asic(desc);
775}
776
777static void sis190_rx_clear(struct sis190_private *tp)
778{
779 unsigned int i;
780
781 for (i = 0; i < NUM_RX_DESC; i++) {
782 if (!tp->Rx_skbuff[i])
783 continue;
784 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
785 }
786}
787
788static void sis190_init_ring_indexes(struct sis190_private *tp)
789{
790 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
791}
792
793static int sis190_init_ring(struct net_device *dev)
794{
795 struct sis190_private *tp = netdev_priv(dev);
796
797 sis190_init_ring_indexes(tp);
798
799 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
800 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
801
802 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
803 goto err_rx_clear;
804
805 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
806
807 return 0;
808
809err_rx_clear:
810 sis190_rx_clear(tp);
811 return -ENOMEM;
812}
813
814static void sis190_set_rx_mode(struct net_device *dev)
815{
816 struct sis190_private *tp = netdev_priv(dev);
817 void __iomem *ioaddr = tp->mmio_addr;
818 unsigned long flags;
819 u32 mc_filter[2]; /* Multicast hash filter */
820 u16 rx_mode;
821
822 if (dev->flags & IFF_PROMISC) {
823 /* Unconditionally log net taps. */
824 net_drv(tp, KERN_NOTICE "%s: Promiscuous mode enabled.\n",
825 dev->name);
826 rx_mode =
827 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
828 AcceptAllPhys;
829 mc_filter[1] = mc_filter[0] = 0xffffffff;
830 } else if ((dev->mc_count > multicast_filter_limit) ||
831 (dev->flags & IFF_ALLMULTI)) {
832 /* Too many to filter perfectly -- accept all multicasts. */
833 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
834 mc_filter[1] = mc_filter[0] = 0xffffffff;
835 } else {
836 struct dev_mc_list *mclist;
837 unsigned int i;
838
839 rx_mode = AcceptBroadcast | AcceptMyPhys;
840 mc_filter[1] = mc_filter[0] = 0;
841 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
842 i++, mclist = mclist->next) {
843 int bit_nr =
844 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
845 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
846 rx_mode |= AcceptMulticast;
847 }
848 }
849
850 spin_lock_irqsave(&tp->lock, flags);
851
852 SIS_W16(RxMacControl, rx_mode | 0x2);
853 SIS_W32(RxHashTable, mc_filter[0]);
854 SIS_W32(RxHashTable + 4, mc_filter[1]);
855
856 spin_unlock_irqrestore(&tp->lock, flags);
857}
858
859static void sis190_soft_reset(void __iomem *ioaddr)
860{
861 SIS_W32(IntrControl, 0x8000);
862 SIS_PCI_COMMIT();
863 msleep(1);
864 SIS_W32(IntrControl, 0x0);
865 sis190_asic_down(ioaddr);
866 msleep(1);
867}
868
869static void sis190_hw_start(struct net_device *dev)
870{
871 struct sis190_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873
874 sis190_soft_reset(ioaddr);
875
876 SIS_W32(TxDescStartAddr, tp->tx_dma);
877 SIS_W32(RxDescStartAddr, tp->rx_dma);
878
879 SIS_W32(IntrStatus, 0xffffffff);
880 SIS_W32(IntrMask, 0x0);
890e8d0a
FR		 881 SIS_W32(GMIIControl, 0x0);
882 SIS_W32(TxMacControl, 0x60);
883 SIS_W16(RxMacControl, 0x02);
884 SIS_W32(RxHashTable, 0x0);
885 SIS_W32(0x6c, 0x0);
188f23ba
FR		 886 SIS_W32(RxWolCtrl, 0x0);
887 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 888
889 SIS_PCI_COMMIT();
890
891 sis190_set_rx_mode(dev);
892
893 /* Enable all known interrupts by setting the interrupt mask. */
894 SIS_W32(IntrMask, sis190_intr_mask);
895
896 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
897 SIS_W32(RxControl, 0x1a1d);
898
899 netif_start_queue(dev);
900}
901
902static void sis190_phy_task(void * data)
903{
904 struct net_device *dev = data;
905 struct sis190_private *tp = netdev_priv(dev);
906 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 907 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 908 u16 val;
909
43afb949
FR		 910 rtnl_lock();
911
9ede109b 912 val = mdio_read(ioaddr, phy_id, MII_BMCR);
890e8d0a
FR		 913 if (val & BMCR_RESET) {
914 // FIXME: needlessly high ? -- FR 02/07/2005
915 mod_timer(&tp->timer, jiffies + HZ/10);
fc10c39d
FR		 916 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
917 BMSR_ANEGCOMPLETE)) {
890e8d0a
FR		 918 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
919 dev->name);
21461380 920 netif_carrier_off(dev);
9ede109b 921 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
890e8d0a
FR		 922 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
923 } else {
924 /* Rejoice ! */
925 struct {
926 int val;
6614a6dc 927 u32 ctl;
890e8d0a 928 const char *msg;
890e8d0a 929 } reg31[] = {
6614a6dc
FR		 930 { LPA_1000XFULL | LPA_SLCT, 0x07000c00 | 0x00001000,
931 "1000 Mbps Full Duplex" },
932 { LPA_1000XHALF | LPA_SLCT, 0x07000c00,
933 "1000 Mbps Half Duplex" },
934 { LPA_100FULL, 0x04000800 | 0x00001000,
935 "100 Mbps Full Duplex" },
936 { LPA_100HALF, 0x04000800,
937 "100 Mbps Half Duplex" },
938 { LPA_10FULL, 0x04000400 | 0x00001000,
939 "10 Mbps Full Duplex" },
940 { LPA_10HALF, 0x04000400,
941 "10 Mbps Half Duplex" },
942 { 0, 0x04000400, "unknown" }
943 }, *p;
8348b4db 944 u16 adv;
890e8d0a 945
9ede109b 946 val = mdio_read(ioaddr, phy_id, 0x1f);
890e8d0a
FR		 947 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
948
9ede109b 949 val = mdio_read(ioaddr, phy_id, MII_LPA);
8348b4db
FR		 950 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
951 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
952 dev->name, val, adv);
953
954 val &= adv;
890e8d0a 955
6614a6dc 956 for (p = reg31; p->val; p++) {
890e8d0a
FR		 957 if ((val & p->val) == p->val)
958 break;
959 }
6614a6dc
FR		 960
961 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
962
963 SIS_W32(StationControl, p->ctl);
964
890e8d0a
FR		 965 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
966 p->msg);
967 netif_carrier_on(dev);
968 }
43afb949
FR		 969
970 rtnl_unlock();
890e8d0a
FR		 971}
972
973static void sis190_phy_timer(unsigned long __opaque)
974{
975 struct net_device *dev = (struct net_device *)__opaque;
976 struct sis190_private *tp = netdev_priv(dev);
977
978 if (likely(netif_running(dev)))
979 schedule_work(&tp->phy_task);
980}
981
982static inline void sis190_delete_timer(struct net_device *dev)
983{
984 struct sis190_private *tp = netdev_priv(dev);
985
986 del_timer_sync(&tp->timer);
987}
988
989static inline void sis190_request_timer(struct net_device *dev)
990{
991 struct sis190_private *tp = netdev_priv(dev);
992 struct timer_list *timer = &tp->timer;
993
994 init_timer(timer);
995 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
996 timer->data = (unsigned long)dev;
997 timer->function = sis190_phy_timer;
998 add_timer(timer);
999}
1000
1001static void sis190_set_rxbufsize(struct sis190_private *tp,
1002 struct net_device *dev)
1003{
1004 unsigned int mtu = dev->mtu;
1005
1006 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
8b5641d4
FR		 1007 /* RxDesc->size has a licence to kill the lower bits */
1008 if (tp->rx_buf_sz & 0x07) {
1009 tp->rx_buf_sz += 8;
1010 tp->rx_buf_sz &= RX_BUF_MASK;
1011 }
890e8d0a
FR		 1012}
1013
1014static int sis190_open(struct net_device *dev)
1015{
1016 struct sis190_private *tp = netdev_priv(dev);
1017 struct pci_dev *pdev = tp->pci_dev;
1018 int rc = -ENOMEM;
1019
1020 sis190_set_rxbufsize(tp, dev);
1021
1022 /*
1023 * Rx and Tx descriptors need 256 bytes alignment.
1024 * pci_alloc_consistent() guarantees a stronger alignment.
1025 */
1026 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1027 if (!tp->TxDescRing)
1028 goto out;
1029
1030 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1031 if (!tp->RxDescRing)
1032 goto err_free_tx_0;
1033
1034 rc = sis190_init_ring(dev);
1035 if (rc < 0)
1036 goto err_free_rx_1;
1037
1038 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1039
1040 sis190_request_timer(dev);
1041
1042 rc = request_irq(dev->irq, sis190_interrupt, SA_SHIRQ, dev->name, dev);
1043 if (rc < 0)
1044 goto err_release_timer_2;
1045
1046 sis190_hw_start(dev);
1047out:
1048 return rc;
1049
1050err_release_timer_2:
1051 sis190_delete_timer(dev);
1052 sis190_rx_clear(tp);
1053err_free_rx_1:
1054 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1055 tp->rx_dma);
1056err_free_tx_0:
1057 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1058 tp->tx_dma);
1059 goto out;
1060}
1061
1062static void sis190_tx_clear(struct sis190_private *tp)
1063{
1064 unsigned int i;
1065
1066 for (i = 0; i < NUM_TX_DESC; i++) {
1067 struct sk_buff *skb = tp->Tx_skbuff[i];
1068
1069 if (!skb)
1070 continue;
1071
1072 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1073 tp->Tx_skbuff[i] = NULL;
1074 dev_kfree_skb(skb);
1075
1076 tp->stats.tx_dropped++;
1077 }
1078 tp->cur_tx = tp->dirty_tx = 0;
1079}
1080
1081static void sis190_down(struct net_device *dev)
1082{
1083 struct sis190_private *tp = netdev_priv(dev);
1084 void __iomem *ioaddr = tp->mmio_addr;
1085 unsigned int poll_locked = 0;
1086
1087 sis190_delete_timer(dev);
1088
1089 netif_stop_queue(dev);
1090
1091 flush_scheduled_work();
1092
1093 do {
1094 spin_lock_irq(&tp->lock);
1095
1096 sis190_asic_down(ioaddr);
1097
1098 spin_unlock_irq(&tp->lock);
1099
1100 synchronize_irq(dev->irq);
1101
1102 if (!poll_locked) {
1103 netif_poll_disable(dev);
1104 poll_locked++;
1105 }
1106
1107 synchronize_sched();
1108
1109 } while (SIS_R32(IntrMask));
1110
1111 sis190_tx_clear(tp);
1112 sis190_rx_clear(tp);
1113}
1114
1115static int sis190_close(struct net_device *dev)
1116{
1117 struct sis190_private *tp = netdev_priv(dev);
1118 struct pci_dev *pdev = tp->pci_dev;
1119
1120 sis190_down(dev);
1121
1122 free_irq(dev->irq, dev);
1123
1124 netif_poll_enable(dev);
1125
1126 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1127 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1128
1129 tp->TxDescRing = NULL;
1130 tp->RxDescRing = NULL;
1131
1132 return 0;
1133}
1134
1135static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1136{
1137 struct sis190_private *tp = netdev_priv(dev);
1138 void __iomem *ioaddr = tp->mmio_addr;
1139 u32 len, entry, dirty_tx;
1140 struct TxDesc *desc;
1141 dma_addr_t mapping;
1142
1143 if (unlikely(skb->len < ETH_ZLEN)) {
1144 skb = skb_padto(skb, ETH_ZLEN);
1145 if (!skb) {
1146 tp->stats.tx_dropped++;
1147 goto out;
1148 }
1149 len = ETH_ZLEN;
1150 } else {
1151 len = skb->len;
1152 }
1153
1154 entry = tp->cur_tx % NUM_TX_DESC;
1155 desc = tp->TxDescRing + entry;
1156
1157 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1158 netif_stop_queue(dev);
1159 net_tx_err(tp, KERN_ERR PFX
1160 "%s: BUG! Tx Ring full when queue awake!\n",
1161 dev->name);
1162 return NETDEV_TX_BUSY;
1163 }
1164
1165 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1166
1167 tp->Tx_skbuff[entry] = skb;
1168
1169 desc->PSize = cpu_to_le32(len);
1170 desc->addr = cpu_to_le32(mapping);
1171
1172 desc->size = cpu_to_le32(len);
1173 if (entry == (NUM_TX_DESC - 1))
1174 desc->size |= cpu_to_le32(RingEnd);
1175
1176 wmb();
1177
1178 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1179
1180 tp->cur_tx++;
1181
1182 smp_wmb();
1183
1184 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1185
1186 dev->trans_start = jiffies;
1187
1188 dirty_tx = tp->dirty_tx;
1189 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1190 netif_stop_queue(dev);
1191 smp_rmb();
1192 if (dirty_tx != tp->dirty_tx)
1193 netif_wake_queue(dev);
1194 }
1195out:
1196 return NETDEV_TX_OK;
1197}
1198
1199static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1200{
1201 struct sis190_private *tp = netdev_priv(dev);
1202
1203 return &tp->stats;
1204}
1205
fcb9821d
FR		 1206static void sis190_free_phy(struct list_head *first_phy)
1207{
1208 struct sis190_phy *cur, *next;
1209
1210 list_for_each_entry_safe(cur, next, first_phy, list) {
1211 kfree(cur);
1212 }
1213}
1214
1215/**
1216 * sis190_default_phy - Select default PHY for sis190 mac.
1217 * @dev: the net device to probe for
1218 *
1219 * Select first detected PHY with link as default.
1220 * If no one is link on, select PHY whose types is HOME as default.
1221 * If HOME doesn't exist, select LAN.
1222 */
1223static u16 sis190_default_phy(struct net_device *dev)
1224{
1225 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1226 struct sis190_private *tp = netdev_priv(dev);
1227 struct mii_if_info *mii_if = &tp->mii_if;
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 u16 status;
1230
1231 phy_home = phy_default = phy_lan = NULL;
1232
1233 list_for_each_entry(phy, &tp->first_phy, list) {
1234 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1235
1236 // Link ON & Not select default PHY & not ghost PHY.
1237 if ((status & BMSR_LSTATUS) &&
1238 !phy_default &&
1239 (phy->type != UNKNOWN)) {
1240 phy_default = phy;
1241 } else {
1242 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1243 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1244 status | BMCR_ANENABLE | BMCR_ISOLATE);
1245 if (phy->type == HOME)
1246 phy_home = phy;
1247 else if (phy->type == LAN)
1248 phy_lan = phy;
1249 }
1250 }
1251
1252 if (!phy_default) {
1253 if (phy_home)
1254 phy_default = phy_home;
1255 else if (phy_lan)
1256 phy_default = phy_lan;
1257 else
1258 phy_default = list_entry(&tp->first_phy,
1259 struct sis190_phy, list);
1260 }
1261
1262 if (mii_if->phy_id != phy_default->phy_id) {
1263 mii_if->phy_id = phy_default->phy_id;
1264 net_probe(tp, KERN_INFO
1265 "%s: Using transceiver at address %d as default.\n",
3690b6c1 1266 pci_name(tp->pci_dev), mii_if->phy_id);
fcb9821d
FR		 1267 }
1268
1269 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1270 status &= (~BMCR_ISOLATE);
1271
1272 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1273 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1274
1275 return status;
1276}
1277
1278static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1279 struct sis190_phy *phy, unsigned int phy_id,
1280 u16 mii_status)
1281{
1282 void __iomem *ioaddr = tp->mmio_addr;
1283 struct mii_chip_info *p;
1284
1285 INIT_LIST_HEAD(&phy->list);
1286 phy->status = mii_status;
1287 phy->phy_id = phy_id;
1288
1289 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1290 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1291
1292 for (p = mii_chip_table; p->type; p++) {
1293 if ((p->id[0] == phy->id[0]) &&
1294 (p->id[1] == (phy->id[1] & 0xfff0))) {
1295 break;
1296 }
1297 }
1298
1299 if (p->id[1]) {
1300 phy->type = (p->type == MIX) ?
1301 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1302 LAN : HOME) : p->type;
900eb9d6 1303 tp->features |= p->feature;
fcb9821d
FR		 1304 } else
1305 phy->type = UNKNOWN;
1306
1307 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
3690b6c1
FR		 1308 pci_name(tp->pci_dev),
1309 (phy->type == UNKNOWN) ? "Unknown PHY" : p->name, phy_id);
fcb9821d
FR		 1310}
1311
900eb9d6
FR		 1312static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1313{
1314 if (tp->features & F_PHY_88E1111) {
1315 void __iomem *ioaddr = tp->mmio_addr;
1316 int phy_id = tp->mii_if.phy_id;
1317 u16 reg[2][2] = {
1318 { 0x808b, 0x0ce1 },
1319 { 0x808f, 0x0c60 }
1320 }, *p;
1321
1322 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1323
1324 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1325 udelay(200);
1326 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1327 udelay(200);
1328 }
1329}
1330
fcb9821d
FR		 1331/**
1332 * sis190_mii_probe - Probe MII PHY for sis190
1333 * @dev: the net device to probe for
1334 *
1335 * Search for total of 32 possible mii phy addresses.
1336 * Identify and set current phy if found one,
1337 * return error if it failed to found.
1338 */
1339static int __devinit sis190_mii_probe(struct net_device *dev)
1340{
1341 struct sis190_private *tp = netdev_priv(dev);
1342 struct mii_if_info *mii_if = &tp->mii_if;
1343 void __iomem *ioaddr = tp->mmio_addr;
1344 int phy_id;
1345 int rc = 0;
1346
1347 INIT_LIST_HEAD(&tp->first_phy);
1348
1349 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1350 struct sis190_phy *phy;
1351 u16 status;
1352
1353 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1354
1355 // Try next mii if the current one is not accessible.
1356 if (status == 0xffff || status == 0x0000)
1357 continue;
1358
1359 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1360 if (!phy) {
1361 sis190_free_phy(&tp->first_phy);
1362 rc = -ENOMEM;
1363 goto out;
1364 }
1365
1366 sis190_init_phy(dev, tp, phy, phy_id, status);
1367
1368 list_add(&tp->first_phy, &phy->list);
1369 }
1370
1371 if (list_empty(&tp->first_phy)) {
1372 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
3690b6c1 1373 pci_name(tp->pci_dev));
fcb9821d
FR		 1374 rc = -EIO;
1375 goto out;
1376 }
1377
1378 /* Select default PHY for mac */
1379 sis190_default_phy(dev);
1380
900eb9d6
FR		 1381 sis190_mii_probe_88e1111_fixup(tp);
1382
fcb9821d
FR		 1383 mii_if->dev = dev;
1384 mii_if->mdio_read = __mdio_read;
1385 mii_if->mdio_write = __mdio_write;
1386 mii_if->phy_id_mask = PHY_ID_ANY;
1387 mii_if->reg_num_mask = MII_REG_ANY;
1388out:
1389 return rc;
1390}
1391
1392static void __devexit sis190_mii_remove(struct net_device *dev)
1393{
1394 struct sis190_private *tp = netdev_priv(dev);
1395
1396 sis190_free_phy(&tp->first_phy);
1397}
1398
890e8d0a
FR		 1399static void sis190_release_board(struct pci_dev *pdev)
1400{
1401 struct net_device *dev = pci_get_drvdata(pdev);
1402 struct sis190_private *tp = netdev_priv(dev);
1403
1404 iounmap(tp->mmio_addr);
1405 pci_release_regions(pdev);
1406 pci_disable_device(pdev);
1407 free_netdev(dev);
1408}
1409
1410static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1411{
1412 struct sis190_private *tp;
1413 struct net_device *dev;
1414 void __iomem *ioaddr;
1415 int rc;
1416
1417 dev = alloc_etherdev(sizeof(*tp));
1418 if (!dev) {
1419 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1420 rc = -ENOMEM;
1421 goto err_out_0;
1422 }
1423
1424 SET_MODULE_OWNER(dev);
1425 SET_NETDEV_DEV(dev, &pdev->dev);
1426
1427 tp = netdev_priv(dev);
1428 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1429
1430 rc = pci_enable_device(pdev);
1431 if (rc < 0) {
1432 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1433 goto err_free_dev_1;
1434 }
1435
1436 rc = -ENODEV;
1437
1438 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1439 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1440 pci_name(pdev));
1441 goto err_pci_disable_2;
1442 }
1443 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1444 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1445 pci_name(pdev));
1446 goto err_pci_disable_2;
1447 }
1448
1449 rc = pci_request_regions(pdev, DRV_NAME);
1450 if (rc < 0) {
1451 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1452 pci_name(pdev));
1453 goto err_pci_disable_2;
1454 }
1455
1456 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1457 if (rc < 0) {
1458 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1459 pci_name(pdev));
1460 goto err_free_res_3;
1461 }
1462
1463 pci_set_master(pdev);
1464
1465 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1466 if (!ioaddr) {
1467 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1468 pci_name(pdev));
1469 rc = -EIO;
1470 goto err_free_res_3;
1471 }
1472
1473 tp->pci_dev = pdev;
1474 tp->mmio_addr = ioaddr;
1475
1476 sis190_irq_mask_and_ack(ioaddr);
1477
1478 sis190_soft_reset(ioaddr);
1479out:
1480 return dev;
1481
1482err_free_res_3:
1483 pci_release_regions(pdev);
1484err_pci_disable_2:
1485 pci_disable_device(pdev);
1486err_free_dev_1:
1487 free_netdev(dev);
1488err_out_0:
1489 dev = ERR_PTR(rc);
1490 goto out;
1491}
1492
1493static void sis190_tx_timeout(struct net_device *dev)
1494{
1495 struct sis190_private *tp = netdev_priv(dev);
1496 void __iomem *ioaddr = tp->mmio_addr;
1497 u8 tmp8;
1498
1499 /* Disable Tx, if not already */
1500 tmp8 = SIS_R8(TxControl);
1501 if (tmp8 & CmdTxEnb)
1502 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1503
188f23ba
FR		 1504
1505 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1506 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1507
890e8d0a
FR		 1508 /* Disable interrupts by clearing the interrupt mask. */
1509 SIS_W32(IntrMask, 0x0000);
1510
1511 /* Stop a shared interrupt from scavenging while we are. */
1512 spin_lock_irq(&tp->lock);
1513 sis190_tx_clear(tp);
1514 spin_unlock_irq(&tp->lock);
1515
1516 /* ...and finally, reset everything. */
1517 sis190_hw_start(dev);
1518
1519 netif_wake_queue(dev);
1520}
1521
900eb9d6
FR		 1522static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1523{
1524 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1525}
1526
830fb7d2
FR		 1527static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1528 struct net_device *dev)
1529{
1530 struct sis190_private *tp = netdev_priv(dev);
1531 void __iomem *ioaddr = tp->mmio_addr;
1532 u16 sig;
1533 int i;
1534
1535 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1536 pci_name(pdev));
1537
1538 /* Check to see if there is a sane EEPROM */
1539 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1540
1541 if ((sig == 0xffff) || (sig == 0x0000)) {
1542 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1543 pci_name(pdev), sig);
1544 return -EIO;
1545 }
1546
1547 /* Get MAC address from EEPROM */
1548 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
3cec93c7 1549 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
830fb7d2
FR		 1550
1551 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w);
1552 }
1553
900eb9d6
FR		 1554 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1555
830fb7d2
FR		 1556 return 0;
1557}
1558
1559/**
1560 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1561 * @pdev: PCI device
1562 * @dev: network device to get address for
1563 *
1564 * SiS965 model, use APC CMOS RAM to store MAC address.
1565 * APC CMOS RAM is accessed through ISA bridge.
1566 * MAC address is read into @net_dev->dev_addr.
1567 */
1568static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1569 struct net_device *dev)
1570{
1571 struct sis190_private *tp = netdev_priv(dev);
1572 struct pci_dev *isa_bridge;
1573 u8 reg, tmp8;
1574 int i;
1575
1576 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1577 pci_name(pdev));
1578
1579 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1580 if (!isa_bridge) {
1581 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1582 pci_name(pdev));
1583 return -EIO;
1584 }
1585
1586 /* Enable port 78h & 79h to access APC Registers. */
1587 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1588 reg = (tmp8 & ~0x02);
1589 pci_write_config_byte(isa_bridge, 0x48, reg);
1590 udelay(50);
1591 pci_read_config_byte(isa_bridge, 0x48, &reg);
1592
1593 for (i = 0; i < MAC_ADDR_LEN; i++) {
1594 outb(0x9 + i, 0x78);
1595 dev->dev_addr[i] = inb(0x79);
1596 }
1597
1598 outb(0x12, 0x78);
1599 reg = inb(0x79);
1600
900eb9d6
FR		 1601 sis190_set_rgmii(tp, reg);
1602
830fb7d2
FR		 1603 /* Restore the value to ISA Bridge */
1604 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1605 pci_dev_put(isa_bridge);
1606
1607 return 0;
1608}
1609
1610/**
1611 * sis190_init_rxfilter - Initialize the Rx filter
1612 * @dev: network device to initialize
1613 *
1614 * Set receive filter address to our MAC address
1615 * and enable packet filtering.
1616 */
1617static inline void sis190_init_rxfilter(struct net_device *dev)
1618{
1619 struct sis190_private *tp = netdev_priv(dev);
1620 void __iomem *ioaddr = tp->mmio_addr;
1621 u16 ctl;
1622 int i;
1623
1624 ctl = SIS_R16(RxMacControl);
1625 /*
1626 * Disable packet filtering before setting filter.
1627 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1628 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1629 */
1630 SIS_W16(RxMacControl, ctl & ~0x0f00);
1631
1632 for (i = 0; i < MAC_ADDR_LEN; i++)
1633 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1634
1635 SIS_W16(RxMacControl, ctl);
1636 SIS_PCI_COMMIT();
1637}
1638
1639static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1640{
1641 u8 from;
1642
1643 pci_read_config_byte(pdev, 0x73, &from);
1644
1645 return (from & 0x00000001) ?
1646 sis190_get_mac_addr_from_apc(pdev, dev) :
1647 sis190_get_mac_addr_from_eeprom(pdev, dev);
1648}
1649
890e8d0a
FR		 1650static void sis190_set_speed_auto(struct net_device *dev)
1651{
1652 struct sis190_private *tp = netdev_priv(dev);
1653 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 1654 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 1655 int val;
1656
1657 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1658
9ede109b 1659 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
890e8d0a
FR		 1660
1661 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1662 // unchanged.
9ede109b 1663 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
890e8d0a
FR		 1664 ADVERTISE_100FULL | ADVERTISE_10FULL |
1665 ADVERTISE_100HALF | ADVERTISE_10HALF);
1666
1667 // Enable 1000 Full Mode.
9ede109b 1668 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
890e8d0a
FR		 1669
1670 // Enable auto-negotiation and restart auto-negotiation.
9ede109b 1671 mdio_write(ioaddr, phy_id, MII_BMCR,
890e8d0a
FR		 1672 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1673}
1674
43afb949
FR		 1675static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1676{
1677 struct sis190_private *tp = netdev_priv(dev);
1678
1679 return mii_ethtool_gset(&tp->mii_if, cmd);
1680}
1681
1682static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1683{
1684 struct sis190_private *tp = netdev_priv(dev);
1685
1686 return mii_ethtool_sset(&tp->mii_if, cmd);
1687}
1688
890e8d0a
FR		 1689static void sis190_get_drvinfo(struct net_device *dev,
1690 struct ethtool_drvinfo *info)
1691{
1692 struct sis190_private *tp = netdev_priv(dev);
1693
1694 strcpy(info->driver, DRV_NAME);
1695 strcpy(info->version, DRV_VERSION);
1696 strcpy(info->bus_info, pci_name(tp->pci_dev));
1697}
1698
1699static int sis190_get_regs_len(struct net_device *dev)
1700{
1701 return SIS190_REGS_SIZE;
1702}
1703
1704static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1705 void *p)
1706{
1707 struct sis190_private *tp = netdev_priv(dev);
1708 unsigned long flags;
1709
1710 if (regs->len > SIS190_REGS_SIZE)
1711 regs->len = SIS190_REGS_SIZE;
1712
1713 spin_lock_irqsave(&tp->lock, flags);
1714 memcpy_fromio(p, tp->mmio_addr, regs->len);
1715 spin_unlock_irqrestore(&tp->lock, flags);
1716}
1717
43afb949
FR		 1718static int sis190_nway_reset(struct net_device *dev)
1719{
1720 struct sis190_private *tp = netdev_priv(dev);
1721
1722 return mii_nway_restart(&tp->mii_if);
1723}
1724
890e8d0a
FR		 1725static u32 sis190_get_msglevel(struct net_device *dev)
1726{
1727 struct sis190_private *tp = netdev_priv(dev);
1728
1729 return tp->msg_enable;
1730}
1731
1732static void sis190_set_msglevel(struct net_device *dev, u32 value)
1733{
1734 struct sis190_private *tp = netdev_priv(dev);
1735
1736 tp->msg_enable = value;
1737}
1738
1739static struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1740 .get_settings = sis190_get_settings,
1741 .set_settings = sis190_set_settings,
890e8d0a
FR		 1742 .get_drvinfo = sis190_get_drvinfo,
1743 .get_regs_len = sis190_get_regs_len,
1744 .get_regs = sis190_get_regs,
1745 .get_link = ethtool_op_get_link,
1746 .get_msglevel = sis190_get_msglevel,
1747 .set_msglevel = sis190_set_msglevel,
43afb949 1748 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1749};
1750
43afb949
FR		 1751static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1752{
1753 struct sis190_private *tp = netdev_priv(dev);
1754
1755 return !netif_running(dev) ? -EINVAL :
1756 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1757}
1758
890e8d0a
FR		 1759static int __devinit sis190_init_one(struct pci_dev *pdev,
1760 const struct pci_device_id *ent)
1761{
1762 static int printed_version = 0;
1763 struct sis190_private *tp;
1764 struct net_device *dev;
1765 void __iomem *ioaddr;
830fb7d2 1766 int rc;
890e8d0a
FR		 1767
1768 if (!printed_version) {
1769 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1770 printed_version = 1;
1771 }
1772
1773 dev = sis190_init_board(pdev);
1774 if (IS_ERR(dev)) {
1775 rc = PTR_ERR(dev);
1776 goto out;
1777 }
1778
1779 tp = netdev_priv(dev);
1780 ioaddr = tp->mmio_addr;
1781
830fb7d2
FR		 1782 rc = sis190_get_mac_addr(pdev, dev);
1783 if (rc < 0)
1784 goto err_release_board;
890e8d0a 1785
830fb7d2 1786 sis190_init_rxfilter(dev);
890e8d0a
FR		 1787
1788 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1789
1790 dev->open = sis190_open;
1791 dev->stop = sis190_close;
43afb949 1792 dev->do_ioctl = sis190_ioctl;
890e8d0a
FR		 1793 dev->get_stats = sis190_get_stats;
1794 dev->tx_timeout = sis190_tx_timeout;
1795 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1796 dev->hard_start_xmit = sis190_start_xmit;
4405d3b5
FR		 1797#ifdef CONFIG_NET_POLL_CONTROLLER
1798 dev->poll_controller = sis190_netpoll;
1799#endif
890e8d0a
FR		 1800 dev->set_multicast_list = sis190_set_rx_mode;
1801 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1802 dev->irq = pdev->irq;
1803 dev->base_addr = (unsigned long) 0xdead;
1804
1805 spin_lock_init(&tp->lock);
3690b6c1
FR		 1806
1807 rc = sis190_mii_probe(dev);
830fb7d2
FR		 1808 if (rc < 0)
1809 goto err_release_board;
890e8d0a 1810
3690b6c1 1811 rc = register_netdev(dev);
fcb9821d 1812 if (rc < 0)
3690b6c1
FR		 1813 goto err_remove_mii;
1814
1815 pci_set_drvdata(pdev, dev);
fcb9821d 1816
890e8d0a
FR		 1817 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1818 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1819 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1820 ioaddr, dev->irq,
1821 dev->dev_addr[0], dev->dev_addr[1],
1822 dev->dev_addr[2], dev->dev_addr[3],
1823 dev->dev_addr[4], dev->dev_addr[5]);
1824
900eb9d6
FR		 1825 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1826 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1827
890e8d0a
FR		 1828 netif_carrier_off(dev);
1829
1830 sis190_set_speed_auto(dev);
1831out:
1832 return rc;
830fb7d2 1833
3690b6c1
FR		 1834err_remove_mii:
1835 sis190_mii_remove(dev);
830fb7d2
FR		 1836err_release_board:
1837 sis190_release_board(pdev);
1838 goto out;
890e8d0a
FR		 1839}
1840
1841static void __devexit sis190_remove_one(struct pci_dev *pdev)
1842{
1843 struct net_device *dev = pci_get_drvdata(pdev);
1844
fcb9821d 1845 sis190_mii_remove(dev);
890e8d0a
FR		 1846 unregister_netdev(dev);
1847 sis190_release_board(pdev);
1848 pci_set_drvdata(pdev, NULL);
1849}
1850
1851static struct pci_driver sis190_pci_driver = {
1852 .name = DRV_NAME,
1853 .id_table = sis190_pci_tbl,
1854 .probe = sis190_init_one,
1855 .remove = __devexit_p(sis190_remove_one),
1856};
1857
1858static int __init sis190_init_module(void)
1859{
1860 return pci_module_init(&sis190_pci_driver);
1861}
1862
1863static void __exit sis190_cleanup_module(void)
1864{
1865 pci_unregister_driver(&sis190_pci_driver);
1866}
1867
1868module_init(sis190_init_module);
1869module_exit(sis190_cleanup_module);