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[PATCH] sis190: PHY identifier for the K8S-MX motherboard.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sis190.c
CommitLineData
890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/netdevice.h>
43afb949 25#include <linux/rtnetlink.h>
890e8d0a
FR		 26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/pci.h>
29#include <linux/mii.h>
30#include <linux/delay.h>
31#include <linux/crc32.h>
32#include <linux/dma-mapping.h>
33#include <asm/irq.h>
34
35#define net_drv(p, arg...) if (netif_msg_drv(p)) \
36 printk(arg)
37#define net_probe(p, arg...) if (netif_msg_probe(p)) \
38 printk(arg)
39#define net_link(p, arg...) if (netif_msg_link(p)) \
40 printk(arg)
41#define net_intr(p, arg...) if (netif_msg_intr(p)) \
42 printk(arg)
43#define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
44 printk(arg)
45
fcb9821d
FR		 46#define PHY_MAX_ADDR 32
47#define PHY_ID_ANY 0x1f
48#define MII_REG_ANY 0x1f
49
890e8d0a
FR		 50#ifdef CONFIG_SIS190_NAPI
51#define NAPI_SUFFIX "-NAPI"
52#else
53#define NAPI_SUFFIX ""
54#endif
55
56#define DRV_VERSION "1.2" NAPI_SUFFIX
57#define DRV_NAME "sis190"
58#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
59#define PFX DRV_NAME ": "
60
61#ifdef CONFIG_SIS190_NAPI
62#define sis190_rx_skb netif_receive_skb
63#define sis190_rx_quota(count, quota) min(count, quota)
64#else
65#define sis190_rx_skb netif_rx
66#define sis190_rx_quota(count, quota) count
67#endif
68
69#define MAC_ADDR_LEN 6
70
bcad5e53
FR		 71#define NUM_TX_DESC 64 /* [8..1024] */
72#define NUM_RX_DESC 64 /* [8..8192] */
890e8d0a
FR		 73#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75#define RX_BUF_SIZE 1536
8b5641d4 76#define RX_BUF_MASK 0xfff8
890e8d0a
FR		 77
78#define SIS190_REGS_SIZE 0x80
79#define SIS190_TX_TIMEOUT (6*HZ)
80#define SIS190_PHY_TIMEOUT (10*HZ)
81#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
83 NETIF_MSG_IFDOWN)
84
85/* Enhanced PHY access register bit definitions */
86#define EhnMIIread 0x0000
87#define EhnMIIwrite 0x0020
88#define EhnMIIdataShift 16
89#define EhnMIIpmdShift 6 /* 7016 only */
90#define EhnMIIregShift 11
91#define EhnMIIreq 0x0010
92#define EhnMIInotDone 0x0010
93
94/* Write/read MMIO register */
95#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
96#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
97#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
98#define SIS_R8(reg) readb (ioaddr + (reg))
99#define SIS_R16(reg) readw (ioaddr + (reg))
100#define SIS_R32(reg) readl (ioaddr + (reg))
101
102#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
103
104enum sis190_registers {
105 TxControl = 0x00,
106 TxDescStartAddr = 0x04,
188f23ba
FR		 107 rsv0 = 0x08, // reserved
108 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 109 RxControl = 0x10,
110 RxDescStartAddr = 0x14,
188f23ba
FR		 111 rsv1 = 0x18, // reserved
112 RxSts = 0x1c, // unused
890e8d0a
FR		 113 IntrStatus = 0x20,
114 IntrMask = 0x24,
115 IntrControl = 0x28,
188f23ba
FR		 116 IntrTimer = 0x2c, // unused (Interupt Timer)
117 PMControl = 0x30, // unused (Power Mgmt Control/Status)
118 rsv2 = 0x34, // reserved
890e8d0a
FR		 119 ROMControl = 0x38,
120 ROMInterface = 0x3c,
121 StationControl = 0x40,
122 GMIIControl = 0x44,
188f23ba
FR		 123 GIoCR = 0x48, // unused (GMAC IO Compensation)
124 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 125 TxMacControl = 0x50,
188f23ba
FR		 126 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
127 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
128 rsv3 = 0x5c, // reserved
890e8d0a
FR		 129 RxMacControl = 0x60,
130 RxMacAddr = 0x62,
131 RxHashTable = 0x68,
132 // Undocumented = 0x6c,
188f23ba
FR		 133 RxWolCtrl = 0x70,
134 RxWolData = 0x74, // unused (Rx WOL Data Access)
135 RxMPSControl = 0x78, // unused (Rx MPS Control)
136 rsv4 = 0x7c, // reserved
890e8d0a
FR		 137};
138
139enum sis190_register_content {
140 /* IntrStatus */
141 SoftInt = 0x40000000, // unused
142 Timeup = 0x20000000, // unused
143 PauseFrame = 0x00080000, // unused
144 MagicPacket = 0x00040000, // unused
145 WakeupFrame = 0x00020000, // unused
146 LinkChange = 0x00010000,
147 RxQEmpty = 0x00000080,
148 RxQInt = 0x00000040,
149 TxQ1Empty = 0x00000020, // unused
150 TxQ1Int = 0x00000010,
151 TxQ0Empty = 0x00000008, // unused
152 TxQ0Int = 0x00000004,
153 RxHalt = 0x00000002,
154 TxHalt = 0x00000001,
155
890e8d0a
FR		 156 /* {Rx/Tx}CmdBits */
157 CmdReset = 0x10,
158 CmdRxEnb = 0x08, // unused
159 CmdTxEnb = 0x01,
160 RxBufEmpty = 0x01, // unused
161
162 /* Cfg9346Bits */
163 Cfg9346_Lock = 0x00, // unused
164 Cfg9346_Unlock = 0xc0, // unused
165
166 /* RxMacControl */
167 AcceptErr = 0x20, // unused
168 AcceptRunt = 0x10, // unused
169 AcceptBroadcast = 0x0800,
170 AcceptMulticast = 0x0400,
171 AcceptMyPhys = 0x0200,
172 AcceptAllPhys = 0x0100,
173
174 /* RxConfigBits */
175 RxCfgFIFOShift = 13,
176 RxCfgDMAShift = 8, // 0x1a in RxControl ?
177
178 /* TxConfigBits */
179 TxInterFrameGapShift = 24,
180 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
181
182 /* StationControl */
183 _1000bpsF = 0x1c00,
184 _1000bpsH = 0x0c00,
185 _100bpsF = 0x1800,
186 _100bpsH = 0x0800,
187 _10bpsF = 0x1400,
188 _10bpsH = 0x0400,
189
190 LinkStatus = 0x02, // unused
191 FullDup = 0x01, // unused
192
193 /* TBICSRBit */
194 TBILinkOK = 0x02000000, // unused
195};
196
197struct TxDesc {
3cec93c7
FR		 198 __le32 PSize;
199 __le32 status;
200 __le32 addr;
201 __le32 size;
890e8d0a
FR		 202};
203
204struct RxDesc {
3cec93c7
FR		 205 __le32 PSize;
206 __le32 status;
207 __le32 addr;
208 __le32 size;
890e8d0a
FR		 209};
210
211enum _DescStatusBit {
212 /* _Desc.status */
bcad5e53
FR		 213 OWNbit = 0x80000000, // RXOWN/TXOWN
214 INTbit = 0x40000000, // RXINT/TXINT
215 CRCbit = 0x00020000, // CRCOFF/CRCEN
216 PADbit = 0x00010000, // PREADD/PADEN
890e8d0a 217 /* _Desc.size */
bcad5e53
FR		 218 RingEnd = 0x80000000,
219 /* TxDesc.status */
220 LSEN = 0x08000000, // TSO ? -- FR
221 IPCS = 0x04000000,
222 TCPCS = 0x02000000,
223 UDPCS = 0x01000000,
224 BSTEN = 0x00800000,
225 EXTEN = 0x00400000,
226 DEFEN = 0x00200000,
227 BKFEN = 0x00100000,
228 CRSEN = 0x00080000,
229 COLEN = 0x00040000,
230 THOL3 = 0x30000000,
231 THOL2 = 0x20000000,
232 THOL1 = 0x10000000,
233 THOL0 = 0x00000000,
234 /* RxDesc.status */
235 IPON = 0x20000000,
236 TCPON = 0x10000000,
237 UDPON = 0x08000000,
238 Wakup = 0x00400000,
239 Magic = 0x00200000,
240 Pause = 0x00100000,
241 DEFbit = 0x00200000,
242 BCAST = 0x000c0000,
243 MCAST = 0x00080000,
244 UCAST = 0x00040000,
245 /* RxDesc.PSize */
246 TAGON = 0x80000000,
247 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
248 ABORT = 0x00800000,
249 SHORT = 0x00400000,
250 LIMIT = 0x00200000,
251 MIIER = 0x00100000,
252 OVRUN = 0x00080000,
253 NIBON = 0x00040000,
254 COLON = 0x00020000,
255 CRCOK = 0x00010000,
890e8d0a 256 RxSizeMask = 0x0000ffff
bcad5e53
FR		 257 /*
258 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
259 * provide two (unused with Linux) Tx queues. No publically
260 * available documentation alas.
261 */
890e8d0a
FR		 262};
263
40292fb0
FR		 264enum sis190_eeprom_access_register_bits {
265 EECS = 0x00000001, // unused
266 EECLK = 0x00000002, // unused
267 EEDO = 0x00000008, // unused
268 EEDI = 0x00000004, // unused
269 EEREQ = 0x00000080,
270 EEROP = 0x00000200,
271 EEWOP = 0x00000100 // unused
272};
273
830fb7d2
FR		 274/* EEPROM Addresses */
275enum sis190_eeprom_address {
276 EEPROMSignature = 0x00,
277 EEPROMCLK = 0x01, // unused
278 EEPROMInfo = 0x02,
279 EEPROMMACAddr = 0x03
280};
281
890e8d0a
FR		 282struct sis190_private {
283 void __iomem *mmio_addr;
284 struct pci_dev *pci_dev;
285 struct net_device_stats stats;
286 spinlock_t lock;
287 u32 rx_buf_sz;
288 u32 cur_rx;
289 u32 cur_tx;
290 u32 dirty_rx;
291 u32 dirty_tx;
292 dma_addr_t rx_dma;
293 dma_addr_t tx_dma;
294 struct RxDesc *RxDescRing;
295 struct TxDesc *TxDescRing;
296 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
297 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
298 struct work_struct phy_task;
299 struct timer_list timer;
300 u32 msg_enable;
43afb949 301 struct mii_if_info mii_if;
fcb9821d
FR		 302 struct list_head first_phy;
303};
304
305struct sis190_phy {
306 struct list_head list;
307 int phy_id;
308 u16 id[2];
309 u16 status;
310 u8 type;
311};
312
313enum sis190_phy_type {
314 UNKNOWN = 0x00,
315 HOME = 0x01,
316 LAN = 0x02,
317 MIX = 0x03
318};
319
320static struct mii_chip_info {
321 const char *name;
322 u16 id[2];
323 unsigned int type;
324} mii_chip_table[] = {
325 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN },
326 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN },
327 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN },
560d3d52 328 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN },
fcb9821d 329 { NULL, }
890e8d0a
FR		 330};
331
332const static struct {
333 const char *name;
334 u8 version; /* depend on docs */
335 u32 RxConfigMask; /* clear the bits supported by this chip */
336} sis_chip_info[] = {
337 { DRV_NAME, 0x00, 0xff7e1880, },
338};
339
340static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
341 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
342 { 0, },
343};
344
345MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
346
347static int rx_copybreak = 200;
348
349static struct {
350 u32 msg_enable;
351} debug = { -1 };
352
353MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
354module_param(rx_copybreak, int, 0);
355MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
356module_param_named(debug, debug.msg_enable, int, 0);
357MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
358MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
359MODULE_VERSION(DRV_VERSION);
360MODULE_LICENSE("GPL");
361
362static const u32 sis190_intr_mask =
363 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt;
364
365/*
366 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
367 * The chips use a 64 element hash table based on the Ethernet CRC.
368 */
369static int multicast_filter_limit = 32;
370
371static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
372{
373 unsigned int i;
374
375 SIS_W32(GMIIControl, ctl);
376
377 msleep(1);
378
379 for (i = 0; i < 100; i++) {
380 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
381 break;
382 msleep(1);
383 }
384
385 if (i > 999)
386 printk(KERN_ERR PFX "PHY command failed !\n");
387}
388
9ede109b 389static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
890e8d0a 390{
890e8d0a 391 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
9ede109b 392 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
890e8d0a
FR		 393 (((u32) val) << EhnMIIdataShift));
394}
395
9ede109b 396static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
890e8d0a 397{
890e8d0a 398 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
9ede109b 399 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
890e8d0a
FR		 400
401 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
402}
403
43afb949
FR		 404static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
405{
406 struct sis190_private *tp = netdev_priv(dev);
407
9ede109b 408 mdio_write(tp->mmio_addr, phy_id, reg, val);
43afb949
FR		 409}
410
411static int __mdio_read(struct net_device *dev, int phy_id, int reg)
412{
413 struct sis190_private *tp = netdev_priv(dev);
414
9ede109b 415 return mdio_read(tp->mmio_addr, phy_id, reg);
43afb949
FR		 416}
417
fc10c39d
FR		 418static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
419{
420 mdio_read(ioaddr, phy_id, reg);
421 return mdio_read(ioaddr, phy_id, reg);
422}
423
40292fb0 424static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 425{
40292fb0 426 u16 data = 0xffff;
890e8d0a 427 unsigned int i;
890e8d0a
FR		 428
429 if (!(SIS_R32(ROMControl) & 0x0002))
430 return 0;
431
40292fb0 432 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 433
434 for (i = 0; i < 200; i++) {
40292fb0
FR		 435 if (!(SIS_R32(ROMInterface) & EEREQ)) {
436 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 437 break;
40292fb0 438 }
890e8d0a
FR		 439 msleep(1);
440 }
441
890e8d0a
FR		 442 return data;
443}
444
445static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
446{
447 SIS_W32(IntrMask, 0x00);
448 SIS_W32(IntrStatus, 0xffffffff);
449 SIS_PCI_COMMIT();
450}
451
452static void sis190_asic_down(void __iomem *ioaddr)
453{
454 /* Stop the chip's Tx and Rx DMA processes. */
455
456 SIS_W32(TxControl, 0x1a00);
457 SIS_W32(RxControl, 0x1a00);
458
459 sis190_irq_mask_and_ack(ioaddr);
460}
461
462static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
463{
464 desc->size |= cpu_to_le32(RingEnd);
465}
466
467static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
468{
469 u32 eor = le32_to_cpu(desc->size) & RingEnd;
470
471 desc->PSize = 0x0;
8b5641d4 472 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
890e8d0a
FR		 473 wmb();
474 desc->status = cpu_to_le32(OWNbit | INTbit);
475}
476
477static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
478 u32 rx_buf_sz)
479{
480 desc->addr = cpu_to_le32(mapping);
481 sis190_give_to_asic(desc, rx_buf_sz);
482}
483
484static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
485{
486 desc->PSize = 0x0;
487 desc->addr = 0xdeadbeef;
488 desc->size &= cpu_to_le32(RingEnd);
489 wmb();
490 desc->status = 0x0;
491}
492
493static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
494 struct RxDesc *desc, u32 rx_buf_sz)
495{
496 struct sk_buff *skb;
497 dma_addr_t mapping;
498 int ret = 0;
499
500 skb = dev_alloc_skb(rx_buf_sz);
501 if (!skb)
502 goto err_out;
503
504 *sk_buff = skb;
505
506 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
507 PCI_DMA_FROMDEVICE);
508
509 sis190_map_to_asic(desc, mapping, rx_buf_sz);
510out:
511 return ret;
512
513err_out:
514 ret = -ENOMEM;
515 sis190_make_unusable_by_asic(desc);
516 goto out;
517}
518
519static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
520 u32 start, u32 end)
521{
522 u32 cur;
523
524 for (cur = start; cur < end; cur++) {
525 int ret, i = cur % NUM_RX_DESC;
526
527 if (tp->Rx_skbuff[i])
528 continue;
529
530 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
531 tp->RxDescRing + i, tp->rx_buf_sz);
532 if (ret < 0)
533 break;
534 }
535 return cur - start;
536}
537
538static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
539 struct RxDesc *desc, int rx_buf_sz)
540{
541 int ret = -1;
542
543 if (pkt_size < rx_copybreak) {
544 struct sk_buff *skb;
545
546 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
547 if (skb) {
548 skb_reserve(skb, NET_IP_ALIGN);
549 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
550 *sk_buff = skb;
551 sis190_give_to_asic(desc, rx_buf_sz);
552 ret = 0;
553 }
554 }
555 return ret;
556}
557
bcad5e53
FR		 558static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
559{
560#define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
561
562 if ((status & CRCOK) && !(status & ErrMask))
563 return 0;
564
565 if (!(status & CRCOK))
566 stats->rx_crc_errors++;
567 else if (status & OVRUN)
568 stats->rx_over_errors++;
569 else if (status & (SHORT | LIMIT))
570 stats->rx_length_errors++;
571 else if (status & (MIIER | NIBON | COLON))
572 stats->rx_frame_errors++;
573
574 stats->rx_errors++;
575 return -1;
576}
577
890e8d0a
FR		 578static int sis190_rx_interrupt(struct net_device *dev,
579 struct sis190_private *tp, void __iomem *ioaddr)
580{
581 struct net_device_stats *stats = &tp->stats;
582 u32 rx_left, cur_rx = tp->cur_rx;
583 u32 delta, count;
584
585 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
586 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
587
588 for (; rx_left > 0; rx_left--, cur_rx++) {
589 unsigned int entry = cur_rx % NUM_RX_DESC;
590 struct RxDesc *desc = tp->RxDescRing + entry;
591 u32 status;
592
593 if (desc->status & OWNbit)
594 break;
595
596 status = le32_to_cpu(desc->PSize);
597
598 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
599 // status);
600
bcad5e53 601 if (sis190_rx_pkt_err(status, stats) < 0)
890e8d0a 602 sis190_give_to_asic(desc, tp->rx_buf_sz);
bcad5e53 603 else {
890e8d0a
FR		 604 struct sk_buff *skb = tp->Rx_skbuff[entry];
605 int pkt_size = (status & RxSizeMask) - 4;
606 void (*pci_action)(struct pci_dev *, dma_addr_t,
607 size_t, int) = pci_dma_sync_single_for_device;
608
609 if (unlikely(pkt_size > tp->rx_buf_sz)) {
610 net_intr(tp, KERN_INFO
611 "%s: (frag) status = %08x.\n",
612 dev->name, status);
613 stats->rx_dropped++;
614 stats->rx_length_errors++;
615 sis190_give_to_asic(desc, tp->rx_buf_sz);
616 continue;
617 }
618
619 pci_dma_sync_single_for_cpu(tp->pci_dev,
620 le32_to_cpu(desc->addr), tp->rx_buf_sz,
621 PCI_DMA_FROMDEVICE);
622
623 if (sis190_try_rx_copy(&skb, pkt_size, desc,
624 tp->rx_buf_sz)) {
625 pci_action = pci_unmap_single;
626 tp->Rx_skbuff[entry] = NULL;
627 sis190_make_unusable_by_asic(desc);
628 }
629
630 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
631 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
632
633 skb->dev = dev;
634 skb_put(skb, pkt_size);
635 skb->protocol = eth_type_trans(skb, dev);
636
637 sis190_rx_skb(skb);
638
639 dev->last_rx = jiffies;
890e8d0a 640 stats->rx_packets++;
bcad5e53
FR		 641 stats->rx_bytes += pkt_size;
642 if ((status & BCAST) == MCAST)
643 stats->multicast++;
890e8d0a
FR		 644 }
645 }
646 count = cur_rx - tp->cur_rx;
647 tp->cur_rx = cur_rx;
648
649 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
650 if (!delta && count && netif_msg_intr(tp))
651 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
652 tp->dirty_rx += delta;
653
654 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
655 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
656
657 return count;
658}
659
660static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
661 struct TxDesc *desc)
662{
663 unsigned int len;
664
665 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
666
667 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
668
669 memset(desc, 0x00, sizeof(*desc));
670}
671
672static void sis190_tx_interrupt(struct net_device *dev,
673 struct sis190_private *tp, void __iomem *ioaddr)
674{
675 u32 pending, dirty_tx = tp->dirty_tx;
676 /*
677 * It would not be needed if queueing was allowed to be enabled
678 * again too early (hint: think preempt and unclocked smp systems).
679 */
680 unsigned int queue_stopped;
681
682 smp_rmb();
683 pending = tp->cur_tx - dirty_tx;
684 queue_stopped = (pending == NUM_TX_DESC);
685
686 for (; pending; pending--, dirty_tx++) {
687 unsigned int entry = dirty_tx % NUM_TX_DESC;
688 struct TxDesc *txd = tp->TxDescRing + entry;
689 struct sk_buff *skb;
690
691 if (le32_to_cpu(txd->status) & OWNbit)
692 break;
693
694 skb = tp->Tx_skbuff[entry];
695
696 tp->stats.tx_packets++;
697 tp->stats.tx_bytes += skb->len;
698
699 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
700 tp->Tx_skbuff[entry] = NULL;
701 dev_kfree_skb_irq(skb);
702 }
703
704 if (tp->dirty_tx != dirty_tx) {
705 tp->dirty_tx = dirty_tx;
706 smp_wmb();
707 if (queue_stopped)
708 netif_wake_queue(dev);
709 }
710}
711
712/*
713 * The interrupt handler does all of the Rx thread work and cleans up after
714 * the Tx thread.
715 */
716static irqreturn_t sis190_interrupt(int irq, void *__dev, struct pt_regs *regs)
717{
718 struct net_device *dev = __dev;
719 struct sis190_private *tp = netdev_priv(dev);
720 void __iomem *ioaddr = tp->mmio_addr;
721 unsigned int handled = 0;
722 u32 status;
723
724 status = SIS_R32(IntrStatus);
725
726 if ((status == 0xffffffff) || !status)
727 goto out;
728
729 handled = 1;
730
731 if (unlikely(!netif_running(dev))) {
732 sis190_asic_down(ioaddr);
733 goto out;
734 }
735
736 SIS_W32(IntrStatus, status);
737
738 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
739
740 if (status & LinkChange) {
741 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
742 schedule_work(&tp->phy_task);
743 }
744
745 if (status & RxQInt)
746 sis190_rx_interrupt(dev, tp, ioaddr);
747
748 if (status & TxQ0Int)
749 sis190_tx_interrupt(dev, tp, ioaddr);
750out:
751 return IRQ_RETVAL(handled);
752}
753
4405d3b5
FR		 754#ifdef CONFIG_NET_POLL_CONTROLLER
755static void sis190_netpoll(struct net_device *dev)
756{
757 struct sis190_private *tp = netdev_priv(dev);
758 struct pci_dev *pdev = tp->pci_dev;
759
760 disable_irq(pdev->irq);
761 sis190_interrupt(pdev->irq, dev, NULL);
762 enable_irq(pdev->irq);
763}
764#endif
765
890e8d0a
FR		 766static void sis190_free_rx_skb(struct sis190_private *tp,
767 struct sk_buff **sk_buff, struct RxDesc *desc)
768{
769 struct pci_dev *pdev = tp->pci_dev;
770
771 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
772 PCI_DMA_FROMDEVICE);
773 dev_kfree_skb(*sk_buff);
774 *sk_buff = NULL;
775 sis190_make_unusable_by_asic(desc);
776}
777
778static void sis190_rx_clear(struct sis190_private *tp)
779{
780 unsigned int i;
781
782 for (i = 0; i < NUM_RX_DESC; i++) {
783 if (!tp->Rx_skbuff[i])
784 continue;
785 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
786 }
787}
788
789static void sis190_init_ring_indexes(struct sis190_private *tp)
790{
791 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
792}
793
794static int sis190_init_ring(struct net_device *dev)
795{
796 struct sis190_private *tp = netdev_priv(dev);
797
798 sis190_init_ring_indexes(tp);
799
800 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
801 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
802
803 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
804 goto err_rx_clear;
805
806 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
807
808 return 0;
809
810err_rx_clear:
811 sis190_rx_clear(tp);
812 return -ENOMEM;
813}
814
815static void sis190_set_rx_mode(struct net_device *dev)
816{
817 struct sis190_private *tp = netdev_priv(dev);
818 void __iomem *ioaddr = tp->mmio_addr;
819 unsigned long flags;
820 u32 mc_filter[2]; /* Multicast hash filter */
821 u16 rx_mode;
822
823 if (dev->flags & IFF_PROMISC) {
824 /* Unconditionally log net taps. */
825 net_drv(tp, KERN_NOTICE "%s: Promiscuous mode enabled.\n",
826 dev->name);
827 rx_mode =
828 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
829 AcceptAllPhys;
830 mc_filter[1] = mc_filter[0] = 0xffffffff;
831 } else if ((dev->mc_count > multicast_filter_limit) ||
832 (dev->flags & IFF_ALLMULTI)) {
833 /* Too many to filter perfectly -- accept all multicasts. */
834 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
835 mc_filter[1] = mc_filter[0] = 0xffffffff;
836 } else {
837 struct dev_mc_list *mclist;
838 unsigned int i;
839
840 rx_mode = AcceptBroadcast | AcceptMyPhys;
841 mc_filter[1] = mc_filter[0] = 0;
842 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
843 i++, mclist = mclist->next) {
844 int bit_nr =
845 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
846 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
847 rx_mode |= AcceptMulticast;
848 }
849 }
850
851 spin_lock_irqsave(&tp->lock, flags);
852
853 SIS_W16(RxMacControl, rx_mode | 0x2);
854 SIS_W32(RxHashTable, mc_filter[0]);
855 SIS_W32(RxHashTable + 4, mc_filter[1]);
856
857 spin_unlock_irqrestore(&tp->lock, flags);
858}
859
860static void sis190_soft_reset(void __iomem *ioaddr)
861{
862 SIS_W32(IntrControl, 0x8000);
863 SIS_PCI_COMMIT();
864 msleep(1);
865 SIS_W32(IntrControl, 0x0);
866 sis190_asic_down(ioaddr);
867 msleep(1);
868}
869
870static void sis190_hw_start(struct net_device *dev)
871{
872 struct sis190_private *tp = netdev_priv(dev);
873 void __iomem *ioaddr = tp->mmio_addr;
874
875 sis190_soft_reset(ioaddr);
876
877 SIS_W32(TxDescStartAddr, tp->tx_dma);
878 SIS_W32(RxDescStartAddr, tp->rx_dma);
879
880 SIS_W32(IntrStatus, 0xffffffff);
881 SIS_W32(IntrMask, 0x0);
882 /*
883 * Default is 100Mbps.
884 * A bit strange: 100Mbps is 0x1801 elsewhere -- FR 2005/06/09
885 */
886 SIS_W16(StationControl, 0x1901);
887 SIS_W32(GMIIControl, 0x0);
888 SIS_W32(TxMacControl, 0x60);
889 SIS_W16(RxMacControl, 0x02);
890 SIS_W32(RxHashTable, 0x0);
891 SIS_W32(0x6c, 0x0);
188f23ba
FR		 892 SIS_W32(RxWolCtrl, 0x0);
893 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 894
895 SIS_PCI_COMMIT();
896
897 sis190_set_rx_mode(dev);
898
899 /* Enable all known interrupts by setting the interrupt mask. */
900 SIS_W32(IntrMask, sis190_intr_mask);
901
902 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
903 SIS_W32(RxControl, 0x1a1d);
904
905 netif_start_queue(dev);
906}
907
908static void sis190_phy_task(void * data)
909{
910 struct net_device *dev = data;
911 struct sis190_private *tp = netdev_priv(dev);
912 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 913 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 914 u16 val;
915
43afb949
FR		 916 rtnl_lock();
917
9ede109b 918 val = mdio_read(ioaddr, phy_id, MII_BMCR);
890e8d0a
FR		 919 if (val & BMCR_RESET) {
920 // FIXME: needlessly high ? -- FR 02/07/2005
921 mod_timer(&tp->timer, jiffies + HZ/10);
fc10c39d
FR		 922 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
923 BMSR_ANEGCOMPLETE)) {
890e8d0a
FR		 924 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
925 dev->name);
9ede109b 926 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
890e8d0a
FR		 927 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
928 } else {
929 /* Rejoice ! */
930 struct {
931 int val;
932 const char *msg;
933 u16 ctl;
934 } reg31[] = {
935 { LPA_1000XFULL | LPA_SLCT,
936 "1000 Mbps Full Duplex",
937 0x01 | _1000bpsF },
938 { LPA_1000XHALF | LPA_SLCT,
939 "1000 Mbps Half Duplex",
940 0x01 | _1000bpsH },
941 { LPA_100FULL,
942 "100 Mbps Full Duplex",
943 0x01 | _100bpsF },
944 { LPA_100HALF,
945 "100 Mbps Half Duplex",
946 0x01 | _100bpsH },
947 { LPA_10FULL,
948 "10 Mbps Full Duplex",
949 0x01 | _10bpsF },
950 { LPA_10HALF,
951 "10 Mbps Half Duplex",
952 0x01 | _10bpsH },
953 { 0, "unknown", 0x0000 }
954 }, *p;
955
9ede109b 956 val = mdio_read(ioaddr, phy_id, 0x1f);
890e8d0a
FR		 957 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
958
9ede109b 959 val = mdio_read(ioaddr, phy_id, MII_LPA);
890e8d0a
FR		 960 net_link(tp, KERN_INFO "%s: mii lpa = %04x.\n", dev->name, val);
961
962 for (p = reg31; p->ctl; p++) {
963 if ((val & p->val) == p->val)
964 break;
965 }
966 if (p->ctl)
967 SIS_W16(StationControl, p->ctl);
968 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
969 p->msg);
970 netif_carrier_on(dev);
971 }
43afb949
FR		 972
973 rtnl_unlock();
890e8d0a
FR		 974}
975
976static void sis190_phy_timer(unsigned long __opaque)
977{
978 struct net_device *dev = (struct net_device *)__opaque;
979 struct sis190_private *tp = netdev_priv(dev);
980
981 if (likely(netif_running(dev)))
982 schedule_work(&tp->phy_task);
983}
984
985static inline void sis190_delete_timer(struct net_device *dev)
986{
987 struct sis190_private *tp = netdev_priv(dev);
988
989 del_timer_sync(&tp->timer);
990}
991
992static inline void sis190_request_timer(struct net_device *dev)
993{
994 struct sis190_private *tp = netdev_priv(dev);
995 struct timer_list *timer = &tp->timer;
996
997 init_timer(timer);
998 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
999 timer->data = (unsigned long)dev;
1000 timer->function = sis190_phy_timer;
1001 add_timer(timer);
1002}
1003
1004static void sis190_set_rxbufsize(struct sis190_private *tp,
1005 struct net_device *dev)
1006{
1007 unsigned int mtu = dev->mtu;
1008
1009 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
8b5641d4
FR		 1010 /* RxDesc->size has a licence to kill the lower bits */
1011 if (tp->rx_buf_sz & 0x07) {
1012 tp->rx_buf_sz += 8;
1013 tp->rx_buf_sz &= RX_BUF_MASK;
1014 }
890e8d0a
FR		 1015}
1016
1017static int sis190_open(struct net_device *dev)
1018{
1019 struct sis190_private *tp = netdev_priv(dev);
1020 struct pci_dev *pdev = tp->pci_dev;
1021 int rc = -ENOMEM;
1022
1023 sis190_set_rxbufsize(tp, dev);
1024
1025 /*
1026 * Rx and Tx descriptors need 256 bytes alignment.
1027 * pci_alloc_consistent() guarantees a stronger alignment.
1028 */
1029 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1030 if (!tp->TxDescRing)
1031 goto out;
1032
1033 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1034 if (!tp->RxDescRing)
1035 goto err_free_tx_0;
1036
1037 rc = sis190_init_ring(dev);
1038 if (rc < 0)
1039 goto err_free_rx_1;
1040
1041 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1042
1043 sis190_request_timer(dev);
1044
1045 rc = request_irq(dev->irq, sis190_interrupt, SA_SHIRQ, dev->name, dev);
1046 if (rc < 0)
1047 goto err_release_timer_2;
1048
1049 sis190_hw_start(dev);
1050out:
1051 return rc;
1052
1053err_release_timer_2:
1054 sis190_delete_timer(dev);
1055 sis190_rx_clear(tp);
1056err_free_rx_1:
1057 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1058 tp->rx_dma);
1059err_free_tx_0:
1060 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1061 tp->tx_dma);
1062 goto out;
1063}
1064
1065static void sis190_tx_clear(struct sis190_private *tp)
1066{
1067 unsigned int i;
1068
1069 for (i = 0; i < NUM_TX_DESC; i++) {
1070 struct sk_buff *skb = tp->Tx_skbuff[i];
1071
1072 if (!skb)
1073 continue;
1074
1075 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1076 tp->Tx_skbuff[i] = NULL;
1077 dev_kfree_skb(skb);
1078
1079 tp->stats.tx_dropped++;
1080 }
1081 tp->cur_tx = tp->dirty_tx = 0;
1082}
1083
1084static void sis190_down(struct net_device *dev)
1085{
1086 struct sis190_private *tp = netdev_priv(dev);
1087 void __iomem *ioaddr = tp->mmio_addr;
1088 unsigned int poll_locked = 0;
1089
1090 sis190_delete_timer(dev);
1091
1092 netif_stop_queue(dev);
1093
1094 flush_scheduled_work();
1095
1096 do {
1097 spin_lock_irq(&tp->lock);
1098
1099 sis190_asic_down(ioaddr);
1100
1101 spin_unlock_irq(&tp->lock);
1102
1103 synchronize_irq(dev->irq);
1104
1105 if (!poll_locked) {
1106 netif_poll_disable(dev);
1107 poll_locked++;
1108 }
1109
1110 synchronize_sched();
1111
1112 } while (SIS_R32(IntrMask));
1113
1114 sis190_tx_clear(tp);
1115 sis190_rx_clear(tp);
1116}
1117
1118static int sis190_close(struct net_device *dev)
1119{
1120 struct sis190_private *tp = netdev_priv(dev);
1121 struct pci_dev *pdev = tp->pci_dev;
1122
1123 sis190_down(dev);
1124
1125 free_irq(dev->irq, dev);
1126
1127 netif_poll_enable(dev);
1128
1129 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1130 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1131
1132 tp->TxDescRing = NULL;
1133 tp->RxDescRing = NULL;
1134
1135 return 0;
1136}
1137
1138static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1139{
1140 struct sis190_private *tp = netdev_priv(dev);
1141 void __iomem *ioaddr = tp->mmio_addr;
1142 u32 len, entry, dirty_tx;
1143 struct TxDesc *desc;
1144 dma_addr_t mapping;
1145
1146 if (unlikely(skb->len < ETH_ZLEN)) {
1147 skb = skb_padto(skb, ETH_ZLEN);
1148 if (!skb) {
1149 tp->stats.tx_dropped++;
1150 goto out;
1151 }
1152 len = ETH_ZLEN;
1153 } else {
1154 len = skb->len;
1155 }
1156
1157 entry = tp->cur_tx % NUM_TX_DESC;
1158 desc = tp->TxDescRing + entry;
1159
1160 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1161 netif_stop_queue(dev);
1162 net_tx_err(tp, KERN_ERR PFX
1163 "%s: BUG! Tx Ring full when queue awake!\n",
1164 dev->name);
1165 return NETDEV_TX_BUSY;
1166 }
1167
1168 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1169
1170 tp->Tx_skbuff[entry] = skb;
1171
1172 desc->PSize = cpu_to_le32(len);
1173 desc->addr = cpu_to_le32(mapping);
1174
1175 desc->size = cpu_to_le32(len);
1176 if (entry == (NUM_TX_DESC - 1))
1177 desc->size |= cpu_to_le32(RingEnd);
1178
1179 wmb();
1180
1181 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1182
1183 tp->cur_tx++;
1184
1185 smp_wmb();
1186
1187 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1188
1189 dev->trans_start = jiffies;
1190
1191 dirty_tx = tp->dirty_tx;
1192 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1193 netif_stop_queue(dev);
1194 smp_rmb();
1195 if (dirty_tx != tp->dirty_tx)
1196 netif_wake_queue(dev);
1197 }
1198out:
1199 return NETDEV_TX_OK;
1200}
1201
1202static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1203{
1204 struct sis190_private *tp = netdev_priv(dev);
1205
1206 return &tp->stats;
1207}
1208
fcb9821d
FR		 1209static void sis190_free_phy(struct list_head *first_phy)
1210{
1211 struct sis190_phy *cur, *next;
1212
1213 list_for_each_entry_safe(cur, next, first_phy, list) {
1214 kfree(cur);
1215 }
1216}
1217
1218/**
1219 * sis190_default_phy - Select default PHY for sis190 mac.
1220 * @dev: the net device to probe for
1221 *
1222 * Select first detected PHY with link as default.
1223 * If no one is link on, select PHY whose types is HOME as default.
1224 * If HOME doesn't exist, select LAN.
1225 */
1226static u16 sis190_default_phy(struct net_device *dev)
1227{
1228 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1229 struct sis190_private *tp = netdev_priv(dev);
1230 struct mii_if_info *mii_if = &tp->mii_if;
1231 void __iomem *ioaddr = tp->mmio_addr;
1232 u16 status;
1233
1234 phy_home = phy_default = phy_lan = NULL;
1235
1236 list_for_each_entry(phy, &tp->first_phy, list) {
1237 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1238
1239 // Link ON & Not select default PHY & not ghost PHY.
1240 if ((status & BMSR_LSTATUS) &&
1241 !phy_default &&
1242 (phy->type != UNKNOWN)) {
1243 phy_default = phy;
1244 } else {
1245 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1246 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1247 status | BMCR_ANENABLE | BMCR_ISOLATE);
1248 if (phy->type == HOME)
1249 phy_home = phy;
1250 else if (phy->type == LAN)
1251 phy_lan = phy;
1252 }
1253 }
1254
1255 if (!phy_default) {
1256 if (phy_home)
1257 phy_default = phy_home;
1258 else if (phy_lan)
1259 phy_default = phy_lan;
1260 else
1261 phy_default = list_entry(&tp->first_phy,
1262 struct sis190_phy, list);
1263 }
1264
1265 if (mii_if->phy_id != phy_default->phy_id) {
1266 mii_if->phy_id = phy_default->phy_id;
1267 net_probe(tp, KERN_INFO
1268 "%s: Using transceiver at address %d as default.\n",
1269 dev->name, mii_if->phy_id);
1270 }
1271
1272 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1273 status &= (~BMCR_ISOLATE);
1274
1275 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1276 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1277
1278 return status;
1279}
1280
1281static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1282 struct sis190_phy *phy, unsigned int phy_id,
1283 u16 mii_status)
1284{
1285 void __iomem *ioaddr = tp->mmio_addr;
1286 struct mii_chip_info *p;
1287
1288 INIT_LIST_HEAD(&phy->list);
1289 phy->status = mii_status;
1290 phy->phy_id = phy_id;
1291
1292 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1293 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1294
1295 for (p = mii_chip_table; p->type; p++) {
1296 if ((p->id[0] == phy->id[0]) &&
1297 (p->id[1] == (phy->id[1] & 0xfff0))) {
1298 break;
1299 }
1300 }
1301
1302 if (p->id[1]) {
1303 phy->type = (p->type == MIX) ?
1304 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1305 LAN : HOME) : p->type;
1306 } else
1307 phy->type = UNKNOWN;
1308
1309 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
1310 dev->name, (phy->type == UNKNOWN) ? "Unknown PHY" : p->name,
1311 phy_id);
1312}
1313
1314/**
1315 * sis190_mii_probe - Probe MII PHY for sis190
1316 * @dev: the net device to probe for
1317 *
1318 * Search for total of 32 possible mii phy addresses.
1319 * Identify and set current phy if found one,
1320 * return error if it failed to found.
1321 */
1322static int __devinit sis190_mii_probe(struct net_device *dev)
1323{
1324 struct sis190_private *tp = netdev_priv(dev);
1325 struct mii_if_info *mii_if = &tp->mii_if;
1326 void __iomem *ioaddr = tp->mmio_addr;
1327 int phy_id;
1328 int rc = 0;
1329
1330 INIT_LIST_HEAD(&tp->first_phy);
1331
1332 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1333 struct sis190_phy *phy;
1334 u16 status;
1335
1336 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1337
1338 // Try next mii if the current one is not accessible.
1339 if (status == 0xffff || status == 0x0000)
1340 continue;
1341
1342 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1343 if (!phy) {
1344 sis190_free_phy(&tp->first_phy);
1345 rc = -ENOMEM;
1346 goto out;
1347 }
1348
1349 sis190_init_phy(dev, tp, phy, phy_id, status);
1350
1351 list_add(&tp->first_phy, &phy->list);
1352 }
1353
1354 if (list_empty(&tp->first_phy)) {
1355 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
1356 dev->name);
1357 rc = -EIO;
1358 goto out;
1359 }
1360
1361 /* Select default PHY for mac */
1362 sis190_default_phy(dev);
1363
1364 mii_if->dev = dev;
1365 mii_if->mdio_read = __mdio_read;
1366 mii_if->mdio_write = __mdio_write;
1367 mii_if->phy_id_mask = PHY_ID_ANY;
1368 mii_if->reg_num_mask = MII_REG_ANY;
1369out:
1370 return rc;
1371}
1372
1373static void __devexit sis190_mii_remove(struct net_device *dev)
1374{
1375 struct sis190_private *tp = netdev_priv(dev);
1376
1377 sis190_free_phy(&tp->first_phy);
1378}
1379
890e8d0a
FR		 1380static void sis190_release_board(struct pci_dev *pdev)
1381{
1382 struct net_device *dev = pci_get_drvdata(pdev);
1383 struct sis190_private *tp = netdev_priv(dev);
1384
1385 iounmap(tp->mmio_addr);
1386 pci_release_regions(pdev);
1387 pci_disable_device(pdev);
1388 free_netdev(dev);
1389}
1390
1391static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1392{
1393 struct sis190_private *tp;
1394 struct net_device *dev;
1395 void __iomem *ioaddr;
1396 int rc;
1397
1398 dev = alloc_etherdev(sizeof(*tp));
1399 if (!dev) {
1400 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1401 rc = -ENOMEM;
1402 goto err_out_0;
1403 }
1404
1405 SET_MODULE_OWNER(dev);
1406 SET_NETDEV_DEV(dev, &pdev->dev);
1407
1408 tp = netdev_priv(dev);
1409 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1410
1411 rc = pci_enable_device(pdev);
1412 if (rc < 0) {
1413 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1414 goto err_free_dev_1;
1415 }
1416
1417 rc = -ENODEV;
1418
1419 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1420 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1421 pci_name(pdev));
1422 goto err_pci_disable_2;
1423 }
1424 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1425 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1426 pci_name(pdev));
1427 goto err_pci_disable_2;
1428 }
1429
1430 rc = pci_request_regions(pdev, DRV_NAME);
1431 if (rc < 0) {
1432 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1433 pci_name(pdev));
1434 goto err_pci_disable_2;
1435 }
1436
1437 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1438 if (rc < 0) {
1439 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1440 pci_name(pdev));
1441 goto err_free_res_3;
1442 }
1443
1444 pci_set_master(pdev);
1445
1446 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1447 if (!ioaddr) {
1448 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1449 pci_name(pdev));
1450 rc = -EIO;
1451 goto err_free_res_3;
1452 }
1453
1454 tp->pci_dev = pdev;
1455 tp->mmio_addr = ioaddr;
1456
1457 sis190_irq_mask_and_ack(ioaddr);
1458
1459 sis190_soft_reset(ioaddr);
1460out:
1461 return dev;
1462
1463err_free_res_3:
1464 pci_release_regions(pdev);
1465err_pci_disable_2:
1466 pci_disable_device(pdev);
1467err_free_dev_1:
1468 free_netdev(dev);
1469err_out_0:
1470 dev = ERR_PTR(rc);
1471 goto out;
1472}
1473
1474static void sis190_tx_timeout(struct net_device *dev)
1475{
1476 struct sis190_private *tp = netdev_priv(dev);
1477 void __iomem *ioaddr = tp->mmio_addr;
1478 u8 tmp8;
1479
1480 /* Disable Tx, if not already */
1481 tmp8 = SIS_R8(TxControl);
1482 if (tmp8 & CmdTxEnb)
1483 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1484
188f23ba
FR		 1485
1486 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1487 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1488
890e8d0a
FR		 1489 /* Disable interrupts by clearing the interrupt mask. */
1490 SIS_W32(IntrMask, 0x0000);
1491
1492 /* Stop a shared interrupt from scavenging while we are. */
1493 spin_lock_irq(&tp->lock);
1494 sis190_tx_clear(tp);
1495 spin_unlock_irq(&tp->lock);
1496
1497 /* ...and finally, reset everything. */
1498 sis190_hw_start(dev);
1499
1500 netif_wake_queue(dev);
1501}
1502
830fb7d2
FR		 1503static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1504 struct net_device *dev)
1505{
1506 struct sis190_private *tp = netdev_priv(dev);
1507 void __iomem *ioaddr = tp->mmio_addr;
1508 u16 sig;
1509 int i;
1510
1511 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1512 pci_name(pdev));
1513
1514 /* Check to see if there is a sane EEPROM */
1515 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1516
1517 if ((sig == 0xffff) || (sig == 0x0000)) {
1518 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1519 pci_name(pdev), sig);
1520 return -EIO;
1521 }
1522
1523 /* Get MAC address from EEPROM */
1524 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
3cec93c7 1525 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
830fb7d2
FR		 1526
1527 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w);
1528 }
1529
1530 return 0;
1531}
1532
1533/**
1534 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1535 * @pdev: PCI device
1536 * @dev: network device to get address for
1537 *
1538 * SiS965 model, use APC CMOS RAM to store MAC address.
1539 * APC CMOS RAM is accessed through ISA bridge.
1540 * MAC address is read into @net_dev->dev_addr.
1541 */
1542static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1543 struct net_device *dev)
1544{
1545 struct sis190_private *tp = netdev_priv(dev);
1546 struct pci_dev *isa_bridge;
1547 u8 reg, tmp8;
1548 int i;
1549
1550 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1551 pci_name(pdev));
1552
1553 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1554 if (!isa_bridge) {
1555 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1556 pci_name(pdev));
1557 return -EIO;
1558 }
1559
1560 /* Enable port 78h & 79h to access APC Registers. */
1561 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1562 reg = (tmp8 & ~0x02);
1563 pci_write_config_byte(isa_bridge, 0x48, reg);
1564 udelay(50);
1565 pci_read_config_byte(isa_bridge, 0x48, &reg);
1566
1567 for (i = 0; i < MAC_ADDR_LEN; i++) {
1568 outb(0x9 + i, 0x78);
1569 dev->dev_addr[i] = inb(0x79);
1570 }
1571
1572 outb(0x12, 0x78);
1573 reg = inb(0x79);
1574
1575 /* Restore the value to ISA Bridge */
1576 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1577 pci_dev_put(isa_bridge);
1578
1579 return 0;
1580}
1581
1582/**
1583 * sis190_init_rxfilter - Initialize the Rx filter
1584 * @dev: network device to initialize
1585 *
1586 * Set receive filter address to our MAC address
1587 * and enable packet filtering.
1588 */
1589static inline void sis190_init_rxfilter(struct net_device *dev)
1590{
1591 struct sis190_private *tp = netdev_priv(dev);
1592 void __iomem *ioaddr = tp->mmio_addr;
1593 u16 ctl;
1594 int i;
1595
1596 ctl = SIS_R16(RxMacControl);
1597 /*
1598 * Disable packet filtering before setting filter.
1599 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1600 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1601 */
1602 SIS_W16(RxMacControl, ctl & ~0x0f00);
1603
1604 for (i = 0; i < MAC_ADDR_LEN; i++)
1605 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1606
1607 SIS_W16(RxMacControl, ctl);
1608 SIS_PCI_COMMIT();
1609}
1610
1611static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1612{
1613 u8 from;
1614
1615 pci_read_config_byte(pdev, 0x73, &from);
1616
1617 return (from & 0x00000001) ?
1618 sis190_get_mac_addr_from_apc(pdev, dev) :
1619 sis190_get_mac_addr_from_eeprom(pdev, dev);
1620}
1621
890e8d0a
FR		 1622static void sis190_set_speed_auto(struct net_device *dev)
1623{
1624 struct sis190_private *tp = netdev_priv(dev);
1625 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 1626 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 1627 int val;
1628
1629 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1630
9ede109b 1631 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
890e8d0a
FR		 1632
1633 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1634 // unchanged.
9ede109b 1635 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
890e8d0a
FR		 1636 ADVERTISE_100FULL | ADVERTISE_10FULL |
1637 ADVERTISE_100HALF | ADVERTISE_10HALF);
1638
1639 // Enable 1000 Full Mode.
9ede109b 1640 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
890e8d0a
FR		 1641
1642 // Enable auto-negotiation and restart auto-negotiation.
9ede109b 1643 mdio_write(ioaddr, phy_id, MII_BMCR,
890e8d0a
FR		 1644 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1645}
1646
43afb949
FR		 1647static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1648{
1649 struct sis190_private *tp = netdev_priv(dev);
1650
1651 return mii_ethtool_gset(&tp->mii_if, cmd);
1652}
1653
1654static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1655{
1656 struct sis190_private *tp = netdev_priv(dev);
1657
1658 return mii_ethtool_sset(&tp->mii_if, cmd);
1659}
1660
890e8d0a
FR		 1661static void sis190_get_drvinfo(struct net_device *dev,
1662 struct ethtool_drvinfo *info)
1663{
1664 struct sis190_private *tp = netdev_priv(dev);
1665
1666 strcpy(info->driver, DRV_NAME);
1667 strcpy(info->version, DRV_VERSION);
1668 strcpy(info->bus_info, pci_name(tp->pci_dev));
1669}
1670
1671static int sis190_get_regs_len(struct net_device *dev)
1672{
1673 return SIS190_REGS_SIZE;
1674}
1675
1676static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1677 void *p)
1678{
1679 struct sis190_private *tp = netdev_priv(dev);
1680 unsigned long flags;
1681
1682 if (regs->len > SIS190_REGS_SIZE)
1683 regs->len = SIS190_REGS_SIZE;
1684
1685 spin_lock_irqsave(&tp->lock, flags);
1686 memcpy_fromio(p, tp->mmio_addr, regs->len);
1687 spin_unlock_irqrestore(&tp->lock, flags);
1688}
1689
43afb949
FR		 1690static int sis190_nway_reset(struct net_device *dev)
1691{
1692 struct sis190_private *tp = netdev_priv(dev);
1693
1694 return mii_nway_restart(&tp->mii_if);
1695}
1696
890e8d0a
FR		 1697static u32 sis190_get_msglevel(struct net_device *dev)
1698{
1699 struct sis190_private *tp = netdev_priv(dev);
1700
1701 return tp->msg_enable;
1702}
1703
1704static void sis190_set_msglevel(struct net_device *dev, u32 value)
1705{
1706 struct sis190_private *tp = netdev_priv(dev);
1707
1708 tp->msg_enable = value;
1709}
1710
1711static struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1712 .get_settings = sis190_get_settings,
1713 .set_settings = sis190_set_settings,
890e8d0a
FR		 1714 .get_drvinfo = sis190_get_drvinfo,
1715 .get_regs_len = sis190_get_regs_len,
1716 .get_regs = sis190_get_regs,
1717 .get_link = ethtool_op_get_link,
1718 .get_msglevel = sis190_get_msglevel,
1719 .set_msglevel = sis190_set_msglevel,
43afb949 1720 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1721};
1722
43afb949
FR		 1723static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1724{
1725 struct sis190_private *tp = netdev_priv(dev);
1726
1727 return !netif_running(dev) ? -EINVAL :
1728 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1729}
1730
890e8d0a
FR		 1731static int __devinit sis190_init_one(struct pci_dev *pdev,
1732 const struct pci_device_id *ent)
1733{
1734 static int printed_version = 0;
1735 struct sis190_private *tp;
1736 struct net_device *dev;
1737 void __iomem *ioaddr;
830fb7d2 1738 int rc;
890e8d0a
FR		 1739
1740 if (!printed_version) {
1741 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1742 printed_version = 1;
1743 }
1744
1745 dev = sis190_init_board(pdev);
1746 if (IS_ERR(dev)) {
1747 rc = PTR_ERR(dev);
1748 goto out;
1749 }
1750
1751 tp = netdev_priv(dev);
1752 ioaddr = tp->mmio_addr;
1753
830fb7d2
FR		 1754 rc = sis190_get_mac_addr(pdev, dev);
1755 if (rc < 0)
1756 goto err_release_board;
890e8d0a 1757
830fb7d2 1758 sis190_init_rxfilter(dev);
890e8d0a
FR		 1759
1760 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1761
1762 dev->open = sis190_open;
1763 dev->stop = sis190_close;
43afb949 1764 dev->do_ioctl = sis190_ioctl;
890e8d0a
FR		 1765 dev->get_stats = sis190_get_stats;
1766 dev->tx_timeout = sis190_tx_timeout;
1767 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1768 dev->hard_start_xmit = sis190_start_xmit;
4405d3b5
FR		 1769#ifdef CONFIG_NET_POLL_CONTROLLER
1770 dev->poll_controller = sis190_netpoll;
1771#endif
890e8d0a
FR		 1772 dev->set_multicast_list = sis190_set_rx_mode;
1773 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1774 dev->irq = pdev->irq;
1775 dev->base_addr = (unsigned long) 0xdead;
1776
1777 spin_lock_init(&tp->lock);
1778 rc = register_netdev(dev);
830fb7d2
FR		 1779 if (rc < 0)
1780 goto err_release_board;
890e8d0a
FR		 1781
1782 pci_set_drvdata(pdev, dev);
1783
fcb9821d
FR		 1784 rc = sis190_mii_probe(dev);
1785 if (rc < 0)
1786 goto err_unregister_dev;
1787
890e8d0a
FR		 1788 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1789 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1790 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1791 ioaddr, dev->irq,
1792 dev->dev_addr[0], dev->dev_addr[1],
1793 dev->dev_addr[2], dev->dev_addr[3],
1794 dev->dev_addr[4], dev->dev_addr[5]);
1795
1796 netif_carrier_off(dev);
1797
1798 sis190_set_speed_auto(dev);
1799out:
1800 return rc;
830fb7d2 1801
fcb9821d
FR		 1802err_unregister_dev:
1803 unregister_netdev(dev);
830fb7d2
FR		 1804err_release_board:
1805 sis190_release_board(pdev);
1806 goto out;
890e8d0a
FR		 1807}
1808
1809static void __devexit sis190_remove_one(struct pci_dev *pdev)
1810{
1811 struct net_device *dev = pci_get_drvdata(pdev);
1812
fcb9821d 1813 sis190_mii_remove(dev);
890e8d0a
FR		 1814 unregister_netdev(dev);
1815 sis190_release_board(pdev);
1816 pci_set_drvdata(pdev, NULL);
1817}
1818
1819static struct pci_driver sis190_pci_driver = {
1820 .name = DRV_NAME,
1821 .id_table = sis190_pci_tbl,
1822 .probe = sis190_init_one,
1823 .remove = __devexit_p(sis190_remove_one),
1824};
1825
1826static int __init sis190_init_module(void)
1827{
1828 return pci_module_init(&sis190_pci_driver);
1829}
1830
1831static void __exit sis190_cleanup_module(void)
1832{
1833 pci_unregister_driver(&sis190_pci_driver);
1834}
1835
1836module_init(sis190_init_module);
1837module_exit(sis190_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)