[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sfc / xfp_phy.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */
/*
 * Driver for SFP+ and XFP optical PHYs plus some support specific to the
 * AMCC QT20xx adapters; see www.amcc.com for details
 */

#include <linux/timer.h>
#include <linux/delay.h>
#include "efx.h"
#include "mdio_10g.h"
#include "phy.h"
#include "falcon.h"

#define XFP_REQUIRED_DEVS (MDIO_DEVS_PCS |	\
			   MDIO_DEVS_PMAPMD |	\
			   MDIO_DEVS_PHYXS)

#define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) |		\
		       (1 << LOOPBACK_PMAPMD) |		\
		       (1 << LOOPBACK_NETWORK))

/****************************************************************************/
/* Quake-specific MDIO registers */
#define MDIO_QUAKE_LED0_REG	(0xD006)

/* QT2025C only */
#define PCS_FW_HEARTBEAT_REG	0xd7ee
#define PCS_FW_HEARTB_LBN	0
#define PCS_FW_HEARTB_WIDTH	8
#define PCS_UC8051_STATUS_REG	0xd7fd
#define PCS_UC_STATUS_LBN	0
#define PCS_UC_STATUS_WIDTH	8
#define PCS_UC_STATUS_FW_SAVE	0x20
#define PMA_PMD_FTX_CTRL2_REG	0xc309
#define PMA_PMD_FTX_STATIC_LBN	13
#define PMA_PMD_VEND1_REG	0xc001
#define PMA_PMD_VEND1_LBTXD_LBN	15
#define PCS_VEND1_REG	   	0xc000
#define PCS_VEND1_LBTXD_LBN	5

void xfp_set_led(struct efx_nic *p, int led, int mode)
{
	int addr = MDIO_QUAKE_LED0_REG + led;
	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
}

struct xfp_phy_data {
	enum efx_phy_mode phy_mode;
};

#define XFP_MAX_RESET_TIME 500
#define XFP_RESET_WAIT 10

static int qt2025c_wait_reset(struct efx_nic *efx)
{
	unsigned long timeout = jiffies + 10 * HZ;
	int reg, old_counter = 0;

	/* Wait for firmware heartbeat to start */
	for (;;) {
		int counter;
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
		if (reg < 0)
			return reg;
		counter = ((reg >> PCS_FW_HEARTB_LBN) &
			    ((1 << PCS_FW_HEARTB_WIDTH) - 1));
		if (old_counter == 0)
			old_counter = counter;
		else if (counter != old_counter)
			break;
		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
		msleep(10);
	}

	/* Wait for firmware status to look good */
	for (;;) {
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
		if (reg < 0)
			return reg;
		if ((reg &
		     ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
		    PCS_UC_STATUS_FW_SAVE)
			break;
		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
		msleep(100);
	}

	return 0;
}

static int xfp_reset_phy(struct efx_nic *efx)
{
	int rc;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		/* Wait for the reset triggered by falcon_reset_hw()
		 * to complete */
		rc = qt2025c_wait_reset(efx);
		if (rc < 0)
			goto fail;
	} else {
		/* Reset the PHYXS MMD. This is documented as doing
		 * a complete soft reset. */
		rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
					XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
					XFP_RESET_WAIT);
		if (rc < 0)
			goto fail;
	}

	/* Wait 250ms for the PHY to complete bootup */
	msleep(250);

	/* Check that all the MMDs we expect are present and responding. We
	 * expect faults on some if the link is down, but not on the PHY XS */
	rc = efx_mdio_check_mmds(efx, XFP_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
	if (rc < 0)
		goto fail;

	efx->board_info.init_leds(efx);

	return rc;

 fail:
	EFX_ERR(efx, "PHY reset timed out\n");
	return rc;
}

static int xfp_phy_init(struct efx_nic *efx)
{
	struct xfp_phy_data *phy_data;
	u32 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
	int rc;

	phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;

	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
		 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
		 efx_mdio_id_rev(devid));

	phy_data->phy_mode = efx->phy_mode;

	rc = xfp_reset_phy(efx);

	EFX_INFO(efx, "PHY init %s.\n",
		 rc ? "failed" : "successful");
	if (rc < 0)
		goto fail;

	return 0;

 fail:
	kfree(efx->phy_data);
	efx->phy_data = NULL;
	return rc;
}

static void xfp_phy_clear_interrupt(struct efx_nic *efx)
{
	/* Read to clear link status alarm */
	efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT);
}

static int xfp_link_ok(struct efx_nic *efx)
{
	return efx_mdio_links_ok(efx, XFP_REQUIRED_DEVS);
}

static void xfp_phy_poll(struct efx_nic *efx)
{
	int link_up = xfp_link_ok(efx);
	/* Simulate a PHY event if link state has changed */
	if (link_up != efx->link_up)
		falcon_sim_phy_event(efx);
}

static void xfp_phy_reconfigure(struct efx_nic *efx)
{
	struct xfp_phy_data *phy_data = efx->phy_data;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		/* There are several different register bits which can
		 * disable TX (and save power) on direct-attach cables
		 * or optical transceivers, varying somewhat between
		 * firmware versions.  Only 'static mode' appears to
		 * cover everything. */
		mdio_set_flag(
			&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
			PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
			efx->phy_mode & PHY_MODE_TX_DISABLED ||
			efx->phy_mode & PHY_MODE_LOW_POWER ||
			efx->loopback_mode == LOOPBACK_PCS ||
			efx->loopback_mode == LOOPBACK_PMAPMD);
	} else {
		/* Reset the PHY when moving from tx off to tx on */
		if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
		    (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
			xfp_reset_phy(efx);

		efx_mdio_transmit_disable(efx);
	}

	efx_mdio_phy_reconfigure(efx);

	phy_data->phy_mode = efx->phy_mode;
	efx->link_up = xfp_link_ok(efx);
	efx->link_speed = 10000;
	efx->link_fd = true;
	efx->link_fc = efx->wanted_fc;
}

static void xfp_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	mdio45_ethtool_gset(&efx->mdio, ecmd);
}

static void xfp_phy_fini(struct efx_nic *efx)
{
	/* Clobber the LED if it was blinking */
	efx->board_info.blink(efx, false);

	/* Free the context block */
	kfree(efx->phy_data);
	efx->phy_data = NULL;
}

struct efx_phy_operations falcon_xfp_phy_ops = {
	.macs		 = EFX_XMAC,
	.init            = xfp_phy_init,
	.reconfigure     = xfp_phy_reconfigure,
	.poll            = xfp_phy_poll,
	.fini            = xfp_phy_fini,
	.clear_interrupt = xfp_phy_clear_interrupt,
	.get_settings    = xfp_phy_get_settings,
	.set_settings	 = efx_mdio_set_settings,
	.mmds            = XFP_REQUIRED_DEVS,
	.loopbacks       = XFP_LOOPBACKS,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2006-2008 Solarflare Communications Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9	/*
d2d2c373 BH	10	* Driver for SFP+ and XFP optical PHYs plus some support specific to the
d2d2c373 BH	11	* AMCC QT20xx adapters; see www.amcc.com for details
8ceee660 BH	12	*/
	13
	14	#include <linux/timer.h>
	15	#include <linux/delay.h>
	16	#include "efx.h"
8ceee660	17	#include "mdio_10g.h"
8ceee660	18	#include "phy.h"
177dfcd8	19	#include "falcon.h"
8ceee660	20
68e7f45e BH	21	#define XFP_REQUIRED_DEVS (MDIO_DEVS_PCS \| \
	22	MDIO_DEVS_PMAPMD \| \
	23	MDIO_DEVS_PHYXS)
8ceee660	24
3273c2e8 BH	25	#define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) \| \
	26	(1 << LOOPBACK_PMAPMD) \| \
	27	(1 << LOOPBACK_NETWORK))
	28
8ceee660 BH	29	/****************************************************************************/
	30	/* Quake-specific MDIO registers */
	31	#define MDIO_QUAKE_LED0_REG (0xD006)
	32
d2d2c373 BH	33	/* QT2025C only */
	34	#define PCS_FW_HEARTBEAT_REG 0xd7ee
	35	#define PCS_FW_HEARTB_LBN 0
	36	#define PCS_FW_HEARTB_WIDTH 8
	37	#define PCS_UC8051_STATUS_REG 0xd7fd
	38	#define PCS_UC_STATUS_LBN 0
	39	#define PCS_UC_STATUS_WIDTH 8
	40	#define PCS_UC_STATUS_FW_SAVE 0x20
	41	#define PMA_PMD_FTX_CTRL2_REG 0xc309
	42	#define PMA_PMD_FTX_STATIC_LBN 13
	43	#define PMA_PMD_VEND1_REG 0xc001
	44	#define PMA_PMD_VEND1_LBTXD_LBN 15
	45	#define PCS_VEND1_REG 0xc000
	46	#define PCS_VEND1_LBTXD_LBN 5
	47
8ceee660 BH	48	void xfp_set_led(struct efx_nic *p, int led, int mode)
	49	{
	50	int addr = MDIO_QUAKE_LED0_REG + led;
68e7f45e	51	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
8ceee660 BH	52	}
8ceee660 BH	53
3273c2e8	54	struct xfp_phy_data {
f8b87c17	55	enum efx_phy_mode phy_mode;
3273c2e8 BH	56	};
3273c2e8 BH	57
8ceee660 BH	58	#define XFP_MAX_RESET_TIME 500
	59	#define XFP_RESET_WAIT 10
	60
d2d2c373 BH	61	static int qt2025c_wait_reset(struct efx_nic *efx)
	62	{
	63	unsigned long timeout = jiffies + 10 * HZ;
d2d2c373 BH	64	int reg, old_counter = 0;
	65
	66	/* Wait for firmware heartbeat to start */
	67	for (;;) {
	68	int counter;
68e7f45e	69	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
d2d2c373 BH	70	if (reg < 0)
	71	return reg;
	72	counter = ((reg >> PCS_FW_HEARTB_LBN) &
	73	((1 << PCS_FW_HEARTB_WIDTH) - 1));
	74	if (old_counter == 0)
	75	old_counter = counter;
	76	else if (counter != old_counter)
	77	break;
	78	if (time_after(jiffies, timeout))
	79	return -ETIMEDOUT;
	80	msleep(10);
	81	}
	82
	83	/* Wait for firmware status to look good */
	84	for (;;) {
68e7f45e	85	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
d2d2c373 BH	86	if (reg < 0)
	87	return reg;
	88	if ((reg &
	89	((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
	90	PCS_UC_STATUS_FW_SAVE)
	91	break;
	92	if (time_after(jiffies, timeout))
	93	return -ETIMEDOUT;
	94	msleep(100);
	95	}
	96
	97	return 0;
	98	}
	99
8ceee660 BH	100	static int xfp_reset_phy(struct efx_nic *efx)
	101	{
	102	int rc;
	103
d2d2c373	104	if (efx->phy_type == PHY_TYPE_QT2025C) {
5afaa753 BH	105	/* Wait for the reset triggered by falcon_reset_hw()
5afaa753 BH	106	* to complete */
d2d2c373 BH	107	rc = qt2025c_wait_reset(efx);
	108	if (rc < 0)
	109	goto fail;
5afaa753 BH	110	} else {
	111	/* Reset the PHYXS MMD. This is documented as doing
	112	* a complete soft reset. */
	113	rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
	114	XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
	115	XFP_RESET_WAIT);
	116	if (rc < 0)
	117	goto fail;
d2d2c373 BH	118	}
d2d2c373 BH	119
8ceee660 BH	120	/* Wait 250ms for the PHY to complete bootup */
	121	msleep(250);
	122
	123	/* Check that all the MMDs we expect are present and responding. We
	124	* expect faults on some if the link is down, but not on the PHY XS */
68e7f45e	125	rc = efx_mdio_check_mmds(efx, XFP_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
8ceee660 BH	126	if (rc < 0)
	127	goto fail;
	128
	129	efx->board_info.init_leds(efx);
	130
	131	return rc;
	132
	133	fail:
f794fd44	134	EFX_ERR(efx, "PHY reset timed out\n");
8ceee660 BH	135	return rc;
	136	}
	137
	138	static int xfp_phy_init(struct efx_nic *efx)
	139	{
3273c2e8	140	struct xfp_phy_data *phy_data;
68e7f45e	141	u32 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
8ceee660 BH	142	int rc;
8ceee660 BH	143
3273c2e8	144	phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
9b7bfc4c BH	145	if (!phy_data)
9b7bfc4c BH	146	return -ENOMEM;
d3208b5e	147	efx->phy_data = phy_data;
3273c2e8	148
3f39a5e9	149	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
68e7f45e BH	150	devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
68e7f45e BH	151	efx_mdio_id_rev(devid));
8ceee660	152
f8b87c17	153	phy_data->phy_mode = efx->phy_mode;
3273c2e8	154
8ceee660 BH	155	rc = xfp_reset_phy(efx);
8ceee660 BH	156
f794fd44	157	EFX_INFO(efx, "PHY init %s.\n",
8ceee660	158	rc ? "failed" : "successful");
3273c2e8 BH	159	if (rc < 0)
3273c2e8 BH	160	goto fail;
8ceee660	161
3273c2e8 BH	162	return 0;
	163
	164	fail:
	165	kfree(efx->phy_data);
	166	efx->phy_data = NULL;
8ceee660 BH	167	return rc;
	168	}
	169
	170	static void xfp_phy_clear_interrupt(struct efx_nic *efx)
	171	{
6bc5046e BH	172	/* Read to clear link status alarm */
6bc5046e BH	173	efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT);
8ceee660 BH	174	}
	175
	176	static int xfp_link_ok(struct efx_nic *efx)
	177	{
68e7f45e	178	return efx_mdio_links_ok(efx, XFP_REQUIRED_DEVS);
8ceee660 BH	179	}
8ceee660 BH	180
766ca0fa	181	static void xfp_phy_poll(struct efx_nic *efx)
8ceee660	182	{
8ceee660 BH	183	int link_up = xfp_link_ok(efx);
	184	/* Simulate a PHY event if link state has changed */
	185	if (link_up != efx->link_up)
177dfcd8	186	falcon_sim_phy_event(efx);
8ceee660 BH	187	}
	188
	189	static void xfp_phy_reconfigure(struct efx_nic *efx)
	190	{
3273c2e8 BH	191	struct xfp_phy_data *phy_data = efx->phy_data;
3273c2e8 BH	192
d2d2c373 BH	193	if (efx->phy_type == PHY_TYPE_QT2025C) {
	194	/* There are several different register bits which can
	195	* disable TX (and save power) on direct-attach cables
	196	* or optical transceivers, varying somewhat between
	197	* firmware versions. Only 'static mode' appears to
	198	* cover everything. */
68e7f45e BH	199	mdio_set_flag(
	200	&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
	201	PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
d2d2c373 BH	202	efx->phy_mode & PHY_MODE_TX_DISABLED \|\|
	203	efx->phy_mode & PHY_MODE_LOW_POWER \|\|
	204	efx->loopback_mode == LOOPBACK_PCS \|\|
	205	efx->loopback_mode == LOOPBACK_PMAPMD);
	206	} else {
	207	/* Reset the PHY when moving from tx off to tx on */
	208	if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
	209	(phy_data->phy_mode & PHY_MODE_TX_DISABLED))
	210	xfp_reset_phy(efx);
	211
68e7f45e	212	efx_mdio_transmit_disable(efx);
d2d2c373	213	}
3273c2e8	214
68e7f45e	215	efx_mdio_phy_reconfigure(efx);
3273c2e8	216
f8b87c17	217	phy_data->phy_mode = efx->phy_mode;
8ceee660	218	efx->link_up = xfp_link_ok(efx);
f31a45d2 BH	219	efx->link_speed = 10000;
f31a45d2 BH	220	efx->link_fd = true;
04cc8cac	221	efx->link_fc = efx->wanted_fc;
8ceee660 BH	222	}
8ceee660 BH	223
68e7f45e BH	224	static void xfp_phy_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
	225	{
	226	mdio45_ethtool_gset(&efx->mdio, ecmd);
	227	}
8ceee660 BH	228
	229	static void xfp_phy_fini(struct efx_nic *efx)
	230	{
	231	/* Clobber the LED if it was blinking */
dc8cfa55	232	efx->board_info.blink(efx, false);
3273c2e8 BH	233
	234	/* Free the context block */
	235	kfree(efx->phy_data);
	236	efx->phy_data = NULL;
8ceee660 BH	237	}
	238
	239	struct efx_phy_operations falcon_xfp_phy_ops = {
177dfcd8	240	.macs = EFX_XMAC,
8ceee660 BH	241	.init = xfp_phy_init,
8ceee660 BH	242	.reconfigure = xfp_phy_reconfigure,
766ca0fa	243	.poll = xfp_phy_poll,
8ceee660 BH	244	.fini = xfp_phy_fini,
8ceee660 BH	245	.clear_interrupt = xfp_phy_clear_interrupt,
68e7f45e BH	246	.get_settings = xfp_phy_get_settings,
68e7f45e BH	247	.set_settings = efx_mdio_set_settings,
8ceee660	248	.mmds = XFP_REQUIRED_DEVS,
3273c2e8	249	.loopbacks = XFP_LOOPBACKS,
8ceee660	250	};