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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2010 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
738a8f4b | 15 | #include <linux/ipv6.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
738a8f4b | 17 | #include <net/ipv6.h> |
8ceee660 BH |
18 | #include <linux/if_ether.h> |
19 | #include <linux/highmem.h> | |
20 | #include "net_driver.h" | |
8ceee660 | 21 | #include "efx.h" |
744093c9 | 22 | #include "nic.h" |
8ceee660 BH |
23 | #include "workarounds.h" |
24 | ||
25 | /* | |
26 | * TX descriptor ring full threshold | |
27 | * | |
28 | * The tx_queue descriptor ring fill-level must fall below this value | |
29 | * before we restart the netif queue | |
30 | */ | |
ecc910f5 | 31 | #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u) |
8ceee660 | 32 | |
4d566063 BH |
33 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
34 | struct efx_tx_buffer *buffer) | |
8ceee660 BH |
35 | { |
36 | if (buffer->unmap_len) { | |
37 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
cc12dac2 BH |
38 | dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len - |
39 | buffer->unmap_len); | |
8ceee660 | 40 | if (buffer->unmap_single) |
cc12dac2 BH |
41 | pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len, |
42 | PCI_DMA_TODEVICE); | |
8ceee660 | 43 | else |
cc12dac2 BH |
44 | pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len, |
45 | PCI_DMA_TODEVICE); | |
8ceee660 | 46 | buffer->unmap_len = 0; |
dc8cfa55 | 47 | buffer->unmap_single = false; |
8ceee660 BH |
48 | } |
49 | ||
50 | if (buffer->skb) { | |
51 | dev_kfree_skb_any((struct sk_buff *) buffer->skb); | |
52 | buffer->skb = NULL; | |
62776d03 BH |
53 | netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, |
54 | "TX queue %d transmission id %x complete\n", | |
55 | tx_queue->queue, tx_queue->read_count); | |
8ceee660 BH |
56 | } |
57 | } | |
58 | ||
b9b39b62 BH |
59 | /** |
60 | * struct efx_tso_header - a DMA mapped buffer for packet headers | |
61 | * @next: Linked list of free ones. | |
62 | * The list is protected by the TX queue lock. | |
63 | * @dma_unmap_len: Length to unmap for an oversize buffer, or 0. | |
64 | * @dma_addr: The DMA address of the header below. | |
65 | * | |
66 | * This controls the memory used for a TSO header. Use TSOH_DATA() | |
67 | * to find the packet header data. Use TSOH_SIZE() to calculate the | |
68 | * total size required for a given packet header length. TSO headers | |
69 | * in the free list are exactly %TSOH_STD_SIZE bytes in size. | |
70 | */ | |
71 | struct efx_tso_header { | |
72 | union { | |
73 | struct efx_tso_header *next; | |
74 | size_t unmap_len; | |
75 | }; | |
76 | dma_addr_t dma_addr; | |
77 | }; | |
78 | ||
79 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 80 | struct sk_buff *skb); |
b9b39b62 BH |
81 | static void efx_fini_tso(struct efx_tx_queue *tx_queue); |
82 | static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, | |
83 | struct efx_tso_header *tsoh); | |
84 | ||
4d566063 BH |
85 | static void efx_tsoh_free(struct efx_tx_queue *tx_queue, |
86 | struct efx_tx_buffer *buffer) | |
b9b39b62 BH |
87 | { |
88 | if (buffer->tsoh) { | |
89 | if (likely(!buffer->tsoh->unmap_len)) { | |
90 | buffer->tsoh->next = tx_queue->tso_headers_free; | |
91 | tx_queue->tso_headers_free = buffer->tsoh; | |
92 | } else { | |
93 | efx_tsoh_heap_free(tx_queue, buffer->tsoh); | |
94 | } | |
95 | buffer->tsoh = NULL; | |
96 | } | |
97 | } | |
98 | ||
8ceee660 | 99 | |
63f19884 BH |
100 | static inline unsigned |
101 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
102 | { | |
103 | /* Depending on the NIC revision, we can use descriptor | |
104 | * lengths up to 8K or 8K-1. However, since PCI Express | |
105 | * devices must split read requests at 4K boundaries, there is | |
106 | * little benefit from using descriptors that cross those | |
107 | * boundaries and we keep things simple by not doing so. | |
108 | */ | |
109 | unsigned len = (~dma_addr & 0xfff) + 1; | |
110 | ||
111 | /* Work around hardware bug for unaligned buffers. */ | |
112 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
113 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
114 | ||
115 | return len; | |
116 | } | |
117 | ||
8ceee660 BH |
118 | /* |
119 | * Add a socket buffer to a TX queue | |
120 | * | |
121 | * This maps all fragments of a socket buffer for DMA and adds them to | |
122 | * the TX queue. The queue's insert pointer will be incremented by | |
123 | * the number of fragments in the socket buffer. | |
124 | * | |
125 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
126 | * the queue's insert pointer will be restored to its original value. | |
127 | * | |
497f5ba3 BH |
128 | * This function is split out from efx_hard_start_xmit to allow the |
129 | * loopback test to direct packets via specific TX queues. | |
130 | * | |
8ceee660 BH |
131 | * Returns NETDEV_TX_OK or NETDEV_TX_BUSY |
132 | * You must hold netif_tx_lock() to call this function. | |
133 | */ | |
497f5ba3 | 134 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
8ceee660 BH |
135 | { |
136 | struct efx_nic *efx = tx_queue->efx; | |
137 | struct pci_dev *pci_dev = efx->pci_dev; | |
138 | struct efx_tx_buffer *buffer; | |
139 | skb_frag_t *fragment; | |
140 | struct page *page; | |
141 | int page_offset; | |
63f19884 | 142 | unsigned int len, unmap_len = 0, fill_level, insert_ptr; |
8ceee660 BH |
143 | dma_addr_t dma_addr, unmap_addr = 0; |
144 | unsigned int dma_len; | |
dc8cfa55 | 145 | bool unmap_single; |
8ceee660 | 146 | int q_space, i = 0; |
61357325 | 147 | netdev_tx_t rc = NETDEV_TX_OK; |
8ceee660 BH |
148 | |
149 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
150 | ||
9bc183d7 | 151 | if (skb_shinfo(skb)->gso_size) |
b9b39b62 BH |
152 | return efx_enqueue_skb_tso(tx_queue, skb); |
153 | ||
8ceee660 BH |
154 | /* Get size of the initial fragment */ |
155 | len = skb_headlen(skb); | |
156 | ||
bb145a9e BH |
157 | /* Pad if necessary */ |
158 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
159 | EFX_BUG_ON_PARANOID(skb->data_len); | |
160 | len = 32 + 1; | |
161 | if (skb_pad(skb, len - skb->len)) | |
162 | return NETDEV_TX_OK; | |
163 | } | |
164 | ||
8ceee660 | 165 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; |
ecc910f5 | 166 | q_space = efx->txq_entries - 1 - fill_level; |
8ceee660 BH |
167 | |
168 | /* Map for DMA. Use pci_map_single rather than pci_map_page | |
169 | * since this is more efficient on machines with sparse | |
170 | * memory. | |
171 | */ | |
dc8cfa55 | 172 | unmap_single = true; |
8ceee660 BH |
173 | dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
174 | ||
175 | /* Process all fragments */ | |
176 | while (1) { | |
8d8bb39b | 177 | if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr))) |
8ceee660 BH |
178 | goto pci_err; |
179 | ||
180 | /* Store fields for marking in the per-fragment final | |
181 | * descriptor */ | |
182 | unmap_len = len; | |
183 | unmap_addr = dma_addr; | |
184 | ||
185 | /* Add to TX queue, splitting across DMA boundaries */ | |
186 | do { | |
187 | if (unlikely(q_space-- <= 0)) { | |
188 | /* It might be that completions have | |
189 | * happened since the xmit path last | |
190 | * checked. Update the xmit path's | |
191 | * copy of read_count. | |
192 | */ | |
c04bfc6b | 193 | netif_tx_stop_queue(tx_queue->core_txq); |
8ceee660 | 194 | /* This memory barrier protects the |
c04bfc6b | 195 | * change of queue state from the access |
8ceee660 BH |
196 | * of read_count. */ |
197 | smp_mb(); | |
198 | tx_queue->old_read_count = | |
51c56f40 | 199 | ACCESS_ONCE(tx_queue->read_count); |
8ceee660 BH |
200 | fill_level = (tx_queue->insert_count |
201 | - tx_queue->old_read_count); | |
ecc910f5 | 202 | q_space = efx->txq_entries - 1 - fill_level; |
c04bfc6b BH |
203 | if (unlikely(q_space-- <= 0)) { |
204 | rc = NETDEV_TX_BUSY; | |
205 | goto unwind; | |
206 | } | |
8ceee660 | 207 | smp_mb(); |
c04bfc6b | 208 | netif_tx_start_queue(tx_queue->core_txq); |
8ceee660 BH |
209 | } |
210 | ||
ecc910f5 | 211 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 212 | buffer = &tx_queue->buffer[insert_ptr]; |
b9b39b62 BH |
213 | efx_tsoh_free(tx_queue, buffer); |
214 | EFX_BUG_ON_PARANOID(buffer->tsoh); | |
8ceee660 BH |
215 | EFX_BUG_ON_PARANOID(buffer->skb); |
216 | EFX_BUG_ON_PARANOID(buffer->len); | |
dc8cfa55 | 217 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
8ceee660 BH |
218 | EFX_BUG_ON_PARANOID(buffer->unmap_len); |
219 | ||
63f19884 BH |
220 | dma_len = efx_max_tx_len(efx, dma_addr); |
221 | if (likely(dma_len >= len)) | |
8ceee660 BH |
222 | dma_len = len; |
223 | ||
8ceee660 BH |
224 | /* Fill out per descriptor fields */ |
225 | buffer->len = dma_len; | |
226 | buffer->dma_addr = dma_addr; | |
227 | len -= dma_len; | |
228 | dma_addr += dma_len; | |
229 | ++tx_queue->insert_count; | |
230 | } while (len); | |
231 | ||
232 | /* Transfer ownership of the unmapping to the final buffer */ | |
8ceee660 BH |
233 | buffer->unmap_single = unmap_single; |
234 | buffer->unmap_len = unmap_len; | |
235 | unmap_len = 0; | |
236 | ||
237 | /* Get address and size of next fragment */ | |
238 | if (i >= skb_shinfo(skb)->nr_frags) | |
239 | break; | |
240 | fragment = &skb_shinfo(skb)->frags[i]; | |
241 | len = fragment->size; | |
242 | page = fragment->page; | |
243 | page_offset = fragment->page_offset; | |
244 | i++; | |
245 | /* Map for DMA */ | |
dc8cfa55 | 246 | unmap_single = false; |
8ceee660 BH |
247 | dma_addr = pci_map_page(pci_dev, page, page_offset, len, |
248 | PCI_DMA_TODEVICE); | |
249 | } | |
250 | ||
251 | /* Transfer ownership of the skb to the final buffer */ | |
252 | buffer->skb = skb; | |
dc8cfa55 | 253 | buffer->continuation = false; |
8ceee660 BH |
254 | |
255 | /* Pass off to hardware */ | |
152b6a62 | 256 | efx_nic_push_buffers(tx_queue); |
8ceee660 BH |
257 | |
258 | return NETDEV_TX_OK; | |
259 | ||
260 | pci_err: | |
62776d03 BH |
261 | netif_err(efx, tx_err, efx->net_dev, |
262 | " TX queue %d could not map skb with %d bytes %d " | |
263 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
264 | skb_shinfo(skb)->nr_frags + 1); | |
8ceee660 BH |
265 | |
266 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
9bc183d7 | 267 | dev_kfree_skb_any(skb); |
8ceee660 BH |
268 | |
269 | unwind: | |
270 | /* Work backwards until we hit the original insert pointer value */ | |
271 | while (tx_queue->insert_count != tx_queue->write_count) { | |
272 | --tx_queue->insert_count; | |
ecc910f5 | 273 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 BH |
274 | buffer = &tx_queue->buffer[insert_ptr]; |
275 | efx_dequeue_buffer(tx_queue, buffer); | |
276 | buffer->len = 0; | |
277 | } | |
278 | ||
279 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 BH |
280 | if (unmap_len) { |
281 | if (unmap_single) | |
282 | pci_unmap_single(pci_dev, unmap_addr, unmap_len, | |
283 | PCI_DMA_TODEVICE); | |
284 | else | |
285 | pci_unmap_page(pci_dev, unmap_addr, unmap_len, | |
286 | PCI_DMA_TODEVICE); | |
287 | } | |
8ceee660 BH |
288 | |
289 | return rc; | |
290 | } | |
291 | ||
292 | /* Remove packets from the TX queue | |
293 | * | |
294 | * This removes packets from the TX queue, up to and including the | |
295 | * specified index. | |
296 | */ | |
4d566063 BH |
297 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
298 | unsigned int index) | |
8ceee660 BH |
299 | { |
300 | struct efx_nic *efx = tx_queue->efx; | |
301 | unsigned int stop_index, read_ptr; | |
8ceee660 | 302 | |
ecc910f5 SH |
303 | stop_index = (index + 1) & tx_queue->ptr_mask; |
304 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; | |
8ceee660 BH |
305 | |
306 | while (read_ptr != stop_index) { | |
307 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
308 | if (unlikely(buffer->len == 0)) { | |
62776d03 BH |
309 | netif_err(efx, tx_err, efx->net_dev, |
310 | "TX queue %d spurious TX completion id %x\n", | |
311 | tx_queue->queue, read_ptr); | |
8ceee660 BH |
312 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
313 | return; | |
314 | } | |
315 | ||
316 | efx_dequeue_buffer(tx_queue, buffer); | |
dc8cfa55 | 317 | buffer->continuation = true; |
8ceee660 BH |
318 | buffer->len = 0; |
319 | ||
320 | ++tx_queue->read_count; | |
ecc910f5 | 321 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
8ceee660 BH |
322 | } |
323 | } | |
324 | ||
8ceee660 BH |
325 | /* Initiate a packet transmission. We use one channel per CPU |
326 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
327 | * completion events will be directed back to the CPU that transmitted | |
328 | * the packet, which should be cache-efficient. | |
329 | * | |
330 | * Context: non-blocking. | |
331 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
332 | * OS to free the skb. | |
333 | */ | |
61357325 SH |
334 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
335 | struct net_device *net_dev) | |
8ceee660 | 336 | { |
767e468c | 337 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 | 338 | struct efx_tx_queue *tx_queue; |
94b274bf | 339 | unsigned index, type; |
60ac1065 | 340 | |
a7ef5933 BH |
341 | if (unlikely(efx->port_inhibited)) |
342 | return NETDEV_TX_BUSY; | |
343 | ||
94b274bf BH |
344 | index = skb_get_queue_mapping(skb); |
345 | type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0; | |
346 | if (index >= efx->n_tx_channels) { | |
347 | index -= efx->n_tx_channels; | |
348 | type |= EFX_TXQ_TYPE_HIGHPRI; | |
349 | } | |
350 | tx_queue = efx_get_tx_queue(efx, index, type); | |
60ac1065 | 351 | |
497f5ba3 | 352 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
353 | } |
354 | ||
60031fcc BH |
355 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
356 | { | |
94b274bf BH |
357 | struct efx_nic *efx = tx_queue->efx; |
358 | ||
60031fcc | 359 | /* Must be inverse of queue lookup in efx_hard_start_xmit() */ |
94b274bf BH |
360 | tx_queue->core_txq = |
361 | netdev_get_tx_queue(efx->net_dev, | |
362 | tx_queue->queue / EFX_TXQ_TYPES + | |
363 | ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? | |
364 | efx->n_tx_channels : 0)); | |
365 | } | |
366 | ||
367 | int efx_setup_tc(struct net_device *net_dev, u8 num_tc) | |
368 | { | |
369 | struct efx_nic *efx = netdev_priv(net_dev); | |
370 | struct efx_channel *channel; | |
371 | struct efx_tx_queue *tx_queue; | |
372 | unsigned tc; | |
373 | int rc; | |
374 | ||
375 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC) | |
376 | return -EINVAL; | |
377 | ||
378 | if (num_tc == net_dev->num_tc) | |
379 | return 0; | |
380 | ||
381 | for (tc = 0; tc < num_tc; tc++) { | |
382 | net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; | |
383 | net_dev->tc_to_txq[tc].count = efx->n_tx_channels; | |
384 | } | |
385 | ||
386 | if (num_tc > net_dev->num_tc) { | |
387 | /* Initialise high-priority queues as necessary */ | |
388 | efx_for_each_channel(channel, efx) { | |
389 | efx_for_each_possible_channel_tx_queue(tx_queue, | |
390 | channel) { | |
391 | if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI)) | |
392 | continue; | |
393 | if (!tx_queue->buffer) { | |
394 | rc = efx_probe_tx_queue(tx_queue); | |
395 | if (rc) | |
396 | return rc; | |
397 | } | |
398 | if (!tx_queue->initialised) | |
399 | efx_init_tx_queue(tx_queue); | |
400 | efx_init_tx_queue_core_txq(tx_queue); | |
401 | } | |
402 | } | |
403 | } else { | |
404 | /* Reduce number of classes before number of queues */ | |
405 | net_dev->num_tc = num_tc; | |
406 | } | |
407 | ||
408 | rc = netif_set_real_num_tx_queues(net_dev, | |
409 | max_t(int, num_tc, 1) * | |
410 | efx->n_tx_channels); | |
411 | if (rc) | |
412 | return rc; | |
413 | ||
414 | /* Do not destroy high-priority queues when they become | |
415 | * unused. We would have to flush them first, and it is | |
416 | * fairly difficult to flush a subset of TX queues. Leave | |
417 | * it to efx_fini_channels(). | |
418 | */ | |
419 | ||
420 | net_dev->num_tc = num_tc; | |
421 | return 0; | |
60031fcc BH |
422 | } |
423 | ||
8ceee660 BH |
424 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) |
425 | { | |
426 | unsigned fill_level; | |
427 | struct efx_nic *efx = tx_queue->efx; | |
428 | ||
ecc910f5 | 429 | EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); |
8ceee660 BH |
430 | |
431 | efx_dequeue_buffers(tx_queue, index); | |
432 | ||
433 | /* See if we need to restart the netif queue. This barrier | |
c04bfc6b BH |
434 | * separates the update of read_count from the test of the |
435 | * queue state. */ | |
8ceee660 | 436 | smp_mb(); |
c04bfc6b | 437 | if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && |
9d1aea62 NT |
438 | likely(efx->port_enabled) && |
439 | likely(!efx->port_inhibited)) { | |
8ceee660 | 440 | fill_level = tx_queue->insert_count - tx_queue->read_count; |
ecc910f5 | 441 | if (fill_level < EFX_TXQ_THRESHOLD(efx)) { |
55668611 | 442 | EFX_BUG_ON_PARANOID(!efx_dev_registered(efx)); |
c04bfc6b | 443 | netif_tx_wake_queue(tx_queue->core_txq); |
8ceee660 BH |
444 | } |
445 | } | |
cd38557d BH |
446 | |
447 | /* Check whether the hardware queue is now empty */ | |
448 | if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { | |
449 | tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); | |
450 | if (tx_queue->read_count == tx_queue->old_write_count) { | |
451 | smp_mb(); | |
452 | tx_queue->empty_read_count = | |
453 | tx_queue->read_count | EFX_EMPTY_COUNT_VALID; | |
454 | } | |
455 | } | |
8ceee660 BH |
456 | } |
457 | ||
458 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) | |
459 | { | |
460 | struct efx_nic *efx = tx_queue->efx; | |
ecc910f5 | 461 | unsigned int entries; |
8ceee660 BH |
462 | int i, rc; |
463 | ||
ecc910f5 SH |
464 | /* Create the smallest power-of-two aligned ring */ |
465 | entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); | |
466 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
467 | tx_queue->ptr_mask = entries - 1; | |
468 | ||
469 | netif_dbg(efx, probe, efx->net_dev, | |
470 | "creating TX queue %d size %#x mask %#x\n", | |
471 | tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); | |
8ceee660 BH |
472 | |
473 | /* Allocate software ring */ | |
ecc910f5 SH |
474 | tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer), |
475 | GFP_KERNEL); | |
60ac1065 BH |
476 | if (!tx_queue->buffer) |
477 | return -ENOMEM; | |
ecc910f5 | 478 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
dc8cfa55 | 479 | tx_queue->buffer[i].continuation = true; |
8ceee660 BH |
480 | |
481 | /* Allocate hardware ring */ | |
152b6a62 | 482 | rc = efx_nic_probe_tx(tx_queue); |
8ceee660 | 483 | if (rc) |
60ac1065 | 484 | goto fail; |
8ceee660 BH |
485 | |
486 | return 0; | |
487 | ||
60ac1065 | 488 | fail: |
8ceee660 BH |
489 | kfree(tx_queue->buffer); |
490 | tx_queue->buffer = NULL; | |
8ceee660 BH |
491 | return rc; |
492 | } | |
493 | ||
bc3c90a2 | 494 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 | 495 | { |
62776d03 BH |
496 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
497 | "initialising TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
498 | |
499 | tx_queue->insert_count = 0; | |
500 | tx_queue->write_count = 0; | |
cd38557d | 501 | tx_queue->old_write_count = 0; |
8ceee660 BH |
502 | tx_queue->read_count = 0; |
503 | tx_queue->old_read_count = 0; | |
cd38557d | 504 | tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; |
8ceee660 BH |
505 | |
506 | /* Set up TX descriptor ring */ | |
152b6a62 | 507 | efx_nic_init_tx(tx_queue); |
94b274bf BH |
508 | |
509 | tx_queue->initialised = true; | |
8ceee660 BH |
510 | } |
511 | ||
512 | void efx_release_tx_buffers(struct efx_tx_queue *tx_queue) | |
513 | { | |
514 | struct efx_tx_buffer *buffer; | |
515 | ||
516 | if (!tx_queue->buffer) | |
517 | return; | |
518 | ||
519 | /* Free any buffers left in the ring */ | |
520 | while (tx_queue->read_count != tx_queue->write_count) { | |
ecc910f5 | 521 | buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; |
8ceee660 | 522 | efx_dequeue_buffer(tx_queue, buffer); |
dc8cfa55 | 523 | buffer->continuation = true; |
8ceee660 BH |
524 | buffer->len = 0; |
525 | ||
526 | ++tx_queue->read_count; | |
527 | } | |
528 | } | |
529 | ||
530 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) | |
531 | { | |
94b274bf BH |
532 | if (!tx_queue->initialised) |
533 | return; | |
534 | ||
62776d03 BH |
535 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
536 | "shutting down TX queue %d\n", tx_queue->queue); | |
8ceee660 | 537 | |
94b274bf BH |
538 | tx_queue->initialised = false; |
539 | ||
8ceee660 | 540 | /* Flush TX queue, remove descriptor ring */ |
152b6a62 | 541 | efx_nic_fini_tx(tx_queue); |
8ceee660 BH |
542 | |
543 | efx_release_tx_buffers(tx_queue); | |
544 | ||
b9b39b62 BH |
545 | /* Free up TSO header cache */ |
546 | efx_fini_tso(tx_queue); | |
8ceee660 BH |
547 | } |
548 | ||
549 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) | |
550 | { | |
94b274bf BH |
551 | if (!tx_queue->buffer) |
552 | return; | |
553 | ||
62776d03 BH |
554 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
555 | "destroying TX queue %d\n", tx_queue->queue); | |
152b6a62 | 556 | efx_nic_remove_tx(tx_queue); |
8ceee660 BH |
557 | |
558 | kfree(tx_queue->buffer); | |
559 | tx_queue->buffer = NULL; | |
8ceee660 BH |
560 | } |
561 | ||
562 | ||
b9b39b62 BH |
563 | /* Efx TCP segmentation acceleration. |
564 | * | |
565 | * Why? Because by doing it here in the driver we can go significantly | |
566 | * faster than the GSO. | |
567 | * | |
568 | * Requires TX checksum offload support. | |
569 | */ | |
570 | ||
571 | /* Number of bytes inserted at the start of a TSO header buffer, | |
572 | * similar to NET_IP_ALIGN. | |
573 | */ | |
13e9ab11 | 574 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
b9b39b62 BH |
575 | #define TSOH_OFFSET 0 |
576 | #else | |
577 | #define TSOH_OFFSET NET_IP_ALIGN | |
578 | #endif | |
579 | ||
580 | #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET) | |
581 | ||
582 | /* Total size of struct efx_tso_header, buffer and padding */ | |
583 | #define TSOH_SIZE(hdr_len) \ | |
584 | (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len) | |
585 | ||
586 | /* Size of blocks on free list. Larger blocks must be allocated from | |
587 | * the heap. | |
588 | */ | |
589 | #define TSOH_STD_SIZE 128 | |
590 | ||
591 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) | |
592 | #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data) | |
593 | #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data) | |
594 | #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data) | |
738a8f4b | 595 | #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data) |
b9b39b62 BH |
596 | |
597 | /** | |
598 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 599 | * @out_len: Remaining length in current segment |
b9b39b62 | 600 | * @seqnum: Current sequence number |
23d9e60b | 601 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 602 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
603 | * @dma_addr: DMA address of current position |
604 | * @in_len: Remaining length in current SKB fragment | |
605 | * @unmap_len: Length of SKB fragment | |
606 | * @unmap_addr: DMA address of SKB fragment | |
607 | * @unmap_single: DMA single vs page mapping flag | |
738a8f4b | 608 | * @protocol: Network protocol (after any VLAN header) |
23d9e60b BH |
609 | * @header_len: Number of bytes of header |
610 | * @full_packet_size: Number of bytes to put in each outgoing segment | |
b9b39b62 BH |
611 | * |
612 | * The state used during segmentation. It is put into this data structure | |
613 | * just to make it easy to pass into inline functions. | |
614 | */ | |
615 | struct tso_state { | |
23d9e60b BH |
616 | /* Output position */ |
617 | unsigned out_len; | |
b9b39b62 | 618 | unsigned seqnum; |
23d9e60b | 619 | unsigned ipv4_id; |
b9b39b62 BH |
620 | unsigned packet_space; |
621 | ||
23d9e60b BH |
622 | /* Input position */ |
623 | dma_addr_t dma_addr; | |
624 | unsigned in_len; | |
625 | unsigned unmap_len; | |
626 | dma_addr_t unmap_addr; | |
627 | bool unmap_single; | |
628 | ||
738a8f4b | 629 | __be16 protocol; |
23d9e60b BH |
630 | unsigned header_len; |
631 | int full_packet_size; | |
b9b39b62 BH |
632 | }; |
633 | ||
634 | ||
635 | /* | |
636 | * Verify that our various assumptions about sk_buffs and the conditions | |
738a8f4b | 637 | * under which TSO will be attempted hold true. Return the protocol number. |
b9b39b62 | 638 | */ |
738a8f4b | 639 | static __be16 efx_tso_check_protocol(struct sk_buff *skb) |
b9b39b62 | 640 | { |
740847da BH |
641 | __be16 protocol = skb->protocol; |
642 | ||
b9b39b62 | 643 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
644 | protocol); |
645 | if (protocol == htons(ETH_P_8021Q)) { | |
646 | /* Find the encapsulated protocol; reset network header | |
647 | * and transport header based on that. */ | |
648 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; | |
649 | protocol = veh->h_vlan_encapsulated_proto; | |
650 | skb_set_network_header(skb, sizeof(*veh)); | |
651 | if (protocol == htons(ETH_P_IP)) | |
652 | skb_set_transport_header(skb, sizeof(*veh) + | |
653 | 4 * ip_hdr(skb)->ihl); | |
738a8f4b BH |
654 | else if (protocol == htons(ETH_P_IPV6)) |
655 | skb_set_transport_header(skb, sizeof(*veh) + | |
656 | sizeof(struct ipv6hdr)); | |
740847da BH |
657 | } |
658 | ||
738a8f4b BH |
659 | if (protocol == htons(ETH_P_IP)) { |
660 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); | |
661 | } else { | |
662 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); | |
663 | EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); | |
664 | } | |
b9b39b62 BH |
665 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) |
666 | + (tcp_hdr(skb)->doff << 2u)) > | |
667 | skb_headlen(skb)); | |
738a8f4b BH |
668 | |
669 | return protocol; | |
b9b39b62 BH |
670 | } |
671 | ||
672 | ||
673 | /* | |
674 | * Allocate a page worth of efx_tso_header structures, and string them | |
675 | * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM. | |
676 | */ | |
677 | static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue) | |
678 | { | |
679 | ||
680 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
681 | struct efx_tso_header *tsoh; | |
682 | dma_addr_t dma_addr; | |
683 | u8 *base_kva, *kva; | |
684 | ||
685 | base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr); | |
686 | if (base_kva == NULL) { | |
62776d03 BH |
687 | netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev, |
688 | "Unable to allocate page for TSO headers\n"); | |
b9b39b62 BH |
689 | return -ENOMEM; |
690 | } | |
691 | ||
692 | /* pci_alloc_consistent() allocates pages. */ | |
693 | EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u)); | |
694 | ||
695 | for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) { | |
696 | tsoh = (struct efx_tso_header *)kva; | |
697 | tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva); | |
698 | tsoh->next = tx_queue->tso_headers_free; | |
699 | tx_queue->tso_headers_free = tsoh; | |
700 | } | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | ||
706 | /* Free up a TSO header, and all others in the same page. */ | |
707 | static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue, | |
708 | struct efx_tso_header *tsoh, | |
709 | struct pci_dev *pci_dev) | |
710 | { | |
711 | struct efx_tso_header **p; | |
712 | unsigned long base_kva; | |
713 | dma_addr_t base_dma; | |
714 | ||
715 | base_kva = (unsigned long)tsoh & PAGE_MASK; | |
716 | base_dma = tsoh->dma_addr & PAGE_MASK; | |
717 | ||
718 | p = &tx_queue->tso_headers_free; | |
b3475645 | 719 | while (*p != NULL) { |
b9b39b62 BH |
720 | if (((unsigned long)*p & PAGE_MASK) == base_kva) |
721 | *p = (*p)->next; | |
722 | else | |
723 | p = &(*p)->next; | |
b3475645 | 724 | } |
b9b39b62 BH |
725 | |
726 | pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma); | |
727 | } | |
728 | ||
729 | static struct efx_tso_header * | |
730 | efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len) | |
731 | { | |
732 | struct efx_tso_header *tsoh; | |
733 | ||
734 | tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA); | |
735 | if (unlikely(!tsoh)) | |
736 | return NULL; | |
737 | ||
738 | tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev, | |
739 | TSOH_BUFFER(tsoh), header_len, | |
740 | PCI_DMA_TODEVICE); | |
8d8bb39b FT |
741 | if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev, |
742 | tsoh->dma_addr))) { | |
b9b39b62 BH |
743 | kfree(tsoh); |
744 | return NULL; | |
745 | } | |
746 | ||
747 | tsoh->unmap_len = header_len; | |
748 | return tsoh; | |
749 | } | |
750 | ||
751 | static void | |
752 | efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh) | |
753 | { | |
754 | pci_unmap_single(tx_queue->efx->pci_dev, | |
755 | tsoh->dma_addr, tsoh->unmap_len, | |
756 | PCI_DMA_TODEVICE); | |
757 | kfree(tsoh); | |
758 | } | |
759 | ||
760 | /** | |
761 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
762 | * @tx_queue: Efx TX queue | |
763 | * @dma_addr: DMA address of fragment | |
764 | * @len: Length of fragment | |
ecbd95c1 | 765 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 BH |
766 | * |
767 | * Push descriptors onto the TX queue. Return 0 on success or 1 if | |
768 | * @tx_queue full. | |
769 | */ | |
770 | static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue, | |
771 | dma_addr_t dma_addr, unsigned len, | |
ecbd95c1 | 772 | struct efx_tx_buffer **final_buffer) |
b9b39b62 BH |
773 | { |
774 | struct efx_tx_buffer *buffer; | |
775 | struct efx_nic *efx = tx_queue->efx; | |
63f19884 | 776 | unsigned dma_len, fill_level, insert_ptr; |
b9b39b62 BH |
777 | int q_space; |
778 | ||
779 | EFX_BUG_ON_PARANOID(len <= 0); | |
780 | ||
781 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; | |
782 | /* -1 as there is no way to represent all descriptors used */ | |
ecc910f5 | 783 | q_space = efx->txq_entries - 1 - fill_level; |
b9b39b62 BH |
784 | |
785 | while (1) { | |
786 | if (unlikely(q_space-- <= 0)) { | |
787 | /* It might be that completions have happened | |
788 | * since the xmit path last checked. Update | |
789 | * the xmit path's copy of read_count. | |
790 | */ | |
c04bfc6b | 791 | netif_tx_stop_queue(tx_queue->core_txq); |
b9b39b62 | 792 | /* This memory barrier protects the change of |
c04bfc6b | 793 | * queue state from the access of read_count. */ |
b9b39b62 BH |
794 | smp_mb(); |
795 | tx_queue->old_read_count = | |
51c56f40 | 796 | ACCESS_ONCE(tx_queue->read_count); |
b9b39b62 BH |
797 | fill_level = (tx_queue->insert_count |
798 | - tx_queue->old_read_count); | |
ecc910f5 | 799 | q_space = efx->txq_entries - 1 - fill_level; |
ecbd95c1 BH |
800 | if (unlikely(q_space-- <= 0)) { |
801 | *final_buffer = NULL; | |
b9b39b62 | 802 | return 1; |
ecbd95c1 | 803 | } |
b9b39b62 | 804 | smp_mb(); |
c04bfc6b | 805 | netif_tx_start_queue(tx_queue->core_txq); |
b9b39b62 BH |
806 | } |
807 | ||
ecc910f5 | 808 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
b9b39b62 BH |
809 | buffer = &tx_queue->buffer[insert_ptr]; |
810 | ++tx_queue->insert_count; | |
811 | ||
812 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
ecc910f5 SH |
813 | tx_queue->read_count >= |
814 | efx->txq_entries); | |
b9b39b62 BH |
815 | |
816 | efx_tsoh_free(tx_queue, buffer); | |
817 | EFX_BUG_ON_PARANOID(buffer->len); | |
818 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
819 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 820 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
821 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
822 | ||
823 | buffer->dma_addr = dma_addr; | |
824 | ||
63f19884 | 825 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
826 | |
827 | /* If there is enough space to send then do so */ | |
828 | if (dma_len >= len) | |
829 | break; | |
830 | ||
831 | buffer->len = dma_len; /* Don't set the other members */ | |
832 | dma_addr += dma_len; | |
833 | len -= dma_len; | |
834 | } | |
835 | ||
836 | EFX_BUG_ON_PARANOID(!len); | |
837 | buffer->len = len; | |
ecbd95c1 | 838 | *final_buffer = buffer; |
b9b39b62 BH |
839 | return 0; |
840 | } | |
841 | ||
842 | ||
843 | /* | |
844 | * Put a TSO header into the TX queue. | |
845 | * | |
846 | * This is special-cased because we know that it is small enough to fit in | |
847 | * a single fragment, and we know it doesn't cross a page boundary. It | |
848 | * also allows us to not worry about end-of-packet etc. | |
849 | */ | |
4d566063 BH |
850 | static void efx_tso_put_header(struct efx_tx_queue *tx_queue, |
851 | struct efx_tso_header *tsoh, unsigned len) | |
b9b39b62 BH |
852 | { |
853 | struct efx_tx_buffer *buffer; | |
854 | ||
ecc910f5 | 855 | buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask]; |
b9b39b62 BH |
856 | efx_tsoh_free(tx_queue, buffer); |
857 | EFX_BUG_ON_PARANOID(buffer->len); | |
858 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
859 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 860 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
861 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
862 | buffer->len = len; | |
863 | buffer->dma_addr = tsoh->dma_addr; | |
864 | buffer->tsoh = tsoh; | |
865 | ||
866 | ++tx_queue->insert_count; | |
867 | } | |
868 | ||
869 | ||
870 | /* Remove descriptors put into a tx_queue. */ | |
871 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) | |
872 | { | |
873 | struct efx_tx_buffer *buffer; | |
cc12dac2 | 874 | dma_addr_t unmap_addr; |
b9b39b62 BH |
875 | |
876 | /* Work backwards until we hit the original insert pointer value */ | |
877 | while (tx_queue->insert_count != tx_queue->write_count) { | |
878 | --tx_queue->insert_count; | |
879 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
ecc910f5 | 880 | tx_queue->ptr_mask]; |
b9b39b62 BH |
881 | efx_tsoh_free(tx_queue, buffer); |
882 | EFX_BUG_ON_PARANOID(buffer->skb); | |
b9b39b62 | 883 | if (buffer->unmap_len) { |
cc12dac2 BH |
884 | unmap_addr = (buffer->dma_addr + buffer->len - |
885 | buffer->unmap_len); | |
ecbd95c1 BH |
886 | if (buffer->unmap_single) |
887 | pci_unmap_single(tx_queue->efx->pci_dev, | |
cc12dac2 | 888 | unmap_addr, buffer->unmap_len, |
ecbd95c1 BH |
889 | PCI_DMA_TODEVICE); |
890 | else | |
891 | pci_unmap_page(tx_queue->efx->pci_dev, | |
cc12dac2 | 892 | unmap_addr, buffer->unmap_len, |
ecbd95c1 | 893 | PCI_DMA_TODEVICE); |
b9b39b62 BH |
894 | buffer->unmap_len = 0; |
895 | } | |
a7ebd27a NT |
896 | buffer->len = 0; |
897 | buffer->continuation = true; | |
b9b39b62 BH |
898 | } |
899 | } | |
900 | ||
901 | ||
902 | /* Parse the SKB header and initialise state. */ | |
4d566063 | 903 | static void tso_start(struct tso_state *st, const struct sk_buff *skb) |
b9b39b62 BH |
904 | { |
905 | /* All ethernet/IP/TCP headers combined size is TCP header size | |
906 | * plus offset of TCP header relative to start of packet. | |
907 | */ | |
23d9e60b BH |
908 | st->header_len = ((tcp_hdr(skb)->doff << 2u) |
909 | + PTR_DIFF(tcp_hdr(skb), skb->data)); | |
910 | st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size; | |
b9b39b62 | 911 | |
738a8f4b BH |
912 | if (st->protocol == htons(ETH_P_IP)) |
913 | st->ipv4_id = ntohs(ip_hdr(skb)->id); | |
914 | else | |
915 | st->ipv4_id = 0; | |
b9b39b62 BH |
916 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
917 | ||
918 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
919 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
920 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
921 | ||
23d9e60b BH |
922 | st->packet_space = st->full_packet_size; |
923 | st->out_len = skb->len - st->header_len; | |
924 | st->unmap_len = 0; | |
925 | st->unmap_single = false; | |
b9b39b62 BH |
926 | } |
927 | ||
4d566063 BH |
928 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
929 | skb_frag_t *frag) | |
b9b39b62 | 930 | { |
23d9e60b BH |
931 | st->unmap_addr = pci_map_page(efx->pci_dev, frag->page, |
932 | frag->page_offset, frag->size, | |
933 | PCI_DMA_TODEVICE); | |
934 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
935 | st->unmap_single = false; | |
936 | st->unmap_len = frag->size; | |
937 | st->in_len = frag->size; | |
938 | st->dma_addr = st->unmap_addr; | |
ecbd95c1 BH |
939 | return 0; |
940 | } | |
941 | return -ENOMEM; | |
942 | } | |
943 | ||
4d566063 BH |
944 | static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx, |
945 | const struct sk_buff *skb) | |
ecbd95c1 | 946 | { |
23d9e60b | 947 | int hl = st->header_len; |
ecbd95c1 | 948 | int len = skb_headlen(skb) - hl; |
b9b39b62 | 949 | |
23d9e60b BH |
950 | st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl, |
951 | len, PCI_DMA_TODEVICE); | |
952 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
953 | st->unmap_single = true; | |
954 | st->unmap_len = len; | |
955 | st->in_len = len; | |
956 | st->dma_addr = st->unmap_addr; | |
b9b39b62 BH |
957 | return 0; |
958 | } | |
959 | return -ENOMEM; | |
960 | } | |
961 | ||
962 | ||
963 | /** | |
964 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
965 | * @tx_queue: Efx TX queue | |
966 | * @skb: Socket buffer | |
967 | * @st: TSO state | |
968 | * | |
969 | * Form descriptors for the current fragment, until we reach the end | |
970 | * of fragment or end-of-packet. Return 0 on success, 1 if not enough | |
971 | * space in @tx_queue. | |
972 | */ | |
4d566063 BH |
973 | static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
974 | const struct sk_buff *skb, | |
975 | struct tso_state *st) | |
b9b39b62 | 976 | { |
ecbd95c1 | 977 | struct efx_tx_buffer *buffer; |
b9b39b62 BH |
978 | int n, end_of_packet, rc; |
979 | ||
23d9e60b | 980 | if (st->in_len == 0) |
b9b39b62 BH |
981 | return 0; |
982 | if (st->packet_space == 0) | |
983 | return 0; | |
984 | ||
23d9e60b | 985 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
986 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
987 | ||
23d9e60b | 988 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
989 | |
990 | st->packet_space -= n; | |
23d9e60b BH |
991 | st->out_len -= n; |
992 | st->in_len -= n; | |
b9b39b62 | 993 | |
23d9e60b | 994 | rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
ecbd95c1 | 995 | if (likely(rc == 0)) { |
23d9e60b | 996 | if (st->out_len == 0) |
ecbd95c1 BH |
997 | /* Transfer ownership of the skb */ |
998 | buffer->skb = skb; | |
b9b39b62 | 999 | |
23d9e60b | 1000 | end_of_packet = st->out_len == 0 || st->packet_space == 0; |
ecbd95c1 | 1001 | buffer->continuation = !end_of_packet; |
b9b39b62 | 1002 | |
23d9e60b | 1003 | if (st->in_len == 0) { |
ecbd95c1 | 1004 | /* Transfer ownership of the pci mapping */ |
23d9e60b BH |
1005 | buffer->unmap_len = st->unmap_len; |
1006 | buffer->unmap_single = st->unmap_single; | |
1007 | st->unmap_len = 0; | |
ecbd95c1 BH |
1008 | } |
1009 | } | |
1010 | ||
23d9e60b | 1011 | st->dma_addr += n; |
b9b39b62 BH |
1012 | return rc; |
1013 | } | |
1014 | ||
1015 | ||
1016 | /** | |
1017 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
1018 | * @tx_queue: Efx TX queue | |
1019 | * @skb: Socket buffer | |
1020 | * @st: TSO state | |
1021 | * | |
1022 | * Generate a new header and prepare for the new packet. Return 0 on | |
1023 | * success, or -1 if failed to alloc header. | |
1024 | */ | |
4d566063 BH |
1025 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
1026 | const struct sk_buff *skb, | |
1027 | struct tso_state *st) | |
b9b39b62 BH |
1028 | { |
1029 | struct efx_tso_header *tsoh; | |
b9b39b62 BH |
1030 | struct tcphdr *tsoh_th; |
1031 | unsigned ip_length; | |
1032 | u8 *header; | |
1033 | ||
1034 | /* Allocate a DMA-mapped header buffer. */ | |
23d9e60b | 1035 | if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) { |
b3475645 | 1036 | if (tx_queue->tso_headers_free == NULL) { |
b9b39b62 BH |
1037 | if (efx_tsoh_block_alloc(tx_queue)) |
1038 | return -1; | |
b3475645 | 1039 | } |
b9b39b62 BH |
1040 | EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free); |
1041 | tsoh = tx_queue->tso_headers_free; | |
1042 | tx_queue->tso_headers_free = tsoh->next; | |
1043 | tsoh->unmap_len = 0; | |
1044 | } else { | |
1045 | tx_queue->tso_long_headers++; | |
23d9e60b | 1046 | tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len); |
b9b39b62 BH |
1047 | if (unlikely(!tsoh)) |
1048 | return -1; | |
1049 | } | |
1050 | ||
1051 | header = TSOH_BUFFER(tsoh); | |
1052 | tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb)); | |
b9b39b62 BH |
1053 | |
1054 | /* Copy and update the headers. */ | |
23d9e60b | 1055 | memcpy(header, skb->data, st->header_len); |
b9b39b62 BH |
1056 | |
1057 | tsoh_th->seq = htonl(st->seqnum); | |
1058 | st->seqnum += skb_shinfo(skb)->gso_size; | |
23d9e60b | 1059 | if (st->out_len > skb_shinfo(skb)->gso_size) { |
b9b39b62 | 1060 | /* This packet will not finish the TSO burst. */ |
23d9e60b | 1061 | ip_length = st->full_packet_size - ETH_HDR_LEN(skb); |
b9b39b62 BH |
1062 | tsoh_th->fin = 0; |
1063 | tsoh_th->psh = 0; | |
1064 | } else { | |
1065 | /* This packet will be the last in the TSO burst. */ | |
23d9e60b | 1066 | ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len; |
b9b39b62 BH |
1067 | tsoh_th->fin = tcp_hdr(skb)->fin; |
1068 | tsoh_th->psh = tcp_hdr(skb)->psh; | |
1069 | } | |
b9b39b62 | 1070 | |
738a8f4b BH |
1071 | if (st->protocol == htons(ETH_P_IP)) { |
1072 | struct iphdr *tsoh_iph = | |
1073 | (struct iphdr *)(header + SKB_IPV4_OFF(skb)); | |
1074 | ||
1075 | tsoh_iph->tot_len = htons(ip_length); | |
1076 | ||
1077 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
1078 | tsoh_iph->id = htons(st->ipv4_id); | |
1079 | st->ipv4_id++; | |
1080 | } else { | |
1081 | struct ipv6hdr *tsoh_iph = | |
1082 | (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb)); | |
1083 | ||
1084 | tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph)); | |
1085 | } | |
b9b39b62 BH |
1086 | |
1087 | st->packet_space = skb_shinfo(skb)->gso_size; | |
1088 | ++tx_queue->tso_packets; | |
1089 | ||
1090 | /* Form a descriptor for this header. */ | |
23d9e60b | 1091 | efx_tso_put_header(tx_queue, tsoh, st->header_len); |
b9b39b62 BH |
1092 | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | ||
1097 | /** | |
1098 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1099 | * @tx_queue: Efx TX queue | |
1100 | * @skb: Socket buffer | |
1101 | * | |
1102 | * Context: You must hold netif_tx_lock() to call this function. | |
1103 | * | |
1104 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1105 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
1106 | * %NETDEV_TX_OK or %NETDEV_TX_BUSY. | |
1107 | */ | |
1108 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1109 | struct sk_buff *skb) |
b9b39b62 | 1110 | { |
ecbd95c1 | 1111 | struct efx_nic *efx = tx_queue->efx; |
b9b39b62 BH |
1112 | int frag_i, rc, rc2 = NETDEV_TX_OK; |
1113 | struct tso_state state; | |
b9b39b62 | 1114 | |
738a8f4b BH |
1115 | /* Find the packet protocol and sanity-check it */ |
1116 | state.protocol = efx_tso_check_protocol(skb); | |
b9b39b62 BH |
1117 | |
1118 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
1119 | ||
1120 | tso_start(&state, skb); | |
1121 | ||
1122 | /* Assume that skb header area contains exactly the headers, and | |
1123 | * all payload is in the frag list. | |
1124 | */ | |
23d9e60b | 1125 | if (skb_headlen(skb) == state.header_len) { |
b9b39b62 BH |
1126 | /* Grab the first payload fragment. */ |
1127 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1128 | frag_i = 0; | |
ecbd95c1 BH |
1129 | rc = tso_get_fragment(&state, efx, |
1130 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1131 | if (rc) |
1132 | goto mem_err; | |
1133 | } else { | |
ecbd95c1 | 1134 | rc = tso_get_head_fragment(&state, efx, skb); |
b9b39b62 BH |
1135 | if (rc) |
1136 | goto mem_err; | |
1137 | frag_i = -1; | |
1138 | } | |
1139 | ||
1140 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1141 | goto mem_err; | |
1142 | ||
1143 | while (1) { | |
1144 | rc = tso_fill_packet_with_fragment(tx_queue, skb, &state); | |
c04bfc6b BH |
1145 | if (unlikely(rc)) { |
1146 | rc2 = NETDEV_TX_BUSY; | |
1147 | goto unwind; | |
1148 | } | |
b9b39b62 BH |
1149 | |
1150 | /* Move onto the next fragment? */ | |
23d9e60b | 1151 | if (state.in_len == 0) { |
b9b39b62 BH |
1152 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1153 | /* End of payload reached. */ | |
1154 | break; | |
ecbd95c1 BH |
1155 | rc = tso_get_fragment(&state, efx, |
1156 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1157 | if (rc) |
1158 | goto mem_err; | |
1159 | } | |
1160 | ||
1161 | /* Start at new packet? */ | |
1162 | if (state.packet_space == 0 && | |
1163 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1164 | goto mem_err; | |
1165 | } | |
1166 | ||
1167 | /* Pass off to hardware */ | |
152b6a62 | 1168 | efx_nic_push_buffers(tx_queue); |
b9b39b62 BH |
1169 | |
1170 | tx_queue->tso_bursts++; | |
1171 | return NETDEV_TX_OK; | |
1172 | ||
1173 | mem_err: | |
62776d03 BH |
1174 | netif_err(efx, tx_err, efx->net_dev, |
1175 | "Out of memory for TSO headers, or PCI mapping error\n"); | |
9bc183d7 | 1176 | dev_kfree_skb_any(skb); |
b9b39b62 BH |
1177 | |
1178 | unwind: | |
5988b63a | 1179 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b BH |
1180 | if (state.unmap_len) { |
1181 | if (state.unmap_single) | |
1182 | pci_unmap_single(efx->pci_dev, state.unmap_addr, | |
1183 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1184 | else |
23d9e60b BH |
1185 | pci_unmap_page(efx->pci_dev, state.unmap_addr, |
1186 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1187 | } |
5988b63a | 1188 | |
b9b39b62 BH |
1189 | efx_enqueue_unwind(tx_queue); |
1190 | return rc2; | |
1191 | } | |
1192 | ||
1193 | ||
1194 | /* | |
1195 | * Free up all TSO datastructures associated with tx_queue. This | |
1196 | * routine should be called only once the tx_queue is both empty and | |
1197 | * will no longer be used. | |
1198 | */ | |
1199 | static void efx_fini_tso(struct efx_tx_queue *tx_queue) | |
1200 | { | |
1201 | unsigned i; | |
1202 | ||
b3475645 | 1203 | if (tx_queue->buffer) { |
ecc910f5 | 1204 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
b9b39b62 | 1205 | efx_tsoh_free(tx_queue, &tx_queue->buffer[i]); |
b3475645 | 1206 | } |
b9b39b62 BH |
1207 | |
1208 | while (tx_queue->tso_headers_free != NULL) | |
1209 | efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free, | |
1210 | tx_queue->efx->pci_dev); | |
1211 | } |