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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
15 | #include <linux/if_ether.h> | |
16 | #include <linux/highmem.h> | |
17 | #include "net_driver.h" | |
18 | #include "tx.h" | |
19 | #include "efx.h" | |
20 | #include "falcon.h" | |
21 | #include "workarounds.h" | |
22 | ||
23 | /* | |
24 | * TX descriptor ring full threshold | |
25 | * | |
26 | * The tx_queue descriptor ring fill-level must fall below this value | |
27 | * before we restart the netif queue | |
28 | */ | |
3ffeabdd | 29 | #define EFX_TXQ_THRESHOLD (EFX_TXQ_MASK / 2u) |
8ceee660 BH |
30 | |
31 | /* We want to be able to nest calls to netif_stop_queue(), since each | |
32 | * channel can have an individual stop on the queue. | |
33 | */ | |
34 | void efx_stop_queue(struct efx_nic *efx) | |
35 | { | |
36 | spin_lock_bh(&efx->netif_stop_lock); | |
37 | EFX_TRACE(efx, "stop TX queue\n"); | |
38 | ||
39 | atomic_inc(&efx->netif_stop_count); | |
40 | netif_stop_queue(efx->net_dev); | |
41 | ||
42 | spin_unlock_bh(&efx->netif_stop_lock); | |
43 | } | |
44 | ||
45 | /* Wake netif's TX queue | |
46 | * We want to be able to nest calls to netif_stop_queue(), since each | |
47 | * channel can have an individual stop on the queue. | |
48 | */ | |
4d566063 | 49 | void efx_wake_queue(struct efx_nic *efx) |
8ceee660 BH |
50 | { |
51 | local_bh_disable(); | |
52 | if (atomic_dec_and_lock(&efx->netif_stop_count, | |
53 | &efx->netif_stop_lock)) { | |
54 | EFX_TRACE(efx, "waking TX queue\n"); | |
55 | netif_wake_queue(efx->net_dev); | |
56 | spin_unlock(&efx->netif_stop_lock); | |
57 | } | |
58 | local_bh_enable(); | |
59 | } | |
60 | ||
4d566063 BH |
61 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
62 | struct efx_tx_buffer *buffer) | |
8ceee660 BH |
63 | { |
64 | if (buffer->unmap_len) { | |
65 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
cc12dac2 BH |
66 | dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len - |
67 | buffer->unmap_len); | |
8ceee660 | 68 | if (buffer->unmap_single) |
cc12dac2 BH |
69 | pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len, |
70 | PCI_DMA_TODEVICE); | |
8ceee660 | 71 | else |
cc12dac2 BH |
72 | pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len, |
73 | PCI_DMA_TODEVICE); | |
8ceee660 | 74 | buffer->unmap_len = 0; |
dc8cfa55 | 75 | buffer->unmap_single = false; |
8ceee660 BH |
76 | } |
77 | ||
78 | if (buffer->skb) { | |
79 | dev_kfree_skb_any((struct sk_buff *) buffer->skb); | |
80 | buffer->skb = NULL; | |
81 | EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x " | |
82 | "complete\n", tx_queue->queue, read_ptr); | |
83 | } | |
84 | } | |
85 | ||
b9b39b62 BH |
86 | /** |
87 | * struct efx_tso_header - a DMA mapped buffer for packet headers | |
88 | * @next: Linked list of free ones. | |
89 | * The list is protected by the TX queue lock. | |
90 | * @dma_unmap_len: Length to unmap for an oversize buffer, or 0. | |
91 | * @dma_addr: The DMA address of the header below. | |
92 | * | |
93 | * This controls the memory used for a TSO header. Use TSOH_DATA() | |
94 | * to find the packet header data. Use TSOH_SIZE() to calculate the | |
95 | * total size required for a given packet header length. TSO headers | |
96 | * in the free list are exactly %TSOH_STD_SIZE bytes in size. | |
97 | */ | |
98 | struct efx_tso_header { | |
99 | union { | |
100 | struct efx_tso_header *next; | |
101 | size_t unmap_len; | |
102 | }; | |
103 | dma_addr_t dma_addr; | |
104 | }; | |
105 | ||
106 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 107 | struct sk_buff *skb); |
b9b39b62 BH |
108 | static void efx_fini_tso(struct efx_tx_queue *tx_queue); |
109 | static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, | |
110 | struct efx_tso_header *tsoh); | |
111 | ||
4d566063 BH |
112 | static void efx_tsoh_free(struct efx_tx_queue *tx_queue, |
113 | struct efx_tx_buffer *buffer) | |
b9b39b62 BH |
114 | { |
115 | if (buffer->tsoh) { | |
116 | if (likely(!buffer->tsoh->unmap_len)) { | |
117 | buffer->tsoh->next = tx_queue->tso_headers_free; | |
118 | tx_queue->tso_headers_free = buffer->tsoh; | |
119 | } else { | |
120 | efx_tsoh_heap_free(tx_queue, buffer->tsoh); | |
121 | } | |
122 | buffer->tsoh = NULL; | |
123 | } | |
124 | } | |
125 | ||
8ceee660 | 126 | |
63f19884 BH |
127 | static inline unsigned |
128 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
129 | { | |
130 | /* Depending on the NIC revision, we can use descriptor | |
131 | * lengths up to 8K or 8K-1. However, since PCI Express | |
132 | * devices must split read requests at 4K boundaries, there is | |
133 | * little benefit from using descriptors that cross those | |
134 | * boundaries and we keep things simple by not doing so. | |
135 | */ | |
136 | unsigned len = (~dma_addr & 0xfff) + 1; | |
137 | ||
138 | /* Work around hardware bug for unaligned buffers. */ | |
139 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
140 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
141 | ||
142 | return len; | |
143 | } | |
144 | ||
8ceee660 BH |
145 | /* |
146 | * Add a socket buffer to a TX queue | |
147 | * | |
148 | * This maps all fragments of a socket buffer for DMA and adds them to | |
149 | * the TX queue. The queue's insert pointer will be incremented by | |
150 | * the number of fragments in the socket buffer. | |
151 | * | |
152 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
153 | * the queue's insert pointer will be restored to its original value. | |
154 | * | |
155 | * Returns NETDEV_TX_OK or NETDEV_TX_BUSY | |
156 | * You must hold netif_tx_lock() to call this function. | |
157 | */ | |
61357325 SH |
158 | static netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, |
159 | struct sk_buff *skb) | |
8ceee660 BH |
160 | { |
161 | struct efx_nic *efx = tx_queue->efx; | |
162 | struct pci_dev *pci_dev = efx->pci_dev; | |
163 | struct efx_tx_buffer *buffer; | |
164 | skb_frag_t *fragment; | |
165 | struct page *page; | |
166 | int page_offset; | |
63f19884 | 167 | unsigned int len, unmap_len = 0, fill_level, insert_ptr; |
8ceee660 BH |
168 | dma_addr_t dma_addr, unmap_addr = 0; |
169 | unsigned int dma_len; | |
dc8cfa55 | 170 | bool unmap_single; |
8ceee660 | 171 | int q_space, i = 0; |
61357325 | 172 | netdev_tx_t rc = NETDEV_TX_OK; |
8ceee660 BH |
173 | |
174 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
175 | ||
b9b39b62 BH |
176 | if (skb_shinfo((struct sk_buff *)skb)->gso_size) |
177 | return efx_enqueue_skb_tso(tx_queue, skb); | |
178 | ||
8ceee660 BH |
179 | /* Get size of the initial fragment */ |
180 | len = skb_headlen(skb); | |
181 | ||
bb145a9e BH |
182 | /* Pad if necessary */ |
183 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
184 | EFX_BUG_ON_PARANOID(skb->data_len); | |
185 | len = 32 + 1; | |
186 | if (skb_pad(skb, len - skb->len)) | |
187 | return NETDEV_TX_OK; | |
188 | } | |
189 | ||
8ceee660 | 190 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; |
3ffeabdd | 191 | q_space = EFX_TXQ_MASK - 1 - fill_level; |
8ceee660 BH |
192 | |
193 | /* Map for DMA. Use pci_map_single rather than pci_map_page | |
194 | * since this is more efficient on machines with sparse | |
195 | * memory. | |
196 | */ | |
dc8cfa55 | 197 | unmap_single = true; |
8ceee660 BH |
198 | dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
199 | ||
200 | /* Process all fragments */ | |
201 | while (1) { | |
8d8bb39b | 202 | if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr))) |
8ceee660 BH |
203 | goto pci_err; |
204 | ||
205 | /* Store fields for marking in the per-fragment final | |
206 | * descriptor */ | |
207 | unmap_len = len; | |
208 | unmap_addr = dma_addr; | |
209 | ||
210 | /* Add to TX queue, splitting across DMA boundaries */ | |
211 | do { | |
212 | if (unlikely(q_space-- <= 0)) { | |
213 | /* It might be that completions have | |
214 | * happened since the xmit path last | |
215 | * checked. Update the xmit path's | |
216 | * copy of read_count. | |
217 | */ | |
218 | ++tx_queue->stopped; | |
219 | /* This memory barrier protects the | |
220 | * change of stopped from the access | |
221 | * of read_count. */ | |
222 | smp_mb(); | |
223 | tx_queue->old_read_count = | |
224 | *(volatile unsigned *) | |
225 | &tx_queue->read_count; | |
226 | fill_level = (tx_queue->insert_count | |
227 | - tx_queue->old_read_count); | |
3ffeabdd | 228 | q_space = EFX_TXQ_MASK - 1 - fill_level; |
8ceee660 BH |
229 | if (unlikely(q_space-- <= 0)) |
230 | goto stop; | |
231 | smp_mb(); | |
232 | --tx_queue->stopped; | |
233 | } | |
234 | ||
3ffeabdd | 235 | insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK; |
8ceee660 | 236 | buffer = &tx_queue->buffer[insert_ptr]; |
b9b39b62 BH |
237 | efx_tsoh_free(tx_queue, buffer); |
238 | EFX_BUG_ON_PARANOID(buffer->tsoh); | |
8ceee660 BH |
239 | EFX_BUG_ON_PARANOID(buffer->skb); |
240 | EFX_BUG_ON_PARANOID(buffer->len); | |
dc8cfa55 | 241 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
8ceee660 BH |
242 | EFX_BUG_ON_PARANOID(buffer->unmap_len); |
243 | ||
63f19884 BH |
244 | dma_len = efx_max_tx_len(efx, dma_addr); |
245 | if (likely(dma_len >= len)) | |
8ceee660 BH |
246 | dma_len = len; |
247 | ||
8ceee660 BH |
248 | /* Fill out per descriptor fields */ |
249 | buffer->len = dma_len; | |
250 | buffer->dma_addr = dma_addr; | |
251 | len -= dma_len; | |
252 | dma_addr += dma_len; | |
253 | ++tx_queue->insert_count; | |
254 | } while (len); | |
255 | ||
256 | /* Transfer ownership of the unmapping to the final buffer */ | |
8ceee660 BH |
257 | buffer->unmap_single = unmap_single; |
258 | buffer->unmap_len = unmap_len; | |
259 | unmap_len = 0; | |
260 | ||
261 | /* Get address and size of next fragment */ | |
262 | if (i >= skb_shinfo(skb)->nr_frags) | |
263 | break; | |
264 | fragment = &skb_shinfo(skb)->frags[i]; | |
265 | len = fragment->size; | |
266 | page = fragment->page; | |
267 | page_offset = fragment->page_offset; | |
268 | i++; | |
269 | /* Map for DMA */ | |
dc8cfa55 | 270 | unmap_single = false; |
8ceee660 BH |
271 | dma_addr = pci_map_page(pci_dev, page, page_offset, len, |
272 | PCI_DMA_TODEVICE); | |
273 | } | |
274 | ||
275 | /* Transfer ownership of the skb to the final buffer */ | |
276 | buffer->skb = skb; | |
dc8cfa55 | 277 | buffer->continuation = false; |
8ceee660 BH |
278 | |
279 | /* Pass off to hardware */ | |
280 | falcon_push_buffers(tx_queue); | |
281 | ||
282 | return NETDEV_TX_OK; | |
283 | ||
284 | pci_err: | |
285 | EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d " | |
286 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
287 | skb_shinfo(skb)->nr_frags + 1); | |
288 | ||
289 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
290 | dev_kfree_skb_any((struct sk_buff *)skb); | |
291 | goto unwind; | |
292 | ||
293 | stop: | |
294 | rc = NETDEV_TX_BUSY; | |
295 | ||
296 | if (tx_queue->stopped == 1) | |
297 | efx_stop_queue(efx); | |
298 | ||
299 | unwind: | |
300 | /* Work backwards until we hit the original insert pointer value */ | |
301 | while (tx_queue->insert_count != tx_queue->write_count) { | |
302 | --tx_queue->insert_count; | |
3ffeabdd | 303 | insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK; |
8ceee660 BH |
304 | buffer = &tx_queue->buffer[insert_ptr]; |
305 | efx_dequeue_buffer(tx_queue, buffer); | |
306 | buffer->len = 0; | |
307 | } | |
308 | ||
309 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 BH |
310 | if (unmap_len) { |
311 | if (unmap_single) | |
312 | pci_unmap_single(pci_dev, unmap_addr, unmap_len, | |
313 | PCI_DMA_TODEVICE); | |
314 | else | |
315 | pci_unmap_page(pci_dev, unmap_addr, unmap_len, | |
316 | PCI_DMA_TODEVICE); | |
317 | } | |
8ceee660 BH |
318 | |
319 | return rc; | |
320 | } | |
321 | ||
322 | /* Remove packets from the TX queue | |
323 | * | |
324 | * This removes packets from the TX queue, up to and including the | |
325 | * specified index. | |
326 | */ | |
4d566063 BH |
327 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
328 | unsigned int index) | |
8ceee660 BH |
329 | { |
330 | struct efx_nic *efx = tx_queue->efx; | |
331 | unsigned int stop_index, read_ptr; | |
8ceee660 | 332 | |
3ffeabdd BH |
333 | stop_index = (index + 1) & EFX_TXQ_MASK; |
334 | read_ptr = tx_queue->read_count & EFX_TXQ_MASK; | |
8ceee660 BH |
335 | |
336 | while (read_ptr != stop_index) { | |
337 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
338 | if (unlikely(buffer->len == 0)) { | |
339 | EFX_ERR(tx_queue->efx, "TX queue %d spurious TX " | |
340 | "completion id %x\n", tx_queue->queue, | |
341 | read_ptr); | |
342 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); | |
343 | return; | |
344 | } | |
345 | ||
346 | efx_dequeue_buffer(tx_queue, buffer); | |
dc8cfa55 | 347 | buffer->continuation = true; |
8ceee660 BH |
348 | buffer->len = 0; |
349 | ||
350 | ++tx_queue->read_count; | |
3ffeabdd | 351 | read_ptr = tx_queue->read_count & EFX_TXQ_MASK; |
8ceee660 BH |
352 | } |
353 | } | |
354 | ||
355 | /* Initiate a packet transmission on the specified TX queue. | |
356 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
357 | * OS to free the skb. | |
358 | * | |
359 | * This function is split out from efx_hard_start_xmit to allow the | |
360 | * loopback test to direct packets via specific TX queues. It is | |
361 | * therefore a non-static inline, so as not to penalise performance | |
362 | * for non-loopback transmissions. | |
363 | * | |
364 | * Context: netif_tx_lock held | |
365 | */ | |
61357325 SH |
366 | inline netdev_tx_t efx_xmit(struct efx_nic *efx, |
367 | struct efx_tx_queue *tx_queue, struct sk_buff *skb) | |
8ceee660 | 368 | { |
8ceee660 | 369 | /* Map fragments for DMA and add to TX queue */ |
61357325 | 370 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
371 | } |
372 | ||
373 | /* Initiate a packet transmission. We use one channel per CPU | |
374 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
375 | * completion events will be directed back to the CPU that transmitted | |
376 | * the packet, which should be cache-efficient. | |
377 | * | |
378 | * Context: non-blocking. | |
379 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
380 | * OS to free the skb. | |
381 | */ | |
61357325 SH |
382 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
383 | struct net_device *net_dev) | |
8ceee660 | 384 | { |
767e468c | 385 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 BH |
386 | struct efx_tx_queue *tx_queue; |
387 | ||
a7ef5933 BH |
388 | if (unlikely(efx->port_inhibited)) |
389 | return NETDEV_TX_BUSY; | |
390 | ||
60ac1065 BH |
391 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) |
392 | tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM]; | |
393 | else | |
394 | tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM]; | |
395 | ||
396 | return efx_xmit(efx, tx_queue, skb); | |
8ceee660 BH |
397 | } |
398 | ||
399 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) | |
400 | { | |
401 | unsigned fill_level; | |
402 | struct efx_nic *efx = tx_queue->efx; | |
403 | ||
3ffeabdd | 404 | EFX_BUG_ON_PARANOID(index > EFX_TXQ_MASK); |
8ceee660 BH |
405 | |
406 | efx_dequeue_buffers(tx_queue, index); | |
407 | ||
408 | /* See if we need to restart the netif queue. This barrier | |
409 | * separates the update of read_count from the test of | |
410 | * stopped. */ | |
411 | smp_mb(); | |
32d76007 | 412 | if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) { |
8ceee660 | 413 | fill_level = tx_queue->insert_count - tx_queue->read_count; |
3ffeabdd | 414 | if (fill_level < EFX_TXQ_THRESHOLD) { |
55668611 | 415 | EFX_BUG_ON_PARANOID(!efx_dev_registered(efx)); |
8ceee660 BH |
416 | |
417 | /* Do this under netif_tx_lock(), to avoid racing | |
418 | * with efx_xmit(). */ | |
419 | netif_tx_lock(efx->net_dev); | |
420 | if (tx_queue->stopped) { | |
421 | tx_queue->stopped = 0; | |
422 | efx_wake_queue(efx); | |
423 | } | |
424 | netif_tx_unlock(efx->net_dev); | |
425 | } | |
426 | } | |
427 | } | |
428 | ||
429 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) | |
430 | { | |
431 | struct efx_nic *efx = tx_queue->efx; | |
432 | unsigned int txq_size; | |
433 | int i, rc; | |
434 | ||
435 | EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue); | |
436 | ||
437 | /* Allocate software ring */ | |
3ffeabdd | 438 | txq_size = EFX_TXQ_SIZE * sizeof(*tx_queue->buffer); |
8ceee660 | 439 | tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL); |
60ac1065 BH |
440 | if (!tx_queue->buffer) |
441 | return -ENOMEM; | |
3ffeabdd | 442 | for (i = 0; i <= EFX_TXQ_MASK; ++i) |
dc8cfa55 | 443 | tx_queue->buffer[i].continuation = true; |
8ceee660 BH |
444 | |
445 | /* Allocate hardware ring */ | |
446 | rc = falcon_probe_tx(tx_queue); | |
447 | if (rc) | |
60ac1065 | 448 | goto fail; |
8ceee660 BH |
449 | |
450 | return 0; | |
451 | ||
60ac1065 | 452 | fail: |
8ceee660 BH |
453 | kfree(tx_queue->buffer); |
454 | tx_queue->buffer = NULL; | |
8ceee660 BH |
455 | return rc; |
456 | } | |
457 | ||
bc3c90a2 | 458 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
459 | { |
460 | EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue); | |
461 | ||
462 | tx_queue->insert_count = 0; | |
463 | tx_queue->write_count = 0; | |
464 | tx_queue->read_count = 0; | |
465 | tx_queue->old_read_count = 0; | |
466 | BUG_ON(tx_queue->stopped); | |
467 | ||
468 | /* Set up TX descriptor ring */ | |
bc3c90a2 | 469 | falcon_init_tx(tx_queue); |
8ceee660 BH |
470 | } |
471 | ||
472 | void efx_release_tx_buffers(struct efx_tx_queue *tx_queue) | |
473 | { | |
474 | struct efx_tx_buffer *buffer; | |
475 | ||
476 | if (!tx_queue->buffer) | |
477 | return; | |
478 | ||
479 | /* Free any buffers left in the ring */ | |
480 | while (tx_queue->read_count != tx_queue->write_count) { | |
3ffeabdd | 481 | buffer = &tx_queue->buffer[tx_queue->read_count & EFX_TXQ_MASK]; |
8ceee660 | 482 | efx_dequeue_buffer(tx_queue, buffer); |
dc8cfa55 | 483 | buffer->continuation = true; |
8ceee660 BH |
484 | buffer->len = 0; |
485 | ||
486 | ++tx_queue->read_count; | |
487 | } | |
488 | } | |
489 | ||
490 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) | |
491 | { | |
492 | EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue); | |
493 | ||
494 | /* Flush TX queue, remove descriptor ring */ | |
495 | falcon_fini_tx(tx_queue); | |
496 | ||
497 | efx_release_tx_buffers(tx_queue); | |
498 | ||
b9b39b62 BH |
499 | /* Free up TSO header cache */ |
500 | efx_fini_tso(tx_queue); | |
501 | ||
8ceee660 BH |
502 | /* Release queue's stop on port, if any */ |
503 | if (tx_queue->stopped) { | |
504 | tx_queue->stopped = 0; | |
505 | efx_wake_queue(tx_queue->efx); | |
506 | } | |
507 | } | |
508 | ||
509 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) | |
510 | { | |
511 | EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue); | |
512 | falcon_remove_tx(tx_queue); | |
513 | ||
514 | kfree(tx_queue->buffer); | |
515 | tx_queue->buffer = NULL; | |
8ceee660 BH |
516 | } |
517 | ||
518 | ||
b9b39b62 BH |
519 | /* Efx TCP segmentation acceleration. |
520 | * | |
521 | * Why? Because by doing it here in the driver we can go significantly | |
522 | * faster than the GSO. | |
523 | * | |
524 | * Requires TX checksum offload support. | |
525 | */ | |
526 | ||
527 | /* Number of bytes inserted at the start of a TSO header buffer, | |
528 | * similar to NET_IP_ALIGN. | |
529 | */ | |
13e9ab11 | 530 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
b9b39b62 BH |
531 | #define TSOH_OFFSET 0 |
532 | #else | |
533 | #define TSOH_OFFSET NET_IP_ALIGN | |
534 | #endif | |
535 | ||
536 | #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET) | |
537 | ||
538 | /* Total size of struct efx_tso_header, buffer and padding */ | |
539 | #define TSOH_SIZE(hdr_len) \ | |
540 | (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len) | |
541 | ||
542 | /* Size of blocks on free list. Larger blocks must be allocated from | |
543 | * the heap. | |
544 | */ | |
545 | #define TSOH_STD_SIZE 128 | |
546 | ||
547 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) | |
548 | #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data) | |
549 | #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data) | |
550 | #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data) | |
551 | ||
552 | /** | |
553 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 554 | * @out_len: Remaining length in current segment |
b9b39b62 | 555 | * @seqnum: Current sequence number |
23d9e60b | 556 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 557 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
558 | * @dma_addr: DMA address of current position |
559 | * @in_len: Remaining length in current SKB fragment | |
560 | * @unmap_len: Length of SKB fragment | |
561 | * @unmap_addr: DMA address of SKB fragment | |
562 | * @unmap_single: DMA single vs page mapping flag | |
563 | * @header_len: Number of bytes of header | |
564 | * @full_packet_size: Number of bytes to put in each outgoing segment | |
b9b39b62 BH |
565 | * |
566 | * The state used during segmentation. It is put into this data structure | |
567 | * just to make it easy to pass into inline functions. | |
568 | */ | |
569 | struct tso_state { | |
23d9e60b BH |
570 | /* Output position */ |
571 | unsigned out_len; | |
b9b39b62 | 572 | unsigned seqnum; |
23d9e60b | 573 | unsigned ipv4_id; |
b9b39b62 BH |
574 | unsigned packet_space; |
575 | ||
23d9e60b BH |
576 | /* Input position */ |
577 | dma_addr_t dma_addr; | |
578 | unsigned in_len; | |
579 | unsigned unmap_len; | |
580 | dma_addr_t unmap_addr; | |
581 | bool unmap_single; | |
582 | ||
583 | unsigned header_len; | |
584 | int full_packet_size; | |
b9b39b62 BH |
585 | }; |
586 | ||
587 | ||
588 | /* | |
589 | * Verify that our various assumptions about sk_buffs and the conditions | |
590 | * under which TSO will be attempted hold true. | |
591 | */ | |
740847da | 592 | static void efx_tso_check_safe(struct sk_buff *skb) |
b9b39b62 | 593 | { |
740847da BH |
594 | __be16 protocol = skb->protocol; |
595 | ||
b9b39b62 | 596 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
597 | protocol); |
598 | if (protocol == htons(ETH_P_8021Q)) { | |
599 | /* Find the encapsulated protocol; reset network header | |
600 | * and transport header based on that. */ | |
601 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; | |
602 | protocol = veh->h_vlan_encapsulated_proto; | |
603 | skb_set_network_header(skb, sizeof(*veh)); | |
604 | if (protocol == htons(ETH_P_IP)) | |
605 | skb_set_transport_header(skb, sizeof(*veh) + | |
606 | 4 * ip_hdr(skb)->ihl); | |
607 | } | |
608 | ||
609 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP)); | |
b9b39b62 BH |
610 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); |
611 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) | |
612 | + (tcp_hdr(skb)->doff << 2u)) > | |
613 | skb_headlen(skb)); | |
614 | } | |
615 | ||
616 | ||
617 | /* | |
618 | * Allocate a page worth of efx_tso_header structures, and string them | |
619 | * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM. | |
620 | */ | |
621 | static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue) | |
622 | { | |
623 | ||
624 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
625 | struct efx_tso_header *tsoh; | |
626 | dma_addr_t dma_addr; | |
627 | u8 *base_kva, *kva; | |
628 | ||
629 | base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr); | |
630 | if (base_kva == NULL) { | |
631 | EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO" | |
632 | " headers\n"); | |
633 | return -ENOMEM; | |
634 | } | |
635 | ||
636 | /* pci_alloc_consistent() allocates pages. */ | |
637 | EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u)); | |
638 | ||
639 | for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) { | |
640 | tsoh = (struct efx_tso_header *)kva; | |
641 | tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva); | |
642 | tsoh->next = tx_queue->tso_headers_free; | |
643 | tx_queue->tso_headers_free = tsoh; | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | ||
650 | /* Free up a TSO header, and all others in the same page. */ | |
651 | static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue, | |
652 | struct efx_tso_header *tsoh, | |
653 | struct pci_dev *pci_dev) | |
654 | { | |
655 | struct efx_tso_header **p; | |
656 | unsigned long base_kva; | |
657 | dma_addr_t base_dma; | |
658 | ||
659 | base_kva = (unsigned long)tsoh & PAGE_MASK; | |
660 | base_dma = tsoh->dma_addr & PAGE_MASK; | |
661 | ||
662 | p = &tx_queue->tso_headers_free; | |
b3475645 | 663 | while (*p != NULL) { |
b9b39b62 BH |
664 | if (((unsigned long)*p & PAGE_MASK) == base_kva) |
665 | *p = (*p)->next; | |
666 | else | |
667 | p = &(*p)->next; | |
b3475645 | 668 | } |
b9b39b62 BH |
669 | |
670 | pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma); | |
671 | } | |
672 | ||
673 | static struct efx_tso_header * | |
674 | efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len) | |
675 | { | |
676 | struct efx_tso_header *tsoh; | |
677 | ||
678 | tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA); | |
679 | if (unlikely(!tsoh)) | |
680 | return NULL; | |
681 | ||
682 | tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev, | |
683 | TSOH_BUFFER(tsoh), header_len, | |
684 | PCI_DMA_TODEVICE); | |
8d8bb39b FT |
685 | if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev, |
686 | tsoh->dma_addr))) { | |
b9b39b62 BH |
687 | kfree(tsoh); |
688 | return NULL; | |
689 | } | |
690 | ||
691 | tsoh->unmap_len = header_len; | |
692 | return tsoh; | |
693 | } | |
694 | ||
695 | static void | |
696 | efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh) | |
697 | { | |
698 | pci_unmap_single(tx_queue->efx->pci_dev, | |
699 | tsoh->dma_addr, tsoh->unmap_len, | |
700 | PCI_DMA_TODEVICE); | |
701 | kfree(tsoh); | |
702 | } | |
703 | ||
704 | /** | |
705 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
706 | * @tx_queue: Efx TX queue | |
707 | * @dma_addr: DMA address of fragment | |
708 | * @len: Length of fragment | |
ecbd95c1 | 709 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 BH |
710 | * |
711 | * Push descriptors onto the TX queue. Return 0 on success or 1 if | |
712 | * @tx_queue full. | |
713 | */ | |
714 | static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue, | |
715 | dma_addr_t dma_addr, unsigned len, | |
ecbd95c1 | 716 | struct efx_tx_buffer **final_buffer) |
b9b39b62 BH |
717 | { |
718 | struct efx_tx_buffer *buffer; | |
719 | struct efx_nic *efx = tx_queue->efx; | |
63f19884 | 720 | unsigned dma_len, fill_level, insert_ptr; |
b9b39b62 BH |
721 | int q_space; |
722 | ||
723 | EFX_BUG_ON_PARANOID(len <= 0); | |
724 | ||
725 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; | |
726 | /* -1 as there is no way to represent all descriptors used */ | |
3ffeabdd | 727 | q_space = EFX_TXQ_MASK - 1 - fill_level; |
b9b39b62 BH |
728 | |
729 | while (1) { | |
730 | if (unlikely(q_space-- <= 0)) { | |
731 | /* It might be that completions have happened | |
732 | * since the xmit path last checked. Update | |
733 | * the xmit path's copy of read_count. | |
734 | */ | |
735 | ++tx_queue->stopped; | |
736 | /* This memory barrier protects the change of | |
737 | * stopped from the access of read_count. */ | |
738 | smp_mb(); | |
739 | tx_queue->old_read_count = | |
740 | *(volatile unsigned *)&tx_queue->read_count; | |
741 | fill_level = (tx_queue->insert_count | |
742 | - tx_queue->old_read_count); | |
3ffeabdd | 743 | q_space = EFX_TXQ_MASK - 1 - fill_level; |
ecbd95c1 BH |
744 | if (unlikely(q_space-- <= 0)) { |
745 | *final_buffer = NULL; | |
b9b39b62 | 746 | return 1; |
ecbd95c1 | 747 | } |
b9b39b62 BH |
748 | smp_mb(); |
749 | --tx_queue->stopped; | |
750 | } | |
751 | ||
3ffeabdd | 752 | insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK; |
b9b39b62 BH |
753 | buffer = &tx_queue->buffer[insert_ptr]; |
754 | ++tx_queue->insert_count; | |
755 | ||
756 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
757 | tx_queue->read_count > | |
3ffeabdd | 758 | EFX_TXQ_MASK); |
b9b39b62 BH |
759 | |
760 | efx_tsoh_free(tx_queue, buffer); | |
761 | EFX_BUG_ON_PARANOID(buffer->len); | |
762 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
763 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 764 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
765 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
766 | ||
767 | buffer->dma_addr = dma_addr; | |
768 | ||
63f19884 | 769 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
770 | |
771 | /* If there is enough space to send then do so */ | |
772 | if (dma_len >= len) | |
773 | break; | |
774 | ||
775 | buffer->len = dma_len; /* Don't set the other members */ | |
776 | dma_addr += dma_len; | |
777 | len -= dma_len; | |
778 | } | |
779 | ||
780 | EFX_BUG_ON_PARANOID(!len); | |
781 | buffer->len = len; | |
ecbd95c1 | 782 | *final_buffer = buffer; |
b9b39b62 BH |
783 | return 0; |
784 | } | |
785 | ||
786 | ||
787 | /* | |
788 | * Put a TSO header into the TX queue. | |
789 | * | |
790 | * This is special-cased because we know that it is small enough to fit in | |
791 | * a single fragment, and we know it doesn't cross a page boundary. It | |
792 | * also allows us to not worry about end-of-packet etc. | |
793 | */ | |
4d566063 BH |
794 | static void efx_tso_put_header(struct efx_tx_queue *tx_queue, |
795 | struct efx_tso_header *tsoh, unsigned len) | |
b9b39b62 BH |
796 | { |
797 | struct efx_tx_buffer *buffer; | |
798 | ||
3ffeabdd | 799 | buffer = &tx_queue->buffer[tx_queue->insert_count & EFX_TXQ_MASK]; |
b9b39b62 BH |
800 | efx_tsoh_free(tx_queue, buffer); |
801 | EFX_BUG_ON_PARANOID(buffer->len); | |
802 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
803 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 804 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
805 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
806 | buffer->len = len; | |
807 | buffer->dma_addr = tsoh->dma_addr; | |
808 | buffer->tsoh = tsoh; | |
809 | ||
810 | ++tx_queue->insert_count; | |
811 | } | |
812 | ||
813 | ||
814 | /* Remove descriptors put into a tx_queue. */ | |
815 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) | |
816 | { | |
817 | struct efx_tx_buffer *buffer; | |
cc12dac2 | 818 | dma_addr_t unmap_addr; |
b9b39b62 BH |
819 | |
820 | /* Work backwards until we hit the original insert pointer value */ | |
821 | while (tx_queue->insert_count != tx_queue->write_count) { | |
822 | --tx_queue->insert_count; | |
823 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
3ffeabdd | 824 | EFX_TXQ_MASK]; |
b9b39b62 BH |
825 | efx_tsoh_free(tx_queue, buffer); |
826 | EFX_BUG_ON_PARANOID(buffer->skb); | |
827 | buffer->len = 0; | |
dc8cfa55 | 828 | buffer->continuation = true; |
b9b39b62 | 829 | if (buffer->unmap_len) { |
cc12dac2 BH |
830 | unmap_addr = (buffer->dma_addr + buffer->len - |
831 | buffer->unmap_len); | |
ecbd95c1 BH |
832 | if (buffer->unmap_single) |
833 | pci_unmap_single(tx_queue->efx->pci_dev, | |
cc12dac2 | 834 | unmap_addr, buffer->unmap_len, |
ecbd95c1 BH |
835 | PCI_DMA_TODEVICE); |
836 | else | |
837 | pci_unmap_page(tx_queue->efx->pci_dev, | |
cc12dac2 | 838 | unmap_addr, buffer->unmap_len, |
ecbd95c1 | 839 | PCI_DMA_TODEVICE); |
b9b39b62 BH |
840 | buffer->unmap_len = 0; |
841 | } | |
842 | } | |
843 | } | |
844 | ||
845 | ||
846 | /* Parse the SKB header and initialise state. */ | |
4d566063 | 847 | static void tso_start(struct tso_state *st, const struct sk_buff *skb) |
b9b39b62 BH |
848 | { |
849 | /* All ethernet/IP/TCP headers combined size is TCP header size | |
850 | * plus offset of TCP header relative to start of packet. | |
851 | */ | |
23d9e60b BH |
852 | st->header_len = ((tcp_hdr(skb)->doff << 2u) |
853 | + PTR_DIFF(tcp_hdr(skb), skb->data)); | |
854 | st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size; | |
b9b39b62 | 855 | |
23d9e60b | 856 | st->ipv4_id = ntohs(ip_hdr(skb)->id); |
b9b39b62 BH |
857 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
858 | ||
859 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
860 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
861 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
862 | ||
23d9e60b BH |
863 | st->packet_space = st->full_packet_size; |
864 | st->out_len = skb->len - st->header_len; | |
865 | st->unmap_len = 0; | |
866 | st->unmap_single = false; | |
b9b39b62 BH |
867 | } |
868 | ||
4d566063 BH |
869 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
870 | skb_frag_t *frag) | |
b9b39b62 | 871 | { |
23d9e60b BH |
872 | st->unmap_addr = pci_map_page(efx->pci_dev, frag->page, |
873 | frag->page_offset, frag->size, | |
874 | PCI_DMA_TODEVICE); | |
875 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
876 | st->unmap_single = false; | |
877 | st->unmap_len = frag->size; | |
878 | st->in_len = frag->size; | |
879 | st->dma_addr = st->unmap_addr; | |
ecbd95c1 BH |
880 | return 0; |
881 | } | |
882 | return -ENOMEM; | |
883 | } | |
884 | ||
4d566063 BH |
885 | static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx, |
886 | const struct sk_buff *skb) | |
ecbd95c1 | 887 | { |
23d9e60b | 888 | int hl = st->header_len; |
ecbd95c1 | 889 | int len = skb_headlen(skb) - hl; |
b9b39b62 | 890 | |
23d9e60b BH |
891 | st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl, |
892 | len, PCI_DMA_TODEVICE); | |
893 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
894 | st->unmap_single = true; | |
895 | st->unmap_len = len; | |
896 | st->in_len = len; | |
897 | st->dma_addr = st->unmap_addr; | |
b9b39b62 BH |
898 | return 0; |
899 | } | |
900 | return -ENOMEM; | |
901 | } | |
902 | ||
903 | ||
904 | /** | |
905 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
906 | * @tx_queue: Efx TX queue | |
907 | * @skb: Socket buffer | |
908 | * @st: TSO state | |
909 | * | |
910 | * Form descriptors for the current fragment, until we reach the end | |
911 | * of fragment or end-of-packet. Return 0 on success, 1 if not enough | |
912 | * space in @tx_queue. | |
913 | */ | |
4d566063 BH |
914 | static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
915 | const struct sk_buff *skb, | |
916 | struct tso_state *st) | |
b9b39b62 | 917 | { |
ecbd95c1 | 918 | struct efx_tx_buffer *buffer; |
b9b39b62 BH |
919 | int n, end_of_packet, rc; |
920 | ||
23d9e60b | 921 | if (st->in_len == 0) |
b9b39b62 BH |
922 | return 0; |
923 | if (st->packet_space == 0) | |
924 | return 0; | |
925 | ||
23d9e60b | 926 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
927 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
928 | ||
23d9e60b | 929 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
930 | |
931 | st->packet_space -= n; | |
23d9e60b BH |
932 | st->out_len -= n; |
933 | st->in_len -= n; | |
b9b39b62 | 934 | |
23d9e60b | 935 | rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
ecbd95c1 | 936 | if (likely(rc == 0)) { |
23d9e60b | 937 | if (st->out_len == 0) |
ecbd95c1 BH |
938 | /* Transfer ownership of the skb */ |
939 | buffer->skb = skb; | |
b9b39b62 | 940 | |
23d9e60b | 941 | end_of_packet = st->out_len == 0 || st->packet_space == 0; |
ecbd95c1 | 942 | buffer->continuation = !end_of_packet; |
b9b39b62 | 943 | |
23d9e60b | 944 | if (st->in_len == 0) { |
ecbd95c1 | 945 | /* Transfer ownership of the pci mapping */ |
23d9e60b BH |
946 | buffer->unmap_len = st->unmap_len; |
947 | buffer->unmap_single = st->unmap_single; | |
948 | st->unmap_len = 0; | |
ecbd95c1 BH |
949 | } |
950 | } | |
951 | ||
23d9e60b | 952 | st->dma_addr += n; |
b9b39b62 BH |
953 | return rc; |
954 | } | |
955 | ||
956 | ||
957 | /** | |
958 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
959 | * @tx_queue: Efx TX queue | |
960 | * @skb: Socket buffer | |
961 | * @st: TSO state | |
962 | * | |
963 | * Generate a new header and prepare for the new packet. Return 0 on | |
964 | * success, or -1 if failed to alloc header. | |
965 | */ | |
4d566063 BH |
966 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
967 | const struct sk_buff *skb, | |
968 | struct tso_state *st) | |
b9b39b62 BH |
969 | { |
970 | struct efx_tso_header *tsoh; | |
971 | struct iphdr *tsoh_iph; | |
972 | struct tcphdr *tsoh_th; | |
973 | unsigned ip_length; | |
974 | u8 *header; | |
975 | ||
976 | /* Allocate a DMA-mapped header buffer. */ | |
23d9e60b | 977 | if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) { |
b3475645 | 978 | if (tx_queue->tso_headers_free == NULL) { |
b9b39b62 BH |
979 | if (efx_tsoh_block_alloc(tx_queue)) |
980 | return -1; | |
b3475645 | 981 | } |
b9b39b62 BH |
982 | EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free); |
983 | tsoh = tx_queue->tso_headers_free; | |
984 | tx_queue->tso_headers_free = tsoh->next; | |
985 | tsoh->unmap_len = 0; | |
986 | } else { | |
987 | tx_queue->tso_long_headers++; | |
23d9e60b | 988 | tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len); |
b9b39b62 BH |
989 | if (unlikely(!tsoh)) |
990 | return -1; | |
991 | } | |
992 | ||
993 | header = TSOH_BUFFER(tsoh); | |
994 | tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb)); | |
995 | tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb)); | |
996 | ||
997 | /* Copy and update the headers. */ | |
23d9e60b | 998 | memcpy(header, skb->data, st->header_len); |
b9b39b62 BH |
999 | |
1000 | tsoh_th->seq = htonl(st->seqnum); | |
1001 | st->seqnum += skb_shinfo(skb)->gso_size; | |
23d9e60b | 1002 | if (st->out_len > skb_shinfo(skb)->gso_size) { |
b9b39b62 | 1003 | /* This packet will not finish the TSO burst. */ |
23d9e60b | 1004 | ip_length = st->full_packet_size - ETH_HDR_LEN(skb); |
b9b39b62 BH |
1005 | tsoh_th->fin = 0; |
1006 | tsoh_th->psh = 0; | |
1007 | } else { | |
1008 | /* This packet will be the last in the TSO burst. */ | |
23d9e60b | 1009 | ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len; |
b9b39b62 BH |
1010 | tsoh_th->fin = tcp_hdr(skb)->fin; |
1011 | tsoh_th->psh = tcp_hdr(skb)->psh; | |
1012 | } | |
1013 | tsoh_iph->tot_len = htons(ip_length); | |
1014 | ||
1015 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
23d9e60b BH |
1016 | tsoh_iph->id = htons(st->ipv4_id); |
1017 | st->ipv4_id++; | |
b9b39b62 BH |
1018 | |
1019 | st->packet_space = skb_shinfo(skb)->gso_size; | |
1020 | ++tx_queue->tso_packets; | |
1021 | ||
1022 | /* Form a descriptor for this header. */ | |
23d9e60b | 1023 | efx_tso_put_header(tx_queue, tsoh, st->header_len); |
b9b39b62 BH |
1024 | |
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | ||
1029 | /** | |
1030 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1031 | * @tx_queue: Efx TX queue | |
1032 | * @skb: Socket buffer | |
1033 | * | |
1034 | * Context: You must hold netif_tx_lock() to call this function. | |
1035 | * | |
1036 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1037 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
1038 | * %NETDEV_TX_OK or %NETDEV_TX_BUSY. | |
1039 | */ | |
1040 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1041 | struct sk_buff *skb) |
b9b39b62 | 1042 | { |
ecbd95c1 | 1043 | struct efx_nic *efx = tx_queue->efx; |
b9b39b62 BH |
1044 | int frag_i, rc, rc2 = NETDEV_TX_OK; |
1045 | struct tso_state state; | |
b9b39b62 BH |
1046 | |
1047 | /* Verify TSO is safe - these checks should never fail. */ | |
1048 | efx_tso_check_safe(skb); | |
1049 | ||
1050 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
1051 | ||
1052 | tso_start(&state, skb); | |
1053 | ||
1054 | /* Assume that skb header area contains exactly the headers, and | |
1055 | * all payload is in the frag list. | |
1056 | */ | |
23d9e60b | 1057 | if (skb_headlen(skb) == state.header_len) { |
b9b39b62 BH |
1058 | /* Grab the first payload fragment. */ |
1059 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1060 | frag_i = 0; | |
ecbd95c1 BH |
1061 | rc = tso_get_fragment(&state, efx, |
1062 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1063 | if (rc) |
1064 | goto mem_err; | |
1065 | } else { | |
ecbd95c1 | 1066 | rc = tso_get_head_fragment(&state, efx, skb); |
b9b39b62 BH |
1067 | if (rc) |
1068 | goto mem_err; | |
1069 | frag_i = -1; | |
1070 | } | |
1071 | ||
1072 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1073 | goto mem_err; | |
1074 | ||
1075 | while (1) { | |
1076 | rc = tso_fill_packet_with_fragment(tx_queue, skb, &state); | |
1077 | if (unlikely(rc)) | |
1078 | goto stop; | |
1079 | ||
1080 | /* Move onto the next fragment? */ | |
23d9e60b | 1081 | if (state.in_len == 0) { |
b9b39b62 BH |
1082 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1083 | /* End of payload reached. */ | |
1084 | break; | |
ecbd95c1 BH |
1085 | rc = tso_get_fragment(&state, efx, |
1086 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1087 | if (rc) |
1088 | goto mem_err; | |
1089 | } | |
1090 | ||
1091 | /* Start at new packet? */ | |
1092 | if (state.packet_space == 0 && | |
1093 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1094 | goto mem_err; | |
1095 | } | |
1096 | ||
1097 | /* Pass off to hardware */ | |
1098 | falcon_push_buffers(tx_queue); | |
1099 | ||
1100 | tx_queue->tso_bursts++; | |
1101 | return NETDEV_TX_OK; | |
1102 | ||
1103 | mem_err: | |
ecbd95c1 | 1104 | EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n"); |
b9b39b62 BH |
1105 | dev_kfree_skb_any((struct sk_buff *)skb); |
1106 | goto unwind; | |
1107 | ||
1108 | stop: | |
1109 | rc2 = NETDEV_TX_BUSY; | |
1110 | ||
1111 | /* Stop the queue if it wasn't stopped before. */ | |
1112 | if (tx_queue->stopped == 1) | |
ecbd95c1 | 1113 | efx_stop_queue(efx); |
b9b39b62 BH |
1114 | |
1115 | unwind: | |
5988b63a | 1116 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b BH |
1117 | if (state.unmap_len) { |
1118 | if (state.unmap_single) | |
1119 | pci_unmap_single(efx->pci_dev, state.unmap_addr, | |
1120 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1121 | else |
23d9e60b BH |
1122 | pci_unmap_page(efx->pci_dev, state.unmap_addr, |
1123 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1124 | } |
5988b63a | 1125 | |
b9b39b62 BH |
1126 | efx_enqueue_unwind(tx_queue); |
1127 | return rc2; | |
1128 | } | |
1129 | ||
1130 | ||
1131 | /* | |
1132 | * Free up all TSO datastructures associated with tx_queue. This | |
1133 | * routine should be called only once the tx_queue is both empty and | |
1134 | * will no longer be used. | |
1135 | */ | |
1136 | static void efx_fini_tso(struct efx_tx_queue *tx_queue) | |
1137 | { | |
1138 | unsigned i; | |
1139 | ||
b3475645 | 1140 | if (tx_queue->buffer) { |
3ffeabdd | 1141 | for (i = 0; i <= EFX_TXQ_MASK; ++i) |
b9b39b62 | 1142 | efx_tsoh_free(tx_queue, &tx_queue->buffer[i]); |
b3475645 | 1143 | } |
b9b39b62 BH |
1144 | |
1145 | while (tx_queue->tso_headers_free != NULL) | |
1146 | efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free, | |
1147 | tx_queue->efx->pci_dev); | |
1148 | } |