[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sfc / qt202x_phy.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */
/*
 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
 */

#include <linux/timer.h>
#include <linux/delay.h>
#include "efx.h"
#include "mdio_10g.h"
#include "phy.h"
#include "nic.h"

#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |		\
			      MDIO_DEVS_PMAPMD |	\
			      MDIO_DEVS_PHYXS)

#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |		\
			  (1 << LOOPBACK_PMAPMD) |	\
			  (1 << LOOPBACK_PHYXS_WS))

/****************************************************************************/
/* Quake-specific MDIO registers */
#define MDIO_QUAKE_LED0_REG	(0xD006)

/* QT2025C only */
#define PCS_FW_HEARTBEAT_REG	0xd7ee
#define PCS_FW_HEARTB_LBN	0
#define PCS_FW_HEARTB_WIDTH	8
#define PCS_UC8051_STATUS_REG	0xd7fd
#define PCS_UC_STATUS_LBN	0
#define PCS_UC_STATUS_WIDTH	8
#define PCS_UC_STATUS_FW_SAVE	0x20
#define PMA_PMD_FTX_CTRL2_REG	0xc309
#define PMA_PMD_FTX_STATIC_LBN	13
#define PMA_PMD_VEND1_REG	0xc001
#define PMA_PMD_VEND1_LBTXD_LBN	15
#define PCS_VEND1_REG	   	0xc000
#define PCS_VEND1_LBTXD_LBN	5

void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
{
	int addr = MDIO_QUAKE_LED0_REG + led;
	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
}

struct qt202x_phy_data {
	enum efx_phy_mode phy_mode;
};

#define QT2022C2_MAX_RESET_TIME 500
#define QT2022C2_RESET_WAIT 10

static int qt2025c_wait_reset(struct efx_nic *efx)
{
	unsigned long timeout = jiffies + 10 * HZ;
	int reg, old_counter = 0;

	/* Wait for firmware heartbeat to start */
	for (;;) {
		int counter;
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
		if (reg < 0)
			return reg;
		counter = ((reg >> PCS_FW_HEARTB_LBN) &
			    ((1 << PCS_FW_HEARTB_WIDTH) - 1));
		if (old_counter == 0)
			old_counter = counter;
		else if (counter != old_counter)
			break;
		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
		msleep(10);
	}

	/* Wait for firmware status to look good */
	for (;;) {
		reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
		if (reg < 0)
			return reg;
		if ((reg &
		     ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
		    PCS_UC_STATUS_FW_SAVE)
			break;
		if (time_after(jiffies, timeout))
			return -ETIMEDOUT;
		msleep(100);
	}

	return 0;
}

static int qt202x_reset_phy(struct efx_nic *efx)
{
	int rc;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		/* Wait for the reset triggered by falcon_reset_hw()
		 * to complete */
		rc = qt2025c_wait_reset(efx);
		if (rc < 0)
			goto fail;
	} else {
		/* Reset the PHYXS MMD. This is documented as doing
		 * a complete soft reset. */
		rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
					QT2022C2_MAX_RESET_TIME /
					QT2022C2_RESET_WAIT,
					QT2022C2_RESET_WAIT);
		if (rc < 0)
			goto fail;
	}

	/* Wait 250ms for the PHY to complete bootup */
	msleep(250);

	/* Check that all the MMDs we expect are present and responding. We
	 * expect faults on some if the link is down, but not on the PHY XS */
	rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
	if (rc < 0)
		goto fail;

	falcon_board(efx)->type->init_phy(efx);

	return rc;

 fail:
	EFX_ERR(efx, "PHY reset timed out\n");
	return rc;
}

static int qt202x_phy_probe(struct efx_nic *efx)
{
	efx->mdio.mmds = QT202X_REQUIRED_DEVS;
	efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
	efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
	return 0;
}

static int qt202x_phy_init(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data;
	u32 devid;
	int rc;

	rc = qt202x_reset_phy(efx);
	if (rc) {
		EFX_ERR(efx, "PHY init failed\n");
		return rc;
	}

	phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;

	devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
		 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
		 efx_mdio_id_rev(devid));

	phy_data->phy_mode = efx->phy_mode;
	return 0;
}

static int qt202x_link_ok(struct efx_nic *efx)
{
	return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
}

static bool qt202x_phy_poll(struct efx_nic *efx)
{
	bool was_up = efx->link_state.up;

	efx->link_state.up = qt202x_link_ok(efx);
	efx->link_state.speed = 10000;
	efx->link_state.fd = true;
	efx->link_state.fc = efx->wanted_fc;

	return efx->link_state.up != was_up;
}

static int qt202x_phy_reconfigure(struct efx_nic *efx)
{
	struct qt202x_phy_data *phy_data = efx->phy_data;

	if (efx->phy_type == PHY_TYPE_QT2025C) {
		/* There are several different register bits which can
		 * disable TX (and save power) on direct-attach cables
		 * or optical transceivers, varying somewhat between
		 * firmware versions.  Only 'static mode' appears to
		 * cover everything. */
		mdio_set_flag(
			&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
			PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
			efx->phy_mode & PHY_MODE_TX_DISABLED ||
			efx->phy_mode & PHY_MODE_LOW_POWER ||
			efx->loopback_mode == LOOPBACK_PCS ||
			efx->loopback_mode == LOOPBACK_PMAPMD);
	} else {
		/* Reset the PHY when moving from tx off to tx on */
		if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
		    (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
			qt202x_reset_phy(efx);

		efx_mdio_transmit_disable(efx);
	}

	efx_mdio_phy_reconfigure(efx);

	phy_data->phy_mode = efx->phy_mode;

	return 0;
}

static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	mdio45_ethtool_gset(&efx->mdio, ecmd);
}

static void qt202x_phy_fini(struct efx_nic *efx)
{
	/* Free the context block */
	kfree(efx->phy_data);
	efx->phy_data = NULL;
}

struct efx_phy_operations falcon_qt202x_phy_ops = {
	.probe		 = qt202x_phy_probe,
	.init		 = qt202x_phy_init,
	.reconfigure	 = qt202x_phy_reconfigure,
	.poll	     	 = qt202x_phy_poll,
	.fini	  	 = qt202x_phy_fini,
	.get_settings	 = qt202x_phy_get_settings,
	.set_settings	 = efx_mdio_set_settings,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
8ceee660 BH	2	* Driver for Solarflare Solarstorm network controllers and boards
906bb26c	3	* Copyright 2006-2009 Solarflare Communications Inc.
8ceee660 BH	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9	/*
b37b62fe	10	* Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
8ceee660 BH	11	*/
	12
	13	#include <linux/timer.h>
	14	#include <linux/delay.h>
	15	#include "efx.h"
8ceee660	16	#include "mdio_10g.h"
8ceee660	17	#include "phy.h"
744093c9	18	#include "nic.h"
8ceee660	19
b37b62fe BH	20	#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS \| \
	21	MDIO_DEVS_PMAPMD \| \
	22	MDIO_DEVS_PHYXS)
8ceee660	23
b37b62fe BH	24	#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) \| \
b37b62fe BH	25	(1 << LOOPBACK_PMAPMD) \| \
e58f69f4	26	(1 << LOOPBACK_PHYXS_WS))
3273c2e8	27
8ceee660 BH	28	/****************************************************************************/
	29	/* Quake-specific MDIO registers */
	30	#define MDIO_QUAKE_LED0_REG (0xD006)
	31
d2d2c373 BH	32	/* QT2025C only */
	33	#define PCS_FW_HEARTBEAT_REG 0xd7ee
	34	#define PCS_FW_HEARTB_LBN 0
	35	#define PCS_FW_HEARTB_WIDTH 8
	36	#define PCS_UC8051_STATUS_REG 0xd7fd
	37	#define PCS_UC_STATUS_LBN 0
	38	#define PCS_UC_STATUS_WIDTH 8
	39	#define PCS_UC_STATUS_FW_SAVE 0x20
	40	#define PMA_PMD_FTX_CTRL2_REG 0xc309
	41	#define PMA_PMD_FTX_STATIC_LBN 13
	42	#define PMA_PMD_VEND1_REG 0xc001
	43	#define PMA_PMD_VEND1_LBTXD_LBN 15
	44	#define PCS_VEND1_REG 0xc000
	45	#define PCS_VEND1_LBTXD_LBN 5
	46
b37b62fe	47	void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
8ceee660 BH	48	{
8ceee660 BH	49	int addr = MDIO_QUAKE_LED0_REG + led;
68e7f45e	50	efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
8ceee660 BH	51	}
8ceee660 BH	52
b37b62fe	53	struct qt202x_phy_data {
f8b87c17	54	enum efx_phy_mode phy_mode;
3273c2e8 BH	55	};
3273c2e8 BH	56
b37b62fe BH	57	#define QT2022C2_MAX_RESET_TIME 500
b37b62fe BH	58	#define QT2022C2_RESET_WAIT 10
8ceee660	59
d2d2c373 BH	60	static int qt2025c_wait_reset(struct efx_nic *efx)
	61	{
	62	unsigned long timeout = jiffies + 10 * HZ;
d2d2c373 BH	63	int reg, old_counter = 0;
	64
	65	/* Wait for firmware heartbeat to start */
	66	for (;;) {
	67	int counter;
68e7f45e	68	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
d2d2c373 BH	69	if (reg < 0)
	70	return reg;
	71	counter = ((reg >> PCS_FW_HEARTB_LBN) &
	72	((1 << PCS_FW_HEARTB_WIDTH) - 1));
	73	if (old_counter == 0)
	74	old_counter = counter;
	75	else if (counter != old_counter)
	76	break;
	77	if (time_after(jiffies, timeout))
	78	return -ETIMEDOUT;
	79	msleep(10);
	80	}
	81
	82	/* Wait for firmware status to look good */
	83	for (;;) {
68e7f45e	84	reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
d2d2c373 BH	85	if (reg < 0)
	86	return reg;
	87	if ((reg &
	88	((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
	89	PCS_UC_STATUS_FW_SAVE)
	90	break;
	91	if (time_after(jiffies, timeout))
	92	return -ETIMEDOUT;
	93	msleep(100);
	94	}
	95
	96	return 0;
	97	}
	98
b37b62fe	99	static int qt202x_reset_phy(struct efx_nic *efx)
8ceee660 BH	100	{
	101	int rc;
	102
d2d2c373	103	if (efx->phy_type == PHY_TYPE_QT2025C) {
5afaa753 BH	104	/* Wait for the reset triggered by falcon_reset_hw()
5afaa753 BH	105	* to complete */
d2d2c373 BH	106	rc = qt2025c_wait_reset(efx);
	107	if (rc < 0)
	108	goto fail;
5afaa753 BH	109	} else {
	110	/* Reset the PHYXS MMD. This is documented as doing
	111	* a complete soft reset. */
	112	rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
b37b62fe BH	113	QT2022C2_MAX_RESET_TIME /
	114	QT2022C2_RESET_WAIT,
	115	QT2022C2_RESET_WAIT);
5afaa753 BH	116	if (rc < 0)
5afaa753 BH	117	goto fail;
d2d2c373 BH	118	}
d2d2c373 BH	119
8ceee660 BH	120	/* Wait 250ms for the PHY to complete bootup */
	121	msleep(250);
	122
	123	/* Check that all the MMDs we expect are present and responding. We
	124	* expect faults on some if the link is down, but not on the PHY XS */
b37b62fe	125	rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
8ceee660 BH	126	if (rc < 0)
	127	goto fail;
	128
44838a44	129	falcon_board(efx)->type->init_phy(efx);
8ceee660 BH	130
	131	return rc;
	132
	133	fail:
f794fd44	134	EFX_ERR(efx, "PHY reset timed out\n");
8ceee660 BH	135	return rc;
	136	}
	137
c1c4f453 BH	138	static int qt202x_phy_probe(struct efx_nic *efx)
	139	{
	140	efx->mdio.mmds = QT202X_REQUIRED_DEVS;
	141	efx->mdio.mode_support = MDIO_SUPPORTS_C45 \| MDIO_EMULATE_C22;
	142	efx->loopback_modes = QT202X_LOOPBACKS \| FALCON_XMAC_LOOPBACKS;
	143	return 0;
	144	}
	145
b37b62fe	146	static int qt202x_phy_init(struct efx_nic *efx)
8ceee660	147	{
b37b62fe	148	struct qt202x_phy_data *phy_data;
47c3d19f	149	u32 devid;
8ceee660 BH	150	int rc;
8ceee660 BH	151
47c3d19f SH	152	rc = qt202x_reset_phy(efx);
	153	if (rc) {
	154	EFX_ERR(efx, "PHY init failed\n");
	155	return rc;
	156	}
	157
b37b62fe	158	phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
9b7bfc4c BH	159	if (!phy_data)
9b7bfc4c BH	160	return -ENOMEM;
d3208b5e	161	efx->phy_data = phy_data;
3273c2e8	162
47c3d19f	163	devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
3f39a5e9	164	EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
68e7f45e BH	165	devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
68e7f45e BH	166	efx_mdio_id_rev(devid));
8ceee660	167
f8b87c17	168	phy_data->phy_mode = efx->phy_mode;
3273c2e8	169	return 0;
8ceee660 BH	170	}
8ceee660 BH	171
b37b62fe	172	static int qt202x_link_ok(struct efx_nic *efx)
8ceee660	173	{
b37b62fe	174	return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
8ceee660 BH	175	}
8ceee660 BH	176
fdaa9aed	177	static bool qt202x_phy_poll(struct efx_nic *efx)
8ceee660	178	{
fdaa9aed SH	179	bool was_up = efx->link_state.up;
	180
	181	efx->link_state.up = qt202x_link_ok(efx);
	182	efx->link_state.speed = 10000;
	183	efx->link_state.fd = true;
	184	efx->link_state.fc = efx->wanted_fc;
	185
	186	return efx->link_state.up != was_up;
8ceee660 BH	187	}
8ceee660 BH	188
d3245b28	189	static int qt202x_phy_reconfigure(struct efx_nic *efx)
8ceee660	190	{
b37b62fe	191	struct qt202x_phy_data *phy_data = efx->phy_data;
3273c2e8	192
d2d2c373 BH	193	if (efx->phy_type == PHY_TYPE_QT2025C) {
	194	/* There are several different register bits which can
	195	* disable TX (and save power) on direct-attach cables
	196	* or optical transceivers, varying somewhat between
	197	* firmware versions. Only 'static mode' appears to
	198	* cover everything. */
68e7f45e BH	199	mdio_set_flag(
	200	&efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
	201	PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
d2d2c373 BH	202	efx->phy_mode & PHY_MODE_TX_DISABLED \|\|
	203	efx->phy_mode & PHY_MODE_LOW_POWER \|\|
	204	efx->loopback_mode == LOOPBACK_PCS \|\|
	205	efx->loopback_mode == LOOPBACK_PMAPMD);
	206	} else {
	207	/* Reset the PHY when moving from tx off to tx on */
	208	if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
	209	(phy_data->phy_mode & PHY_MODE_TX_DISABLED))
b37b62fe	210	qt202x_reset_phy(efx);
d2d2c373	211
68e7f45e	212	efx_mdio_transmit_disable(efx);
d2d2c373	213	}
3273c2e8	214
68e7f45e	215	efx_mdio_phy_reconfigure(efx);
3273c2e8	216
f8b87c17	217	phy_data->phy_mode = efx->phy_mode;
d3245b28 BH	218
d3245b28 BH	219	return 0;
8ceee660 BH	220	}
8ceee660 BH	221
b37b62fe	222	static void qt202x_phy_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
68e7f45e BH	223	{
	224	mdio45_ethtool_gset(&efx->mdio, ecmd);
	225	}
8ceee660	226
b37b62fe	227	static void qt202x_phy_fini(struct efx_nic *efx)
8ceee660	228	{
3273c2e8 BH	229	/* Free the context block */
	230	kfree(efx->phy_data);
	231	efx->phy_data = NULL;
8ceee660 BH	232	}
8ceee660 BH	233
b37b62fe	234	struct efx_phy_operations falcon_qt202x_phy_ops = {
c1c4f453	235	.probe = qt202x_phy_probe,
b37b62fe BH	236	.init = qt202x_phy_init,
	237	.reconfigure = qt202x_phy_reconfigure,
	238	.poll = qt202x_phy_poll,
	239	.fini = qt202x_phy_fini,
b37b62fe	240	.get_settings = qt202x_phy_get_settings,
68e7f45e	241	.set_settings = efx_mdio_set_settings,
8ceee660	242	};