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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
906bb26c | 3 | * Copyright 2006-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | /* | |
b37b62fe | 10 | * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details |
8ceee660 BH |
11 | */ |
12 | ||
13 | #include <linux/timer.h> | |
14 | #include <linux/delay.h> | |
15 | #include "efx.h" | |
8ceee660 | 16 | #include "mdio_10g.h" |
8ceee660 | 17 | #include "phy.h" |
744093c9 | 18 | #include "nic.h" |
8ceee660 | 19 | |
b37b62fe BH |
20 | #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \ |
21 | MDIO_DEVS_PMAPMD | \ | |
22 | MDIO_DEVS_PHYXS) | |
8ceee660 | 23 | |
b37b62fe BH |
24 | #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \ |
25 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 26 | (1 << LOOPBACK_PHYXS_WS)) |
3273c2e8 | 27 | |
8ceee660 BH |
28 | /****************************************************************************/ |
29 | /* Quake-specific MDIO registers */ | |
30 | #define MDIO_QUAKE_LED0_REG (0xD006) | |
31 | ||
d2d2c373 BH |
32 | /* QT2025C only */ |
33 | #define PCS_FW_HEARTBEAT_REG 0xd7ee | |
34 | #define PCS_FW_HEARTB_LBN 0 | |
35 | #define PCS_FW_HEARTB_WIDTH 8 | |
36 | #define PCS_UC8051_STATUS_REG 0xd7fd | |
37 | #define PCS_UC_STATUS_LBN 0 | |
38 | #define PCS_UC_STATUS_WIDTH 8 | |
39 | #define PCS_UC_STATUS_FW_SAVE 0x20 | |
40 | #define PMA_PMD_FTX_CTRL2_REG 0xc309 | |
41 | #define PMA_PMD_FTX_STATIC_LBN 13 | |
42 | #define PMA_PMD_VEND1_REG 0xc001 | |
43 | #define PMA_PMD_VEND1_LBTXD_LBN 15 | |
44 | #define PCS_VEND1_REG 0xc000 | |
45 | #define PCS_VEND1_LBTXD_LBN 5 | |
46 | ||
b37b62fe | 47 | void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode) |
8ceee660 BH |
48 | { |
49 | int addr = MDIO_QUAKE_LED0_REG + led; | |
68e7f45e | 50 | efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode); |
8ceee660 BH |
51 | } |
52 | ||
b37b62fe | 53 | struct qt202x_phy_data { |
f8b87c17 | 54 | enum efx_phy_mode phy_mode; |
17d6aeaf MS |
55 | bool bug17190_in_bad_state; |
56 | unsigned long bug17190_timer; | |
3273c2e8 BH |
57 | }; |
58 | ||
b37b62fe BH |
59 | #define QT2022C2_MAX_RESET_TIME 500 |
60 | #define QT2022C2_RESET_WAIT 10 | |
8ceee660 | 61 | |
17d6aeaf MS |
62 | #define BUG17190_INTERVAL (2 * HZ) |
63 | ||
d2d2c373 BH |
64 | static int qt2025c_wait_reset(struct efx_nic *efx) |
65 | { | |
66 | unsigned long timeout = jiffies + 10 * HZ; | |
d2d2c373 BH |
67 | int reg, old_counter = 0; |
68 | ||
69 | /* Wait for firmware heartbeat to start */ | |
70 | for (;;) { | |
71 | int counter; | |
68e7f45e | 72 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG); |
d2d2c373 BH |
73 | if (reg < 0) |
74 | return reg; | |
75 | counter = ((reg >> PCS_FW_HEARTB_LBN) & | |
76 | ((1 << PCS_FW_HEARTB_WIDTH) - 1)); | |
77 | if (old_counter == 0) | |
78 | old_counter = counter; | |
79 | else if (counter != old_counter) | |
80 | break; | |
81 | if (time_after(jiffies, timeout)) | |
82 | return -ETIMEDOUT; | |
83 | msleep(10); | |
84 | } | |
85 | ||
86 | /* Wait for firmware status to look good */ | |
87 | for (;;) { | |
68e7f45e | 88 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG); |
d2d2c373 BH |
89 | if (reg < 0) |
90 | return reg; | |
91 | if ((reg & | |
92 | ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= | |
93 | PCS_UC_STATUS_FW_SAVE) | |
94 | break; | |
95 | if (time_after(jiffies, timeout)) | |
96 | return -ETIMEDOUT; | |
97 | msleep(100); | |
98 | } | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
17d6aeaf MS |
103 | static void qt2025c_bug17190_workaround(struct efx_nic *efx) |
104 | { | |
105 | struct qt202x_phy_data *phy_data = efx->phy_data; | |
106 | ||
107 | /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD | |
108 | * layers up, but PCS down (no block_lock). If we notice this state | |
109 | * persisting for a couple of seconds, we switch PMA/PMD loopback | |
110 | * briefly on and then off again, which is normally sufficient to | |
111 | * recover it. | |
112 | */ | |
113 | if (efx->link_state.up || | |
114 | !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) { | |
115 | phy_data->bug17190_in_bad_state = false; | |
116 | return; | |
117 | } | |
118 | ||
119 | if (!phy_data->bug17190_in_bad_state) { | |
120 | phy_data->bug17190_in_bad_state = true; | |
121 | phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL; | |
122 | return; | |
123 | } | |
124 | ||
125 | if (time_after_eq(jiffies, phy_data->bug17190_timer)) { | |
126 | EFX_LOG(efx, "bashing QT2025C PMA/PMD\n"); | |
127 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, | |
128 | MDIO_PMA_CTRL1_LOOPBACK, true); | |
129 | msleep(100); | |
130 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, | |
131 | MDIO_PMA_CTRL1_LOOPBACK, false); | |
132 | phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL; | |
133 | } | |
134 | } | |
135 | ||
b37b62fe | 136 | static int qt202x_reset_phy(struct efx_nic *efx) |
8ceee660 BH |
137 | { |
138 | int rc; | |
139 | ||
d2d2c373 | 140 | if (efx->phy_type == PHY_TYPE_QT2025C) { |
5afaa753 BH |
141 | /* Wait for the reset triggered by falcon_reset_hw() |
142 | * to complete */ | |
d2d2c373 BH |
143 | rc = qt2025c_wait_reset(efx); |
144 | if (rc < 0) | |
145 | goto fail; | |
5afaa753 BH |
146 | } else { |
147 | /* Reset the PHYXS MMD. This is documented as doing | |
148 | * a complete soft reset. */ | |
149 | rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS, | |
b37b62fe BH |
150 | QT2022C2_MAX_RESET_TIME / |
151 | QT2022C2_RESET_WAIT, | |
152 | QT2022C2_RESET_WAIT); | |
5afaa753 BH |
153 | if (rc < 0) |
154 | goto fail; | |
d2d2c373 BH |
155 | } |
156 | ||
8ceee660 BH |
157 | /* Wait 250ms for the PHY to complete bootup */ |
158 | msleep(250); | |
159 | ||
160 | /* Check that all the MMDs we expect are present and responding. We | |
161 | * expect faults on some if the link is down, but not on the PHY XS */ | |
b37b62fe | 162 | rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS); |
8ceee660 BH |
163 | if (rc < 0) |
164 | goto fail; | |
165 | ||
44838a44 | 166 | falcon_board(efx)->type->init_phy(efx); |
8ceee660 BH |
167 | |
168 | return rc; | |
169 | ||
170 | fail: | |
f794fd44 | 171 | EFX_ERR(efx, "PHY reset timed out\n"); |
8ceee660 BH |
172 | return rc; |
173 | } | |
174 | ||
c1c4f453 BH |
175 | static int qt202x_phy_probe(struct efx_nic *efx) |
176 | { | |
ff3b00a0 SH |
177 | struct qt202x_phy_data *phy_data; |
178 | ||
179 | phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL); | |
180 | if (!phy_data) | |
181 | return -ENOMEM; | |
182 | efx->phy_data = phy_data; | |
183 | phy_data->phy_mode = efx->phy_mode; | |
17d6aeaf MS |
184 | phy_data->bug17190_in_bad_state = false; |
185 | phy_data->bug17190_timer = 0; | |
ff3b00a0 | 186 | |
c1c4f453 BH |
187 | efx->mdio.mmds = QT202X_REQUIRED_DEVS; |
188 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
189 | efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | |
190 | return 0; | |
191 | } | |
192 | ||
b37b62fe | 193 | static int qt202x_phy_init(struct efx_nic *efx) |
8ceee660 | 194 | { |
47c3d19f | 195 | u32 devid; |
8ceee660 BH |
196 | int rc; |
197 | ||
47c3d19f SH |
198 | rc = qt202x_reset_phy(efx); |
199 | if (rc) { | |
200 | EFX_ERR(efx, "PHY init failed\n"); | |
201 | return rc; | |
202 | } | |
203 | ||
47c3d19f | 204 | devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS); |
3f39a5e9 | 205 | EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n", |
68e7f45e BH |
206 | devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid), |
207 | efx_mdio_id_rev(devid)); | |
8ceee660 | 208 | |
3273c2e8 | 209 | return 0; |
8ceee660 BH |
210 | } |
211 | ||
b37b62fe | 212 | static int qt202x_link_ok(struct efx_nic *efx) |
8ceee660 | 213 | { |
b37b62fe | 214 | return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS); |
8ceee660 BH |
215 | } |
216 | ||
fdaa9aed | 217 | static bool qt202x_phy_poll(struct efx_nic *efx) |
8ceee660 | 218 | { |
fdaa9aed SH |
219 | bool was_up = efx->link_state.up; |
220 | ||
221 | efx->link_state.up = qt202x_link_ok(efx); | |
222 | efx->link_state.speed = 10000; | |
223 | efx->link_state.fd = true; | |
224 | efx->link_state.fc = efx->wanted_fc; | |
225 | ||
17d6aeaf MS |
226 | if (efx->phy_type == PHY_TYPE_QT2025C) |
227 | qt2025c_bug17190_workaround(efx); | |
228 | ||
fdaa9aed | 229 | return efx->link_state.up != was_up; |
8ceee660 BH |
230 | } |
231 | ||
d3245b28 | 232 | static int qt202x_phy_reconfigure(struct efx_nic *efx) |
8ceee660 | 233 | { |
b37b62fe | 234 | struct qt202x_phy_data *phy_data = efx->phy_data; |
3273c2e8 | 235 | |
d2d2c373 BH |
236 | if (efx->phy_type == PHY_TYPE_QT2025C) { |
237 | /* There are several different register bits which can | |
238 | * disable TX (and save power) on direct-attach cables | |
239 | * or optical transceivers, varying somewhat between | |
240 | * firmware versions. Only 'static mode' appears to | |
241 | * cover everything. */ | |
68e7f45e BH |
242 | mdio_set_flag( |
243 | &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD, | |
244 | PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN, | |
d2d2c373 BH |
245 | efx->phy_mode & PHY_MODE_TX_DISABLED || |
246 | efx->phy_mode & PHY_MODE_LOW_POWER || | |
247 | efx->loopback_mode == LOOPBACK_PCS || | |
248 | efx->loopback_mode == LOOPBACK_PMAPMD); | |
249 | } else { | |
250 | /* Reset the PHY when moving from tx off to tx on */ | |
251 | if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) && | |
252 | (phy_data->phy_mode & PHY_MODE_TX_DISABLED)) | |
b37b62fe | 253 | qt202x_reset_phy(efx); |
d2d2c373 | 254 | |
68e7f45e | 255 | efx_mdio_transmit_disable(efx); |
d2d2c373 | 256 | } |
3273c2e8 | 257 | |
68e7f45e | 258 | efx_mdio_phy_reconfigure(efx); |
3273c2e8 | 259 | |
f8b87c17 | 260 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 BH |
261 | |
262 | return 0; | |
8ceee660 BH |
263 | } |
264 | ||
b37b62fe | 265 | static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
68e7f45e BH |
266 | { |
267 | mdio45_ethtool_gset(&efx->mdio, ecmd); | |
268 | } | |
8ceee660 | 269 | |
ff3b00a0 | 270 | static void qt202x_phy_remove(struct efx_nic *efx) |
8ceee660 | 271 | { |
3273c2e8 BH |
272 | /* Free the context block */ |
273 | kfree(efx->phy_data); | |
274 | efx->phy_data = NULL; | |
8ceee660 BH |
275 | } |
276 | ||
b37b62fe | 277 | struct efx_phy_operations falcon_qt202x_phy_ops = { |
c1c4f453 | 278 | .probe = qt202x_phy_probe, |
b37b62fe BH |
279 | .init = qt202x_phy_init, |
280 | .reconfigure = qt202x_phy_reconfigure, | |
281 | .poll = qt202x_phy_poll, | |
ff3b00a0 SH |
282 | .fini = efx_port_dummy_op_void, |
283 | .remove = qt202x_phy_remove, | |
b37b62fe | 284 | .get_settings = qt202x_phy_get_settings, |
68e7f45e | 285 | .set_settings = efx_mdio_set_settings, |
8ceee660 | 286 | }; |