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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include "net_driver.h" | |
13 | #include "efx.h" | |
14 | #include "falcon.h" | |
15 | #include "falcon_hwdefs.h" | |
16 | #include "falcon_io.h" | |
17 | #include "mac.h" | |
8ceee660 BH |
18 | #include "mdio_10g.h" |
19 | #include "phy.h" | |
20 | #include "boards.h" | |
21 | #include "workarounds.h" | |
22 | ||
8ceee660 BH |
23 | /************************************************************************** |
24 | * | |
25 | * MAC operations | |
26 | * | |
27 | *************************************************************************/ | |
8ceee660 BH |
28 | |
29 | /* Configure the XAUI driver that is an output from Falcon */ | |
30 | static void falcon_setup_xaui(struct efx_nic *efx) | |
31 | { | |
c1e5fcc9 | 32 | efx_oword_t sdctl, txdrv; |
8ceee660 BH |
33 | |
34 | /* Move the XAUI into low power, unless there is no PHY, in | |
35 | * which case the XAUI will have to drive a cable. */ | |
36 | if (efx->phy_type == PHY_TYPE_NONE) | |
37 | return; | |
38 | ||
c1e5fcc9 BH |
39 | falcon_read(efx, &sdctl, XX_SD_CTL_REG); |
40 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT); | |
41 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT); | |
42 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT); | |
43 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT); | |
44 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT); | |
45 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT); | |
46 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT); | |
47 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT); | |
48 | falcon_write(efx, &sdctl, XX_SD_CTL_REG); | |
49 | ||
50 | EFX_POPULATE_OWORD_8(txdrv, | |
8ceee660 BH |
51 | XX_DEQD, XX_TXDRV_DEQ_DEFAULT, |
52 | XX_DEQC, XX_TXDRV_DEQ_DEFAULT, | |
53 | XX_DEQB, XX_TXDRV_DEQ_DEFAULT, | |
54 | XX_DEQA, XX_TXDRV_DEQ_DEFAULT, | |
55 | XX_DTXD, XX_TXDRV_DTX_DEFAULT, | |
56 | XX_DTXC, XX_TXDRV_DTX_DEFAULT, | |
57 | XX_DTXB, XX_TXDRV_DTX_DEFAULT, | |
58 | XX_DTXA, XX_TXDRV_DTX_DEFAULT); | |
c1e5fcc9 | 59 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); |
8ceee660 BH |
60 | } |
61 | ||
ef08af03 | 62 | int falcon_reset_xaui(struct efx_nic *efx) |
8ceee660 | 63 | { |
c1e5fcc9 | 64 | efx_oword_t reg; |
8ceee660 BH |
65 | int count; |
66 | ||
d4ec09ac | 67 | /* Start reset sequence */ |
8ceee660 | 68 | EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); |
c1e5fcc9 | 69 | falcon_write(efx, ®, XX_PWR_RST_REG); |
8ceee660 | 70 | |
d4ec09ac BH |
71 | /* Wait up to 10 ms for completion, then reinitialise */ |
72 | for (count = 0; count < 1000; count++) { | |
c1e5fcc9 | 73 | falcon_read(efx, ®, XX_PWR_RST_REG); |
d4ec09ac BH |
74 | if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0 && |
75 | EFX_OWORD_FIELD(reg, XX_SD_RST_ACT) == 0) { | |
8ceee660 BH |
76 | falcon_setup_xaui(efx); |
77 | return 0; | |
78 | } | |
79 | udelay(10); | |
80 | } | |
81 | EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n"); | |
82 | return -ETIMEDOUT; | |
83 | } | |
84 | ||
177dfcd8 | 85 | static void falcon_mask_status_intr(struct efx_nic *efx, bool enable) |
8ceee660 | 86 | { |
c1e5fcc9 | 87 | efx_oword_t reg; |
8ceee660 | 88 | |
177dfcd8 BH |
89 | if ((falcon_rev(efx) != FALCON_REV_B0) || LOOPBACK_INTERNAL(efx)) |
90 | return; | |
8ceee660 | 91 | |
177dfcd8 BH |
92 | /* We expect xgmii faults if the wireside link is up */ |
93 | if (!EFX_WORKAROUND_5147(efx) || !efx->link_up) | |
94 | return; | |
8ceee660 | 95 | |
177dfcd8 BH |
96 | /* We can only use this interrupt to signal the negative edge of |
97 | * xaui_align [we have to poll the positive edge]. */ | |
98 | if (!efx->mac_up) | |
8ceee660 BH |
99 | return; |
100 | ||
101 | /* Flush the ISR */ | |
102 | if (enable) | |
c1e5fcc9 | 103 | falcon_read(efx, ®, XM_MGT_INT_REG_B0); |
8ceee660 | 104 | |
c1e5fcc9 | 105 | EFX_POPULATE_OWORD_2(reg, |
8ceee660 BH |
106 | XM_MSK_RMTFLT, !enable, |
107 | XM_MSK_LCLFLT, !enable); | |
c1e5fcc9 | 108 | falcon_write(efx, ®, XM_MGT_INT_MSK_REG_B0); |
8ceee660 BH |
109 | } |
110 | ||
177dfcd8 | 111 | /* Get status of XAUI link */ |
dc8cfa55 | 112 | bool falcon_xaui_link_ok(struct efx_nic *efx) |
8ceee660 | 113 | { |
c1e5fcc9 | 114 | efx_oword_t reg; |
dc8cfa55 BH |
115 | bool align_done, link_ok = false; |
116 | int sync_status; | |
8ceee660 | 117 | |
3273c2e8 | 118 | if (LOOPBACK_INTERNAL(efx)) |
dc8cfa55 | 119 | return true; |
3273c2e8 | 120 | |
8ceee660 | 121 | /* Read link status */ |
c1e5fcc9 | 122 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
8ceee660 | 123 | |
c1e5fcc9 BH |
124 | align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE); |
125 | sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT); | |
8ceee660 | 126 | if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED)) |
dc8cfa55 | 127 | link_ok = true; |
8ceee660 BH |
128 | |
129 | /* Clear link status ready for next read */ | |
c1e5fcc9 BH |
130 | EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET); |
131 | EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET); | |
132 | EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET); | |
133 | falcon_write(efx, ®, XX_CORE_STAT_REG); | |
8ceee660 | 134 | |
177dfcd8 BH |
135 | /* If the link is up, then check the phy side of the xaui link */ |
136 | if (efx->link_up && link_ok) | |
dc8cfa55 | 137 | if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS)) |
68e7f45e | 138 | link_ok = efx_mdio_phyxgxs_lane_sync(efx); |
8ceee660 BH |
139 | |
140 | return link_ok; | |
141 | } | |
142 | ||
143 | static void falcon_reconfigure_xmac_core(struct efx_nic *efx) | |
144 | { | |
145 | unsigned int max_frame_len; | |
c1e5fcc9 | 146 | efx_oword_t reg; |
04cc8cac | 147 | bool rx_fc = !!(efx->link_fc & EFX_FC_RX); |
8ceee660 BH |
148 | |
149 | /* Configure MAC - cut-thru mode is hard wired on */ | |
150 | EFX_POPULATE_DWORD_3(reg, | |
151 | XM_RX_JUMBO_MODE, 1, | |
152 | XM_TX_STAT_EN, 1, | |
153 | XM_RX_STAT_EN, 1); | |
c1e5fcc9 | 154 | falcon_write(efx, ®, XM_GLB_CFG_REG); |
8ceee660 BH |
155 | |
156 | /* Configure TX */ | |
157 | EFX_POPULATE_DWORD_6(reg, | |
158 | XM_TXEN, 1, | |
159 | XM_TX_PRMBL, 1, | |
160 | XM_AUTO_PAD, 1, | |
161 | XM_TXCRC, 1, | |
162 | XM_FCNTL, 1, | |
163 | XM_IPG, 0x3); | |
c1e5fcc9 | 164 | falcon_write(efx, ®, XM_TX_CFG_REG); |
8ceee660 BH |
165 | |
166 | /* Configure RX */ | |
167 | EFX_POPULATE_DWORD_5(reg, | |
168 | XM_RXEN, 1, | |
169 | XM_AUTO_DEPAD, 0, | |
170 | XM_ACPT_ALL_MCAST, 1, | |
171 | XM_ACPT_ALL_UCAST, efx->promiscuous, | |
172 | XM_PASS_CRC_ERR, 1); | |
c1e5fcc9 | 173 | falcon_write(efx, ®, XM_RX_CFG_REG); |
8ceee660 BH |
174 | |
175 | /* Set frame length */ | |
176 | max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); | |
177 | EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len); | |
c1e5fcc9 | 178 | falcon_write(efx, ®, XM_RX_PARAM_REG); |
8ceee660 BH |
179 | EFX_POPULATE_DWORD_2(reg, |
180 | XM_MAX_TX_FRM_SIZE, max_frame_len, | |
181 | XM_TX_JUMBO_MODE, 1); | |
c1e5fcc9 | 182 | falcon_write(efx, ®, XM_TX_PARAM_REG); |
8ceee660 BH |
183 | |
184 | EFX_POPULATE_DWORD_2(reg, | |
185 | XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ | |
dc8cfa55 | 186 | XM_DIS_FCNTL, !rx_fc); |
c1e5fcc9 | 187 | falcon_write(efx, ®, XM_FC_REG); |
8ceee660 BH |
188 | |
189 | /* Set MAC address */ | |
190 | EFX_POPULATE_DWORD_4(reg, | |
191 | XM_ADR_0, efx->net_dev->dev_addr[0], | |
192 | XM_ADR_1, efx->net_dev->dev_addr[1], | |
193 | XM_ADR_2, efx->net_dev->dev_addr[2], | |
194 | XM_ADR_3, efx->net_dev->dev_addr[3]); | |
c1e5fcc9 | 195 | falcon_write(efx, ®, XM_ADR_LO_REG); |
8ceee660 BH |
196 | EFX_POPULATE_DWORD_2(reg, |
197 | XM_ADR_4, efx->net_dev->dev_addr[4], | |
198 | XM_ADR_5, efx->net_dev->dev_addr[5]); | |
c1e5fcc9 | 199 | falcon_write(efx, ®, XM_ADR_HI_REG); |
8ceee660 BH |
200 | } |
201 | ||
3273c2e8 BH |
202 | static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) |
203 | { | |
c1e5fcc9 | 204 | efx_oword_t reg; |
dc8cfa55 BH |
205 | bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS); |
206 | bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI); | |
207 | bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII); | |
3273c2e8 BH |
208 | |
209 | /* XGXS block is flaky and will need to be reset if moving | |
210 | * into our out of XGMII, XGXS or XAUI loopbacks. */ | |
211 | if (EFX_WORKAROUND_5147(efx)) { | |
dc8cfa55 BH |
212 | bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; |
213 | bool reset_xgxs; | |
3273c2e8 | 214 | |
c1e5fcc9 BH |
215 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
216 | old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN); | |
217 | old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN); | |
3273c2e8 | 218 | |
c1e5fcc9 BH |
219 | falcon_read(efx, ®, XX_SD_CTL_REG); |
220 | old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA); | |
3273c2e8 BH |
221 | |
222 | /* The PHY driver may have turned XAUI off */ | |
223 | reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) || | |
224 | (xaui_loopback != old_xaui_loopback) || | |
225 | (xgmii_loopback != old_xgmii_loopback)); | |
8c8661e4 BH |
226 | |
227 | if (reset_xgxs) | |
228 | falcon_reset_xaui(efx); | |
3273c2e8 BH |
229 | } |
230 | ||
c1e5fcc9 BH |
231 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
232 | EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG, | |
3273c2e8 BH |
233 | (xgxs_loopback || xaui_loopback) ? |
234 | XX_FORCE_SIG_DECODE_FORCED : 0); | |
c1e5fcc9 BH |
235 | EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback); |
236 | EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback); | |
237 | falcon_write(efx, ®, XX_CORE_STAT_REG); | |
238 | ||
239 | falcon_read(efx, ®, XX_SD_CTL_REG); | |
240 | EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback); | |
241 | EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback); | |
242 | EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback); | |
243 | EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback); | |
244 | falcon_write(efx, ®, XX_SD_CTL_REG); | |
3273c2e8 BH |
245 | } |
246 | ||
247 | ||
8ceee660 BH |
248 | /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails |
249 | * to come back up. Bash it until it comes back up */ | |
177dfcd8 | 250 | static void falcon_check_xaui_link_up(struct efx_nic *efx, int tries) |
8ceee660 | 251 | { |
177dfcd8 | 252 | efx->mac_up = falcon_xaui_link_ok(efx); |
8ceee660 | 253 | |
3273c2e8 | 254 | if ((efx->loopback_mode == LOOPBACK_NETWORK) || |
f8b87c17 | 255 | efx_phy_mode_disabled(efx->phy_mode)) |
177dfcd8 BH |
256 | /* XAUI link is expected to be down */ |
257 | return; | |
8ceee660 | 258 | |
177dfcd8 BH |
259 | while (!efx->mac_up && tries) { |
260 | EFX_LOG(efx, "bashing xaui\n"); | |
91ad757c | 261 | falcon_reset_xaui(efx); |
8ceee660 | 262 | udelay(200); |
8ceee660 | 263 | |
177dfcd8 BH |
264 | efx->mac_up = falcon_xaui_link_ok(efx); |
265 | --tries; | |
266 | } | |
8ceee660 BH |
267 | } |
268 | ||
177dfcd8 | 269 | static void falcon_reconfigure_xmac(struct efx_nic *efx) |
8ceee660 | 270 | { |
dc8cfa55 | 271 | falcon_mask_status_intr(efx, false); |
8ceee660 | 272 | |
3273c2e8 | 273 | falcon_reconfigure_xgxs_core(efx); |
8ceee660 | 274 | falcon_reconfigure_xmac_core(efx); |
3273c2e8 | 275 | |
8ceee660 BH |
276 | falcon_reconfigure_mac_wrapper(efx); |
277 | ||
177dfcd8 BH |
278 | falcon_check_xaui_link_up(efx, 5); |
279 | falcon_mask_status_intr(efx, true); | |
8ceee660 BH |
280 | } |
281 | ||
177dfcd8 | 282 | static void falcon_update_stats_xmac(struct efx_nic *efx) |
8ceee660 BH |
283 | { |
284 | struct efx_mac_stats *mac_stats = &efx->mac_stats; | |
285 | int rc; | |
286 | ||
287 | rc = falcon_dma_stats(efx, XgDmaDone_offset); | |
288 | if (rc) | |
289 | return; | |
290 | ||
291 | /* Update MAC stats from DMAed values */ | |
292 | FALCON_STAT(efx, XgRxOctets, rx_bytes); | |
293 | FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes); | |
294 | FALCON_STAT(efx, XgRxPkts, rx_packets); | |
295 | FALCON_STAT(efx, XgRxPktsOK, rx_good); | |
296 | FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast); | |
297 | FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast); | |
298 | FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast); | |
299 | FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64); | |
300 | FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo); | |
301 | FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo); | |
302 | FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64); | |
303 | FALCON_STAT(efx, XgRxDropEvents, rx_overflow); | |
304 | FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad); | |
305 | FALCON_STAT(efx, XgRxAlignError, rx_align_error); | |
306 | FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error); | |
307 | FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error); | |
308 | FALCON_STAT(efx, XgRxControlPkts, rx_control); | |
309 | FALCON_STAT(efx, XgRxPausePkts, rx_pause); | |
310 | FALCON_STAT(efx, XgRxPkts64Octets, rx_64); | |
311 | FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127); | |
312 | FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255); | |
313 | FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511); | |
314 | FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023); | |
315 | FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx); | |
316 | FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo); | |
317 | FALCON_STAT(efx, XgRxLengthError, rx_length_error); | |
318 | FALCON_STAT(efx, XgTxPkts, tx_packets); | |
319 | FALCON_STAT(efx, XgTxOctets, tx_bytes); | |
320 | FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast); | |
321 | FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast); | |
322 | FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast); | |
323 | FALCON_STAT(efx, XgTxControlPkts, tx_control); | |
324 | FALCON_STAT(efx, XgTxPausePkts, tx_pause); | |
325 | FALCON_STAT(efx, XgTxPkts64Octets, tx_64); | |
326 | FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127); | |
327 | FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255); | |
328 | FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511); | |
329 | FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023); | |
330 | FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx); | |
331 | FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo); | |
332 | FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64); | |
333 | FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo); | |
334 | FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp); | |
335 | FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error); | |
336 | FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error); | |
337 | ||
338 | /* Update derived statistics */ | |
339 | mac_stats->tx_good_bytes = | |
c264361d BH |
340 | (mac_stats->tx_bytes - mac_stats->tx_bad_bytes - |
341 | mac_stats->tx_control * 64); | |
8ceee660 | 342 | mac_stats->rx_bad_bytes = |
c264361d BH |
343 | (mac_stats->rx_bytes - mac_stats->rx_good_bytes - |
344 | mac_stats->rx_control * 64); | |
8ceee660 BH |
345 | } |
346 | ||
766ca0fa | 347 | static void falcon_xmac_irq(struct efx_nic *efx) |
8ceee660 | 348 | { |
766ca0fa BH |
349 | /* The XGMII link has a transient fault, which indicates either: |
350 | * - there's a transient xgmii fault | |
351 | * - falcon's end of the xaui link may need a kick | |
352 | * - the wire-side link may have gone down, but the lasi/poll() | |
353 | * hasn't noticed yet. | |
354 | * | |
355 | * We only want to even bother polling XAUI if we're confident it's | |
356 | * not (1) or (3). In both cases, the only reliable way to spot this | |
357 | * is to wait a bit. We do this here by forcing the mac link state | |
358 | * to down, and waiting for the mac poll to come round and check | |
359 | */ | |
360 | efx->mac_up = false; | |
361 | } | |
8ceee660 | 362 | |
766ca0fa BH |
363 | static void falcon_poll_xmac(struct efx_nic *efx) |
364 | { | |
365 | if (!EFX_WORKAROUND_5147(efx) || !efx->link_up || efx->mac_up) | |
366 | return; | |
3273c2e8 | 367 | |
dc8cfa55 | 368 | falcon_mask_status_intr(efx, false); |
766ca0fa BH |
369 | falcon_check_xaui_link_up(efx, 1); |
370 | falcon_mask_status_intr(efx, true); | |
8ceee660 BH |
371 | } |
372 | ||
177dfcd8 BH |
373 | struct efx_mac_operations falcon_xmac_operations = { |
374 | .reconfigure = falcon_reconfigure_xmac, | |
375 | .update_stats = falcon_update_stats_xmac, | |
766ca0fa BH |
376 | .irq = falcon_xmac_irq, |
377 | .poll = falcon_poll_xmac, | |
177dfcd8 | 378 | }; |