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S2io: Multiqueue network device support implementation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / s2io.h
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
b7b5a128 17#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
1da177e4
LT		 18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
19a60522 33#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
faa4f796 34#define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL
19a60522 35#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
9fc93a41
SS		 36#define S2IO_BIT_RESET 1
37#define S2IO_BIT_SET 2
bd1034f0
AR		 38#define CHECKBIT(value, nbit) (value & (1 << nbit))
39
20346722
K		 40/* Maximum time to flicker LED when asked to identify NIC using ethtool */
41#define MAX_FLICKER_TIME 60000 /* 60 Secs */
42
1da177e4 43/* Maximum outstanding splits to be configured into xena. */
1ee6dd77 44enum {
1da177e4
LT		 45 XENA_ONE_SPLIT_TRANSACTION = 0,
46 XENA_TWO_SPLIT_TRANSACTION = 1,
47 XENA_THREE_SPLIT_TRANSACTION = 2,
48 XENA_FOUR_SPLIT_TRANSACTION = 3,
49 XENA_EIGHT_SPLIT_TRANSACTION = 4,
50 XENA_TWELVE_SPLIT_TRANSACTION = 5,
51 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
52 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
1ee6dd77 53};
1da177e4
LT		 54#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
55
56/* OS concerned variables and constants */
20346722
K		 57#define WATCH_DOG_TIMEOUT 15*HZ
58#define EFILL 0x1234
59#define ALIGN_SIZE 127
60#define PCIX_COMMAND_REGISTER 0x62
1da177e4
LT		 61
62/*
63 * Debug related variables.
64 */
65/* different debug levels. */
66#define ERR_DBG 0
67#define INIT_DBG 1
68#define INFO_DBG 2
69#define TX_DBG 3
70#define INTR_DBG 4
71
72/* Global variable that defines the present debug level of the driver. */
26df54bf 73static int debug_level = ERR_DBG;
1da177e4
LT		 74
75/* DEBUG message print. */
76#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
77
491abf25
VP		 78#ifndef DMA_ERROR_CODE
79#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
80#endif
81
1da177e4
LT		 82/* Protocol assist features of the NIC */
83#define L3_CKSUM_OK 0xFFFF
84#define L4_CKSUM_OK 0xFFFF
85#define S2IO_JUMBO_SIZE 9600
86
20346722 87/* Driver statistics maintained by driver */
1ee6dd77 88struct swStat {
20346722
K		 89 unsigned long long single_ecc_errs;
90 unsigned long long double_ecc_errs;
bd1034f0
AR		 91 unsigned long long parity_err_cnt;
92 unsigned long long serious_err_cnt;
93 unsigned long long soft_reset_cnt;
94 unsigned long long fifo_full_cnt;
8116f3cf 95 unsigned long long ring_full_cnt[8];
7d3d0439
RA		 96 /* LRO statistics */
97 unsigned long long clubbed_frms_cnt;
98 unsigned long long sending_both;
99 unsigned long long outof_sequence_pkts;
100 unsigned long long flush_max_pkts;
101 unsigned long long sum_avg_pkts_aggregated;
102 unsigned long long num_aggregations;
c53d4945
SH		 103 /* Other statistics */
104 unsigned long long mem_alloc_fail_cnt;
491abf25 105 unsigned long long pci_map_fail_cnt;
c53d4945 106 unsigned long long watchdog_timer_cnt;
491976b2
SH		 107 unsigned long long mem_allocated;
108 unsigned long long mem_freed;
109 unsigned long long link_up_cnt;
110 unsigned long long link_down_cnt;
111 unsigned long long link_up_time;
112 unsigned long long link_down_time;
113
114 /* Transfer Code statistics */
115 unsigned long long tx_buf_abort_cnt;
116 unsigned long long tx_desc_abort_cnt;
117 unsigned long long tx_parity_err_cnt;
118 unsigned long long tx_link_loss_cnt;
119 unsigned long long tx_list_proc_err_cnt;
120
121 unsigned long long rx_parity_err_cnt;
122 unsigned long long rx_abort_cnt;
123 unsigned long long rx_parity_abort_cnt;
124 unsigned long long rx_rda_fail_cnt;
125 unsigned long long rx_unkn_prot_cnt;
126 unsigned long long rx_fcs_err_cnt;
127 unsigned long long rx_buf_size_err_cnt;
128 unsigned long long rx_rxd_corrupt_cnt;
129 unsigned long long rx_unkn_err_cnt;
8116f3cf
SS		 130
131 /* Error/alarm statistics*/
132 unsigned long long tda_err_cnt;
133 unsigned long long pfc_err_cnt;
134 unsigned long long pcc_err_cnt;
135 unsigned long long tti_err_cnt;
136 unsigned long long lso_err_cnt;
137 unsigned long long tpa_err_cnt;
138 unsigned long long sm_err_cnt;
139 unsigned long long mac_tmac_err_cnt;
140 unsigned long long mac_rmac_err_cnt;
141 unsigned long long xgxs_txgxs_err_cnt;
142 unsigned long long xgxs_rxgxs_err_cnt;
143 unsigned long long rc_err_cnt;
144 unsigned long long prc_pcix_err_cnt;
145 unsigned long long rpa_err_cnt;
146 unsigned long long rda_err_cnt;
147 unsigned long long rti_err_cnt;
148 unsigned long long mc_err_cnt;
149
1ee6dd77 150};
20346722 151
bd1034f0 152/* Xpak releated alarm and warnings */
1ee6dd77 153struct xpakStat {
bd1034f0
AR		 154 u64 alarm_transceiver_temp_high;
155 u64 alarm_transceiver_temp_low;
156 u64 alarm_laser_bias_current_high;
157 u64 alarm_laser_bias_current_low;
158 u64 alarm_laser_output_power_high;
159 u64 alarm_laser_output_power_low;
160 u64 warn_transceiver_temp_high;
161 u64 warn_transceiver_temp_low;
162 u64 warn_laser_bias_current_high;
163 u64 warn_laser_bias_current_low;
164 u64 warn_laser_output_power_high;
165 u64 warn_laser_output_power_low;
166 u64 xpak_regs_stat;
167 u32 xpak_timer_count;
1ee6dd77 168};
bd1034f0
AR		 169
170
1da177e4 171/* The statistics block of Xena */
1ee6dd77 172struct stat_block {
1da177e4 173/* Tx MAC statistics counters. */
107c3a73
AV		 174 __le32 tmac_data_octets;
175 __le32 tmac_frms;
176 __le64 tmac_drop_frms;
177 __le32 tmac_bcst_frms;
178 __le32 tmac_mcst_frms;
179 __le64 tmac_pause_ctrl_frms;
180 __le32 tmac_ucst_frms;
181 __le32 tmac_ttl_octets;
182 __le32 tmac_any_err_frms;
183 __le32 tmac_nucst_frms;
184 __le64 tmac_ttl_less_fb_octets;
185 __le64 tmac_vld_ip_octets;
186 __le32 tmac_drop_ip;
187 __le32 tmac_vld_ip;
188 __le32 tmac_rst_tcp;
189 __le32 tmac_icmp;
190 __le64 tmac_tcp;
191 __le32 reserved_0;
192 __le32 tmac_udp;
1da177e4
LT		 193
194/* Rx MAC Statistics counters. */
107c3a73
AV		 195 __le32 rmac_data_octets;
196 __le32 rmac_vld_frms;
197 __le64 rmac_fcs_err_frms;
198 __le64 rmac_drop_frms;
199 __le32 rmac_vld_bcst_frms;
200 __le32 rmac_vld_mcst_frms;
201 __le32 rmac_out_rng_len_err_frms;
202 __le32 rmac_in_rng_len_err_frms;
203 __le64 rmac_long_frms;
204 __le64 rmac_pause_ctrl_frms;
205 __le64 rmac_unsup_ctrl_frms;
206 __le32 rmac_accepted_ucst_frms;
207 __le32 rmac_ttl_octets;
208 __le32 rmac_discarded_frms;
209 __le32 rmac_accepted_nucst_frms;
210 __le32 reserved_1;
211 __le32 rmac_drop_events;
212 __le64 rmac_ttl_less_fb_octets;
213 __le64 rmac_ttl_frms;
214 __le64 reserved_2;
215 __le32 rmac_usized_frms;
216 __le32 reserved_3;
217 __le32 rmac_frag_frms;
218 __le32 rmac_osized_frms;
219 __le32 reserved_4;
220 __le32 rmac_jabber_frms;
221 __le64 rmac_ttl_64_frms;
222 __le64 rmac_ttl_65_127_frms;
223 __le64 reserved_5;
224 __le64 rmac_ttl_128_255_frms;
225 __le64 rmac_ttl_256_511_frms;
226 __le64 reserved_6;
227 __le64 rmac_ttl_512_1023_frms;
228 __le64 rmac_ttl_1024_1518_frms;
229 __le32 rmac_ip;
230 __le32 reserved_7;
231 __le64 rmac_ip_octets;
232 __le32 rmac_drop_ip;
233 __le32 rmac_hdr_err_ip;
234 __le32 reserved_8;
235 __le32 rmac_icmp;
236 __le64 rmac_tcp;
237 __le32 rmac_err_drp_udp;
238 __le32 rmac_udp;
239 __le64 rmac_xgmii_err_sym;
240 __le64 rmac_frms_q0;
241 __le64 rmac_frms_q1;
242 __le64 rmac_frms_q2;
243 __le64 rmac_frms_q3;
244 __le64 rmac_frms_q4;
245 __le64 rmac_frms_q5;
246 __le64 rmac_frms_q6;
247 __le64 rmac_frms_q7;
248 __le16 rmac_full_q3;
249 __le16 rmac_full_q2;
250 __le16 rmac_full_q1;
251 __le16 rmac_full_q0;
252 __le16 rmac_full_q7;
253 __le16 rmac_full_q6;
254 __le16 rmac_full_q5;
255 __le16 rmac_full_q4;
256 __le32 reserved_9;
257 __le32 rmac_pause_cnt;
258 __le64 rmac_xgmii_data_err_cnt;
259 __le64 rmac_xgmii_ctrl_err_cnt;
260 __le32 rmac_err_tcp;
261 __le32 rmac_accepted_ip;
1da177e4
LT		 262
263/* PCI/PCI-X Read transaction statistics. */
107c3a73
AV		 264 __le32 new_rd_req_cnt;
265 __le32 rd_req_cnt;
266 __le32 rd_rtry_cnt;
267 __le32 new_rd_req_rtry_cnt;
1da177e4
LT		 268
269/* PCI/PCI-X Write/Read transaction statistics. */
107c3a73
AV		 270 __le32 wr_req_cnt;
271 __le32 wr_rtry_rd_ack_cnt;
272 __le32 new_wr_req_rtry_cnt;
273 __le32 new_wr_req_cnt;
274 __le32 wr_disc_cnt;
275 __le32 wr_rtry_cnt;
1da177e4
LT		 276
277/* PCI/PCI-X Write / DMA Transaction statistics. */
107c3a73
AV		 278 __le32 txp_wr_cnt;
279 __le32 rd_rtry_wr_ack_cnt;
280 __le32 txd_wr_cnt;
281 __le32 txd_rd_cnt;
282 __le32 rxd_wr_cnt;
283 __le32 rxd_rd_cnt;
284 __le32 rxf_wr_cnt;
285 __le32 txf_rd_cnt;
7ba013ac 286
541ae68f 287/* Tx MAC statistics overflow counters. */
107c3a73
AV		 288 __le32 tmac_data_octets_oflow;
289 __le32 tmac_frms_oflow;
290 __le32 tmac_bcst_frms_oflow;
291 __le32 tmac_mcst_frms_oflow;
292 __le32 tmac_ucst_frms_oflow;
293 __le32 tmac_ttl_octets_oflow;
294 __le32 tmac_any_err_frms_oflow;
295 __le32 tmac_nucst_frms_oflow;
296 __le64 tmac_vlan_frms;
297 __le32 tmac_drop_ip_oflow;
298 __le32 tmac_vld_ip_oflow;
299 __le32 tmac_rst_tcp_oflow;
300 __le32 tmac_icmp_oflow;
301 __le32 tpa_unknown_protocol;
302 __le32 tmac_udp_oflow;
303 __le32 reserved_10;
304 __le32 tpa_parse_failure;
541ae68f
K		 305
306/* Rx MAC Statistics overflow counters. */
107c3a73
AV		 307 __le32 rmac_data_octets_oflow;
308 __le32 rmac_vld_frms_oflow;
309 __le32 rmac_vld_bcst_frms_oflow;
310 __le32 rmac_vld_mcst_frms_oflow;
311 __le32 rmac_accepted_ucst_frms_oflow;
312 __le32 rmac_ttl_octets_oflow;
313 __le32 rmac_discarded_frms_oflow;
314 __le32 rmac_accepted_nucst_frms_oflow;
315 __le32 rmac_usized_frms_oflow;
316 __le32 rmac_drop_events_oflow;
317 __le32 rmac_frag_frms_oflow;
318 __le32 rmac_osized_frms_oflow;
319 __le32 rmac_ip_oflow;
320 __le32 rmac_jabber_frms_oflow;
321 __le32 rmac_icmp_oflow;
322 __le32 rmac_drop_ip_oflow;
323 __le32 rmac_err_drp_udp_oflow;
324 __le32 rmac_udp_oflow;
325 __le32 reserved_11;
326 __le32 rmac_pause_cnt_oflow;
327 __le64 rmac_ttl_1519_4095_frms;
328 __le64 rmac_ttl_4096_8191_frms;
329 __le64 rmac_ttl_8192_max_frms;
330 __le64 rmac_ttl_gt_max_frms;
331 __le64 rmac_osized_alt_frms;
332 __le64 rmac_jabber_alt_frms;
333 __le64 rmac_gt_max_alt_frms;
334 __le64 rmac_vlan_frms;
335 __le32 rmac_len_discard;
336 __le32 rmac_fcs_discard;
337 __le32 rmac_pf_discard;
338 __le32 rmac_da_discard;
339 __le32 rmac_red_discard;
340 __le32 rmac_rts_discard;
341 __le32 reserved_12;
342 __le32 rmac_ingm_full_discard;
343 __le32 reserved_13;
344 __le32 rmac_accepted_ip_oflow;
345 __le32 reserved_14;
346 __le32 link_fault_cnt;
bd1034f0 347 u8 buffer[20];
1ee6dd77
RB		 348 struct swStat sw_stat;
349 struct xpakStat xpak_stat;
350};
1da177e4 351
926930b2
SS		 352/* Default value for 'vlan_strip_tag' configuration parameter */
353#define NO_STRIP_IN_PROMISC 2
354
20346722
K		 355/*
356 * Structures representing different init time configuration
1da177e4
LT		 357 * parameters of the NIC.
358 */
359
20346722
K		 360#define MAX_TX_FIFOS 8
361#define MAX_RX_RINGS 8
362
2fda096d
SR		 363#define FIFO_DEFAULT_NUM 1
364
0cec35eb
SH		 365#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
366#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
367#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
368#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
369
20346722 370/* FIFO mappings for all possible number of fifos configured */
26df54bf 371static int fifo_map[][MAX_TX_FIFOS] = {
20346722
K		 372 {0, 0, 0, 0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 1, 1, 1, 1},
374 {0, 0, 0, 1, 1, 1, 2, 2},
375 {0, 0, 1, 1, 2, 2, 3, 3},
376 {0, 0, 1, 1, 2, 2, 3, 4},
377 {0, 0, 1, 1, 2, 3, 4, 5},
378 {0, 0, 1, 2, 3, 4, 5, 6},
379 {0, 1, 2, 3, 4, 5, 6, 7},
380};
381
1da177e4 382/* Maintains Per FIFO related information. */
1ee6dd77 383struct tx_fifo_config {
1da177e4
LT		 384#define MAX_AVAILABLE_TXDS 8192
385 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
386/* Priority definition */
387#define TX_FIFO_PRI_0 0 /*Highest */
388#define TX_FIFO_PRI_1 1
389#define TX_FIFO_PRI_2 2
390#define TX_FIFO_PRI_3 3
391#define TX_FIFO_PRI_4 4
392#define TX_FIFO_PRI_5 5
393#define TX_FIFO_PRI_6 6
394#define TX_FIFO_PRI_7 7 /*lowest */
395 u8 fifo_priority; /* specifies pointer level for FIFO */
396 /* user should not set twos fifos with same pri */
397 u8 f_no_snoop;
398#define NO_SNOOP_TXD 0x01
399#define NO_SNOOP_TXD_BUFFER 0x02
1ee6dd77 400};
1da177e4
LT		 401
402
403/* Maintains per Ring related information */
1ee6dd77 404struct rx_ring_config {
1da177e4
LT		 405 u32 num_rxd; /*No of RxDs per Rx Ring */
406#define RX_RING_PRI_0 0 /* highest */
407#define RX_RING_PRI_1 1
408#define RX_RING_PRI_2 2
409#define RX_RING_PRI_3 3
410#define RX_RING_PRI_4 4
411#define RX_RING_PRI_5 5
412#define RX_RING_PRI_6 6
413#define RX_RING_PRI_7 7 /* lowest */
414
415 u8 ring_priority; /*Specifies service priority of ring */
416 /* OSM should not set any two rings with same priority */
417 u8 ring_org; /*Organization of ring */
418#define RING_ORG_BUFF1 0x01
419#define RX_RING_ORG_BUFF3 0x03
420#define RX_RING_ORG_BUFF5 0x05
421
422 u8 f_no_snoop;
423#define NO_SNOOP_RXD 0x01
424#define NO_SNOOP_RXD_BUFFER 0x02
1ee6dd77 425};
1da177e4 426
20346722
K		 427/* This structure provides contains values of the tunable parameters
428 * of the H/W
1da177e4
LT		 429 */
430struct config_param {
431/* Tx Side */
432 u32 tx_fifo_num; /*Number of Tx FIFOs */
1da177e4 433
20346722 434 u8 fifo_mapping[MAX_TX_FIFOS];
1ee6dd77 435 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
1da177e4
LT		 436 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
437 u64 tx_intr_type;
8abc4d5b
SS		 438#define INTA 0
439#define MSI_X 2
440 u8 intr_type;
c77dd43e 441 u8 napi;
8abc4d5b 442
1da177e4
LT		 443 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
444
445/* Rx Side */
446 u32 rx_ring_num; /*Number of receive rings */
1da177e4
LT		 447#define MAX_RX_BLOCKS_PER_RING 150
448
1ee6dd77 449 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
1da177e4
LT		 450
451#define HEADER_ETHERNET_II_802_3_SIZE 14
452#define HEADER_802_2_SIZE 3
453#define HEADER_SNAP_SIZE 5
454#define HEADER_VLAN_SIZE 4
455
456#define MIN_MTU 46
457#define MAX_PYLD 1500
458#define MAX_MTU (MAX_PYLD+18)
459#define MAX_MTU_VLAN (MAX_PYLD+22)
460#define MAX_PYLD_JUMBO 9600
461#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
462#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
20346722 463 u16 bus_speed;
faa4f796
SH		 464 int max_mc_addr; /* xena=64 herc=256 */
465 int max_mac_addr; /* xena=16 herc=64 */
466 int mc_start_offset; /* xena=16 herc=64 */
3a3d5756 467 u8 multiq;
1da177e4
LT		 468};
469
470/* Structure representing MAC Addrs */
1ee6dd77 471struct mac_addr {
1da177e4 472 u8 mac_addr[ETH_ALEN];
1ee6dd77 473};
1da177e4
LT		 474
475/* Structure that represent every FIFO element in the BAR1
20346722 476 * Address location.
1da177e4 477 */
1ee6dd77 478struct TxFIFO_element {
1da177e4
LT		 479 u64 TxDL_Pointer;
480
481 u64 List_Control;
482#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
b7b5a128
JS		 483#define TX_FIFO_FIRST_LIST s2BIT(14)
484#define TX_FIFO_LAST_LIST s2BIT(15)
1da177e4 485#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
b7b5a128
JS		 486#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
487#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
488#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
1ee6dd77 489};
1da177e4
LT		 490
491/* Tx descriptor structure */
1ee6dd77 492struct TxD {
1da177e4
LT		 493 u64 Control_1;
494/* bit mask */
b7b5a128
JS		 495#define TXD_LIST_OWN_XENA s2BIT(7)
496#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
1da177e4
LT		 497#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
498#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
b7b5a128
JS		 499#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
500#define TXD_GATHER_CODE_FIRST s2BIT(22)
501#define TXD_GATHER_CODE_LAST s2BIT(23)
502#define TXD_TCP_LSO_EN s2BIT(30)
503#define TXD_UDP_COF_EN s2BIT(31)
504#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
1da177e4 505#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
fed5eccd 506#define TXD_UFO_MSS(val) vBIT(val,34,14)
1da177e4
LT		 507#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
508
509 u64 Control_2;
b7b5a128
JS		 510#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
511#define TXD_TX_CKO_IPV4_EN s2BIT(5)
512#define TXD_TX_CKO_TCP_EN s2BIT(6)
513#define TXD_TX_CKO_UDP_EN s2BIT(7)
514#define TXD_VLAN_ENABLE s2BIT(15)
1da177e4
LT		 515#define TXD_VLAN_TAG(val) vBIT(val,16,16)
516#define TXD_INT_NUMBER(val) vBIT(val,34,6)
b7b5a128
JS		 517#define TXD_INT_TYPE_PER_LIST s2BIT(47)
518#define TXD_INT_TYPE_UTILZ s2BIT(46)
1da177e4
LT		 519#define TXD_SET_MARKER vBIT(0x6,0,4)
520
521 u64 Buffer_Pointer;
522 u64 Host_Control; /* reserved for host */
1ee6dd77 523};
1da177e4
LT		 524
525/* Structure to hold the phy and virt addr of every TxDL. */
1ee6dd77 526struct list_info_hold {
1da177e4
LT		 527 dma_addr_t list_phy_addr;
528 void *list_virt_addr;
1ee6dd77 529};
1da177e4 530
da6971d8 531/* Rx descriptor structure for 1 buffer mode */
1ee6dd77 532struct RxD_t {
1da177e4
LT		 533 u64 Host_Control; /* reserved for host */
534 u64 Control_1;
b7b5a128
JS		 535#define RXD_OWN_XENA s2BIT(7)
536#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
1da177e4 537#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
b7b5a128
JS		 538#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
539#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
540#define RXD_FRAME_IP_FRAG s2BIT(29)
541#define RXD_FRAME_PROTO_TCP s2BIT(30)
542#define RXD_FRAME_PROTO_UDP s2BIT(31)
1da177e4
LT		 543#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
544#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
545#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
546
547 u64 Control_2;
5e25b9dd
K		 548#define THE_RXD_MARK 0x3
549#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
550#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
551
1da177e4
LT		 552#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
553#define SET_VLAN_TAG(val) vBIT(val,48,16)
554#define SET_NUM_TAG(val) vBIT(val,16,32)
555
da6971d8 556
1ee6dd77 557};
da6971d8 558/* Rx descriptor structure for 1 buffer mode */
1ee6dd77
RB		 559struct RxD1 {
560 struct RxD_t h;
da6971d8
AR		 561
562#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
563#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
564#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
565 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
566 u64 Buffer0_ptr;
1ee6dd77 567};
da6971d8
AR		 568/* Rx descriptor structure for 3 or 2 buffer mode */
569
1ee6dd77
RB		 570struct RxD3 {
571 struct RxD_t h;
da6971d8
AR		 572
573#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
574#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
575#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
576#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
577#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
578#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
579#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
580 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
581#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
582 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
583#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
584 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
1da177e4
LT		 585#define BUF0_LEN 40
586#define BUF1_LEN 1
1da177e4
LT		 587
588 u64 Buffer0_ptr;
1da177e4
LT		 589 u64 Buffer1_ptr;
590 u64 Buffer2_ptr;
1ee6dd77 591};
da6971d8 592
1da177e4 593
20346722 594/* Structure that represents the Rx descriptor block which contains
1da177e4
LT		 595 * 128 Rx descriptors.
596 */
1ee6dd77 597struct RxD_block {
da6971d8 598#define MAX_RXDS_PER_BLOCK_1 127
1ee6dd77 599 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
1da177e4
LT		 600
601 u64 reserved_0;
602#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
20346722 603 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
1da177e4
LT		 604 * Rxd in this blk */
605 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
606 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
20346722 607 * the upper 32 bits should
1da177e4 608 * be 0 */
1ee6dd77 609};
1da177e4 610
1da177e4
LT		 611#define SIZE_OF_BLOCK 4096
612
19a60522 613#define RXD_MODE_1 0 /* One Buffer mode */
6d517a27 614#define RXD_MODE_3B 1 /* Two Buffer mode */
da6971d8 615
20346722 616/* Structure to hold virtual addresses of Buf0 and Buf1 in
1da177e4 617 * 2buf mode. */
1ee6dd77 618struct buffAdd {
1da177e4
LT		 619 void *ba_0_org;
620 void *ba_1_org;
621 void *ba_0;
622 void *ba_1;
1ee6dd77 623};
1da177e4
LT		 624
625/* Structure which stores all the MAC control parameters */
626
20346722
K		 627/* This structure stores the offset of the RxD in the ring
628 * from which the Rx Interrupt processor can start picking
1da177e4
LT		 629 * up the RxDs for processing.
630 */
1ee6dd77 631struct rx_curr_get_info {
1da177e4
LT		 632 u32 block_index;
633 u32 offset;
634 u32 ring_len;
1ee6dd77 635};
1da177e4 636
1ee6dd77
RB		 637struct rx_curr_put_info {
638 u32 block_index;
639 u32 offset;
640 u32 ring_len;
641};
1da177e4
LT		 642
643/* This structure stores the offset of the TxDl in the FIFO
20346722 644 * from which the Tx Interrupt processor can start picking
1da177e4
LT		 645 * up the TxDLs for send complete interrupt processing.
646 */
1ee6dd77 647struct tx_curr_get_info {
1da177e4
LT		 648 u32 offset;
649 u32 fifo_len;
1ee6dd77 650};
1da177e4 651
1ee6dd77
RB		 652struct tx_curr_put_info {
653 u32 offset;
654 u32 fifo_len;
655};
da6971d8 656
1ee6dd77 657struct rxd_info {
da6971d8
AR		 658 void *virt_addr;
659 dma_addr_t dma_addr;
1ee6dd77 660};
da6971d8 661
20346722 662/* Structure that holds the Phy and virt addresses of the Blocks */
1ee6dd77 663struct rx_block_info {
da6971d8 664 void *block_virt_addr;
20346722 665 dma_addr_t block_dma_addr;
1ee6dd77
RB		 666 struct rxd_info *rxds;
667};
20346722
K		 668
669/* Ring specific structure */
1ee6dd77 670struct ring_info {
20346722
K		 671 /* The ring number */
672 int ring_no;
673
674 /*
675 * Place holders for the virtual and physical addresses of
676 * all the Rx Blocks
677 */
1ee6dd77 678 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
20346722
K		 679 int block_count;
680 int pkt_cnt;
681
682 /*
683 * Put pointer info which indictes which RxD has to be replenished
1da177e4
LT		 684 * with a new buffer.
685 */
1ee6dd77 686 struct rx_curr_put_info rx_curr_put_info;
1da177e4 687
20346722
K		 688 /*
689 * Get pointer info which indictes which is the last RxD that was
1da177e4
LT		 690 * processed by the driver.
691 */
1ee6dd77 692 struct rx_curr_get_info rx_curr_get_info;
1da177e4 693
20346722
K		 694 /* Index to the absolute position of the put pointer of Rx ring */
695 int put_pos;
20346722 696
20346722 697 /* Buffer Address store. */
1ee6dd77
RB		 698 struct buffAdd **ba;
699 struct s2io_nic *nic;
700};
1da177e4 701
20346722 702/* Fifo specific structure */
1ee6dd77 703struct fifo_info {
20346722
K		 704 /* FIFO number */
705 int fifo_no;
706
707 /* Maximum TxDs per TxDL */
708 int max_txds;
709
710 /* Place holder of all the TX List's Phy and Virt addresses. */
1ee6dd77 711 struct list_info_hold *list_info;
20346722
K		 712
713 /*
714 * Current offset within the tx FIFO where driver would write
715 * new Tx frame
716 */
1ee6dd77 717 struct tx_curr_put_info tx_curr_put_info;
20346722
K		 718
719 /*
720 * Current offset within tx FIFO from where the driver would start freeing
721 * the buffers
722 */
1ee6dd77 723 struct tx_curr_get_info tx_curr_get_info;
3a3d5756
SH		 724#define FIFO_QUEUE_START 0
725#define FIFO_QUEUE_STOP 1
726 int queue_state;
727
728 /* copy of sp->dev pointer */
729 struct net_device *dev;
730
731 /* copy of multiq status */
732 u8 multiq;
20346722 733
2fda096d
SR		 734 /* Per fifo lock */
735 spinlock_t tx_lock;
736
737 /* Per fifo UFO in band structure */
738 u64 *ufo_in_band_v;
739
1ee6dd77 740 struct s2io_nic *nic;
2fda096d 741} ____cacheline_aligned;
20346722 742
47bdd718 743/* Information related to the Tx and Rx FIFOs and Rings of Xena
20346722
K		 744 * is maintained in this structure.
745 */
1ee6dd77 746struct mac_info {
1da177e4
LT		 747/* tx side stuff */
748 /* logical pointer of start of each Tx FIFO */
1ee6dd77 749 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
1da177e4 750
20346722 751 /* Fifo specific structure */
1ee6dd77 752 struct fifo_info fifos[MAX_TX_FIFOS];
20346722 753
776bd20f 754 /* Save virtual address of TxD page with zero DMA addr(if any) */
755 void *zerodma_virt_addr;
756
20346722
K		 757/* rx side stuff */
758 /* Ring specific structure */
1ee6dd77 759 struct ring_info rings[MAX_RX_RINGS];
20346722
K		 760
761 u16 rmac_pause_time;
762 u16 mc_pause_threshold_q0q3;
763 u16 mc_pause_threshold_q4q7;
1da177e4
LT		 764
765 void *stats_mem; /* orignal pointer to allocated mem */
766 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
767 u32 stats_mem_sz;
1ee6dd77
RB		 768 struct stat_block *stats_info; /* Logical address of the stat block */
769};
1da177e4
LT		 770
771/* structure representing the user defined MAC addresses */
1ee6dd77 772struct usr_addr {
1da177e4
LT		 773 char addr[ETH_ALEN];
774 int usage_cnt;
1ee6dd77 775};
1da177e4 776
1da177e4 777/* Default Tunable parameters of the NIC. */
9dc737a7
AR		 778#define DEFAULT_FIFO_0_LEN 4096
779#define DEFAULT_FIFO_1_7_LEN 512
c92ca04b
AR		 780#define SMALL_BLK_CNT 30
781#define LARGE_BLK_CNT 100
1da177e4 782
cc6e7c44
RA		 783/*
784 * Structure to keep track of the MSI-X vectors and the corresponding
785 * argument registered against each vector
786 */
787#define MAX_REQUESTED_MSI_X 17
788struct s2io_msix_entry
789{
790 u16 vector;
791 u16 entry;
792 void *arg;
793
794 u8 type;
795#define MSIX_FIFO_TYPE 1
796#define MSIX_RING_TYPE 2
797
798 u8 in_use;
799#define MSIX_REGISTERED_SUCCESS 0xAA
800};
801
802struct msix_info_st {
803 u64 addr;
804 u64 data;
805};
806
7d3d0439 807/* Data structure to represent a LRO session */
1ee6dd77 808struct lro {
7d3d0439 809 struct sk_buff *parent;
75c30b13 810 struct sk_buff *last_frag;
7d3d0439
RA		 811 u8 *l2h;
812 struct iphdr *iph;
813 struct tcphdr *tcph;
814 u32 tcp_next_seq;
bd4f3ae1 815 __be32 tcp_ack;
7d3d0439
RA		 816 int total_len;
817 int frags_len;
818 int sg_num;
819 int in_use;
bd4f3ae1 820 __be16 window;
7d3d0439 821 u32 cur_tsval;
c8855953 822 __be32 cur_tsecr;
7d3d0439 823 u8 saw_ts;
1ee6dd77 824};
7d3d0439 825
92b84437
SS		 826/* These flags represent the devices temporary state */
827enum s2io_device_state_t
828{
829 __S2IO_STATE_LINK_TASK=0,
830 __S2IO_STATE_CARD_UP
831};
832
1da177e4 833/* Structure representing one instance of the NIC */
20346722 834struct s2io_nic {
da6971d8 835 int rxd_mode;
20346722
K		 836 /*
837 * Count of packets to be processed in a given iteration, it will be indicated
838 * by the quota field of the device structure when NAPI is enabled.
839 */
840 int pkts_to_process;
20346722 841 struct net_device *dev;
bea3348e 842 struct napi_struct napi;
1ee6dd77 843 struct mac_info mac_control;
20346722
K		 844 struct config_param config;
845 struct pci_dev *pdev;
846 void __iomem *bar0;
847 void __iomem *bar1;
1da177e4
LT		 848#define MAX_MAC_SUPPORTED 16
849#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
850
faa4f796 851 struct mac_addr def_mac_addr[256];
1da177e4
LT		 852
853 struct net_device_stats stats;
1da177e4 854 int high_dma_flag;
1da177e4
LT		 855 int device_enabled_once;
856
c92ca04b 857 char name[60];
1da177e4
LT		 858 struct tasklet_struct task;
859 volatile unsigned long tasklet_status;
1da177e4 860
25fff88e
K		 861 /* Timer that handles I/O errors/exceptions */
862 struct timer_list alarm_timer;
863
20346722
K		 864 /* Space to back up the PCI config space */
865 u32 config_space[256 / sizeof(u32)];
866
1da177e4
LT		 867 atomic_t rx_bufs_left[MAX_RX_RINGS];
868
1da177e4 869 spinlock_t put_lock;
1da177e4
LT		 870
871#define PROMISC 1
872#define ALL_MULTI 2
873
874#define MAX_ADDRS_SUPPORTED 64
875 u16 usr_addr_count;
876 u16 mc_addr_count;
faa4f796 877 struct usr_addr usr_addrs[256];
1da177e4
LT		 878
879 u16 m_cast_flg;
880 u16 all_multi_pos;
881 u16 promisc_flg;
882
1da177e4
LT		 883 /* Id timer, used to blink NIC to physically identify NIC. */
884 struct timer_list id_timer;
885
886 /* Restart timer, used to restart NIC if the device is stuck and
20346722 887 * a schedule task that will set the correct Link state once the
1da177e4
LT		 888 * NIC's PHY has stabilized after a state change.
889 */
1da177e4
LT		 890 struct work_struct rst_timer_task;
891 struct work_struct set_link_task;
1da177e4 892
20346722 893 /* Flag that can be used to turn on or turn off the Rx checksum
1da177e4
LT		 894 * offload feature.
895 */
896 int rx_csum;
897
20346722 898 /* after blink, the adapter must be restored with original
1da177e4
LT		 899 * values.
900 */
901 u64 adapt_ctrl_org;
902
903 /* Last known link state. */
904 u16 last_link_state;
905#define LINK_DOWN 1
906#define LINK_UP 2
907
1da177e4 908 int task_flag;
491976b2 909 unsigned long long start_time;
be3a6b02 910 struct vlan_group *vlgrp;
cc6e7c44
RA		 911#define MSIX_FLG 0xA5
912 struct msix_entry *entries;
8abc4d5b
SS		 913 int msi_detected;
914 wait_queue_head_t msi_wait;
cc6e7c44 915 struct s2io_msix_entry *s2io_entries;
e6a8fee2 916 char desc[MAX_REQUESTED_MSI_X][25];
cc6e7c44 917
c92ca04b
AR		 918 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
919
cc6e7c44
RA		 920 struct msix_info_st msix_info[0x3f];
921
541ae68f
K		 922#define XFRAME_I_DEVICE 1
923#define XFRAME_II_DEVICE 2
924 u8 device_type;
be3a6b02 925
7d3d0439 926#define MAX_LRO_SESSIONS 32
1ee6dd77 927 struct lro lro0_n[MAX_LRO_SESSIONS];
7d3d0439
RA		 928 unsigned long clubbed_frms_cnt;
929 unsigned long sending_both;
930 u8 lro;
931 u16 lro_max_aggr_per_sess;
92b84437 932 volatile unsigned long state;
7ba013ac 933 spinlock_t rx_lock;
9caab458 934 u64 general_int_mask;
19a60522
SS		 935#define VPD_STRING_LEN 80
936 u8 product_name[VPD_STRING_LEN];
937 u8 serial_num[VPD_STRING_LEN];
20346722 938};
1da177e4
LT		 939
940#define RESET_ERROR 1;
941#define CMD_ERROR 2;
942
943/* OS related system calls */
944#ifndef readq
945static inline u64 readq(void __iomem *addr)
946{
20346722
K		 947 u64 ret = 0;
948 ret = readl(addr + 4);
7ef24b69
AM		 949 ret <<= 32;
950 ret |= readl(addr);
1da177e4
LT		 951
952 return ret;
953}
954#endif
955
956#ifndef writeq
957static inline void writeq(u64 val, void __iomem *addr)
958{
959 writel((u32) (val), addr);
960 writel((u32) (val >> 32), (addr + 4));
961}
c92ca04b 962#endif
1da177e4 963
6aa20a22
JG		 964/*
965 * Some registers have to be written in a particular order to
966 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
967 * is used to perform such ordered writes. Defines UF (Upper First)
c92ca04b 968 * and LF (Lower First) will be used to specify the required write order.
1da177e4
LT		 969 */
970#define UF 1
971#define LF 2
972static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
973{
c92ca04b
AR		 974 u32 ret;
975
1da177e4
LT		 976 if (order == LF) {
977 writel((u32) (val), addr);
c92ca04b 978 ret = readl(addr);
1da177e4 979 writel((u32) (val >> 32), (addr + 4));
c92ca04b 980 ret = readl(addr + 4);
1da177e4
LT		 981 } else {
982 writel((u32) (val >> 32), (addr + 4));
c92ca04b 983 ret = readl(addr + 4);
1da177e4 984 writel((u32) (val), addr);
c92ca04b 985 ret = readl(addr);
1da177e4
LT		 986 }
987}
1da177e4
LT		 988
989/* Interrupt related values of Xena */
990
991#define ENABLE_INTRS 1
992#define DISABLE_INTRS 2
993
994/* Highest level interrupt blocks */
995#define TX_PIC_INTR (0x0001<<0)
996#define TX_DMA_INTR (0x0001<<1)
997#define TX_MAC_INTR (0x0001<<2)
998#define TX_XGXS_INTR (0x0001<<3)
999#define TX_TRAFFIC_INTR (0x0001<<4)
1000#define RX_PIC_INTR (0x0001<<5)
1001#define RX_DMA_INTR (0x0001<<6)
1002#define RX_MAC_INTR (0x0001<<7)
1003#define RX_XGXS_INTR (0x0001<<8)
1004#define RX_TRAFFIC_INTR (0x0001<<9)
1005#define MC_INTR (0x0001<<10)
1006#define ENA_ALL_INTRS ( TX_PIC_INTR | \
1007 TX_DMA_INTR | \
1008 TX_MAC_INTR | \
1009 TX_XGXS_INTR | \
1010 TX_TRAFFIC_INTR | \
1011 RX_PIC_INTR | \
1012 RX_DMA_INTR | \
1013 RX_MAC_INTR | \
1014 RX_XGXS_INTR | \
1015 RX_TRAFFIC_INTR | \
1016 MC_INTR )
1017
1018/* Interrupt masks for the general interrupt mask register */
1019#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1020
b7b5a128
JS		 1021#define TXPIC_INT_M s2BIT(0)
1022#define TXDMA_INT_M s2BIT(1)
1023#define TXMAC_INT_M s2BIT(2)
1024#define TXXGXS_INT_M s2BIT(3)
1025#define TXTRAFFIC_INT_M s2BIT(8)
1026#define PIC_RX_INT_M s2BIT(32)
1027#define RXDMA_INT_M s2BIT(33)
1028#define RXMAC_INT_M s2BIT(34)
1029#define MC_INT_M s2BIT(35)
1030#define RXXGXS_INT_M s2BIT(36)
1031#define RXTRAFFIC_INT_M s2BIT(40)
1da177e4
LT		 1032
1033/* PIC level Interrupts TODO*/
1034
1035/* DMA level Inressupts */
b7b5a128
JS		 1036#define TXDMA_PFC_INT_M s2BIT(0)
1037#define TXDMA_PCC_INT_M s2BIT(2)
1da177e4
LT		 1038
1039/* PFC block interrupts */
b7b5a128 1040#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1da177e4
LT		 1041
1042/* PCC block interrupts. */
1043#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
1044 PCC_FB_ECC Error. */
1045
20346722 1046#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
1da177e4
LT		 1047/*
1048 * Prototype declaration.
1049 */
1050static int __devinit s2io_init_nic(struct pci_dev *pdev,
1051 const struct pci_device_id *pre);
1052static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1053static int init_shared_mem(struct s2io_nic *sp);
1054static void free_shared_mem(struct s2io_nic *sp);
1055static int init_nic(struct s2io_nic *nic);
1ee6dd77
RB		 1056static void rx_intr_handler(struct ring_info *ring_data);
1057static void tx_intr_handler(struct fifo_info *fifo_data);
8116f3cf 1058static void s2io_handle_errors(void * dev_id);
1da177e4
LT		 1059
1060static int s2io_starter(void);
19a60522 1061static void s2io_closer(void);
1da177e4
LT		 1062static void s2io_tx_watchdog(struct net_device *dev);
1063static void s2io_tasklet(unsigned long dev_addr);
1064static void s2io_set_multicast(struct net_device *dev);
1ee6dd77
RB		 1065static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1066static void s2io_link(struct s2io_nic * sp, int link);
1067static void s2io_reset(struct s2io_nic * sp);
bea3348e 1068static int s2io_poll(struct napi_struct *napi, int budget);
1ee6dd77 1069static void s2io_init_pci(struct s2io_nic * sp);
2fd37688 1070static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr);
25fff88e 1071static void s2io_alarm_handle(unsigned long data);
cc6e7c44 1072static irqreturn_t
7d12e780 1073s2io_msix_ring_handle(int irq, void *dev_id);
cc6e7c44 1074static irqreturn_t
7d12e780
DH		 1075s2io_msix_fifo_handle(int irq, void *dev_id);
1076static irqreturn_t s2io_isr(int irq, void *dev_id);
1ee6dd77 1077static int verify_xena_quiescence(struct s2io_nic *sp);
7282d491 1078static const struct ethtool_ops netdev_ethtool_ops;
c4028958 1079static void s2io_set_link(struct work_struct *work);
1ee6dd77
RB		 1080static int s2io_set_swapper(struct s2io_nic * sp);
1081static void s2io_card_down(struct s2io_nic *nic);
1082static int s2io_card_up(struct s2io_nic *nic);
9fc93a41
SS		 1083static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1084 int bit_state);
1ee6dd77
RB		 1085static int s2io_add_isr(struct s2io_nic * sp);
1086static void s2io_rem_isr(struct s2io_nic * sp);
19a60522 1087
1ee6dd77 1088static void restore_xmsi_data(struct s2io_nic *nic);
faa4f796
SH		 1089static void do_s2io_store_unicast_mc(struct s2io_nic *sp);
1090static void do_s2io_restore_unicast_mc(struct s2io_nic *sp);
1091static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset);
1092static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr);
1093static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset);
1094static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr);
7d3d0439 1095
1ee6dd77
RB		 1096static int
1097s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1098 struct RxD_t *rxdp, struct s2io_nic *sp);
1099static void clear_lro_session(struct lro *lro);
7d3d0439 1100static void queue_rx_frame(struct sk_buff *skb);
1ee6dd77
RB		 1101static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1102static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1103 struct sk_buff *skb, u32 tcp_len);
9fc93a41 1104static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
b41477f3 1105
d796fdb7
LV		 1106static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
1107 pci_channel_state_t state);
1108static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev);
1109static void s2io_io_resume(struct pci_dev *pdev);
1110
75c30b13
AR		 1111#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1112#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1113#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1114
b41477f3
AR		 1115#define S2IO_PARM_INT(X, def_val) \
1116 static unsigned int X = def_val;\
1117 module_param(X , uint, 0);
1118
1da177e4 1119#endif /* _S2IO_H */
kernel source for telekom puls (alcatel/mediatek)